Project Statistics |
PROPEXT_xilxBitgCfg_DCIUpdateMode_virtex6=As Required |
PROPEXT_xilxMapPackRegInto_virtex5=For Inputs and Outputs |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2014-01-08T10:14:16 |
PROP_intWbtProjectID=6746599D1FF0C051FBBBABAC91FADE89 |
PROP_intWbtProjectIteration=2 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.top |
PROP_xilxBitgCfg_GenOpt_Compress_virtex5=true |
PROP_xilxBitgStart_IntDone_virtex5=true |
PROP_AutoTop=true |
PROP_DevFamily=Virtex6 |
PROP_xilxMapEnableMultiThreading=2 |
PROP_DevDevice=xc6vlx130t |
PROP_DevFamilyPMName=virtex6 |
PROP_DevPackage=ff1156 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_parEnableMultiThreading_virtex5=2 |
PROP_DevSpeed=-1 |
PROP_PreferredLanguage=Verilog |
FILE_COREGEN=1 |
FILE_UCF=1 |
FILE_VHDL=51 |