top Project Status (01/08/2014 - 11:11:10)
Project File: glib_v3.xise Parser Errors: No Errors
Module Name: top Implementation State: Programming File Generated
Target Device: xc6vlx130t-1ff1156
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
944 Warnings (61 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 3,525 160,000 2%  
    Number used as Flip Flops 3,524      
    Number used as Latches 1      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 3,011 80,000 3%  
    Number used as logic 2,751 80,000 3%  
        Number using O6 output only 1,732      
        Number using O5 output only 117      
        Number using O5 and O6 902      
        Number used as ROM 0      
    Number used as Memory 3 27,840 1%  
        Number used as Dual Port RAM 0      
        Number used as Single Port RAM 0      
        Number used as Shift Register 3      
            Number using O6 output only 3      
            Number using O5 output only 0      
            Number using O5 and O6 0      
    Number used exclusively as route-thrus 257      
        Number with same-slice register load 249      
        Number with same-slice carry load 8      
        Number with other load 0      
Number of occupied Slices 1,067 20,000 5%  
Number of LUT Flip Flop pairs used 3,540      
    Number with an unused Flip Flop 820 3,540 23%  
    Number with an unused LUT 529 3,540 14%  
    Number of fully used LUT-FF pairs 2,191 3,540 61%  
    Number of unique control sets 136      
    Number of slice register sites lost
        to control set restrictions
368 160,000 1%  
Number of bonded IOBs 4 600 1%  
    Number of LOCed IOBs 4 4 100%  
    IOB Flip Flops 1      
    Number of bonded IPADs 4      
        Number of LOCed IPADs 2 4 50%  
    Number of bonded OPADs 2      
Number of RAMB36E1/FIFO36E1s 19 264 7%  
    Number using RAMB36E1 only 19      
    Number using FIFO36E1 only 0      
Number of RAMB18E1/FIFO18E1s 0 528 0%  
Number of BUFG/BUFGCTRLs 3 32 9%  
    Number used as BUFGs 3      
    Number used as BUFGCTRLs 0      
Number of ILOGICE1/ISERDESE1s 0 600 0%  
Number of OLOGICE1/OSERDESE1s 2 600 1%  
    Number used as OLOGICE1s 2      
    Number used as OSERDESE1s 0      
Number of BSCANs 0 4 0%  
Number of BUFHCEs 0 120 0%  
Number of BUFIODQSs 0 60 0%  
Number of BUFRs 1 30 3%  
Number of CAPTUREs 0 1 0%  
Number of DSP48E1s 0 480 0%  
Number of EFUSE_USRs 0 1 0%  
Number of FRAME_ECCs 0 1 0%  
Number of GTXE1s 1 20 5%  
    Number of LOCed GTXE1s 1 1 100%  
Number of IBUFDS_GTXE1s 1 10 10%  
Number of ICAPs 0 2 0%  
Number of IDELAYCTRLs 0 15 0%  
Number of IODELAYE1s 0 600 0%  
Number of MMCM_ADVs 1 10 10%  
Number of PCIE_2_0s 0 2 0%  
Number of STARTUPs 1 1 100%  
Number of SYSMONs 0 1 0%  
Number of TEMAC_SINGLEs 1 4 25%  
Number of RPM macros 5      
Average Fanout of Non-Clock Nets 3.84      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Jan 8 14:59:46 20140944 Warnings (61 new)311 Infos (106 new)
Translation ReportCurrentWed Jan 8 15:00:02 2014001 Info (0 new)
Map ReportCurrentWed Jan 8 15:01:32 2014009 Infos (0 new)
Place and Route ReportCurrentWed Jan 8 15:02:41 2014000
Power Report     
Post-PAR Static Timing ReportCurrentWed Jan 8 15:03:01 2014003 Infos (0 new)
Bitgen ReportCurrentWed Jan 8 15:05:00 2014001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Jan 8 15:05:03 2014
WebTalk Log FileCurrentWed Jan 8 15:05:03 2014

Date Generated: 01/30/2014 - 14:32:45