Release 14.7 Map P.20131013 (lin64) Xilinx Map Application Log File for Design 'top' Design Information ------------------ Command Line : map -intstyle ise -p xc6vlx130t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr b -lc off -power off -o top_map.ncd top.ngd top.pcf Target Device : xc6vlx130t Target Package : ff1156 Target Speed : -1 Mapper Version : virtex6 -- $Revision: 1.55 $ Mapped Date : Wed Jan 8 15:00:04 2014 Mapping design into LUTs... Running directed packing... Running delay-based LUT packing... Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... Total REAL time at the beginning of Placer: 38 secs Total CPU time at the beginning of Placer: 38 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:487caa77) REAL time: 45 secs Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check (Checksum:487caa77) REAL time: 46 secs Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization (Checksum:e0706b69) REAL time: 46 secs Phase 4.37 Local Placement Optimization Phase 4.37 Local Placement Optimization (Checksum:e0706b69) REAL time: 46 secs Phase 5.2 Initial Placement for Architecture Specific Features ...... There are 10 clock regions on the target FPGA device: |------------------------------------------|------------------------------------------| | CLOCKREGION_X0Y4: | CLOCKREGION_X1Y4: | | 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | | 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 1 in use | | 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | | 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | | | | |------------------------------------------|------------------------------------------| | CLOCKREGION_X0Y3: | CLOCKREGION_X1Y3: | | 4 BUFRs available, 0 in use | 2 BUFRs available, 1 in use | | 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 1 in use | | 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | | 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | | | | |------------------------------------------|------------------------------------------| | CLOCKREGION_X0Y2: | CLOCKREGION_X1Y2: | | 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | | 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 1 in use | | 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | | 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | | | | |------------------------------------------|------------------------------------------| | CLOCKREGION_X0Y1: | CLOCKREGION_X1Y1: | | 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | | 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | | 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | | 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | | | | |------------------------------------------|------------------------------------------| | CLOCKREGION_X0Y0: | CLOCKREGION_X1Y0: | | 4 BUFRs available, 0 in use | 2 BUFRs available, 0 in use | | 6 Regional Clock Spines, 0 in use | 6 Regional Clock Spines, 0 in use | | 4 edge BUFIOs available, 0 in use | 0 edge BUFIOs available, 0 in use | | 4 center BUFIOs available, 0 in use | 4 center BUFIOs available, 0 in use | | | | |------------------------------------------|------------------------------------------| Clock-Region: key resource utilizations (used/available): edge-bufios - 0/0; center-bufios - 0/4; bufrs - 1/2; regional-clock-spines - 1/6 |----------------------------------------------------------------------------------------------------------------------------------------------------------- | | clock | BRAM | | | | | | | | | | | | | | region | FIFO | DCM | GT | ILOGIC | OLOGIC | FF | LUTM | LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region) |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- | | Upper Region| 84 | 0 | 0 | 40 | 40 | 16000 | 5760 | 10240 | 48 | 2 | 0 | 0 | <- Available resources in the upper region |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- | |CurrentRegion| 84 | 0 | 0 | 40 | 40 | 15040 | 5600 | 9440 | 48 | 0 | 0 | 1 | <- Available resources in the current region |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- | | Lower Region| 84 | 0 | 0 | 40 | 40 | 16000 | 5760 | 10240 | 48 | 2 | 0 | 0 | <- Available resources in the lower region |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- | clock | region | ----------------------------------------------- | type | expansion | | |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- | BUFR | Upper/Lower | 0 | 0 | 0 | 0 | 0 | 12 | 1 | 0 | 0 | 0 | 0 | 0 | "eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i" |-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|---------------------------------------------- ###################################################################################### # REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT: # # Number of Regional Clocking Regions in the device: 10 (6 clock spines in each) # Number of Regional Clock Networks used in this design: 1 (each network can be # composed of up to 3 clock spines and cover up to 3 regional clock regions) # ###################################################################################### # Regional-Clock "eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i" driven by "BUFR_X2Y6" INST "eth/sgmii/v6_gtxwizard_top_inst/bufr_clk_ds" LOC = "BUFR_X2Y6" ; NET "eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i" TNM_NET = "TN_eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i" ; TIMEGRP "TN_eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i" AREA_GROUP = "CLKAG_eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i" ; AREA_GROUP "CLKAG_eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i" RANGE = CLOCKREGION_X1Y3, CLOCKREGION_X1Y4, CLOCKREGION_X1Y2; Phase 5.2 Initial Placement for Architecture Specific Features (Checksum:d4667de1) REAL time: 55 secs Phase 6.36 Local Placement Optimization Phase 6.36 Local Placement Optimization (Checksum:d4667de1) REAL time: 55 secs Phase 7.30 Global Clock Region Assignment Phase 7.30 Global Clock Region Assignment (Checksum:d4667de1) REAL time: 55 secs Phase 8.3 Local Placement Optimization Phase 8.3 Local Placement Optimization (Checksum:d4667de1) REAL time: 55 secs Phase 9.5 Local Placement Optimization Phase 9.5 Local Placement Optimization (Checksum:d4667de1) REAL time: 55 secs Phase 10.8 Global Placement ................................................................................................................... ........................................................................ ..................................................................................................................... ............................ Phase 10.8 Global Placement (Checksum:7623f3b6) REAL time: 1 mins 11 secs Phase 11.5 Local Placement Optimization Phase 11.5 Local Placement Optimization (Checksum:7623f3b6) REAL time: 1 mins 11 secs Phase 12.18 Placement Optimization Phase 12.18 Placement Optimization (Checksum:80e6b730) REAL time: 1 mins 22 secs Phase 13.5 Local Placement Optimization Phase 13.5 Local Placement Optimization (Checksum:80e6b730) REAL time: 1 mins 22 secs Phase 14.34 Placement Validation Phase 14.34 Placement Validation (Checksum:6b60ebbe) REAL time: 1 mins 22 secs Total REAL time to Placer completion: 1 mins 23 secs Total CPU time to Placer completion: 1 mins 27 secs Running post-placement packing... Writing output files... Design Summary -------------- Design Summary: Number of errors: 0 Number of warnings: 0 Slice Logic Utilization: Number of Slice Registers: 3,525 out of 160,000 2% Number used as Flip Flops: 3,524 Number used as Latches: 1 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 3,011 out of 80,000 3% Number used as logic: 2,751 out of 80,000 3% Number using O6 output only: 1,732 Number using O5 output only: 117 Number using O5 and O6: 902 Number used as ROM: 0 Number used as Memory: 3 out of 27,840 1% Number used as Dual Port RAM: 0 Number used as Single Port RAM: 0 Number used as Shift Register: 3 Number using O6 output only: 3 Number using O5 output only: 0 Number using O5 and O6: 0 Number used exclusively as route-thrus: 257 Number with same-slice register load: 249 Number with same-slice carry load: 8 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 1,067 out of 20,000 5% Number of LUT Flip Flop pairs used: 3,540 Number with an unused Flip Flop: 820 out of 3,540 23% Number with an unused LUT: 529 out of 3,540 14% Number of fully used LUT-FF pairs: 2,191 out of 3,540 61% Number of unique control sets: 136 Number of slice register sites lost to control set restrictions: 368 out of 160,000 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 4 out of 600 1% Number of LOCed IOBs: 4 out of 4 100% IOB Flip Flops: 1 Number of bonded IPADs: 4 Number of LOCed IPADs: 2 out of 4 50% Number of bonded OPADs: 2 Specific Feature Utilization: Number of RAMB36E1/FIFO36E1s: 19 out of 264 7% Number using RAMB36E1 only: 19 Number using FIFO36E1 only: 0 Number of RAMB18E1/FIFO18E1s: 0 out of 528 0% Number of BUFG/BUFGCTRLs: 3 out of 32 9% Number used as BUFGs: 3 Number used as BUFGCTRLs: 0 Number of ILOGICE1/ISERDESE1s: 0 out of 600 0% Number of OLOGICE1/OSERDESE1s: 2 out of 600 1% Number used as OLOGICE1s: 2 Number used as OSERDESE1s: 0 Number of BSCANs: 0 out of 4 0% Number of BUFHCEs: 0 out of 120 0% Number of BUFIODQSs: 0 out of 60 0% Number of BUFRs: 1 out of 30 3% Number of CAPTUREs: 0 out of 1 0% Number of DSP48E1s: 0 out of 480 0% Number of EFUSE_USRs: 0 out of 1 0% Number of FRAME_ECCs: 0 out of 1 0% Number of GTXE1s: 1 out of 20 5% Number of LOCed GTXE1s: 1 out of 1 100% Number of IBUFDS_GTXE1s: 1 out of 10 10% Number of ICAPs: 0 out of 2 0% Number of IDELAYCTRLs: 0 out of 15 0% Number of IODELAYE1s: 0 out of 600 0% Number of MMCM_ADVs: 1 out of 10 10% Number of PCIE_2_0s: 0 out of 2 0% Number of STARTUPs: 1 out of 1 100% Number of SYSMONs: 0 out of 1 0% Number of TEMAC_SINGLEs: 1 out of 4 25% Number of RPM macros: 5 Average Fanout of Non-Clock Nets: 3.84 Peak Memory Usage: 1275 MB Total REAL time to MAP completion: 1 mins 27 secs Total CPU time to MAP completion (all processors): 1 mins 31 secs Mapping completed. See MAP report file "top_map.mrp" for details.