-------------------------------------------------------------------------------- Release 14.7 Trace (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml top.twx top.ncd -o top.twr top.pcf Design file: top.ncd Physical constraint file: top.pcf Device,package,speed: xc6vlx130t,ff1156,C,-1 (PRODUCTION 1.17 2013-10-13) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. ================================================================================ Timing constraint: TS_clk125 = PERIOD TIMEGRP "clk125" 8 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 40492 paths analyzed, 13226 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 6.813ns. -------------------------------------------------------------------------------- Paths for end point ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 (SLICE_X77Y100.D1), 11 paths -------------------------------------------------------------------------------- Slack (setup path): 1.187ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Destination: ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 (FF) Requirement: 8.000ns Data Path Delay: 6.559ns (Levels of Logic = 3) Clock Path Skew: -0.219ns (1.359 - 1.578) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 to ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X2Y21.DOBDO3 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 SLICE_X67Y108.D2 net (fanout=1) 2.041 ipbus/udp_if/ipbus_tx_ram/ram_out<19> SLICE_X67Y108.D Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob41 SLICE_X79Y100.B2 net (fanout=4) 1.652 ipbus/udp_if/udpdob<3> SLICE_X79Y100.B Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT41 SLICE_X77Y100.D1 net (fanout=2) 0.587 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT4 SLICE_X77Y100.CLK Tas 0.070 ipbus/udp_if/tx_main/send_data.mac_tx_data_int<3> ipbus/udp_if/tx_main/Mmux_send_data.mac_tx_data_int[7]_send_data.next_mac_tx_data[7]_mux_77_OUT41 ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 ------------------------------------------------- --------------------------- Total 6.559ns (2.279ns logic, 4.280ns route) (34.7% logic, 65.3% route) -------------------------------------------------------------------------------- Slack (setup path): 1.457ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram1 (RAM) Destination: ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 (FF) Requirement: 8.000ns Data Path Delay: 6.325ns (Levels of Logic = 3) Clock Path Skew: -0.183ns (0.846 - 1.029) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram1 to ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X5Y21.DOBDO3 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram1 ipbus/udp_if/ipbus_tx_ram/Mram_ram1 SLICE_X67Y108.D1 net (fanout=1) 1.807 ipbus/udp_if/ipbus_tx_ram/ram_out<3> SLICE_X67Y108.D Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob41 SLICE_X79Y100.B2 net (fanout=4) 1.652 ipbus/udp_if/udpdob<3> SLICE_X79Y100.B Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT41 SLICE_X77Y100.D1 net (fanout=2) 0.587 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT4 SLICE_X77Y100.CLK Tas 0.070 ipbus/udp_if/tx_main/send_data.mac_tx_data_int<3> ipbus/udp_if/tx_main/Mmux_send_data.mac_tx_data_int[7]_send_data.next_mac_tx_data[7]_mux_77_OUT41 ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 ------------------------------------------------- --------------------------- Total 6.325ns (2.279ns logic, 4.046ns route) (36.0% logic, 64.0% route) -------------------------------------------------------------------------------- Slack (setup path): 2.106ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram3 (RAM) Destination: ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 (FF) Requirement: 8.000ns Data Path Delay: 5.665ns (Levels of Logic = 3) Clock Path Skew: -0.194ns (0.846 - 1.040) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram3 to ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X4Y21.DOBDO3 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram3 ipbus/udp_if/ipbus_tx_ram/Mram_ram3 SLICE_X67Y108.D3 net (fanout=1) 1.147 ipbus/udp_if/ipbus_tx_ram/ram_out<11> SLICE_X67Y108.D Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob41 SLICE_X79Y100.B2 net (fanout=4) 1.652 ipbus/udp_if/udpdob<3> SLICE_X79Y100.B Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT41 SLICE_X77Y100.D1 net (fanout=2) 0.587 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT4 SLICE_X77Y100.CLK Tas 0.070 ipbus/udp_if/tx_main/send_data.mac_tx_data_int<3> ipbus/udp_if/tx_main/Mmux_send_data.mac_tx_data_int[7]_send_data.next_mac_tx_data[7]_mux_77_OUT41 ipbus/udp_if/tx_main/send_data.mac_tx_data_int_3 ------------------------------------------------- --------------------------- Total 5.665ns (2.279ns logic, 3.386ns route) (40.2% logic, 59.8% route) -------------------------------------------------------------------------------- Paths for end point ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 (SLICE_X79Y100.A2), 11 paths -------------------------------------------------------------------------------- Slack (setup path): 1.299ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Destination: ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 (FF) Requirement: 8.000ns Data Path Delay: 6.445ns (Levels of Logic = 3) Clock Path Skew: -0.221ns (1.357 - 1.578) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 to ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X2Y21.DOBDO3 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 SLICE_X67Y108.D2 net (fanout=1) 2.041 ipbus/udp_if/ipbus_tx_ram/ram_out<19> SLICE_X67Y108.D Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob41 SLICE_X79Y100.B2 net (fanout=4) 1.652 ipbus/udp_if/udpdob<3> SLICE_X79Y100.B Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT41 SLICE_X79Y100.A2 net (fanout=2) 0.470 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT4 SLICE_X79Y100.CLK Tas 0.073 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT42 ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 ------------------------------------------------- --------------------------- Total 6.445ns (2.282ns logic, 4.163ns route) (35.4% logic, 64.6% route) -------------------------------------------------------------------------------- Slack (setup path): 1.569ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram1 (RAM) Destination: ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 (FF) Requirement: 8.000ns Data Path Delay: 6.211ns (Levels of Logic = 3) Clock Path Skew: -0.185ns (0.844 - 1.029) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram1 to ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X5Y21.DOBDO3 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram1 ipbus/udp_if/ipbus_tx_ram/Mram_ram1 SLICE_X67Y108.D1 net (fanout=1) 1.807 ipbus/udp_if/ipbus_tx_ram/ram_out<3> SLICE_X67Y108.D Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob41 SLICE_X79Y100.B2 net (fanout=4) 1.652 ipbus/udp_if/udpdob<3> SLICE_X79Y100.B Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT41 SLICE_X79Y100.A2 net (fanout=2) 0.470 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT4 SLICE_X79Y100.CLK Tas 0.073 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT42 ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 ------------------------------------------------- --------------------------- Total 6.211ns (2.282ns logic, 3.929ns route) (36.7% logic, 63.3% route) -------------------------------------------------------------------------------- Slack (setup path): 2.218ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram3 (RAM) Destination: ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 (FF) Requirement: 8.000ns Data Path Delay: 5.551ns (Levels of Logic = 3) Clock Path Skew: -0.196ns (0.844 - 1.040) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram3 to ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X4Y21.DOBDO3 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram3 ipbus/udp_if/ipbus_tx_ram/Mram_ram3 SLICE_X67Y108.D3 net (fanout=1) 1.147 ipbus/udp_if/ipbus_tx_ram/ram_out<11> SLICE_X67Y108.D Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob41 SLICE_X79Y100.B2 net (fanout=4) 1.652 ipbus/udp_if/udpdob<3> SLICE_X79Y100.B Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT41 SLICE_X79Y100.A2 net (fanout=2) 0.470 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT4 SLICE_X79Y100.CLK Tas 0.073 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<4> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT42 ipbus/udp_if/tx_main/send_data.next_mac_tx_data_3 ------------------------------------------------- --------------------------- Total 5.551ns (2.282ns logic, 3.269ns route) (41.1% logic, 58.9% route) -------------------------------------------------------------------------------- Paths for end point ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 (SLICE_X77Y100.C3), 11 paths -------------------------------------------------------------------------------- Slack (setup path): 1.458ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Destination: ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 (FF) Requirement: 8.000ns Data Path Delay: 6.288ns (Levels of Logic = 3) Clock Path Skew: -0.219ns (1.359 - 1.578) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 to ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X2Y21.DOBDO2 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 SLICE_X67Y108.B2 net (fanout=1) 2.190 ipbus/udp_if/ipbus_tx_ram/ram_out<18> SLICE_X67Y108.B Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob31 SLICE_X76Y100.D3 net (fanout=4) 1.356 ipbus/udp_if/udpdob<2> SLICE_X76Y100.D Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<2> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT31 SLICE_X77Y100.C3 net (fanout=2) 0.460 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT3 SLICE_X77Y100.CLK Tas 0.073 ipbus/udp_if/tx_main/send_data.mac_tx_data_int<3> ipbus/udp_if/tx_main/Mmux_send_data.mac_tx_data_int[7]_send_data.next_mac_tx_data[7]_mux_77_OUT31 ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 ------------------------------------------------- --------------------------- Total 6.288ns (2.282ns logic, 4.006ns route) (36.3% logic, 63.7% route) -------------------------------------------------------------------------------- Slack (setup path): 2.132ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram1 (RAM) Destination: ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 (FF) Requirement: 8.000ns Data Path Delay: 5.650ns (Levels of Logic = 3) Clock Path Skew: -0.183ns (0.846 - 1.029) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram1 to ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X5Y21.DOBDO2 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram1 ipbus/udp_if/ipbus_tx_ram/Mram_ram1 SLICE_X67Y108.B5 net (fanout=1) 1.552 ipbus/udp_if/ipbus_tx_ram/ram_out<2> SLICE_X67Y108.B Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob31 SLICE_X76Y100.D3 net (fanout=4) 1.356 ipbus/udp_if/udpdob<2> SLICE_X76Y100.D Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<2> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT31 SLICE_X77Y100.C3 net (fanout=2) 0.460 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT3 SLICE_X77Y100.CLK Tas 0.073 ipbus/udp_if/tx_main/send_data.mac_tx_data_int<3> ipbus/udp_if/tx_main/Mmux_send_data.mac_tx_data_int[7]_send_data.next_mac_tx_data[7]_mux_77_OUT31 ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 ------------------------------------------------- --------------------------- Total 5.650ns (2.282ns logic, 3.368ns route) (40.4% logic, 59.6% route) -------------------------------------------------------------------------------- Slack (setup path): 2.633ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/udp_if/ipbus_tx_ram/Mram_ram3 (RAM) Destination: ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 (FF) Requirement: 8.000ns Data Path Delay: 5.138ns (Levels of Logic = 3) Clock Path Skew: -0.194ns (0.846 - 1.040) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 0.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/udp_if/ipbus_tx_ram/Mram_ram3 to ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB36_X4Y21.DOBDO2 Trcko_DOB 2.073 ipbus/udp_if/ipbus_tx_ram/Mram_ram3 ipbus/udp_if/ipbus_tx_ram/Mram_ram3 SLICE_X67Y108.B3 net (fanout=1) 1.040 ipbus/udp_if/ipbus_tx_ram/ram_out<10> SLICE_X67Y108.B Tilo 0.068 ipbus/udp_if/tx_byte_sum/lo_byte_calc.lo_byte_int<3> ipbus/udp_if/ipbus_tx_ram/Mmux_tx_dob31 SLICE_X76Y100.D3 net (fanout=4) 1.356 ipbus/udp_if/udpdob<2> SLICE_X76Y100.D Tilo 0.068 ipbus/udp_if/tx_main/send_data.next_mac_tx_data<2> ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT31 SLICE_X77Y100.C3 net (fanout=2) 0.460 ipbus/udp_if/tx_main/Mmux_send_data.next_mac_tx_data[7]_GND_158_o_mux_76_OUT3 SLICE_X77Y100.CLK Tas 0.073 ipbus/udp_if/tx_main/send_data.mac_tx_data_int<3> ipbus/udp_if/tx_main/Mmux_send_data.mac_tx_data_int[7]_send_data.next_mac_tx_data[7]_mux_77_OUT31 ipbus/udp_if/tx_main/send_data.mac_tx_data_int_2 ------------------------------------------------- --------------------------- Total 5.138ns (2.282ns logic, 2.856ns route) (44.4% logic, 55.6% route) -------------------------------------------------------------------------------- Hold Paths: TS_clk125 = PERIOD TIMEGRP "clk125" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point ipbus/udp_if/ipbus_rx_ram/Mram_ram21 (RAMB36_X3Y9.DIADI1), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.020ns (requirement - (clock path skew + uncertainty - data path)) Source: ipbus/udp_if/payload/payload_data_sig_1 (FF) Destination: ipbus/udp_if/ipbus_rx_ram/Mram_ram21 (RAM) Requirement: 0.000ns Data Path Delay: 0.171ns (Levels of Logic = 0) Clock Path Skew: 0.151ns (0.559 - 0.408) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: ipbus/udp_if/payload/payload_data_sig_1 to ipbus/udp_if/ipbus_rx_ram/Mram_ram21 Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- SLICE_X66Y51.BQ Tcko 0.098 ipbus/udp_if/payload/payload_data_sig<3> ipbus/udp_if/payload/payload_data_sig_1 RAMB36_X3Y9.DIADI1 net (fanout=5) 0.271 ipbus/udp_if/payload/payload_data_sig<1> RAMB36_X3Y9.CLKARDCLKL Trckd_DIA (-Th) 0.198 ipbus/udp_if/ipbus_rx_ram/Mram_ram21 ipbus/udp_if/ipbus_rx_ram/Mram_ram21 --------------------------------------------------- --------------------------- Total 0.171ns (-0.100ns logic, 0.271ns route) (-58.5% logic, 158.5% route) -------------------------------------------------------------------------------- Paths for end point ipbus/udp_if/ipbus_rx_ram/Mram_ram31 (RAMB36_X3Y11.DIADI1), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.028ns (requirement - (clock path skew + uncertainty - data path)) Source: ipbus/udp_if/payload/payload_data_sig_1 (FF) Destination: ipbus/udp_if/ipbus_rx_ram/Mram_ram31 (RAM) Requirement: 0.000ns Data Path Delay: 0.167ns (Levels of Logic = 0) Clock Path Skew: 0.139ns (0.547 - 0.408) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: ipbus/udp_if/payload/payload_data_sig_1 to ipbus/udp_if/ipbus_rx_ram/Mram_ram31 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X66Y51.BQ Tcko 0.098 ipbus/udp_if/payload/payload_data_sig<3> ipbus/udp_if/payload/payload_data_sig_1 RAMB36_X3Y11.DIADI1 net (fanout=5) 0.267 ipbus/udp_if/payload/payload_data_sig<1> RAMB36_X3Y11.CLKARDCLKL Trckd_DIA (-Th) 0.198 ipbus/udp_if/ipbus_rx_ram/Mram_ram31 ipbus/udp_if/ipbus_rx_ram/Mram_ram31 ---------------------------------------------------- --------------------------- Total 0.167ns (-0.100ns logic, 0.267ns route) (-59.9% logic, 159.9% route) -------------------------------------------------------------------------------- Paths for end point eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i (GTXE1_X0Y10.TXDATA4), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.036ns (requirement - (clock path skew + uncertainty - data path)) Source: eth/sgmii/mgt_tx_data_r_4 (FF) Destination: eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i (HSIO) Requirement: 0.000ns Data Path Delay: 0.477ns (Levels of Logic = 0) Clock Path Skew: 0.441ns (1.299 - 0.858) Source Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Destination Clock: eth/sgmii/tx_mac_aclk_int rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Slow Process Corner: eth/sgmii/mgt_tx_data_r_4 to eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X97Y97.AMUX Tshcko 0.338 eth/sgmii/mgt_tx_data_r<3> eth/sgmii/mgt_tx_data_r_4 GTXE1_X0Y10.TXDATA4 net (fanout=1) 1.004 eth/sgmii/mgt_tx_data_r<4> GTXE1_X0Y10.TXUSRCLK2Tgtxckc_TXDATA(-Th) 0.865 eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i ------------------------------------------------- --------------------------- Total 0.477ns (-0.527ns logic, 1.004ns route) (-110.5% logic, 210.5% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_clk125 = PERIOD TIMEGRP "clk125" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 4.800ns (period - min period limit) Period: 8.000ns Min period limit: 3.200ns (312.500MHz) (Tgtxper_USRCLK) Physical resource: eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i/RXUSRCLK2 Logical resource: eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i/RXUSRCLK2 Location pin: GTXE1_X0Y10.RXUSRCLK2 Clock network: eth/sgmii/tx_mac_aclk_int -------------------------------------------------------------------------------- Slack: 4.800ns (period - min period limit) Period: 8.000ns Min period limit: 3.200ns (312.500MHz) (Tgtxper_USRCLK) Physical resource: eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i/TXUSRCLK2 Logical resource: eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_v6_gtxwizard_i/gtxe1_i/TXUSRCLK2 Location pin: GTXE1_X0Y10.TXUSRCLK2 Clock network: eth/sgmii/tx_mac_aclk_int -------------------------------------------------------------------------------- Slack: 5.778ns (period - min period limit) Period: 8.000ns Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) Physical resource: ipbus/udp_if/ipbus_rx_ram/Mram_ram11/CLKARDCLKL Logical resource: ipbus/udp_if/ipbus_rx_ram/Mram_ram11/CLKARDCLKL Location pin: RAMB36_X3Y10.CLKARDCLKL Clock network: eth/sgmii/tx_mac_aclk_int -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_gtpclk = PERIOD TIMEGRP "gtpclk" 8 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 705 paths analyzed, 206 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 4.000ns. -------------------------------------------------------------------------------- Paths for end point eth/sgmii/v6_gtxwizard_top_inst/reset_r_0 (SLICE_X96Y101.SR), 1 path -------------------------------------------------------------------------------- Slack (setup path): 4.080ns (requirement - (data path - clock path skew + uncertainty)) Source: clocks/rst_eth (FF) Destination: eth/sgmii/v6_gtxwizard_top_inst/reset_r_0 (FF) Requirement: 8.000ns Data Path Delay: 2.802ns (Levels of Logic = 0) Clock Path Skew: -1.083ns (3.842 - 4.925) Source Clock: clk125_fr rising at 0.000ns Destination Clock: eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: clocks/rst_eth to eth/sgmii/v6_gtxwizard_top_inst/reset_r_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X71Y82.AQ Tcko 0.337 clocks/rst_eth clocks/rst_eth SLICE_X96Y101.SR net (fanout=2) 2.094 clocks/rst_eth SLICE_X96Y101.CLK Trck 0.371 eth/sgmii/v6_gtxwizard_top_inst/reset_r<3> eth/sgmii/v6_gtxwizard_top_inst/reset_r_0 ------------------------------------------------- --------------------------- Total 2.802ns (0.708ns logic, 2.094ns route) (25.3% logic, 74.7% route) -------------------------------------------------------------------------------- Paths for end point eth/sgmii/v6_gtxwizard_top_inst/reset_r_1 (SLICE_X96Y101.SR), 1 path -------------------------------------------------------------------------------- Slack (setup path): 4.080ns (requirement - (data path - clock path skew + uncertainty)) Source: clocks/rst_eth (FF) Destination: eth/sgmii/v6_gtxwizard_top_inst/reset_r_1 (FF) Requirement: 8.000ns Data Path Delay: 2.802ns (Levels of Logic = 0) Clock Path Skew: -1.083ns (3.842 - 4.925) Source Clock: clk125_fr rising at 0.000ns Destination Clock: eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: clocks/rst_eth to eth/sgmii/v6_gtxwizard_top_inst/reset_r_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X71Y82.AQ Tcko 0.337 clocks/rst_eth clocks/rst_eth SLICE_X96Y101.SR net (fanout=2) 2.094 clocks/rst_eth SLICE_X96Y101.CLK Trck 0.371 eth/sgmii/v6_gtxwizard_top_inst/reset_r<3> eth/sgmii/v6_gtxwizard_top_inst/reset_r_1 ------------------------------------------------- --------------------------- Total 2.802ns (0.708ns logic, 2.094ns route) (25.3% logic, 74.7% route) -------------------------------------------------------------------------------- Paths for end point eth/sgmii/v6_gtxwizard_top_inst/reset_r_2 (SLICE_X96Y101.SR), 1 path -------------------------------------------------------------------------------- Slack (setup path): 4.080ns (requirement - (data path - clock path skew + uncertainty)) Source: clocks/rst_eth (FF) Destination: eth/sgmii/v6_gtxwizard_top_inst/reset_r_2 (FF) Requirement: 8.000ns Data Path Delay: 2.802ns (Levels of Logic = 0) Clock Path Skew: -1.083ns (3.842 - 4.925) Source Clock: clk125_fr rising at 0.000ns Destination Clock: eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i rising at 8.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: clocks/rst_eth to eth/sgmii/v6_gtxwizard_top_inst/reset_r_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X71Y82.AQ Tcko 0.337 clocks/rst_eth clocks/rst_eth SLICE_X96Y101.SR net (fanout=2) 2.094 clocks/rst_eth SLICE_X96Y101.CLK Trck 0.371 eth/sgmii/v6_gtxwizard_top_inst/reset_r<3> eth/sgmii/v6_gtxwizard_top_inst/reset_r_2 ------------------------------------------------- --------------------------- Total 2.802ns (0.708ns logic, 2.094ns route) (25.3% logic, 74.7% route) -------------------------------------------------------------------------------- Hold Paths: TS_gtpclk = PERIOD TIMEGRP "gtpclk" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done (SLICE_X95Y105.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.110ns (requirement - (clock path skew + uncertainty - data path)) Source: eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done (FF) Destination: eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done (FF) Requirement: 0.000ns Data Path Delay: 0.110ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i rising at 8.000ns Destination Clock: eth/sgmii/v6_gtxwizard_top_inst/clk_ds_i rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done to eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X95Y105.AQ Tcko 0.098 eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done SLICE_X95Y105.A5 net (fanout=2) 0.067 eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done SLICE_X95Y105.CLK Tah (-Th) 0.055 eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done_rstpot1 eth/sgmii/v6_gtxwizard_top_inst/v6_gtxwizard_inst/gtx0_double_reset_i/reset_dly_done ------------------------------------------------- --------------------------- Total 0.110ns (0.043ns logic, 0.067ns route) (39.1% logic, 60.9% route) -------------------------------------------------------------------------------- Paths for end point clocks/clkdiv/cnt_0 (SLICE_X20Y64.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.143ns (requirement - (clock path skew + uncertainty - data path)) Source: clocks/clkdiv/cnt_0 (FF) Destination: clocks/clkdiv/cnt_0 (FF) Requirement: 0.000ns Data Path Delay: 0.143ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: clk125_fr rising at 8.000ns Destination Clock: clk125_fr rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: clocks/clkdiv/cnt_0 to clocks/clkdiv/cnt_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X20Y64.AQ Tcko 0.115 clocks/clkdiv/cnt<3> clocks/clkdiv/cnt_0 SLICE_X20Y64.A5 net (fanout=1) 0.067 clocks/clkdiv/cnt<0> SLICE_X20Y64.CLK Tah (-Th) 0.039 clocks/clkdiv/cnt<3> clocks/clkdiv/Mcount_cnt_lut<0>_INV_0 clocks/clkdiv/Mcount_cnt_cy<3> clocks/clkdiv/cnt_0 ------------------------------------------------- --------------------------- Total 0.143ns (0.076ns logic, 0.067ns route) (53.1% logic, 46.9% route) -------------------------------------------------------------------------------- Paths for end point clocks/clkdiv/cnt_4 (SLICE_X20Y65.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.143ns (requirement - (clock path skew + uncertainty - data path)) Source: clocks/clkdiv/cnt_4 (FF) Destination: clocks/clkdiv/cnt_4 (FF) Requirement: 0.000ns Data Path Delay: 0.143ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: clk125_fr rising at 8.000ns Destination Clock: clk125_fr rising at 8.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: clocks/clkdiv/cnt_4 to clocks/clkdiv/cnt_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X20Y65.AQ Tcko 0.115 clocks/clkdiv/cnt<7> clocks/clkdiv/cnt_4 SLICE_X20Y65.A5 net (fanout=1) 0.067 clocks/clkdiv/cnt<4> SLICE_X20Y65.CLK Tah (-Th) 0.039 clocks/clkdiv/cnt<7> clocks/clkdiv/cnt<4>_rt clocks/clkdiv/Mcount_cnt_cy<7> clocks/clkdiv/cnt_4 ------------------------------------------------- --------------------------- Total 0.143ns (0.076ns logic, 0.067ns route) (53.1% logic, 46.9% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_gtpclk = PERIOD TIMEGRP "gtpclk" 8 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 4.000ns (period - (min low pulse limit / (low pulse / period))) Period: 8.000ns Low pulse: 4.000ns Low pulse limit: 2.000ns (Tdcmpw_CLKIN_100_150) Physical resource: clocks/mmcm/CLKIN1 Logical resource: clocks/mmcm/CLKIN1 Location pin: MMCM_ADV_X0Y0.CLKIN1 Clock network: clk125_fr -------------------------------------------------------------------------------- Slack: 4.000ns (period - (min high pulse limit / (high pulse / period))) Period: 8.000ns High pulse: 4.000ns High pulse limit: 2.000ns (Tdcmpw_CLKIN_100_150) Physical resource: clocks/mmcm/CLKIN1 Logical resource: clocks/mmcm/CLKIN1 Location pin: MMCM_ADV_X0Y0.CLKIN1 Clock network: clk125_fr -------------------------------------------------------------------------------- Slack: 4.668ns (period - min period limit) Period: 8.000ns Min period limit: 3.332ns (300.120MHz) (Tbrper_I) Physical resource: eth/sgmii/v6_gtxwizard_top_inst/bufr_clk_ds/I Logical resource: eth/sgmii/v6_gtxwizard_top_inst/bufr_clk_ds/I Location pin: BUFR_X2Y6.I Clock network: eth/clkin -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_clocks_clk_ipb_i = PERIOD TIMEGRP "clocks_clk_ipb_i" TS_gtpclk / 0.25 HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 23084 paths analyzed, 3007 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 10.533ns. -------------------------------------------------------------------------------- Paths for end point ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAMB36_X2Y21.WEAU2), 27 paths -------------------------------------------------------------------------------- Slack (setup path): 21.467ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/state_FSM_FFd3 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 10.315ns (Levels of Logic = 6) Clock Path Skew: -0.133ns (1.492 - 1.625) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/state_FSM_FFd3 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X56Y70.AQ Tcko 0.381 ipbus/trans/sm/state_FSM_FFd3 ipbus/trans/sm/state_FSM_FFd3 SLICE_X41Y68.C1 net (fanout=66) 1.493 ipbus/trans/sm/state_FSM_FFd3 SLICE_X41Y68.CMUX Tilo 0.191 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAU2 net (fanout=64) 3.440 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKU Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 10.315ns (1.540ns logic, 8.775ns route) (14.9% logic, 85.1% route) -------------------------------------------------------------------------------- Slack (setup path): 21.903ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/hdr_6 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 9.882ns (Levels of Logic = 6) Clock Path Skew: -0.130ns (1.492 - 1.622) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/hdr_6 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X48Y67.CQ Tcko 0.337 ipbus/trans/sm/hdr<7> ipbus/trans/sm/hdr_6 SLICE_X41Y68.C2 net (fanout=13) 1.104 ipbus/trans/sm/hdr<6> SLICE_X41Y68.CMUX Tilo 0.191 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAU2 net (fanout=64) 3.440 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKU Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 9.882ns (1.496ns logic, 8.386ns route) (15.1% logic, 84.9% route) -------------------------------------------------------------------------------- Slack (setup path): 22.247ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/hdr_5 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 9.538ns (Levels of Logic = 6) Clock Path Skew: -0.130ns (1.492 - 1.622) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/hdr_5 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X48Y67.BQ Tcko 0.337 ipbus/trans/sm/hdr<7> ipbus/trans/sm/hdr_5 SLICE_X41Y68.C3 net (fanout=13) 0.772 ipbus/trans/sm/hdr<5> SLICE_X41Y68.CMUX Tilo 0.179 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAU2 net (fanout=64) 3.440 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKU Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 9.538ns (1.484ns logic, 8.054ns route) (15.6% logic, 84.4% route) -------------------------------------------------------------------------------- Paths for end point ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAMB36_X2Y21.WEAU3), 27 paths -------------------------------------------------------------------------------- Slack (setup path): 21.467ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/state_FSM_FFd3 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 10.315ns (Levels of Logic = 6) Clock Path Skew: -0.133ns (1.492 - 1.625) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/state_FSM_FFd3 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X56Y70.AQ Tcko 0.381 ipbus/trans/sm/state_FSM_FFd3 ipbus/trans/sm/state_FSM_FFd3 SLICE_X41Y68.C1 net (fanout=66) 1.493 ipbus/trans/sm/state_FSM_FFd3 SLICE_X41Y68.CMUX Tilo 0.191 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAU3 net (fanout=64) 3.440 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKU Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 10.315ns (1.540ns logic, 8.775ns route) (14.9% logic, 85.1% route) -------------------------------------------------------------------------------- Slack (setup path): 21.903ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/hdr_6 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 9.882ns (Levels of Logic = 6) Clock Path Skew: -0.130ns (1.492 - 1.622) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/hdr_6 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X48Y67.CQ Tcko 0.337 ipbus/trans/sm/hdr<7> ipbus/trans/sm/hdr_6 SLICE_X41Y68.C2 net (fanout=13) 1.104 ipbus/trans/sm/hdr<6> SLICE_X41Y68.CMUX Tilo 0.191 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAU3 net (fanout=64) 3.440 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKU Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 9.882ns (1.496ns logic, 8.386ns route) (15.1% logic, 84.9% route) -------------------------------------------------------------------------------- Slack (setup path): 22.247ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/hdr_5 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 9.538ns (Levels of Logic = 6) Clock Path Skew: -0.130ns (1.492 - 1.622) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/hdr_5 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X48Y67.BQ Tcko 0.337 ipbus/trans/sm/hdr<7> ipbus/trans/sm/hdr_5 SLICE_X41Y68.C3 net (fanout=13) 0.772 ipbus/trans/sm/hdr<5> SLICE_X41Y68.CMUX Tilo 0.179 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAU3 net (fanout=64) 3.440 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKU Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 9.538ns (1.484ns logic, 8.054ns route) (15.6% logic, 84.4% route) -------------------------------------------------------------------------------- Paths for end point ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAMB36_X2Y21.WEAL2), 27 paths -------------------------------------------------------------------------------- Slack (setup path): 21.471ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/state_FSM_FFd3 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 10.311ns (Levels of Logic = 6) Clock Path Skew: -0.133ns (1.492 - 1.625) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/state_FSM_FFd3 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X56Y70.AQ Tcko 0.381 ipbus/trans/sm/state_FSM_FFd3 ipbus/trans/sm/state_FSM_FFd3 SLICE_X41Y68.C1 net (fanout=66) 1.493 ipbus/trans/sm/state_FSM_FFd3 SLICE_X41Y68.CMUX Tilo 0.191 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAL2 net (fanout=64) 3.436 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKL Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 10.311ns (1.540ns logic, 8.771ns route) (14.9% logic, 85.1% route) -------------------------------------------------------------------------------- Slack (setup path): 21.907ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/hdr_6 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 9.878ns (Levels of Logic = 6) Clock Path Skew: -0.130ns (1.492 - 1.622) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/hdr_6 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X48Y67.CQ Tcko 0.337 ipbus/trans/sm/hdr<7> ipbus/trans/sm/hdr_6 SLICE_X41Y68.C2 net (fanout=13) 1.104 ipbus/trans/sm/hdr<6> SLICE_X41Y68.CMUX Tilo 0.191 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAL2 net (fanout=64) 3.436 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKL Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 9.878ns (1.496ns logic, 8.382ns route) (15.1% logic, 84.9% route) -------------------------------------------------------------------------------- Slack (setup path): 22.251ns (requirement - (data path - clock path skew + uncertainty)) Source: ipbus/trans/sm/hdr_5 (FF) Destination: ipbus/udp_if/ipbus_tx_ram/Mram_ram5 (RAM) Requirement: 32.000ns Data Path Delay: 9.534ns (Levels of Logic = 6) Clock Path Skew: -0.130ns (1.492 - 1.622) Source Clock: ipb_clk rising at 0.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.085ns Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.154ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: ipbus/trans/sm/hdr_5 to ipbus/udp_if/ipbus_tx_ram/Mram_ram5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- SLICE_X48Y67.BQ Tcko 0.337 ipbus/trans/sm/hdr<7> ipbus/trans/sm/hdr_5 SLICE_X41Y68.C3 net (fanout=13) 0.772 ipbus/trans/sm/hdr<5> SLICE_X41Y68.CMUX Tilo 0.179 slaves/slave0/reg_0<19> ipbus/trans/sm/strobe1 SLICE_X44Y68.D5 net (fanout=9) 0.360 ipb_master_out_ipb_strobe SLICE_X44Y68.D Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/Mmux_ipb_to_slaves[5]_ipb_strobe11 SLICE_X44Y68.C2 net (fanout=2) 0.475 slaves/ipbw[5]_ipb_strobe SLICE_X44Y68.C Tilo 0.068 slaves/slave1/ipbus_out_ipb_rdata<11> slaves/fabric/ored_ack<0>1 SLICE_X49Y71.D3 net (fanout=9) 0.730 ipb_master_in_ipb_ack SLICE_X49Y71.DMUX Tilo 0.181 ipbus/trans/sm/rmw_input<17> ipbus/trans/sm/tx_we1 SLICE_X57Y84.C2 net (fanout=2) 1.679 ipbus/trans/sm/tx_we SLICE_X57Y84.C Tilo 0.068 ipbus/trans/sm/rmw_write ipbus/trans/sm/tx_we2 SLICE_X59Y83.C3 net (fanout=11) 0.598 ipbus/trans/tx_we SLICE_X59Y83.C Tilo 0.068 ipbus/udp_if/clock_crossing_if/we_buf<1> ipbus/trans/iface/trans_out_we1 RAMB36_X2Y21.WEAL2 net (fanout=64) 3.436 ipbus/trans_out_we RAMB36_X2Y21.CLKARDCLKL Trcck_WEA 0.515 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ipbus/udp_if/ipbus_tx_ram/Mram_ram5 ---------------------------------------------------- --------------------------- Total 9.534ns (1.484ns logic, 8.050ns route) (15.6% logic, 84.4% route) -------------------------------------------------------------------------------- Hold Paths: TS_clocks_clk_ipb_i = PERIOD TIMEGRP "clocks_clk_ipb_i" TS_gtpclk / 0.25 HIGH 50%; -------------------------------------------------------------------------------- Paths for end point slaves/slave1/ipbus_out_ipb_rdata_1 (SLICE_X43Y65.BX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.061ns (requirement - (clock path skew + uncertainty - data path)) Source: slaves/slave1/reg_0_1 (FF) Destination: slaves/slave1/ipbus_out_ipb_rdata_1 (FF) Requirement: 0.000ns Data Path Delay: 0.094ns (Levels of Logic = 0) Clock Path Skew: 0.033ns (0.466 - 0.433) Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: slaves/slave1/reg_0_1 to slaves/slave1/ipbus_out_ipb_rdata_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X45Y65.BQ Tcko 0.098 slaves/slave1/reg_0<3> slaves/slave1/reg_0_1 SLICE_X43Y65.BX net (fanout=1) 0.098 slaves/slave1/reg_0<1> SLICE_X43Y65.CLK Tckdi (-Th) 0.102 slaves/slave3/ipbus_out_ipb_rdata<3> slaves/slave1/ipbus_out_ipb_rdata_1 ------------------------------------------------- --------------------------- Total 0.094ns (-0.004ns logic, 0.098ns route) (-4.3% logic, 104.3% route) -------------------------------------------------------------------------------- Paths for end point slaves/slave1/ipbus_out_ipb_rdata_3 (SLICE_X43Y65.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.061ns (requirement - (clock path skew + uncertainty - data path)) Source: slaves/slave1/reg_0_3 (FF) Destination: slaves/slave1/ipbus_out_ipb_rdata_3 (FF) Requirement: 0.000ns Data Path Delay: 0.094ns (Levels of Logic = 0) Clock Path Skew: 0.033ns (0.466 - 0.433) Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: slaves/slave1/reg_0_3 to slaves/slave1/ipbus_out_ipb_rdata_3 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X45Y65.DQ Tcko 0.098 slaves/slave1/reg_0<3> slaves/slave1/reg_0_3 SLICE_X43Y65.DX net (fanout=1) 0.098 slaves/slave1/reg_0<3> SLICE_X43Y65.CLK Tckdi (-Th) 0.102 slaves/slave3/ipbus_out_ipb_rdata<3> slaves/slave1/ipbus_out_ipb_rdata_3 ------------------------------------------------- --------------------------- Total 0.094ns (-0.004ns logic, 0.098ns route) (-4.3% logic, 104.3% route) -------------------------------------------------------------------------------- Paths for end point slaves/slave1/ipbus_out_ipb_rdata_26 (SLICE_X42Y68.CX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.062ns (requirement - (clock path skew + uncertainty - data path)) Source: slaves/slave1/reg_0_26 (FF) Destination: slaves/slave1/ipbus_out_ipb_rdata_26 (FF) Requirement: 0.000ns Data Path Delay: 0.097ns (Levels of Logic = 0) Clock Path Skew: 0.035ns (0.470 - 0.435) Source Clock: ipb_clk rising at 32.000ns Destination Clock: ipb_clk rising at 32.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: slaves/slave1/reg_0_26 to slaves/slave1/ipbus_out_ipb_rdata_26 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y68.CQ Tcko 0.098 slaves/slave1/reg_0<27> slaves/slave1/reg_0_26 SLICE_X42Y68.CX net (fanout=1) 0.101 slaves/slave1/reg_0<26> SLICE_X42Y68.CLK Tckdi (-Th) 0.102 slaves/slave3/ipbus_out_ipb_rdata<19> slaves/slave1/ipbus_out_ipb_rdata_26 ------------------------------------------------- --------------------------- Total 0.097ns (-0.004ns logic, 0.101ns route) (-4.1% logic, 104.1% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_clocks_clk_ipb_i = PERIOD TIMEGRP "clocks_clk_ipb_i" TS_gtpclk / 0.25 HIGH 50%; -------------------------------------------------------------------------------- Slack: 29.778ns (period - min period limit) Period: 32.000ns Min period limit: 2.222ns (450.045MHz) (Trper_CLKA) Physical resource: slaves/slave2/Mram_reg/CLKARDCLKL Logical resource: slaves/slave2/Mram_reg/CLKARDCLKL Location pin: RAMB36_X2Y14.CLKARDCLKL Clock network: ipb_clk -------------------------------------------------------------------------------- Slack: 29.778ns (period - min period limit) Period: 32.000ns Min period limit: 2.222ns (450.045MHz) (Trper_CLKB) Physical resource: ipbus/udp_if/ipbus_rx_ram/Mram_ram11/CLKBWRCLKL Logical resource: ipbus/udp_if/ipbus_rx_ram/Mram_ram11/CLKBWRCLKL Location pin: RAMB36_X3Y10.CLKBWRCLKL Clock network: ipb_clk -------------------------------------------------------------------------------- Slack: 29.778ns (period - min period limit) Period: 32.000ns Min period limit: 2.222ns (450.045MHz) (Trper_CLKB) Physical resource: ipbus/udp_if/ipbus_rx_ram/Mram_ram12/CLKBWRCLKL Logical resource: ipbus/udp_if/ipbus_rx_ram/Mram_ram12/CLKBWRCLKL Location pin: RAMB36_X2Y12.CLKBWRCLKL Clock network: ipb_clk -------------------------------------------------------------------------------- Derived Constraint Report Derived Constraints for TS_gtpclk +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_gtpclk | 8.000ns| 4.000ns| 2.633ns| 0| 0| 705| 23084| | TS_clocks_clk_ipb_i | 32.000ns| 10.533ns| N/A| 0| 0| 23084| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock sgmii_clkn ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ sgmii_clkn | 10.533| | | | sgmii_clkp | 10.533| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock sgmii_clkp ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ sgmii_clkn | 10.533| | | | sgmii_clkp | 10.533| | | | ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) Constraints cover 64281 paths, 0 nets, and 17515 connections Design statistics: Minimum period: 10.533ns{1} (Maximum frequency: 94.940MHz) ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. Analysis completed Wed Jan 8 15:03:01 2014 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 740 MB