//------------------------------------------------------------------------------
// Project    : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
// File       : v6_emac_v2_3_sgmii_mod.v
// Version    : 2.3
//-----------------------------------------------------------------------------
//
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// Description:  This is the Verilog module instantiation for the Virtex-6
//               Embedded Tri-Mode Ethernet MAC.
//
// ------------------------------------------------------------------------------

   module  v6_emac_v2_3_sgmii
   (

      //-------------------------------------------------------------------------
      // Clock signals - used in rgmii and serial modes
      //-------------------------------------------------------------------------
      input             gtx_clk,
      output            tx_axi_clk_out, // only in rgmii or sgmii

      //-------------------------------------------------------------------------
      // Receiver Interface.
      //-------------------------------------------------------------------------
      input             rx_axi_clk,
      output            rx_reset_out,
      output   [7:0]    rx_axis_mac_tdata,
      output            rx_axis_mac_tvalid,
      output            rx_axis_mac_tlast,
      output            rx_axis_mac_tuser,

      // RX sideband signals
      output   [27:0]   rx_statistics_vector,
      output            rx_statistics_valid,

      //-------------------------------------------------------------------------
      // Transmitter Interface
      //-------------------------------------------------------------------------
      input             tx_axi_clk,
      output            tx_reset_out,
      input    [7:0]    tx_axis_mac_tdata,
      input             tx_axis_mac_tvalid,
      input             tx_axis_mac_tlast,
      input             tx_axis_mac_tuser,
      output            tx_axis_mac_tready,

      // TX sideband signals
      output            tx_retransmit,
      output            tx_collision,
      input    [7:0]    tx_ifg_delay,
      output   [31:0]   tx_statistics_vector,
      output            tx_statistics_valid,

      //-------------------------------------------------------------------------
      // Flow Control
      //-------------------------------------------------------------------------
      input             pause_req,
      input    [15:0]   pause_val,

      //-------------------------------------------------------------------------
      // Speed interface
      //-------------------------------------------------------------------------
      output            speed_is_10_100,

      //-------------------------------------------------------------------------
      // GMII/MII Interface
      //-------------------------------------------------------------------------
      output   [7:0]    gmii_txd,
      input    [7:0]    gmii_rxd,
      input             gmii_rx_dv,

      //-------------------------------------------------------------------------
      // SGMII interface
      //-------------------------------------------------------------------------
      input             dcm_locked,
      output            an_interrupt,
      input             signal_det,
      input    [4:0]    phy_ad,
      output            en_comma_align,
      output            loopback_msb,
      output            mgt_rx_reset,
      output            mgt_tx_reset,
      output            powerdown,
      output            sync_acq_status,
      input    [2:0]    rx_clk_cor_cnt,
      input             rx_buf_status,
      input             rx_char_is_comma,
      input             rx_char_is_k,
      input             rx_disp_err,
      input             rx_not_in_table,
      input             rx_run_disp,
      input             tx_buf_err,
      output            tx_char_disp_mode,
      output            tx_char_disp_val,
      output            tx_char_is_k,

      //-------------------------------------------------------------------------
      // MDIO Interface
      //-------------------------------------------------------------------------
      input             mdc_in,
      input             mdio_in,
      output            mdio_out,
      output            mdio_tri,



      //-------------------------------------------------------------------------
      // Resets
      //-------------------------------------------------------------------------

      input             glbl_rstn,
      input             rx_axi_rstn,
      input             tx_axi_rstn

   );

endmodule