//------------------------------------------------------------------------------ // Project : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC // File : v6_emac_v2_3_sgmii_fifo_block.v // Version : 2.3 //----------------------------------------------------------------------------- // // (c) Copyright 2004-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // Description: This is the FIFO Block level vhdl wrapper for the Virtex-6 // Embedded Tri-Mode Ethernet MAC. This wrapper enhances the // standard MAC core with an example FIFO. The interface to // this FIFO is designed to the AXI-S specification. // Please refer to core documentation for // additional FIFO and AXI-S information. // // _________________________________________________________ // | | // | FIFO BLOCK LEVEL WRAPPER | // | | // | _____________________ ______________________ | // | | _________________ | | | | // | | | | | | | | // -------->| | TX AXI FIFO | |---->| Tx Tx |---------> // | | | | | | AXI-S PHY | | // | | |_________________| | | I/F I/F | | // | | | | | | // AXI | | 10/100/1G | | V6 EMAC CORE | | // Stream | | ETHERNET FIFO | | BLOCK WRAPPER | | PHY I/F // | | | | | | // | | _________________ | | | | // | | | | | | | | // <--------| | RX AXI FIFO | |<----| Rx Rx |<--------- // | | | | | | AXI-S PHY | | // | | |_________________| | | I/F I/F | | // | |_____________________| |______________________| | // | | // |_________________________________________________________| // `timescale 1 ps/1 ps //------------------------------------------------------------------------------ // The module declaration for the FIFO Block level wrapper. //------------------------------------------------------------------------------ module v6_emac_v2_3_sgmii_fifo_block ( input gtx_clk, output clk125_out, // Receiver Statistics Interface //--------------------------------------- output rx_reset, output [27:0] rx_statistics_vector, output rx_statistics_valid, // Receiver (AXI-S) Interface //---------------------------------------- input rx_fifo_clock, input rx_fifo_resetn, output [7:0] rx_axis_fifo_tdata, output rx_axis_fifo_tvalid, input rx_axis_fifo_tready, output rx_axis_fifo_tlast, // Transmitter Statistics Interface //------------------------------------------ output tx_reset, input [7:0] tx_ifg_delay, output [31:0] tx_statistics_vector, output tx_statistics_valid, // Transmitter (AXI-S) Interface //------------------------------------------- input tx_fifo_clock, input tx_fifo_resetn, input [7:0] tx_axis_fifo_tdata, input tx_axis_fifo_tvalid, output tx_axis_fifo_tready, input tx_axis_fifo_tlast, // MAC Control Interface //------------------------ input pause_req, input [15:0] pause_val, // SGMII interface output txp, output txn, input rxp, input rxn, input [4:0] phyad, output resetdone, output syncacqstatus, // SGMII transceiver clock buffer input input clk_ds, // MDIO Interface //--------------- input mdio_i, output mdio_o, output mdio_t, input mdc_in, // asynchronous reset //--------------- input glbl_rstn, input rx_axi_rstn, input tx_axi_rstn ); //---------------------------------------------------------------------------- // Internal signals used in this fifo block level wrapper. //---------------------------------------------------------------------------- // Note: KEEP attributes preserve signal names so they can be displayed in // simulator wave windows wire mac_aclk_int; // MAC user clock wire rx_reset_int; // MAC Rx reset wire tx_reset_int; // MAC Tx reset // MAC receiver client I/F (* KEEP = "TRUE" *) wire [7:0] rx_axis_mac_tdata; (* KEEP = "TRUE" *) wire rx_axis_mac_tvalid; (* KEEP = "TRUE" *) wire rx_axis_mac_tlast; (* KEEP = "TRUE" *) wire rx_axis_mac_tuser; // MAC transmitter client I/F (* KEEP = "TRUE" *) wire [7:0] tx_axis_mac_tdata; (* KEEP = "TRUE" *) wire tx_axis_mac_tvalid; (* KEEP = "TRUE" *) wire tx_axis_mac_tready; (* KEEP = "TRUE" *) wire tx_axis_mac_tlast; (* KEEP = "TRUE" *) wire tx_axis_mac_tuser; wire tx_collision; wire tx_retransmit; //---------------------------------------------------------------------------- // Connect the output clock signals //---------------------------------------------------------------------------- assign rx_reset = rx_reset_int; assign tx_reset = tx_reset_int; //---------------------------------------------------------------------------- // Instantiate the V6 Hard EMAC Block wrapper //---------------------------------------------------------------------------- v6_emac_v2_3_sgmii_block v6emac_block ( .gtx_clk (gtx_clk), .clk125_out (clk125_out), // Receiver Interface //-------------------------- .rx_statistics_vector (rx_statistics_vector), .rx_statistics_valid (rx_statistics_valid), .user_mac_aclk (mac_aclk_int), .rx_reset (rx_reset_int), .rx_axis_mac_tdata (rx_axis_mac_tdata), .rx_axis_mac_tvalid (rx_axis_mac_tvalid), .rx_axis_mac_tlast (rx_axis_mac_tlast), .rx_axis_mac_tuser (rx_axis_mac_tuser), // Transmitter Interface //----------------------------- .tx_ifg_delay (tx_ifg_delay), .tx_statistics_vector (tx_statistics_vector), .tx_statistics_valid (tx_statistics_valid), .tx_reset (tx_reset_int), .tx_axis_mac_tdata (tx_axis_mac_tdata), .tx_axis_mac_tvalid (tx_axis_mac_tvalid), .tx_axis_mac_tlast (tx_axis_mac_tlast), .tx_axis_mac_tuser (tx_axis_mac_tuser), .tx_axis_mac_tready (tx_axis_mac_tready), .tx_collision (tx_collision), .tx_retransmit (tx_retransmit), // MAC Control Interface //---------------------- .pause_req (pause_req), .pause_val (pause_val), // SGMII interface .txp (txp), .txn (txn), .rxp (rxp), .rxn (rxn), .phyad (phyad), .resetdone (resetdone), .syncacqstatus (syncacqstatus), // SGMII transceiver clock buffer input .clk_ds (clk_ds), // MDIO Interface //--------------- // MDIO Interface .mdio_i (mdio_i), .mdio_o (mdio_o), .mdio_t (mdio_t), .mdc_in (mdc_in), .glbl_rstn (glbl_rstn), .rx_axi_rstn (rx_axi_rstn), .tx_axi_rstn (tx_axi_rstn) ); //---------------------------------------------------------------------------- // Instantiate the user side FIFO //---------------------------------------------------------------------------- // create inverted mac resets as the FIFO expects AXI compliant resets assign tx_mac_resetn = !tx_reset_int; assign rx_mac_resetn = !rx_reset_int; ten_100_1g_eth_fifo # ( .FULL_DUPLEX_ONLY (1) ) user_side_FIFO ( // Transmit FIFO MAC TX Interface .tx_fifo_aclk (tx_fifo_clock), .tx_fifo_resetn (tx_fifo_resetn), .tx_axis_fifo_tdata (tx_axis_fifo_tdata), .tx_axis_fifo_tvalid (tx_axis_fifo_tvalid), .tx_axis_fifo_tlast (tx_axis_fifo_tlast), .tx_axis_fifo_tready (tx_axis_fifo_tready), .tx_mac_aclk (mac_aclk_int), .tx_mac_resetn (tx_mac_resetn), .tx_axis_mac_tdata (tx_axis_mac_tdata), .tx_axis_mac_tvalid (tx_axis_mac_tvalid), .tx_axis_mac_tlast (tx_axis_mac_tlast), .tx_axis_mac_tready (tx_axis_mac_tready), .tx_axis_mac_tuser (tx_axis_mac_tuser), .tx_fifo_overflow (), .tx_fifo_status (), .tx_collision (tx_collision), .tx_retransmit (tx_retransmit), .rx_fifo_aclk (rx_fifo_clock), .rx_fifo_resetn (rx_fifo_resetn), .rx_axis_fifo_tdata (rx_axis_fifo_tdata), .rx_axis_fifo_tvalid (rx_axis_fifo_tvalid), .rx_axis_fifo_tlast (rx_axis_fifo_tlast), .rx_axis_fifo_tready (rx_axis_fifo_tready), .rx_mac_aclk (mac_aclk_int), .rx_mac_resetn (rx_mac_resetn), .rx_axis_mac_tdata (rx_axis_mac_tdata), .rx_axis_mac_tvalid (rx_axis_mac_tvalid), .rx_axis_mac_tlast (rx_axis_mac_tlast), .rx_axis_mac_tready (), // not used as MAC cannot throttle .rx_axis_mac_tuser (rx_axis_mac_tuser), .rx_fifo_status (), .rx_fifo_overflow () ); endmodule