##----------------------------------------------------------------------------- ## Title : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC Example ## Constraints File ## Project : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC ## File : v6_emac_v2_3_sgmii_example_design.ucf ## Version : 2.3 ##----------------------------------------------------------------------------- ## ## (c) Copyright 2011 Xilinx, Inc. All rights reserved. ## ## This file contains confidential and proprietary information ## of Xilinx, Inc. and is protected under U.S. and ## international copyright and other intellectual property ## laws. ## ## DISCLAIMER ## This disclaimer is not a license and does not grant any ## rights to the materials distributed herewith. Except as ## otherwise provided in a valid license issued to you by ## Xilinx, and to the maximum extent permitted by applicable ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and ## (2) Xilinx shall not be liable (whether in contract or tort, ## including negligence, or under any other theory of ## liability) for any loss or damage of any kind or nature ## related to, arising under or in connection with these ## materials, including for any direct, or any indirect, ## special, incidental, or consequential loss or damage ## (including loss of data, profits, goodwill, or any type of ## loss or damage suffered as a result of any action brought ## by a third party) even if such damage or loss was ## reasonably foreseeable or Xilinx had been advised of the ## possibility of the same. ## ## CRITICAL APPLICATIONS ## Xilinx products are not designed or intended to be fail- ## safe, or for use in any application requiring fail-safe ## performance, such as life-support or safety devices or ## systems, Class III medical devices, nuclear facilities, ## applications related to the deployment of airbags, or any ## other applications that could lead to death, personal ## injury, or severe property or environmental damage ## (individually and collectively, "Critical ## Applications"). Customer assumes the sole risk and ## liability of any use of Xilinx products in Critical ## Applications, subject only to applicable laws and ## regulations governing limitations on product liability. ## ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS ## PART OF THIS FILE AT ALL TIMES. ## ##----------------------------------------------------------------------------- ## Description: This is an example constraints file for the Virtex-6 Embedded ## Tri-Mode Ethernet MAC. It is designed to apply to the ## example design hierarchical level. In general, the constraints ## in this file are necessary to implement a correctly- ## functioning Ethernet MAC, and some constraints must be ## modified according to your specific design and pinout choices. ##----------------------------------------------------------------------------- # The xc6vlx240tff1156-1 part is chosen for this example design. # this is the chosen device on the ML605 demonstration platform. # This value should be modified to match your device. CONFIG PART = xc6vlx240tff1156-1; # #### ####### ########## ############# ################# ## System level constraints ########## ML605 Board ########## Net mgtclk_n LOC = H5; Net mgtclk_p LOC = H6; Net glbl_rst LOC = H10 | IOSTANDARD = LVCMOS15 | TIG; #### Module LEDs_8Bit constraints Net frame_error LOC = AH28 | IOSTANDARD = LVCMOS25; Net frame_errorn LOC = AH27 | IOSTANDARD = LVCMOS25; #### Module Push_Buttons_4Bit constraints Net update_speed LOC = G26 | IOSTANDARD = LVCMOS15; Net serial_command LOC = G17 | IOSTANDARD = LVCMOS15; Net pause_req_s LOC = A19 | IOSTANDARD = LVCMOS15; Net reset_error LOC = A18 | IOSTANDARD = LVCMOS15; #### Module DIP_Switches_4Bit constraints Net mac_speed<0> LOC = D22 | IOSTANDARD = LVCMOS15; Net mac_speed<1> LOC = C22 | IOSTANDARD = LVCMOS15; Net gen_tx_data LOC = L21 | IOSTANDARD = LVCMOS15; Net chk_tx_data LOC = L20 | IOSTANDARD = LVCMOS15; Net swap_address LOC = C18 | IOSTANDARD = LVCMOS15; Net phy_resetn LOC = AH13 | IOSTANDARD = LVCMOS25 | TIG; Net mdc_in LOC = AP14 | IOSTANDARD = LVCMOS25; Net mdio LOC = AN14 | IOSTANDARD = LVCMOS25; # lock to unused header Net tx_statistics_s LOC = AP22 | IOSTANDARD = LVCMOS25; Net rx_statistics_s LOC = AG21 | IOSTANDARD = LVCMOS25; Net syncacqstatus LOC = AG20 | IOSTANDARD = LVCMOS25; Net txp LOC = A3; Net txn LOC = A4; Net rxp LOC = B5; Net rxn LOC = B6; # #### ####### ########## ############# ################# #EXAMPLE DESIGN CONSTRAINTS ############################################################ # Clock Period Constraints # ############################################################ ############################################################################### # CLOCK CONSTRAINTS # The following constraints are required. If you choose to not use the example # design level of wrapper hierarchy, the net names should be translated to # match your design. ############################################################################### NET "clk_ds" TNM_NET = "mgt_clk"; TIMESPEC "TS_v6_emac_v2_3_sgmii_mgt_clk" = PERIOD "mgt_clk" 8.000 ns HIGH 50% INPUT_JITTER 50.0ps; # Ethernet MAC reference clock driven by transceiver NET "clk125_out" TNM_NET = "clk_gt_clk"; TIMEGRP "v6_emac_v2_3_sgmii_gt_clk" = "clk_gt_clk"; TIMESPEC "TS_v6_emac_v2_3_sgmii_gt_clk" = PERIOD "v6_emac_v2_3_sgmii_gt_clk" 8 ns HIGH 50 %; # define TIGs on reset synchronizer FDPE PRE inputs PIN "*reset_sync1.PRE" TIG; PIN "*reset_sync2.PRE" TIG; # #### ####### ########## ############# ################# #FIFO BLOCK CONSTRAINTS # Group design elements around the Ethernet MAC to assist with timing # closure in this example design. These values may be modified or # removed to best suit your design. INST "*" AREA_GROUP = "AG_example_design"; AREA_GROUP "AG_example_design" RANGE = CLOCKREGION_X1Y0:CLOCKREGION_X1Y3; #INST "*user_side_FIFO?tx_fifo_i?ramgen_l?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X7Y16"; #INST "*user_side_FIFO?rx_fifo_i?ramgen_l?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X7Y17"; #INST "*user_side_FIFO?tx_fifo_i?ramgen_u?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X7Y18"; #INST "*user_side_FIFO?rx_fifo_i?ramgen_u?bram18_tdp_bl?bram18_tdp_bl" LOC = "RAMB36_X7Y19"; ############################################################################### # AXI FIFO CONSTRAINTS # The following constraints are necessary for proper operation of the AXI # FIFO. If you choose to not use the FIFO Block level of wrapper hierarchy, # these constraints should be removed. ############################################################################### # AXI FIFO transmit-side constraints # ----------------------------------------------------------------------------- # Group the clock crossing signals into timing groups INST "*user_side_FIFO?tx_fifo_i?rd_tran_frame_tog" TNM = "tx_fifo_rd_to_wr"; #INST "*user_side_FIFO?tx_fifo_i?rd_retran_frame_tog" TNM = "tx_fifo_rd_to_wr"; #INST "*user_side_FIFO?tx_fifo_i?rd_col_window_pipe_1" TNM = "tx_fifo_rd_to_wr"; INST "*user_side_FIFO?tx_fifo_i?rd_addr_txfer*" TNM = "tx_fifo_rd_to_wr"; INST "*user_side_FIFO?tx_fifo_i?rd_txfer_tog" TNM = "tx_fifo_rd_to_wr"; INST "*user_side_FIFO?tx_fifo_i?wr_frame_in_fifo" TNM = "tx_fifo_wr_to_rd"; TIMESPEC "TS_tx_fifo_rd_to_wr" = FROM "tx_fifo_rd_to_wr" TO "v6_emac_v2_3_sgmii_gt_clk" 8 ns DATAPATHONLY; TIMESPEC "TS_tx_fifo_wr_to_rd" = FROM "tx_fifo_wr_to_rd" TO "v6_emac_v2_3_sgmii_gt_clk" 8 ns DATAPATHONLY; # Reduce clock period to allow for metastability settling time INST "*user_side_FIFO?tx_fifo_i?wr_rd_addr*" TNM = "tx_metastable"; #INST "*user_side_FIFO?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable"; TIMESPEC "TS_tx_meta_protect" = FROM "tx_metastable" 5 ns DATAPATHONLY; # Transmit-side AXI FIFO address bus timing INST "*user_side_FIFO?tx_fifo_i?rd_addr_txfer*" TNM = "tx_addr_rd"; INST "*user_side_FIFO?tx_fifo_i?wr_rd_addr*" TNM = "tx_addr_wr"; TIMESPEC "TS_tx_fifo_addr" = FROM "tx_addr_rd" TO "tx_addr_wr" 10 ns; # AXI FIFO receive-side constraints # ----------------------------------------------------------------------------- # Group the clock crossing signals into timing groups INST "*user_side_FIFO?rx_fifo_i?wr_store_frame_tog" TNM = "rx_fifo_wr_to_rd"; INST "*user_side_FIFO?rx_fifo_i?rd_addr*" TNM = "rx_fifo_rd_to_wr"; TIMESPEC "TS_rx_fifo_wr_to_rd" = FROM "rx_fifo_wr_to_rd" TO "v6_emac_v2_3_sgmii_gt_clk" 8 ns DATAPATHONLY; TIMESPEC "TS_rx_fifo_rd_to_wr" = FROM "rx_fifo_rd_to_wr" TO "v6_emac_v2_3_sgmii_gt_clk" 8 ns DATAPATHONLY; # #### ####### ########## ############# ################# #BLOCK CONSTRAINTS # Locate the Tri-Mode Ethernet MAC instance INST "*v6_emac" LOC = "TEMAC_X0Y0"; ############################################################################### # PHYSICAL INTERFACE CONSTRAINTS # The following constraints are necessary for proper operation, and are tuned # for this example design. They should be modified to suit your design. ############################################################################### # SGMII physical interface constraints # ----------------------------------------------------------------------------- # Place the transceiver components, chosen for this example design. # These values should be modified according to your specific design. # Protect some RX-side registers against possible setup violations causing X # propagation in timing simulation due to asynchronous GTX reset assertion INST "*v6emac_block*gmii_rxd_int*" ASYNC_REG = TRUE; INST "*v6emac_block*rxchariscomma_r" ASYNC_REG = TRUE; INST "*v6emac_block*rxcharisk_r" ASYNC_REG = TRUE; INST "*v6emac_block*rxclkcorcnt_r*" ASYNC_REG = TRUE; INST "*v6emac_block*rxdisperr_r" ASYNC_REG = TRUE; INST "*v6emac_block*rxnotintable_r" ASYNC_REG = TRUE; INST "*v6emac_block*rxrundisp_r" ASYNC_REG = TRUE;