//------------------------------------------------------------------------------ // Project : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC // File : v6_emac_v2_3_sgmii_block.v // Version : 2.3 //----------------------------------------------------------------------------- // // (c) Copyright 2004-2011 Xilinx, Inc. All rights reserved. // // This file contains confidential and proprietary information // of Xilinx, Inc. and is protected under U.S. and // international copyright and other intellectual property // laws. // // DISCLAIMER // This disclaimer is not a license and does not grant any // rights to the materials distributed herewith. Except as // otherwise provided in a valid license issued to you by // Xilinx, and to the maximum extent permitted by applicable // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and // (2) Xilinx shall not be liable (whether in contract or tort, // including negligence, or under any other theory of // liability) for any loss or damage of any kind or nature // related to, arising under or in connection with these // materials, including for any direct, or any indirect, // special, incidental, or consequential loss or damage // (including loss of data, profits, goodwill, or any type of // loss or damage suffered as a result of any action brought // by a third party) even if such damage or loss was // reasonably foreseeable or Xilinx had been advised of the // possibility of the same. // // CRITICAL APPLICATIONS // Xilinx products are not designed or intended to be fail- // safe, or for use in any application requiring fail-safe // performance, such as life-support or safety devices or // systems, Class III medical devices, nuclear facilities, // applications related to the deployment of airbags, or any // other applications that could lead to death, personal // injury, or severe property or environmental damage // (individually and collectively, "Critical // Applications"). Customer assumes the sole risk and // liability of any use of Xilinx products in Critical // Applications, subject only to applicable laws and // regulations governing limitations on product liability. // // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS // PART OF THIS FILE AT ALL TIMES. // // Description: This is the block level Verilog design for the Virtex-6 // Embedded Tri-Mode Ethernet MAC Example Design. // // This block level: // // Please refer to the Datasheet, Getting Started Guide, and // the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for further information. // // // -----------------------------------------| // | BLOCK LEVEL WRAPPER | // | | // | --------------------- | // | | V6 EMAC | | // | | CORE | | // | | | | // --|--->| Tx Tx |-------------->| // | | AXI PHY | | // | | I/F I/F | | // | | | | // | | | | // | | | | // | | Rx Rx | | // | | AXI PHY | | // <-|----| I/F I/F |<--------------| // | | | | // | --------------------- | // | | // -----------------------------------------| // `timescale 1 ps/1 ps //------------------------------------------------------------------------------ // The entity declaration for the block level example design. //------------------------------------------------------------------------------ module v6_emac_v2_3_sgmii_block ( input gtx_clk, output clk125_out, // Receiver Interface //-------------------------- output [27:0] rx_statistics_vector, output rx_statistics_valid, output user_mac_aclk, output rx_reset, output [7:0] rx_axis_mac_tdata, output rx_axis_mac_tvalid, output rx_axis_mac_tlast, output rx_axis_mac_tuser, // Transmitter Interface //----------------------------- input [7:0] tx_ifg_delay, output [31:0] tx_statistics_vector, output tx_statistics_valid, output tx_reset, input [7:0] tx_axis_mac_tdata, input tx_axis_mac_tvalid, input tx_axis_mac_tlast, input tx_axis_mac_tuser, output tx_axis_mac_tready, output tx_collision, output tx_retransmit, // MAC Control Interface //---------------------- input pause_req, input [15:0] pause_val, // SGMII interface output txp, output txn, input rxp, input rxn, input [4:0] phyad, output resetdone, output syncacqstatus, // SGMII transceiver clock buffer input input clk_ds, // MDIO Interface //--------------- input mdio_i, output mdio_o, output mdio_t, input mdc_in, // asynchronous reset //--------------- input glbl_rstn, input rx_axi_rstn, input tx_axi_rstn ); //--------------------------------------------------------------------------- // internal signals used in this block level wrapper. //--------------------------------------------------------------------------- wire [7:0] gmii_txd_int; // Internal gmii_txd signal. reg gmii_rx_dv_int; // gmii_rx_dv registered in IOBs. (* KEEP = "TRUE" *) reg [7:0] gmii_rxd_int; // gmii_rxd registered in IOBs. // Physical interface signals wire emac_locked_i; wire plllock_i; wire [7:0] mgt_rx_data_i; wire signal_detect_i; wire rxelecidle_i; wire resetdone_i; wire encommaalign_i; wire loopback_i; wire mgt_rx_reset_i; wire mgt_tx_reset_i; wire powerdown_i; wire [2:0] rxclkcorcnt_i; wire rxchariscomma_i; wire rxcharisk_i; wire rxdisperr_i; wire rxnotintable_i; wire rxrundisp_i; wire txbuferr_i; wire txchardispmode_i; wire txchardispval_i; wire txcharisk_i; wire rxbufstatus_i; (* KEEP = "TRUE" *) reg rxchariscomma_r; (* KEEP = "TRUE" *) reg rxcharisk_r; (* KEEP = "TRUE" *) reg [2:0] rxclkcorcnt_r; (* KEEP = "TRUE" *) reg rxdisperr_r; (* KEEP = "TRUE" *) reg rxnotintable_r; (* KEEP = "TRUE" *) reg rxrundisp_r; reg txchardispmode_r; reg txchardispval_r; reg txcharisk_r; reg [7:0] mgt_tx_data_r; wire speedis10100_int; // Asserted when speed is 10Mb/s or 100Mb/s. wire tx_axi_clk_out; (* KEEP = "TRUE" *) wire rx_mac_aclk_int; // Internal receive gmii/mii clock signal. (* KEEP = "TRUE" *) wire tx_mac_aclk_int; // Internal transmit gmii/mii clock signal. wire gtx_clk_reset_int; (* ASYNC_REG = "TRUE" *) reg gtx_pre_resetn = 0; (* ASYNC_REG = "TRUE", KEEP = "TRUE" *) reg gtx_resetn = 0; wire gtx_reset; wire tx_reset_int; // Synchronous reset in the MAC and gmii Tx domain wire rx_reset_int; // Synchronous reset in the MAC and gmii Rx domain wire [27:0] rx_statistics_vector_int; wire rx_statistics_valid_int; wire [31:0] tx_statistics_vector_int; wire tx_statistics_valid_int; reset_sync gtx_reset_gen ( .clk (gtx_clk), .enable (plllock_i), .reset_in (!glbl_rstn), .reset_out (gtx_clk_reset_int) ); // Create fully synchronous reset in the gtx_clk domain. always @(posedge gtx_clk) begin if (gtx_clk_reset_int) begin gtx_pre_resetn <= 0; gtx_resetn <= 0; end else begin gtx_pre_resetn <= 1; gtx_resetn <= gtx_pre_resetn; end end assign gtx_reset = !gtx_resetn; // assign outputs assign rx_reset = rx_reset_int; assign tx_reset = tx_reset_int; // Assign the internal clock signals to output ports. assign user_mac_aclk = rx_mac_aclk_int; assign rx_mac_aclk_int = tx_mac_aclk_int; //--------------------------------------------------------------------------- // Instantiate a BUFG for tx phy and user side logic //--------------------------------------------------------------------------- BUFG bufg_tx_axi_clk ( .I (tx_axi_clk_out), .O (tx_mac_aclk_int) ); //------------------------------------------------------------------------- // Instantiate GTX for SGMII or 1000BASE-X PCS/PMA physical interface //------------------------------------------------------------------------- v6_gtxwizard_top v6_gtxwizard_top_inst ( .RESETDONE (resetdone_i), .ENMCOMMAALIGN (encommaalign_i), .ENPCOMMAALIGN (encommaalign_i), .LOOPBACK (loopback_i), .POWERDOWN (powerdown_i), .RXUSRCLK2 (gtx_clk), .RXRESET (mgt_rx_reset_i), .TXCHARDISPMODE (txchardispmode_r), .TXCHARDISPVAL (txchardispval_r), .TXCHARISK (txcharisk_r), .TXDATA (mgt_tx_data_r), .TXUSRCLK2 (gtx_clk), .TXRESET (mgt_tx_reset_i), .RXCHARISCOMMA (rxchariscomma_i), .RXCHARISK (rxcharisk_i), .RXCLKCORCNT (rxclkcorcnt_i), .RXDATA (mgt_rx_data_i), .RXDISPERR (rxdisperr_i), .RXNOTINTABLE (rxnotintable_i), .RXRUNDISP (rxrundisp_i), .RXBUFERR (rxbufstatus_i), .TXBUFERR (txbuferr_i), .PLLLKDET (plllock_i), .TXOUTCLK (clk125_out), .RXELECIDLE (rxelecidle_i), .TXN (txn), .TXP (txp), .RXN (rxn), .RXP (rxp), .CLK_DS (clk_ds), .PMARESET (!glbl_rstn) ); assign resetdone = resetdone_i; // Detect when there has been a disconnect assign signal_detect_i = ~(rxelecidle_i); // PLL lock assign emac_locked_i = plllock_i; //------------------------------------------------------------------------ // Register the signals between EMAC and transceiver for timing purposes //------------------------------------------------------------------------ always @(posedge gtx_clk) begin if (gtx_reset) begin rxchariscomma_r <= 1'b0; rxcharisk_r <= 1'b0; rxclkcorcnt_r <= 0; gmii_rxd_int <= 0; gmii_rx_dv_int <= 1'b0; rxdisperr_r <= 1'b0; rxnotintable_r <= 1'b0; rxrundisp_r <= 1'b0; txchardispmode_r <= 1'b0; txchardispval_r <= 1'b0; txcharisk_r <= 1'b0; mgt_tx_data_r <= 0; end else begin rxchariscomma_r <= rxchariscomma_i; rxcharisk_r <= rxcharisk_i; rxclkcorcnt_r <= rxclkcorcnt_i; gmii_rxd_int <= mgt_rx_data_i; gmii_rx_dv_int <= 1'b0; // RXREALIGN rxdisperr_r <= rxdisperr_i; rxnotintable_r <= rxnotintable_i; rxrundisp_r <= rxrundisp_i; txchardispmode_r <= txchardispmode_i; txchardispval_r <= txchardispval_i ; txcharisk_r <= txcharisk_i; mgt_tx_data_r <= gmii_txd_int; end end assign rx_statistics_vector = rx_statistics_vector_int; assign rx_statistics_valid = rx_statistics_valid_int; assign tx_statistics_vector = tx_statistics_vector_int; assign tx_statistics_valid = tx_statistics_valid_int; //--------------------------------------------------------------------------- // Instantiate the Hard MAC core //--------------------------------------------------------------------------- v6_emac_v2_3_sgmii v6emac_core( //------------------------------------------------------------------------- // Clock signals - used in rgmii and serial modes //------------------------------------------------------------------------- .gtx_clk (gtx_clk), .tx_axi_clk_out (tx_axi_clk_out), // only in rgmii or sgmii //------------------------------------------------------------------------- // Receiver Interface. //------------------------------------------------------------------------- .rx_axi_clk (rx_mac_aclk_int), .rx_reset_out (rx_reset_int), .rx_axis_mac_tdata (rx_axis_mac_tdata), .rx_axis_mac_tvalid (rx_axis_mac_tvalid), .rx_axis_mac_tlast (rx_axis_mac_tlast), .rx_axis_mac_tuser (rx_axis_mac_tuser), // RX sideband signals .rx_statistics_vector (rx_statistics_vector_int), .rx_statistics_valid (rx_statistics_valid_int), //------------------------------------------------------------------------- // Transmitter Interface //------------------------------------------------------------------------- .tx_axi_clk (tx_mac_aclk_int), .tx_reset_out (tx_reset_int), .tx_axis_mac_tdata (tx_axis_mac_tdata), .tx_axis_mac_tvalid (tx_axis_mac_tvalid), .tx_axis_mac_tlast (tx_axis_mac_tlast), .tx_axis_mac_tuser (tx_axis_mac_tuser), .tx_axis_mac_tready (tx_axis_mac_tready), // TX sideband signals .tx_retransmit (tx_retransmit), .tx_collision (tx_collision), .tx_ifg_delay (tx_ifg_delay), .tx_statistics_vector (tx_statistics_vector_int), .tx_statistics_valid (tx_statistics_valid_int), //------------------------------------------------------------------------- // Flow Control //------------------------------------------------------------------------- .pause_req (pause_req), .pause_val (pause_val), //------------------------------------------------------------------------- // Speed interface //------------------------------------------------------------------------- .speed_is_10_100 (speedis10100_int), //------------------------------------------------------------------------- // GMII/MII Interface //------------------------------------------------------------------------- .gmii_txd (gmii_txd_int), .gmii_rxd (gmii_rxd_int), .gmii_rx_dv (gmii_rx_dv_int), //------------------------------------------------------------------------- // SGMII interface //------------------------------------------------------------------------- .dcm_locked (emac_locked_i), .an_interrupt (), .signal_det (signal_detect_i), .phy_ad (phyad), .en_comma_align (encommaalign_i), .loopback_msb (loopback_i), .mgt_rx_reset (mgt_rx_reset_i), .mgt_tx_reset (mgt_tx_reset_i), .powerdown (powerdown_i), .sync_acq_status (syncacqstatus), .rx_clk_cor_cnt (rxclkcorcnt_r), .rx_buf_status (rxbufstatus_i), .rx_char_is_comma (rxchariscomma_r), .rx_char_is_k (rxcharisk_r), .rx_disp_err (rxdisperr_r), .rx_not_in_table (rxnotintable_r), .rx_run_disp (rxrundisp_r), .tx_buf_err (txbuferr_i), .tx_char_disp_mode (txchardispmode_i), .tx_char_disp_val (txchardispval_i), .tx_char_is_k (txcharisk_i), //------------------------------------------------------------------------- // MDIO Interface //------------------------------------------------------------------------- .mdc_in (mdc_in), .mdio_in (mdio_i), .mdio_out (mdio_o), .mdio_tri (mdio_t), //------------------------------------------------------------------------- // Resets //------------------------------------------------------------------------- .glbl_rstn (gtx_resetn), .rx_axi_rstn (rx_axi_rstn), .tx_axi_rstn (tx_axi_rstn) ); endmodule