------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version : 1.9
--  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
--  /   /         Filename : double_reset.vhd
-- /___/   /\
-- \   \  /  \
--  \___\/\___\
--
--
-- Module DOUBLE_RESET
-- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity DOUBLE_RESET is
port
(
	CLK                :   in    std_logic;
	PLLLKDET           :   in    std_logic;
	GTXTEST_DONE       :   out   std_logic;
	GTXTEST_BIT1       :   out   std_logic
);

end DOUBLE_RESET;

architecture RTL of DOUBLE_RESET is
--***********************************Parameter Declarations********************
    constant DLY : time := 1 ns;

--*******************************Register Declarations************************
    signal 	plllkdet_sync	:   std_logic;
    signal 	plllkdet_r	:   std_logic;
    signal 	reset_dly_ctr	:   unsigned(10 downto 0);
    signal      reset_dly_done	:   std_logic;
    signal      testdone_f      :   std_logic_vector(3 downto 0);

begin
--*******************************Main Body of Code****************************

    process(CLK )
    begin
        if(CLK'event and CLK = '1') then
           plllkdet_r    <= PLLLKDET   	after DLY;
           plllkdet_sync <= plllkdet_r 	after DLY;
        end if;
    end process;

    GTXTEST_BIT1 <= reset_dly_done;
    GTXTEST_DONE <= testdone_f(0) when (reset_dly_ctr = b"00000000000") else '0';

    process(CLK )
    begin
        if(CLK'event and CLK = '1') then
          if (plllkdet_sync = '0') then
            reset_dly_ctr 	<= b"11111111111"     after DLY;
          elsif (reset_dly_ctr /= b"00000000000") then
            reset_dly_ctr 	<= reset_dly_ctr - 1	after DLY;
          end if;
        end if;
    end process;

    process(CLK )
    begin
        if(CLK'event and CLK = '1') then
          if (plllkdet_sync = '0') then
             reset_dly_done 	<= '0'   	after DLY;
          elsif (reset_dly_ctr(10) = '0') then
             reset_dly_done 	<= reset_dly_ctr(8)   after DLY;
          end if;
        end if;
    end process;

    process(CLK )
    begin
        if(CLK'event and CLK = '1') then
          if(reset_dly_ctr /= b"00000000000") then
             testdone_f 	<= b"1111" after DLY;
          else
             testdone_f 	<= '0' & testdone_f(3 downto 1) after DLY;
          end if;
        end if;
    end process;


end RTL;