//------------------------------------------------------------------------------
// File       : basic_pat_gen.v
// Author     : Xilinx Inc.
// Project    : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
// File       : basic_pat_gen.v
// Version    : 2.3
//-----------------------------------------------------------------------------
//
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//
// Description:  This module allows either a user side loopback, with address swapping,
// OR the generation of simple packets.  The selection being controlled by a top level input
// which can be sourced fdrom a DIP switch in hardware.
// The packet generation is controlled by simple parameters giving the ability to set the DA,
// SA amd max/min size packets.  The data portion of each packet is always a simple
// incrementing pattern.
// When configured to loopback the first 12 bytes of the packet are accepted and then the
// packet is output with/without address swapping.  Currently, this is hard wired in the address
// swap logic.
//
//
//------------------------------------------------------------------------------

`timescale 1 ps/1 ps

module basic_pat_gen #(
    parameter                            DEST_ADDR = 48'hda0102030405,
    parameter                            SRC_ADDR  = 48'h5a0102030405,
    parameter                            MAX_SIZE  = 16'd500,
    parameter                            MIN_SIZE  = 16'd64
)(
    input                                axi_tclk,
    input                                axi_tresetn,
    input                                check_resetn,

    input                                enable_pat_gen,
    input                                enable_pat_chk,
    input                                enable_address_swap,

    // data from the RX FIFO
    input       [7:0]                    rx_axis_fifo_tdata,
    input                                rx_axis_fifo_tvalid,
    input                                rx_axis_fifo_tlast,
    output                               rx_axis_fifo_tready,
    // data TO the tx fifo
    output      [7:0]                    tx_axis_fifo_tdata,
    output                               tx_axis_fifo_tvalid,
    output                               tx_axis_fifo_tlast,
    input                                tx_axis_fifo_tready,

    output                               frame_error
);

wire     [7:0]       rx_axis_fifo_tdata_int;
wire                 rx_axis_fifo_tvalid_int;
wire                 rx_axis_fifo_tlast_int;
wire                 rx_axis_fifo_tready_int;

wire     [7:0]       pat_gen_tdata;
wire                 pat_gen_tvalid;
wire                 pat_gen_tlast;
wire                 pat_gen_tready;

wire     [7:0]       mux_tdata;
wire                 mux_tvalid;
wire                 mux_tlast;
wire                 mux_tready;

// basic packet generator - this has parametisable
// DA and SA fields but the LT and data will be auto-generated
// based on the min/max size parameters - these can be set
// to the same value to obtain a specific packet size or will
// increment from the lower packet size to the upper
axi_pat_gen #(
   .DEST_ADDR                 (DEST_ADDR),
   .SRC_ADDR                  (SRC_ADDR),
   .MAX_SIZE                  (MAX_SIZE),
   .MIN_SIZE                  (MIN_SIZE)

) axi_pat_gen (
   .axi_tclk                  (axi_tclk),
   .axi_tresetn               (axi_tresetn),

   .enable_pat_gen            (enable_pat_gen),

   .tdata                     (pat_gen_tdata),
   .tvalid                    (pat_gen_tvalid),
   .tlast                     (pat_gen_tlast),
   .tready                    (pat_gen_tready)
);

axi_pat_check #(
   .DEST_ADDR                 (DEST_ADDR),
   .SRC_ADDR                  (SRC_ADDR),
   .MAX_SIZE                  (MAX_SIZE),
   .MIN_SIZE                  (MIN_SIZE)

) axi_pat_check (
   .axi_tclk                  (axi_tclk),
   .axi_tresetn               (check_resetn),

   .enable_pat_chk            (enable_pat_chk),

   .tdata                     (rx_axis_fifo_tdata),
   .tvalid                    (rx_axis_fifo_tvalid),
   .tlast                     (rx_axis_fifo_tlast),
   .tready                    (rx_axis_fifo_tready),

   .frame_error               (frame_error)
);

// simple mux between the rx_fifo AXI interface and the pat gen output
// this is not registered as it is passed through a pipeline stage to limit the impact
axi_mux axi_mux(
   .mux_select                (enable_pat_gen),

   .tdata0                    (rx_axis_fifo_tdata),
   .tvalid0                   (rx_axis_fifo_tvalid),
   .tlast0                    (rx_axis_fifo_tlast),
   .tready0                   (rx_axis_fifo_tready),

   .tdata1                    (pat_gen_tdata),
   .tvalid1                   (pat_gen_tvalid),
   .tlast1                    (pat_gen_tlast),
   .tready1                   (pat_gen_tready),

   .tdata                     (mux_tdata),
   .tvalid                    (mux_tvalid),
   .tlast                     (mux_tlast),
   .tready                    (mux_tready)
);

// a pipeline stage has been added to reduce timing issues and allow
// a pattern generator to be muxed into the path
axi_pipe axi_pipe (
   .axi_tclk                  (axi_tclk),
   .axi_tresetn               (axi_tresetn),

   .rx_axis_fifo_tdata_in     (mux_tdata),
   .rx_axis_fifo_tvalid_in    (mux_tvalid),
   .rx_axis_fifo_tlast_in     (mux_tlast),
   .rx_axis_fifo_tready_in    (mux_tready),

   .rx_axis_fifo_tdata_out    (rx_axis_fifo_tdata_int),
   .rx_axis_fifo_tvalid_out   (rx_axis_fifo_tvalid_int),
   .rx_axis_fifo_tlast_out    (rx_axis_fifo_tlast_int),
   .rx_axis_fifo_tready_out   (rx_axis_fifo_tready_int)

);

// address swap module: based around a Dual port distributed ram
// data is written in and the read only starts once the da/sa have been
// stored.  Can cope with a gap of one cycle between packets.
address_swap address_swap (
   .axi_tclk                  (axi_tclk),
   .axi_tresetn               (axi_tresetn),
   .en_address_swap           (enable_address_swap),

   .rx_axis_fifo_tdata        (rx_axis_fifo_tdata_int),
   .rx_axis_fifo_tvalid       (rx_axis_fifo_tvalid_int),
   .rx_axis_fifo_tlast        (rx_axis_fifo_tlast_int),
   .rx_axis_fifo_tready       (rx_axis_fifo_tready_int),

   .tx_axis_fifo_tdata        (tx_axis_fifo_tdata),
   .tx_axis_fifo_tvalid       (tx_axis_fifo_tvalid),
   .tx_axis_fifo_tlast        (tx_axis_fifo_tlast),
   .tx_axis_fifo_tready       (tx_axis_fifo_tready)
  );


endmodule