//------------------------------------------------------------------------------
// File       : axi_pat_check.v
// Author     : Xilinx Inc.
// Project    : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
// File       : axi_pat_check.v
// Version    : 2.3
//-----------------------------------------------------------------------------
//
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// Description:  A simple pattern checker - expects the same data pattern as generated by the pat_gen
// with the same DA/SA order (it is expected that the frames will pass through
// two address swap blocks).  the checker will first sync to the data and then
// identify any errors (this is a sticky output but the internal signal is
// per byte)
//
//------------------------------------------------------------------------------

`timescale 1 ps/1 ps

module axi_pat_check #(
   parameter               DEST_ADDR = 48'hda0102030405,
   parameter               SRC_ADDR  = 48'h5a0102030405,
   parameter               MAX_SIZE  = 16'd500,
   parameter               MIN_SIZE  = 16'd64

)(
   input                   axi_tclk,
   input                   axi_tresetn,

   input                   enable_pat_chk,

   input       [7:0]       tdata,
   input                   tvalid,
   input                   tlast,
   input                   tready,

   output reg              frame_error
);

parameter   IDLE  = 2'b00,
            INFO  = 2'b01,
            LOOK  = 2'b10,
            PKT   = 2'b11;

reg                  errored_data;
wire  [7:0]          lut_data;
reg   [7:0]          expected_data;
reg   [15:0]         packet_size;
reg   [4:0]          packet_count;
reg   [1:0]          rx_state;
reg   [1:0]          next_rx_state;


// the pattern checker is a slave in all respects so has to look for ackowledged data
// the first and 6 bytes of data are compared against the first byte of DEST_ADDR and SCR_ADDR
// to allow for address swaps being removed

// a simple state machine will keep track of the packet position
always @(rx_state or tlast or tvalid or tready or enable_pat_chk or errored_data)
begin
   next_rx_state = rx_state;
   case (rx_state)
      // cannot simply look for a rise on valid have to see a last first so
      // we know the next asserted valid is new data
      IDLE : begin
         if (tlast & tvalid & tready & enable_pat_chk)
            next_rx_state = INFO;
      end
      // since we don't know where the packet gen will be rx a frame to enable
      // packet size to be initialised
      INFO : begin
         if (tlast & tvalid & tready)
            next_rx_state = LOOK;
      end
      // have seen a last so now look for a start
      LOOK : begin
         if (!tlast & tvalid & tready)
            next_rx_state = PKT;
      end
      // rxd first byte of packet - now stay in this state until we see a last
      PKT : begin
         if (!enable_pat_chk | errored_data)
            next_rx_state = IDLE;
         else if (tlast & tvalid & tready)
            next_rx_state = LOOK;

      end
   endcase
end

always @(posedge axi_tclk)
begin
   if (!axi_tresetn)
      rx_state <= IDLE;
   else
      rx_state <= next_rx_state;
end

// now need a counter for packet size and packet position AND data
always @(posedge axi_tclk)
begin
   if (!axi_tresetn)
      packet_count <= 5'd0;
   else begin
      if ((next_rx_state == PKT || rx_state == PKT || rx_state == INFO) & tvalid & tready & !packet_count[4])
         packet_count <= packet_count + 5'd1;
      else if (next_rx_state == LOOK | rx_state == IDLE)
         packet_count <= 5'd0;
   end
end

// need to get packet size info
// this is first initialised during the info state (the assumption being that
// the generate sends incrementing packet sizes (wrapping at MAX_SIZE)
always @(posedge axi_tclk)
begin
   if ((rx_state == INFO) && (packet_count == 5'd12) & tvalid & tready)
      packet_size[15:8] <= tdata;
   else if ((rx_state == INFO) && (packet_count == 5'd13) & tvalid & tready)
      packet_size[7:0] <= tdata;
      // when in the LOOK state we want to update the packet size to the next expected
   else if (rx_state != LOOK && (next_rx_state == LOOK)) begin
      if (packet_size == MAX_SIZE - 18)
         packet_size <= MIN_SIZE - 18;
      else
         packet_size <= packet_size + 16'd1;
   end
end

// the expected data is updated from the packet size at the end of the LOOK state
always @(posedge axi_tclk)
begin
   if ((rx_state == LOOK) && (next_rx_state == PKT))
      expected_data <= packet_size[7:0];
   else if ((rx_state == PKT) && (packet_count >= 5'd14) & tvalid & tready)
      expected_data <= expected_data - 8'd1;
end

// store the parameterized values in a lut (64 deep)
// this should mean the values could be adjusted in fpga_editor etc..
genvar i;
generate
  for (i=0; i<=7; i=i+1) begin : gen_addr
    LUT6 #(
       .INIT      ({52'd0,
                    SRC_ADDR[i],
                    SRC_ADDR[i+8],
                    SRC_ADDR[i+16],
                    SRC_ADDR[i+24],
                    SRC_ADDR[i+32],
                    SRC_ADDR[i+40],
                    DEST_ADDR[i],
                    DEST_ADDR[i+8],
                    DEST_ADDR[i+16],
                    DEST_ADDR[i+24],
                    DEST_ADDR[i+32],
                    DEST_ADDR[i+40]
                   })   // Specify LUT Contents
    ) LUT6_inst (
       .O         (lut_data[i]),
       .I0        (packet_count[0]),
       .I1        (packet_count[1]),
       .I2        (packet_count[2]),
       .I3        (packet_count[3]),
       .I4        (1'b0),
       .I5        (1'b0)
    );
   end
endgenerate

// finally the check states - errored_data is only high on the cycle after a mismatch
always @(posedge axi_tclk)
begin
   errored_data <= 0;
   if ((packet_count < 5'd12) & tvalid & tready) begin
      if (lut_data != tdata)
         errored_data <= 1;
   end
   else if ((packet_count == 5'd12) & tvalid & tready) begin
      if (packet_size[15:8] != tdata)
         errored_data <= 1;
   end
   else if ((packet_count == 5'd13) & tvalid & tready) begin
      if (packet_size[7:0] != tdata)
         errored_data <= 1;
   end
   else if ((packet_count >= 5'd14) & tvalid & tready && (rx_state == PKT)) begin
      if (expected_data != tdata)
         errored_data <= 1;
   end
end

// capture the error and hold until reset
always @(posedge axi_tclk)
begin
   if (!axi_tresetn)
      frame_error <= 0;
   else if ((rx_state != IDLE) && (rx_state != INFO) & errored_data)
      frame_error <= 1;
end

endmodule