--------------------------------------------------------------------------------
-- File       : axi_mux.v
-- Author     : Xilinx Inc.
-- Project    : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
-- File       : axi_mux.vhd
-- Version    : 2.3
-------------------------------------------------------------------------------
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-- Description:  A simple axi mux
--
--------------------------------------------------------------------------------

library unisim;
use unisim.vcomponents.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity axi_mux is
   port (
      mux_select                 : in  std_logic;

      -- mux inputs
      tdata0                     : in  std_logic_vector(7 downto 0);
      tvalid0                    : in  std_logic;
      tlast0                     : in  std_logic;
      tready0                    : out std_logic;

      tdata1                     : in  std_logic_vector(7 downto 0);
      tvalid1                    : in  std_logic;
      tlast1                     : in  std_logic;
      tready1                    : out std_logic;

      -- mux outputs
      tdata                      : out std_logic_vector(7 downto 0);
      tvalid                     : out std_logic;
      tlast                      : out std_logic;
      tready                     : in  std_logic
   );

end axi_mux;

architecture rtl of axi_mux is

begin

   main_mux : process(mux_select, tdata0, tvalid0, tlast0, tdata1,
                      tvalid1, tlast1)
   begin
      if mux_select = '1' then
         tdata    <= tdata1;
         tvalid   <= tvalid1;
         tlast    <= tlast1;
      else
         tdata    <= tdata0;
         tvalid   <= tvalid0;
         tlast    <= tlast0;
      end if;
   end process;

   split : process (tready, mux_select)
   begin
      if mux_select = '1' then
         tready0     <= '1';
      else
         tready0     <= tready;
      end if;
      tready1     <= tready;
   end process;

end rtl;