//------------------------------------------------------------------------------
// Title      : Synchronous Reset generation flip-flop pair
// Project    : Xilinx LogiCORE Virtex-6 Embedded Tri-Mode Ethernet MAC
// File       : reset_sync.v
// Version    : 2.3
//-----------------------------------------------------------------------------
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//------------------------------------------------------------------------------
// Description: Both flip-flops have the same asynchronous reset signal.
//              Together the flops create a minimum of a 1 clock period
//              duration pulse which is used for synchronous reset.
//
//              The flops are placed, using RLOCs, into the same slice.

`timescale 1ps/1ps

module reset_sync #(
  parameter INITIALISE = 2'b11
)
(
   input       reset_in,
   input       clk,
   input       enable,
   output      reset_out
);


wire  reset_stage1;
wire  reset_stage2;

  (* ASYNC_REG = "TRUE", RLOC = "X0Y0", INIT = "1" *)
  FDPE #(
   .INIT (INITIALISE[0])
  ) reset_sync1 (
  .C  (clk),
  .CE (enable),
  .PRE(reset_in),
  .D  (1'b0),
  .Q  (reset_stage1)
  );

  (* ASYNC_REG = "TRUE", RLOC = "X0Y0", INIT = "1" *)
  FDPE #(
   .INIT (INITIALISE[1])
  ) reset_sync2 (
  .C  (clk),
  .CE (enable),
  .PRE(reset_in),
  .D  (reset_stage1),
  .Q  (reset_stage2)
  );


assign reset_out = reset_stage2;



endmodule