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Customer assumes the sole risk and * * liability of any use of Xilinx products in Critical * * Applications, subject only to applicable laws and * * regulations governing limitations on product liability. * * * * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS * * PART OF THIS FILE AT ALL TIMES. * *******************************************************************************/ // Generated from component ID: xilinx.com:ip:v6_emac:2.3 // The following must be inserted into your Verilog file for this // core to be instantiated. Change the instance name and port connections // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG v6_emac_v2_3_sgmii YourInstanceName ( .glbl_rstn(glbl_rstn), // input glbl_rstn .rx_axi_rstn(rx_axi_rstn), // input rx_axi_rstn .tx_axi_rstn(tx_axi_rstn), // input tx_axi_rstn .gtx_clk(gtx_clk), // input gtx_clk .tx_axi_clk_out(tx_axi_clk_out), // output tx_axi_clk_out .rx_axi_clk(rx_axi_clk), // input rx_axi_clk .rx_reset_out(rx_reset_out), // output rx_reset_out .rx_axis_mac_tdata(rx_axis_mac_tdata), // output [7 : 0] rx_axis_mac_tdata .rx_axis_mac_tvalid(rx_axis_mac_tvalid), // output rx_axis_mac_tvalid .rx_axis_mac_tlast(rx_axis_mac_tlast), // output rx_axis_mac_tlast .rx_axis_mac_tuser(rx_axis_mac_tuser), // output rx_axis_mac_tuser .rx_statistics_vector(rx_statistics_vector), // output [27 : 0] rx_statistics_vector .rx_statistics_valid(rx_statistics_valid), // output rx_statistics_valid .tx_axi_clk(tx_axi_clk), // input tx_axi_clk .tx_reset_out(tx_reset_out), // output tx_reset_out .tx_axis_mac_tdata(tx_axis_mac_tdata), // input [7 : 0] tx_axis_mac_tdata .tx_axis_mac_tvalid(tx_axis_mac_tvalid), // input tx_axis_mac_tvalid .tx_axis_mac_tlast(tx_axis_mac_tlast), // input tx_axis_mac_tlast .tx_axis_mac_tuser(tx_axis_mac_tuser), // input tx_axis_mac_tuser .tx_axis_mac_tready(tx_axis_mac_tready), // output tx_axis_mac_tready .tx_retransmit(tx_retransmit), // output tx_retransmit .tx_collision(tx_collision), // output tx_collision .tx_ifg_delay(tx_ifg_delay), // input [7 : 0] tx_ifg_delay .tx_statistics_vector(tx_statistics_vector), // output [31 : 0] tx_statistics_vector .tx_statistics_valid(tx_statistics_valid), // output tx_statistics_valid .pause_req(pause_req), // input pause_req .pause_val(pause_val), // input [15 : 0] pause_val .speed_is_10_100(speed_is_10_100), // output speed_is_10_100 .gmii_txd(gmii_txd), // output [7 : 0] gmii_txd .gmii_rxd(gmii_rxd), // input [7 : 0] gmii_rxd .gmii_rx_dv(gmii_rx_dv), // input gmii_rx_dv .dcm_locked(dcm_locked), // input dcm_locked .an_interrupt(an_interrupt), // output an_interrupt .signal_det(signal_det), // input signal_det .phy_ad(phy_ad), // input [4 : 0] phy_ad .en_comma_align(en_comma_align), // output en_comma_align .loopback_msb(loopback_msb), // output loopback_msb .mgt_rx_reset(mgt_rx_reset), // output mgt_rx_reset .mgt_tx_reset(mgt_tx_reset), // output mgt_tx_reset .powerdown(powerdown), // output powerdown .sync_acq_status(sync_acq_status), // output sync_acq_status .rx_clk_cor_cnt(rx_clk_cor_cnt), // input [2 : 0] rx_clk_cor_cnt .rx_buf_status(rx_buf_status), // input rx_buf_status .rx_char_is_comma(rx_char_is_comma), // input rx_char_is_comma .rx_char_is_k(rx_char_is_k), // input rx_char_is_k .rx_disp_err(rx_disp_err), // input rx_disp_err .rx_not_in_table(rx_not_in_table), // input rx_not_in_table .rx_run_disp(rx_run_disp), // input rx_run_disp .tx_buf_err(tx_buf_err), // input tx_buf_err .tx_char_disp_mode(tx_char_disp_mode), // output tx_char_disp_mode .tx_char_disp_val(tx_char_disp_val), // output tx_char_disp_val .tx_char_is_k(tx_char_is_k), // output tx_char_is_k .mdc_in(mdc_in), // input mdc_in .mdio_in(mdio_in), // input mdio_in .mdio_out(mdio_out), // output mdio_out .mdio_tri(mdio_tri)); // output mdio_tri // INST_TAG_END ------ End INSTANTIATION Template ---------