Release 14.7 - Xilinx CORE Generator P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. All runtime messages will be recorded in /home/carmijo/glib_ipbus2_sgmii/ipcore_dir/coregen.log INFO:encore:314 - Created non-GUI application for batch mode execution. WARNING:sim:991 - The project IP instance 'v6_emac_v2_3_sgmii' for IP 'Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper v2.3' was generated with a different version of the IP than is currently in the IP Catalog. It was originally generated using IP with the packaged timestamp '2013-03-27+03:45'; the IP in the current catalog has a different packaged timestamp '2013-10-13+18:46'. This mismatch is due to changes made to the IP in the user repositories. It may affect some functionality of the IP, if there are differences between these two versions of the IP. WARNING:sim:991 - The project IP instance 'v6_emac_v2_3_sgmii' for IP 'Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper v2.3' was generated with a different version of the IP than is currently in the IP Catalog. It was originally generated using IP with the packaged timestamp '2013-03-27+03:45'; the IP in the current catalog has a different packaged timestamp '2013-10-13+18:46'. This mismatch is due to changes made to the IP in the user repositories. It may affect some functionality of the IP, if there are differences between these two versions of the IP. INFO:sim:172 - Generating IP... WARNING:sim:100 - The Simulation File Type is not valid for this core. Overriding with File Type . Applying current project options... Finished applying current project options. Resolving generic values... Finished resolving generic values. Generating IP... WARNING:sim:100 - The Simulation File Type is not valid for this core. Overriding with File Type . WARNING:sim:89 - A core named already exists in the output directory. Output products for this core may be overwritten. XST: HDL Parsing XST: HDL Elaboration XST: HDL Synthesis XST: Advanced HDL Synthesis XST: Low Level Synthesis Generating Implementation files. Generating the VHDL instantiation template. Generating NGC file. Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngcbuild -intstyle ise -dd ./tmp/_cg/ ./tmp/_cg/v6_emac_v2_3_sgmii.edn ./tmp/_cg/v6_emac_v2_3_sgmii_unobf.ngc Executing edif2ngd -noa "tmp/_cg/v6_emac_v2_3_sgmii.edn" "tmp/_cg/v6_emac_v2_3_sgmii.ngo" Release 14.7 - edif2ngd P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. INFO:NgdBuild - Release 14.7 edif2ngd P.20131013 (lin64) INFO:NgdBuild - Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Writing module to "tmp/_cg/v6_emac_v2_3_sgmii.ngo"... Reading NGO file "/home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.ngo" ... Loading design module "./tmp/_cg/v6_emac_v2_3_sgmii_emac_wrapper_1.ngc"... Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- NGCBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Writing NGC file "./tmp/_cg/v6_emac_v2_3_sgmii_unobf.ngc" ... Total REAL time to NGCBUILD completion: 7 sec Total CPU time to NGCBUILD completion: 3 sec Writing NGCBUILD log file "./tmp/_cg/v6_emac_v2_3_sgmii_unobf.blc"... NGCBUILD done. Generating VHDL structural model. INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM simulation primitives and has to be used with UNISIM library for correct compilation and simulation. Generating Verilog structural model. INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM simulation primitives and has to be used with UNISIM simulation library for correct compilation and simulation. Finished Generation. Generating IP instantiation template... Generating ASY schematic symbol... INFO:sim:949 - Finished generation of ASY schematic symbol. Generating metadata file... Generating ISE project... XCO file found: v6_emac_v2_3_sgmii.xco XMDF file found: v6_emac_v2_3_sgmii_xmdf.tcl Adding /home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.asy -view all -origin_type imported Adding /home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.ngc -view all -origin_type created Checking file "/home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.ngc" for project device match ... File "/home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.ngc" device information matches project device. Adding /home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.v -view all -origin_type created INFO:HDLCompiler:1845 - Analyzing Verilog file "/home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.v" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. Adding /home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.veo -view all -origin_type imported Adding /home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.vhd -view all -origin_type created INFO:HDLCompiler:1061 - Parsing VHDL file "/home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.vhd" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. Adding /home/carmijo/glib_ipbus2_sgmii/ipcore_dir/tmp/_cg/v6_emac_v2_3_sgmii.vho -view all -origin_type imported INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true. Top level has been set to "/v6_emac_v2_3_sgmii" Generating README file... Generating FLIST file... INFO:sim:948 - Finished FLIST file generation. Moving files to output directory... Finished moving files to output directory Saved CGP file for project 'coregen'.