Block to allow testing of 'out-of-band' interface to transactor. This interface is currently used by the uTCA MMC and the simulation testbench, but could also (e.g.) interface to an on-chip CPU or PCIe slave. Data to be read / written to or from the transactor buffer (16b words). Note that this register is not properly handled across clock domains, so only ever set one bit at a time (otherwise they will not be synchronised on chip). Set to write a data word to the transactor buffer (edge-sensitive). Set to read a data word from the transactor buffer (edge-sensitive). Set to request processing of packet by the transactor (edge-sensitive). Indicates the 'done' status of the transactor buffer.