------------------------------------------------------------------------------- -- Title : Virtex-5 Ethernet MAC Wrapper -- Project : Virtex-5 Embedded Tri-Mode Ethernet MAC Wrapper -- File : v5_emac_v1_8.vhd -- Version : 1.8 ------------------------------------------------------------------------------- -- -- (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -------------------------------------------------------------------------------- -- Description: This wrapper file instantiates the full Virtex-5 Ethernet -- MAC (EMAC) primitive. For one or both of the two Ethernet MACs -- (EMAC0/EMAC1): -- -- * all unused input ports on the primitive will be tied to the -- appropriate logic level; -- -- * all unused output ports on the primitive will be left -- unconnected; -- -- * the Tie-off Vector will be connected based on the options -- selected from CORE Generator; -- -- * only used ports will be connected to the ports of this -- wrapper file. -- -- This simplified wrapper should therefore be used as the -- instantiation template for the EMAC in customer designs. -------------------------------------------------------------------------------- library unisim; use unisim.vcomponents.all; library ieee; use ieee.std_logic_1164.all; -------------------------------------------------------------------------------- -- The entity declaration for the Virtex-5 Embedded Ethernet MAC wrapper. -------------------------------------------------------------------------------- entity v5_emac_v1_8 is port( -- Client Receiver Interface - EMAC0 EMAC0CLIENTRXCLIENTCLKOUT : out std_logic; CLIENTEMAC0RXCLIENTCLKIN : in std_logic; EMAC0CLIENTRXD : out std_logic_vector(7 downto 0); EMAC0CLIENTRXDVLD : out std_logic; EMAC0CLIENTRXDVLDMSW : out std_logic; EMAC0CLIENTRXGOODFRAME : out std_logic; EMAC0CLIENTRXBADFRAME : out std_logic; EMAC0CLIENTRXFRAMEDROP : out std_logic; EMAC0CLIENTRXSTATS : out std_logic_vector(6 downto 0); EMAC0CLIENTRXSTATSVLD : out std_logic; EMAC0CLIENTRXSTATSBYTEVLD : out std_logic; -- Client Transmitter Interface - EMAC0 EMAC0CLIENTTXCLIENTCLKOUT : out std_logic; CLIENTEMAC0TXCLIENTCLKIN : in std_logic; CLIENTEMAC0TXD : in std_logic_vector(7 downto 0); CLIENTEMAC0TXDVLD : in std_logic; CLIENTEMAC0TXDVLDMSW : in std_logic; EMAC0CLIENTTXACK : out std_logic; CLIENTEMAC0TXFIRSTBYTE : in std_logic; CLIENTEMAC0TXUNDERRUN : in std_logic; EMAC0CLIENTTXCOLLISION : out std_logic; EMAC0CLIENTTXRETRANSMIT : out std_logic; CLIENTEMAC0TXIFGDELAY : in std_logic_vector(7 downto 0); EMAC0CLIENTTXSTATS : out std_logic; EMAC0CLIENTTXSTATSVLD : out std_logic; EMAC0CLIENTTXSTATSBYTEVLD : out std_logic; -- MAC Control Interface - EMAC0 CLIENTEMAC0PAUSEREQ : in std_logic; CLIENTEMAC0PAUSEVAL : in std_logic_vector(15 downto 0); -- Clock Signal - EMAC0 GTX_CLK_0 : in std_logic; PHYEMAC0TXGMIIMIICLKIN : in std_logic; EMAC0PHYTXGMIIMIICLKOUT : out std_logic; -- GMII Interface - EMAC0 GMII_TXD_0 : out std_logic_vector(7 downto 0); GMII_TX_EN_0 : out std_logic; GMII_TX_ER_0 : out std_logic; GMII_RXD_0 : in std_logic_vector(7 downto 0); GMII_RX_DV_0 : in std_logic; GMII_RX_ER_0 : in std_logic; GMII_RX_CLK_0 : in std_logic; DCM_LOCKED_0 : in std_logic; -- Asynchronous Reset RESET : in std_logic ); end v5_emac_v1_8; architecture WRAPPER of v5_emac_v1_8 is ---------------------------------------------------------------------------- -- Attribute declarations ---------------------------------------------------------------------------- attribute X_CORE_INFO : string; attribute X_CORE_INFO of WRAPPER : architecture is "v5_emac_v1_8, Coregen 13.1"; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of WRAPPER : architecture is "v5_emac_v1_8,v5_emac_v1_8,{c_emac0=true,c_emac1=false,c_has_mii_emac0=false,c_has_mii_emac1=false,c_has_gmii_emac0=true,c_has_gmii_emac1=true,c_has_rgmii_v1_3_emac0=false,c_has_rgmii_v1_3_emac1=false,c_has_rgmii_v2_0_emac0=false,c_has_rgmii_v2_0_emac1=false,c_has_sgmii_emac0=false,c_has_sgmii_emac1=false,c_has_gpcs_emac0=false,c_has_gpcs_emac1=false,c_tri_speed_emac0=false,c_tri_speed_emac1=false,c_speed_10_emac0=false,c_speed_10_emac1=false,c_speed_100_emac0=false,c_speed_100_emac1=false,c_speed_1000_emac0=true,c_speed_1000_emac1=true,c_has_host=false,c_has_dcr=false,c_has_mdio_emac0=false,c_has_mdio_emac1=false,c_client_16_emac0=false,c_client_16_emac1=false,c_add_filter_emac0=false,c_add_filter_emac1=false,c_has_clock_enable_emac0=false,c_has_clock_enable_emac1=false,}"; -------- -- EMAC0 -------- -- PCS/PMA logic is not in use constant EMAC0_PHYINITAUTONEG_ENABLE : boolean := FALSE; constant EMAC0_PHYISOLATE : boolean := FALSE; constant EMAC0_PHYLOOPBACKMSB : boolean := FALSE; constant EMAC0_PHYPOWERDOWN : boolean := FALSE; constant EMAC0_PHYRESET : boolean := TRUE; constant EMAC0_CONFIGVEC_79 : boolean := FALSE; constant EMAC0_GTLOOPBACK : boolean := FALSE; constant EMAC0_UNIDIRECTION_ENABLE : boolean := FALSE; constant EMAC0_LINKTIMERVAL : bit_vector := x"000"; -- Configure the MAC operating mode -- MDIO is not enabled constant EMAC0_MDIO_ENABLE : boolean := FALSE; -- Speed is defaulted to 1000Mb/s constant EMAC0_SPEED_LSB : boolean := FALSE; constant EMAC0_SPEED_MSB : boolean := TRUE; constant EMAC0_USECLKEN : boolean := FALSE; constant EMAC0_BYTEPHY : boolean := FALSE; constant EMAC0_RGMII_ENABLE : boolean := FALSE; constant EMAC0_SGMII_ENABLE : boolean := FALSE; constant EMAC0_1000BASEX_ENABLE : boolean := FALSE; -- The Host I/F is not in use constant EMAC0_HOST_ENABLE : boolean := FALSE; -- 8-bit interface for Tx client constant EMAC0_TX16BITCLIENT_ENABLE : boolean := FALSE; -- 8-bit interface for Rx client constant EMAC0_RX16BITCLIENT_ENABLE : boolean := FALSE; -- The Address Filter (not enabled) constant EMAC0_ADDRFILTER_ENABLE : boolean := FALSE; -- MAC configuration defaults -- Rx Length/Type checking enabled (standard IEEE operation) constant EMAC0_LTCHECK_DISABLE : boolean := FALSE; -- Rx Flow Control (not enabled) constant EMAC0_RXFLOWCTRL_ENABLE : boolean := FALSE; -- Tx Flow Control (not enabled) constant EMAC0_TXFLOWCTRL_ENABLE : boolean := FALSE; -- Transmitter is not held in reset not asserted (normal operating mode) constant EMAC0_TXRESET : boolean := FALSE; -- Transmitter Jumbo Frames (not enabled) constant EMAC0_TXJUMBOFRAME_ENABLE : boolean := FALSE; -- Transmitter In-band FCS (not enabled) constant EMAC0_TXINBANDFCS_ENABLE : boolean := FALSE; -- Transmitter Enabled constant EMAC0_TX_ENABLE : boolean := TRUE; -- Transmitter VLAN mode (not enabled) constant EMAC0_TXVLAN_ENABLE : boolean := FALSE; -- Transmitter Half Duplex mode (not enabled) constant EMAC0_TXHALFDUPLEX : boolean := FALSE; -- Transmitter IFG Adjust (not enabled) constant EMAC0_TXIFGADJUST_ENABLE : boolean := FALSE; -- Receiver is not held in reset not asserted (normal operating mode) constant EMAC0_RXRESET : boolean := FALSE; -- Receiver Jumbo Frames (not enabled) constant EMAC0_RXJUMBOFRAME_ENABLE : boolean := FALSE; -- Receiver In-band FCS (not enabled) constant EMAC0_RXINBANDFCS_ENABLE : boolean := FALSE; -- Receiver Enabled constant EMAC0_RX_ENABLE : boolean := TRUE; -- Receiver VLAN mode (not enabled) constant EMAC0_RXVLAN_ENABLE : boolean := FALSE; -- Receiver Half Duplex mode (not enabled) constant EMAC0_RXHALFDUPLEX : boolean := FALSE; -- Set the Pause Address Default constant EMAC0_PAUSEADDR : bit_vector := x"FFEEDDCCBBAA"; constant EMAC0_UNICASTADDR : bit_vector := x"000000000000"; constant EMAC0_DCRBASEADDR : bit_vector := X"00"; ---------------------------------------------------------------------------- -- Signals Declarations ---------------------------------------------------------------------------- signal gnd_v48_i : std_logic_vector(47 downto 0); signal client_rx_data_0_i : std_logic_vector(15 downto 0); signal client_tx_data_0_i : std_logic_vector(15 downto 0); signal client_tx_data_valid_0_i : std_logic; signal client_tx_data_valid_msb_0_i : std_logic; begin ---------------------------------------------------------------------------- -- Main Body of Code ---------------------------------------------------------------------------- gnd_v48_i <= "000000000000000000000000000000000000000000000000"; -- 8-bit client data on EMAC0 EMAC0CLIENTRXD <= client_rx_data_0_i(7 downto 0); client_tx_data_0_i <= "00000000" & CLIENTEMAC0TXD after 4 ns; client_tx_data_valid_0_i <= CLIENTEMAC0TXDVLD after 4 ns; client_tx_data_valid_msb_0_i <= '0'; ---------------------------------------------------------------------------- -- Instantiate the Virtex-5 Embedded Ethernet EMAC ---------------------------------------------------------------------------- v5_emac : TEMAC generic map ( EMAC0_1000BASEX_ENABLE => EMAC0_1000BASEX_ENABLE, EMAC0_ADDRFILTER_ENABLE => EMAC0_ADDRFILTER_ENABLE, EMAC0_BYTEPHY => EMAC0_BYTEPHY, EMAC0_CONFIGVEC_79 => EMAC0_CONFIGVEC_79, EMAC0_DCRBASEADDR => EMAC0_DCRBASEADDR, EMAC0_GTLOOPBACK => EMAC0_GTLOOPBACK, EMAC0_HOST_ENABLE => EMAC0_HOST_ENABLE, EMAC0_LINKTIMERVAL => EMAC0_LINKTIMERVAL(3 to 11), EMAC0_LTCHECK_DISABLE => EMAC0_LTCHECK_DISABLE, EMAC0_MDIO_ENABLE => EMAC0_MDIO_ENABLE, EMAC0_PAUSEADDR => EMAC0_PAUSEADDR, EMAC0_PHYINITAUTONEG_ENABLE => EMAC0_PHYINITAUTONEG_ENABLE, EMAC0_PHYISOLATE => EMAC0_PHYISOLATE, EMAC0_PHYLOOPBACKMSB => EMAC0_PHYLOOPBACKMSB, EMAC0_PHYPOWERDOWN => EMAC0_PHYPOWERDOWN, EMAC0_PHYRESET => EMAC0_PHYRESET, EMAC0_RGMII_ENABLE => EMAC0_RGMII_ENABLE, EMAC0_RX16BITCLIENT_ENABLE => EMAC0_RX16BITCLIENT_ENABLE, EMAC0_RXFLOWCTRL_ENABLE => EMAC0_RXFLOWCTRL_ENABLE, EMAC0_RXHALFDUPLEX => EMAC0_RXHALFDUPLEX, EMAC0_RXINBANDFCS_ENABLE => EMAC0_RXINBANDFCS_ENABLE, EMAC0_RXJUMBOFRAME_ENABLE => EMAC0_RXJUMBOFRAME_ENABLE, EMAC0_RXRESET => EMAC0_RXRESET, EMAC0_RXVLAN_ENABLE => EMAC0_RXVLAN_ENABLE, EMAC0_RX_ENABLE => EMAC0_RX_ENABLE, EMAC0_SGMII_ENABLE => EMAC0_SGMII_ENABLE, EMAC0_SPEED_LSB => EMAC0_SPEED_LSB, EMAC0_SPEED_MSB => EMAC0_SPEED_MSB, EMAC0_TX16BITCLIENT_ENABLE => EMAC0_TX16BITCLIENT_ENABLE, EMAC0_TXFLOWCTRL_ENABLE => EMAC0_TXFLOWCTRL_ENABLE, EMAC0_TXHALFDUPLEX => EMAC0_TXHALFDUPLEX, EMAC0_TXIFGADJUST_ENABLE => EMAC0_TXIFGADJUST_ENABLE, EMAC0_TXINBANDFCS_ENABLE => EMAC0_TXINBANDFCS_ENABLE, EMAC0_TXJUMBOFRAME_ENABLE => EMAC0_TXJUMBOFRAME_ENABLE, EMAC0_TXRESET => EMAC0_TXRESET, EMAC0_TXVLAN_ENABLE => EMAC0_TXVLAN_ENABLE, EMAC0_TX_ENABLE => EMAC0_TX_ENABLE, EMAC0_UNICASTADDR => EMAC0_UNICASTADDR, EMAC0_UNIDIRECTION_ENABLE => EMAC0_UNIDIRECTION_ENABLE, EMAC0_USECLKEN => EMAC0_USECLKEN, EMAC1_LINKTIMERVAL => "000000000" ) port map ( RESET => RESET, -- EMAC0 EMAC0CLIENTRXCLIENTCLKOUT => EMAC0CLIENTRXCLIENTCLKOUT, CLIENTEMAC0RXCLIENTCLKIN => CLIENTEMAC0RXCLIENTCLKIN, EMAC0CLIENTRXD => client_rx_data_0_i, EMAC0CLIENTRXDVLD => EMAC0CLIENTRXDVLD, EMAC0CLIENTRXDVLDMSW => EMAC0CLIENTRXDVLDMSW, EMAC0CLIENTRXGOODFRAME => EMAC0CLIENTRXGOODFRAME, EMAC0CLIENTRXBADFRAME => EMAC0CLIENTRXBADFRAME, EMAC0CLIENTRXFRAMEDROP => EMAC0CLIENTRXFRAMEDROP, EMAC0CLIENTRXSTATS => EMAC0CLIENTRXSTATS, EMAC0CLIENTRXSTATSVLD => EMAC0CLIENTRXSTATSVLD, EMAC0CLIENTRXSTATSBYTEVLD => EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTTXCLIENTCLKOUT => EMAC0CLIENTTXCLIENTCLKOUT, CLIENTEMAC0TXCLIENTCLKIN => CLIENTEMAC0TXCLIENTCLKIN, CLIENTEMAC0TXD => client_tx_data_0_i, CLIENTEMAC0TXDVLD => client_tx_data_valid_0_i, CLIENTEMAC0TXDVLDMSW => client_tx_data_valid_msb_0_i, EMAC0CLIENTTXACK => EMAC0CLIENTTXACK, CLIENTEMAC0TXFIRSTBYTE => CLIENTEMAC0TXFIRSTBYTE, CLIENTEMAC0TXUNDERRUN => CLIENTEMAC0TXUNDERRUN, EMAC0CLIENTTXCOLLISION => EMAC0CLIENTTXCOLLISION, EMAC0CLIENTTXRETRANSMIT => EMAC0CLIENTTXRETRANSMIT, CLIENTEMAC0TXIFGDELAY => CLIENTEMAC0TXIFGDELAY, EMAC0CLIENTTXSTATS => EMAC0CLIENTTXSTATS, EMAC0CLIENTTXSTATSVLD => EMAC0CLIENTTXSTATSVLD, EMAC0CLIENTTXSTATSBYTEVLD => EMAC0CLIENTTXSTATSBYTEVLD, CLIENTEMAC0PAUSEREQ => CLIENTEMAC0PAUSEREQ, CLIENTEMAC0PAUSEVAL => CLIENTEMAC0PAUSEVAL, PHYEMAC0GTXCLK => GTX_CLK_0, PHYEMAC0TXGMIIMIICLKIN => PHYEMAC0TXGMIIMIICLKIN, EMAC0PHYTXGMIIMIICLKOUT => EMAC0PHYTXGMIIMIICLKOUT, PHYEMAC0RXCLK => GMII_RX_CLK_0, PHYEMAC0RXD => GMII_RXD_0, PHYEMAC0RXDV => GMII_RX_DV_0, PHYEMAC0RXER => GMII_RX_ER_0, EMAC0PHYTXCLK => open, EMAC0PHYTXD => GMII_TXD_0, EMAC0PHYTXEN => GMII_TX_EN_0, EMAC0PHYTXER => GMII_TX_ER_0, PHYEMAC0MIITXCLK => '0', PHYEMAC0COL => '0', PHYEMAC0CRS => '0', CLIENTEMAC0DCMLOCKED => DCM_LOCKED_0, EMAC0CLIENTANINTERRUPT => open, PHYEMAC0SIGNALDET => '0', PHYEMAC0PHYAD => gnd_v48_i(4 downto 0), EMAC0PHYENCOMMAALIGN => open, EMAC0PHYLOOPBACKMSB => open, EMAC0PHYMGTRXRESET => open, EMAC0PHYMGTTXRESET => open, EMAC0PHYPOWERDOWN => open, EMAC0PHYSYNCACQSTATUS => open, PHYEMAC0RXCLKCORCNT => gnd_v48_i(2 downto 0), PHYEMAC0RXBUFSTATUS => gnd_v48_i(1 downto 0), PHYEMAC0RXBUFERR => '0', PHYEMAC0RXCHARISCOMMA => '0', PHYEMAC0RXCHARISK => '0', PHYEMAC0RXCHECKINGCRC => '0', PHYEMAC0RXCOMMADET => '0', PHYEMAC0RXDISPERR => '0', PHYEMAC0RXLOSSOFSYNC => gnd_v48_i(1 downto 0), PHYEMAC0RXNOTINTABLE => '0', PHYEMAC0RXRUNDISP => '0', PHYEMAC0TXBUFERR => '0', EMAC0PHYTXCHARDISPMODE => open, EMAC0PHYTXCHARDISPVAL => open, EMAC0PHYTXCHARISK => open, EMAC0PHYMCLKOUT => open, PHYEMAC0MCLKIN => '0', PHYEMAC0MDIN => '1', EMAC0PHYMDOUT => open, EMAC0PHYMDTRI => open, EMAC0SPEEDIS10100 => open, -- EMAC1 EMAC1CLIENTRXCLIENTCLKOUT => open, CLIENTEMAC1RXCLIENTCLKIN => '0', EMAC1CLIENTRXD => open, EMAC1CLIENTRXDVLD => open, EMAC1CLIENTRXDVLDMSW => open, EMAC1CLIENTRXGOODFRAME => open, EMAC1CLIENTRXBADFRAME => open, EMAC1CLIENTRXFRAMEDROP => open, EMAC1CLIENTRXSTATS => open, EMAC1CLIENTRXSTATSVLD => open, EMAC1CLIENTRXSTATSBYTEVLD => open, EMAC1CLIENTTXCLIENTCLKOUT => open, CLIENTEMAC1TXCLIENTCLKIN => '0', CLIENTEMAC1TXD => gnd_v48_i(15 downto 0), CLIENTEMAC1TXDVLD => '0', CLIENTEMAC1TXDVLDMSW => '0', EMAC1CLIENTTXACK => open, CLIENTEMAC1TXFIRSTBYTE => '0', CLIENTEMAC1TXUNDERRUN => '0', EMAC1CLIENTTXCOLLISION => open, EMAC1CLIENTTXRETRANSMIT => open, CLIENTEMAC1TXIFGDELAY => gnd_v48_i(7 downto 0), EMAC1CLIENTTXSTATS => open, EMAC1CLIENTTXSTATSVLD => open, EMAC1CLIENTTXSTATSBYTEVLD => open, CLIENTEMAC1PAUSEREQ => '0', CLIENTEMAC1PAUSEVAL => gnd_v48_i(15 downto 0), PHYEMAC1GTXCLK => '0', PHYEMAC1TXGMIIMIICLKIN => '0', EMAC1PHYTXGMIIMIICLKOUT => open, PHYEMAC1RXCLK => '0', PHYEMAC1RXD => gnd_v48_i(7 downto 0), PHYEMAC1RXDV => '0', PHYEMAC1RXER => '0', PHYEMAC1MIITXCLK => '0', EMAC1PHYTXCLK => open, EMAC1PHYTXD => open, EMAC1PHYTXEN => open, EMAC1PHYTXER => open, PHYEMAC1COL => '0', PHYEMAC1CRS => '0', CLIENTEMAC1DCMLOCKED => '1', EMAC1CLIENTANINTERRUPT => open, PHYEMAC1SIGNALDET => '0', PHYEMAC1PHYAD => gnd_v48_i(4 downto 0), EMAC1PHYENCOMMAALIGN => open, EMAC1PHYLOOPBACKMSB => open, EMAC1PHYMGTRXRESET => open, EMAC1PHYMGTTXRESET => open, EMAC1PHYPOWERDOWN => open, EMAC1PHYSYNCACQSTATUS => open, PHYEMAC1RXCLKCORCNT => gnd_v48_i(2 downto 0), PHYEMAC1RXBUFSTATUS => gnd_v48_i(1 downto 0), PHYEMAC1RXBUFERR => '0', PHYEMAC1RXCHARISCOMMA => '0', PHYEMAC1RXCHARISK => '0', PHYEMAC1RXCHECKINGCRC => '0', PHYEMAC1RXCOMMADET => '0', PHYEMAC1RXDISPERR => '0', PHYEMAC1RXLOSSOFSYNC => gnd_v48_i(1 downto 0), PHYEMAC1RXNOTINTABLE => '0', PHYEMAC1RXRUNDISP => '0', PHYEMAC1TXBUFERR => '0', EMAC1PHYTXCHARDISPMODE => open, EMAC1PHYTXCHARDISPVAL => open, EMAC1PHYTXCHARISK => open, EMAC1PHYMCLKOUT => open, PHYEMAC1MCLKIN => '0', PHYEMAC1MDIN => '0', EMAC1PHYMDOUT => open, EMAC1PHYMDTRI => open, EMAC1SPEEDIS10100 => open, -- Host Interface HOSTCLK => '0', HOSTOPCODE => gnd_v48_i(1 downto 0), HOSTREQ => '0', HOSTMIIMSEL => '0', HOSTADDR => gnd_v48_i(9 downto 0), HOSTWRDATA => gnd_v48_i(31 downto 0), HOSTMIIMRDY => open, HOSTRDDATA => open, HOSTEMAC1SEL => '0', -- DCR Interface DCREMACCLK => '0', DCREMACABUS => gnd_v48_i(9 downto 0), DCREMACREAD => '0', DCREMACWRITE => '0', DCREMACDBUS => gnd_v48_i(31 downto 0), EMACDCRACK => open, EMACDCRDBUS => open, DCREMACENABLE => '0', DCRHOSTDONEIR => open ); end WRAPPER;