##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Sat Feb 16 18:59:05 2013
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:v5_emac:1.8
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc5vtx240t
SET devicefamily = virtex5
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1759
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Virtex-5_Embedded_Tri-Mode_Ethernet_MAC_Wrapper xilinx.com:ip:v5_emac:1.8
# END Select
# BEGIN Parameters
CSET address_filter_enable_0=false
CSET address_filter_enable_1=false
CSET byte_phy_0=false
CSET byte_phy_1=false
CSET client_side_data_width_0=8_bit
CSET client_side_data_width_1=8_bit
CSET clock_enable_0=false
CSET clock_enable_1=false
CSET component_name=v5_emac_v1_8_serdes
CSET dcr_base_address_0=00
CSET dcr_base_address_1=01
CSET enable_emac0=true
CSET enable_emac1=false
CSET host_type=None
CSET mdio_0=false
CSET mdio_1=false
CSET phy_an_enable_0=false
CSET phy_an_enable_1=false
CSET phy_isolate_0=false
CSET phy_isolate_1=false
CSET phy_link_timer_value_0=13D
CSET phy_link_timer_value_1=13D
CSET phy_loopback_in_gtp_0=false
CSET phy_loopback_in_gtp_1=false
CSET phy_loopback_msb_0=false
CSET phy_loopback_msb_1=false
CSET phy_powerdown_0=false
CSET phy_powerdown_1=false
CSET phy_reset_0=false
CSET phy_reset_1=false
CSET phy_unidirection_enable_0=false
CSET phy_unidirection_enable_1=false
CSET physical_interface_0=1000BASE_X_PCS_PMA
CSET physical_interface_1=GMII
CSET rx_disable_length_0=false
CSET rx_disable_length_1=false
CSET rx_enable_0=true
CSET rx_enable_1=true
CSET rx_flow_control_enable_0=false
CSET rx_flow_control_enable_1=false
CSET rx_half_duplex_enable_0=false
CSET rx_half_duplex_enable_1=false
CSET rx_in_band_fcs_enable_0=false
CSET rx_in_band_fcs_enable_1=false
CSET rx_jumbo_frame_enable_0=false
CSET rx_jumbo_frame_enable_1=false
CSET rx_reset_0=false
CSET rx_reset_1=false
CSET rx_vlan_enable_0=false
CSET rx_vlan_enable_1=false
CSET sgmii_mode_0=No_clock
CSET sgmii_mode_1=No_clock
CSET speed_0=1000_Mbps
CSET speed_1=1000_Mbps
CSET tx_enable_0=true
CSET tx_enable_1=true
CSET tx_flow_control_enable_0=false
CSET tx_flow_control_enable_1=false
CSET tx_half_duplex_enable_0=false
CSET tx_half_duplex_enable_1=false
CSET tx_ifg_adjust_enable_0=false
CSET tx_ifg_adjust_enable_1=false
CSET tx_in_band_fcs_enable_0=false
CSET tx_in_band_fcs_enable_1=false
CSET tx_jumbo_frame_enable_0=false
CSET tx_jumbo_frame_enable_1=false
CSET tx_reset_0=false
CSET tx_reset_1=false
CSET tx_vlan_enable_0=false
CSET tx_vlan_enable_1=false
CSET unicast_pause_mac_address_0_1=AA
CSET unicast_pause_mac_address_0_2=BB
CSET unicast_pause_mac_address_0_3=CC
CSET unicast_pause_mac_address_0_4=DD
CSET unicast_pause_mac_address_0_5=EE
CSET unicast_pause_mac_address_0_6=FF
CSET unicast_pause_mac_address_1_1=AA
CSET unicast_pause_mac_address_1_2=BB
CSET unicast_pause_mac_address_1_3=CC
CSET unicast_pause_mac_address_1_4=DD
CSET unicast_pause_mac_address_1_5=EE
CSET unicast_pause_mac_address_1_6=FF
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-10-13T03:17:13Z
# END Extra information
GENERATE
# CRC: 48b834e3