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#
# Xilinx Core Generator version 14.3
# Date: Sun Jan 20 14:14:23 2013
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
#  Generated from component: xilinx.com:ip:tri_mode_eth_mac:5.4
#
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#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Tri_Mode_Ethernet_MAC xilinx.com:ip:tri_mode_eth_mac:5.4
# END Select
# BEGIN Parameters
CSET component_name=tri_mode_eth_mac_v5_4_serdes
CSET enable_avb=false
CSET frame_filter=false
CSET half_duplex=false
CSET mac_speed=1000_Mbps
CSET management_interface=false
CSET number_of_table_entries=0
CSET physical_interface=Internal
CSET statistics_counters=false
CSET statistics_reset=true
CSET statistics_width=64bit
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-06-05T21:10:47Z
# END Extra information
GENERATE
# CRC: b0182b60