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#
# Xilinx Core Generator version 14.5
# Date: Sun Apr 21 16:48:00 2013
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
#  Generated from component: xilinx.com:ip:gig_eth_pcs_pma:11.5
#
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#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7vx690t
SET devicefamily = virtex7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1927
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.5
# END Select
# BEGIN Parameters
CSET auto_negotiation=false
CSET component_name=gig_eth_pcs_pma_v11_5
CSET enable_1588=false
CSET management_interface=false
CSET physical_interface=Transceiver
CSET sgmii_mode=10_100_1000
CSET sgmii_phy_mode=false
CSET standard=1000BASEX
CSET timing_sim=false
CSET transceiver_tile=A
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-07-11T07:25:50Z
# END Extra information
GENERATE
# CRC: 60dd7405