#-----------------------------------------------------------
# Vivado v2014.4.1 (64-bit)
# SW Build 1149489 on Thu Feb 19 16:23:09 MST 2015
# IP Build 1147552 on Wed Feb 18 14:25:16 MST 2015
# Start of session at: Wed Apr 22 08:22:41 2015
# Process ID: 6800
# Log file: C:/Users/adowd/AppData/Roaming/Xilinx/Vivado/vivado.log
# Journal file: C:/Users/adowd/AppData/Roaming/Xilinx/Vivado\vivado.jou
#-----------------------------------------------------------
start_gui
open_project C:/export/uaphysics/atlas/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2014.4/data/ip'.
open_project: Time (s): cpu = 00:00:33 ; elapsed = 00:00:19 . Memory (MB): peak = 785.867 ; gain = 231.457
archive_project C:/export/uaphysics/atlas/a7_mmfe_xadc_udp_v2.xpr.zip -force -exclude_run_results
INFO: [Coretcl 2-137] starting archive...
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2014.4/data/ip'.
INFO: [Coretcl 2-1211] Creating project copy for archival...
INFO: [Project 1-495] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience any problem with archiving the project, please consider setting environment variable $TEMP to a shorter path.
Current project path is 'C:/Users/adowd/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-6800-lithe-ad-work/PrjAr/_X_'.
INFO: [Coretcl 2-135] resetting runs for excluding generated files from archive...
WARNING: [Coretcl 2-105] Run 'synth_1' is currently active
INFO: [Coretcl 2-133] re-setting run 'synth_1'...
WARNING: [Coretcl 2-105] Run 'ila_0_synth_1' is currently active
INFO: [Coretcl 2-133] re-setting run 'ila_0_synth_1'...
WARNING: [Coretcl 2-105] Run 'clk_wiz_0_synth_1' is currently active
INFO: [Coretcl 2-133] re-setting run 'clk_wiz_0_synth_1'...
INFO: [Coretcl 2-133] re-setting run 'impl_1'...
INFO: [Coretcl 2-133] re-setting run 'ila_0_impl_1'...
INFO: [Coretcl 2-133] re-setting run 'clk_wiz_0_impl_1'...
INFO: [Coretcl 2-1212] Importing remotely added design sources and verilog include files (if any)...
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'sources_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'ila_0'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'ila_0'
INFO: [filemgmt 20-334] All file(s) are already imported in fileset: 'clk_wiz_0'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'clk_wiz_0'