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All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: counter_f.vhd -- -- Description: Implements a parameterizable N-bit counter_f -- Up/Down Counter -- Count Enable -- Parallel Load -- Synchronous Reset -- The structural implementation has incremental cost -- of one LUT per bit. -- Precedence of operations when simultaneous: -- reset, load, count -- -- A default inferred-RTL implementation is provided and -- is used if the user explicitly specifies C_FAMILY=nofamily -- or ommits C_FAMILY (allowing it to default to nofamily). -- The default implementation is also used -- if needed primitives are not available in FPGAs of the -- type given by C_FAMILY. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- counter_f.vhd -- family_support.vhd -- ------------------------------------------------------------------------------- -- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent -- of counter.vhd. -- History: -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.unsigned; use IEEE.numeric_std."+"; use IEEE.numeric_std."-"; library unisim; use unisim.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity counter_f is generic( C_NUM_BITS : integer := 9; C_FAMILY : string := "nofamily" ); port( Clk : in std_logic; Rst : in std_logic; Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0); Count_Enable : in std_logic; Count_Load : in std_logic; Count_Down : in std_logic; Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0); Carry_Out : out std_logic ); end entity counter_f; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of counter_f is --------------------------------------------------------------------- -- Begin architecture --------------------------------------------------------------------- begin INFERRED_GEN : if (true) generate signal icount_out : unsigned(C_NUM_BITS downto 0); signal icount_out_x : unsigned(C_NUM_BITS downto 0); signal load_in_x : unsigned(C_NUM_BITS downto 0); begin load_in_x <= unsigned('0' & Load_In); -- Mask out carry position to retain legacy self-clear on next enable. -- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0))); ----------------------------------------------------------------- -- Process to generate counter with - synchronous reset, load, -- counter enable, count down / up features. ----------------------------------------------------------------- CNTR_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Rst = '1' then icount_out <= (others => '0'); elsif Count_Load = '1' then icount_out <= load_in_x; elsif Count_Down = '1' and Count_Enable = '1' then icount_out <= icount_out_x - 1; elsif Count_Enable = '1' then icount_out <= icount_out_x + 1; end if; end if; end process CNTR_PROC; Carry_Out <= icount_out(C_NUM_BITS); Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)); end generate INFERRED_GEN; end architecture imp; --------------------------------------------------------------- -- End of file counter_f.vhd ---------------------------------------------------------------