// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:20:35 MST 2015
// Date        : Wed Apr 22 09:07:53 2015
// Host        : phys-pc458-4 running 64-bit Service Pack 1  (build 7601)
// Command     : write_verilog -force -mode funcsim
//               C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/ila_0/ila_0_funcsim.v
// Design      : ila_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a200tfbg484-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ila,Vivado 2014.4.1" *) (* CHECK_LICENSE_TYPE = "ila_0,ila_v5_0_ila,{}" *) 
(* core_generation_info = "ila_0,ila,{x_ipProduct=Vivado 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_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1002_WIDTH=1,C_PROBE1003_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=1,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1}" *) 
(* NotValidForBitStream *)
module ila_0
   (clk,
    probe0,
    probe1,
    probe2,
    probe3,
    probe4,
    probe5,
    probe6,
    probe7,
    probe8,
    probe9,
    probe10,
    probe11,
    probe12);
  input clk;
  input [31:0]probe0;
  input [0:0]probe1;
  input [0:0]probe2;
  input [31:0]probe3;
  input [0:0]probe4;
  input [0:0]probe5;
  input [31:0]probe6;
  input [0:0]probe7;
  input [0:0]probe8;
  input [31:0]probe9;
  input [0:0]probe10;
  input [0:0]probe11;
  input [3:0]probe12;

  wire clk;
  wire [31:0]probe0;
  wire [0:0]probe1;
  wire [0:0]probe10;
  wire [0:0]probe11;
  wire [3:0]probe12;
  wire [0:0]probe2;
  wire [31:0]probe3;
  wire [0:0]probe4;
  wire [0:0]probe5;
  wire [31:0]probe6;
  wire [0:0]probe7;
  wire [0:0]probe8;
  wire [31:0]probe9;
  wire NLW_U0_trig_in_ack_UNCONNECTED;
  wire NLW_U0_trig_out_UNCONNECTED;
  wire [16:0]NLW_U0_sl_oport0_UNCONNECTED;

(* C_ADV_TRIGGER = "1" *) 
   (* C_BUILD_REVISION = "0" *) 
   (* C_CAPTURE_TYPE = "0" *) 
   (* C_CORE_INFO1 = "0" *) 
   (* C_CORE_INFO2 = "0" *) 
   (* C_CORE_MAJOR_VER = "4" *) 
   (* C_CORE_MINOR_VER = "0" *) 
   (* C_CORE_TYPE = "1" *) 
   (* C_CSE_DRV_VER = "1" *) 
   (* C_DATA_DEPTH = "1024" *) 
   (* C_ENABLE_ILA_AXI_MON = "0" *) 
   (* C_EN_STRG_QUAL = "0" *) 
   (* C_INPUT_PIPE_STAGES = "0" *) 
   (* C_MAJOR_VERSION = "2013" *) 
   (* C_MINOR_VERSION = "3" *) 
   (* C_MU_TYPE = "0" *) 
   (* C_NEXT_SLAVE = "0" *) 
   (* C_NUM_MONITOR_SLOTS = "1" *) 
   (* C_NUM_OF_PROBES = "13" *) 
   (* C_PIPE_IFACE = "1" *) 
   (* C_PROBE0_MU_CNT = "1" *) 
   (* C_PROBE0_WIDTH = "32" *) 
   (* C_PROBE1000_MU_CNT = "1" *) 
   (* C_PROBE1000_WIDTH = "1" *) 
   (* C_PROBE1001_MU_CNT = "1" *) 
   (* C_PROBE1001_WIDTH = "1" *) 
   (* C_PROBE1002_MU_CNT = "1" *) 
   (* C_PROBE1002_WIDTH = "1" *) 
   (* C_PROBE1003_MU_CNT = "1" *) 
   (* C_PROBE1003_WIDTH = "1" *) 
   (* C_PROBE1004_MU_CNT = "1" *) 
   (* C_PROBE1004_WIDTH = "1" *) 
   (* C_PROBE1005_MU_CNT = "1" *) 
   (* C_PROBE1005_WIDTH = "1" *) 
   (* C_PROBE1006_MU_CNT = "1" *) 
   (* C_PROBE1006_WIDTH = "1" *) 
   (* C_PROBE1007_MU_CNT = "1" *) 
   (* C_PROBE1007_WIDTH = "1" *) 
   (* C_PROBE1008_MU_CNT = "1" *) 
   (* C_PROBE1008_WIDTH = "1" *) 
   (* C_PROBE1009_MU_CNT = "1" *) 
   (* C_PROBE1009_WIDTH = "1" *) 
   (* C_PROBE100_MU_CNT = "1" *) 
   (* C_PROBE100_WIDTH = "1" *) 
   (* C_PROBE1010_MU_CNT = "1" *) 
   (* C_PROBE1010_WIDTH = "1" *) 
   (* C_PROBE1011_MU_CNT = "1" *) 
   (* C_PROBE1011_WIDTH = "1" *) 
   (* C_PROBE1012_MU_CNT = "1" *) 
   (* C_PROBE1012_WIDTH = "1" *) 
   (* C_PROBE1013_MU_CNT = "1" *) 
   (* C_PROBE1013_WIDTH = "1" *) 
   (* C_PROBE1014_MU_CNT = "1" *) 
   (* C_PROBE1014_WIDTH = "1" *) 
   (* C_PROBE1015_MU_CNT = "1" *) 
   (* C_PROBE1015_WIDTH = "1" *) 
   (* C_PROBE1016_MU_CNT = "1" *) 
   (* C_PROBE1016_WIDTH = "1" *) 
   (* C_PROBE1017_MU_CNT = "1" *) 
   (* C_PROBE1017_WIDTH = "1" *) 
   (* C_PROBE1018_MU_CNT = "1" *) 
   (* C_PROBE1018_WIDTH = "1" *) 
   (* C_PROBE1019_MU_CNT = "1" *) 
   (* C_PROBE1019_WIDTH = "1" *) 
   (* C_PROBE101_MU_CNT = "1" *) 
   (* C_PROBE101_WIDTH = "1" *) 
   (* C_PROBE1020_MU_CNT = "1" *) 
   (* C_PROBE1020_WIDTH = "1" *) 
   (* C_PROBE1021_MU_CNT = "1" *) 
   (* C_PROBE1021_WIDTH = "1" *) 
   (* C_PROBE1022_MU_CNT = "1" *) 
   (* C_PROBE1022_WIDTH = "1" *) 
   (* C_PROBE1023_MU_CNT = "1" *) 
   (* C_PROBE1023_WIDTH = "1" *) 
   (* C_PROBE102_MU_CNT = "1" *) 
   (* C_PROBE102_WIDTH = "1" *) 
   (* C_PROBE103_MU_CNT = "1" *) 
   (* C_PROBE103_WIDTH = "1" *) 
   (* C_PROBE104_MU_CNT = "1" *) 
   (* C_PROBE104_WIDTH = "1" *) 
   (* C_PROBE105_MU_CNT = "1" *) 
   (* C_PROBE105_WIDTH = "1" *) 
   (* C_PROBE106_MU_CNT = "1" *) 
   (* C_PROBE106_WIDTH = "1" *) 
   (* C_PROBE107_MU_CNT = "1" *) 
   (* C_PROBE107_WIDTH = "1" *) 
   (* C_PROBE108_MU_CNT = "1" *) 
   (* C_PROBE108_WIDTH = "1" *) 
   (* C_PROBE109_MU_CNT = "1" *) 
   (* C_PROBE109_WIDTH = "1" *) 
   (* C_PROBE10_MU_CNT = "1" *) 
   (* C_PROBE10_WIDTH = "1" *) 
   (* C_PROBE110_MU_CNT = "1" *) 
   (* C_PROBE110_WIDTH = "1" *) 
   (* C_PROBE111_MU_CNT = "1" *) 
   (* C_PROBE111_WIDTH = "1" *) 
   (* C_PROBE112_MU_CNT = "1" *) 
   (* C_PROBE112_WIDTH = "1" *) 
   (* C_PROBE113_MU_CNT = "1" *) 
   (* C_PROBE113_WIDTH = "1" *) 
   (* C_PROBE114_MU_CNT = "1" *) 
   (* C_PROBE114_WIDTH = "1" *) 
   (* C_PROBE115_MU_CNT = "1" *) 
   (* C_PROBE115_WIDTH = "1" *) 
   (* C_PROBE116_MU_CNT = "1" *) 
   (* C_PROBE116_WIDTH = "1" *) 
   (* C_PROBE117_MU_CNT = "1" *) 
   (* C_PROBE117_WIDTH = "1" *) 
   (* C_PROBE118_MU_CNT = "1" *) 
   (* C_PROBE118_WIDTH = "1" *) 
   (* C_PROBE119_MU_CNT = "1" *) 
   (* C_PROBE119_WIDTH = "1" *) 
   (* C_PROBE11_MU_CNT = "1" *) 
   (* C_PROBE11_WIDTH = "1" *) 
   (* C_PROBE120_MU_CNT = "1" *) 
   (* C_PROBE120_WIDTH = "1" *) 
   (* C_PROBE121_MU_CNT = "1" *) 
   (* C_PROBE121_WIDTH = "1" *) 
   (* C_PROBE122_MU_CNT = "1" *) 
   (* C_PROBE122_WIDTH = "1" *) 
   (* C_PROBE123_MU_CNT = "1" *) 
   (* C_PROBE123_WIDTH = "1" *) 
   (* C_PROBE124_MU_CNT = "1" *) 
   (* C_PROBE124_WIDTH = "1" *) 
   (* C_PROBE125_MU_CNT = "1" *) 
   (* C_PROBE125_WIDTH = "1" *) 
   (* C_PROBE126_MU_CNT = "1" *) 
   (* C_PROBE126_WIDTH = "1" *) 
   (* C_PROBE127_MU_CNT = "1" *) 
   (* C_PROBE127_WIDTH = "1" *) 
   (* C_PROBE128_MU_CNT = "1" *) 
   (* C_PROBE128_WIDTH = "1" *) 
   (* C_PROBE129_MU_CNT = "1" *) 
   (* C_PROBE129_WIDTH = "1" *) 
   (* C_PROBE12_MU_CNT = "1" *) 
   (* C_PROBE12_WIDTH = "4" *) 
   (* C_PROBE130_MU_CNT = "1" *) 
   (* C_PROBE130_WIDTH = "1" *) 
   (* C_PROBE131_MU_CNT = "1" *) 
   (* C_PROBE131_WIDTH = "1" *) 
   (* C_PROBE132_MU_CNT = "1" *) 
   (* C_PROBE132_WIDTH = "1" *) 
   (* C_PROBE133_MU_CNT = "1" *) 
   (* C_PROBE133_WIDTH = "1" *) 
   (* C_PROBE134_MU_CNT = "1" *) 
   (* C_PROBE134_WIDTH = "1" *) 
   (* C_PROBE135_MU_CNT = "1" *) 
   (* C_PROBE135_WIDTH = "1" *) 
   (* C_PROBE136_MU_CNT = "1" *) 
   (* C_PROBE136_WIDTH = "1" *) 
   (* C_PROBE137_MU_CNT = "1" *) 
   (* C_PROBE137_WIDTH = "1" *) 
   (* C_PROBE138_MU_CNT = "1" *) 
   (* C_PROBE138_WIDTH = "1" *) 
   (* C_PROBE139_MU_CNT = "1" *) 
   (* C_PROBE139_WIDTH = "1" *) 
   (* C_PROBE13_MU_CNT = "1" *) 
   (* C_PROBE13_WIDTH = "1" *) 
   (* C_PROBE140_MU_CNT = "1" *) 
   (* C_PROBE140_WIDTH = "1" *) 
   (* C_PROBE141_MU_CNT = "1" *) 
   (* C_PROBE141_WIDTH = "1" *) 
   (* C_PROBE142_MU_CNT = "1" *) 
   (* C_PROBE142_WIDTH = "1" *) 
   (* C_PROBE143_MU_CNT = "1" *) 
   (* C_PROBE143_WIDTH = "1" *) 
   (* C_PROBE144_MU_CNT = "1" *) 
   (* C_PROBE144_WIDTH = "1" *) 
   (* C_PROBE145_MU_CNT = "1" *) 
   (* C_PROBE145_WIDTH = "1" *) 
   (* C_PROBE146_MU_CNT = "1" *) 
   (* C_PROBE146_WIDTH = "1" *) 
   (* C_PROBE147_MU_CNT = "1" *) 
   (* C_PROBE147_WIDTH = "1" *) 
   (* C_PROBE148_MU_CNT = "1" *) 
   (* C_PROBE148_WIDTH = "1" *) 
   (* C_PROBE149_MU_CNT = "1" *) 
   (* C_PROBE149_WIDTH = "1" *) 
   (* C_PROBE14_MU_CNT = "1" *) 
   (* C_PROBE14_WIDTH = "1" *) 
   (* C_PROBE150_MU_CNT = "1" *) 
   (* C_PROBE150_WIDTH = "1" *) 
   (* C_PROBE151_MU_CNT = "1" *) 
   (* C_PROBE151_WIDTH = "1" *) 
   (* C_PROBE152_MU_CNT = "1" *) 
   (* C_PROBE152_WIDTH = "1" *) 
   (* C_PROBE153_MU_CNT = "1" *) 
   (* C_PROBE153_WIDTH = "1" *) 
   (* C_PROBE154_MU_CNT = "1" *) 
   (* C_PROBE154_WIDTH = "1" *) 
   (* C_PROBE155_MU_CNT = "1" *) 
   (* C_PROBE155_WIDTH = "1" *) 
   (* C_PROBE156_MU_CNT = "1" *) 
   (* C_PROBE156_WIDTH = "1" *) 
   (* C_PROBE157_MU_CNT = "1" *) 
   (* C_PROBE157_WIDTH = "1" *) 
   (* C_PROBE158_MU_CNT = "1" *) 
   (* C_PROBE158_WIDTH = "1" *) 
   (* C_PROBE159_MU_CNT = "1" *) 
   (* C_PROBE159_WIDTH = "1" *) 
   (* C_PROBE15_MU_CNT = "1" *) 
   (* C_PROBE15_WIDTH = "1" *) 
   (* C_PROBE160_MU_CNT = "1" *) 
   (* C_PROBE160_WIDTH = "1" *) 
   (* C_PROBE161_MU_CNT = "1" *) 
   (* C_PROBE161_WIDTH = "1" *) 
   (* C_PROBE162_MU_CNT = "1" *) 
   (* C_PROBE162_WIDTH = "1" *) 
   (* C_PROBE163_MU_CNT = "1" *) 
   (* C_PROBE163_WIDTH = "1" *) 
   (* C_PROBE164_MU_CNT = "1" *) 
   (* C_PROBE164_WIDTH = "1" *) 
   (* C_PROBE165_MU_CNT = "1" *) 
   (* C_PROBE165_WIDTH = "1" *) 
   (* C_PROBE166_MU_CNT = "1" *) 
   (* C_PROBE166_WIDTH = "1" *) 
   (* C_PROBE167_MU_CNT = "1" *) 
   (* C_PROBE167_WIDTH = "1" *) 
   (* C_PROBE168_MU_CNT = "1" *) 
   (* C_PROBE168_WIDTH = "1" *) 
   (* C_PROBE169_MU_CNT = "1" *) 
   (* C_PROBE169_WIDTH = "1" *) 
   (* C_PROBE16_MU_CNT = "1" *) 
   (* C_PROBE16_WIDTH = "1" *) 
   (* C_PROBE170_MU_CNT = "1" *) 
   (* C_PROBE170_WIDTH = "1" *) 
   (* C_PROBE171_MU_CNT = "1" *) 
   (* C_PROBE171_WIDTH = "1" *) 
   (* C_PROBE172_MU_CNT = "1" *) 
   (* C_PROBE172_WIDTH = "1" *) 
   (* C_PROBE173_MU_CNT = "1" *) 
   (* C_PROBE173_WIDTH = "1" *) 
   (* C_PROBE174_MU_CNT = "1" *) 
   (* C_PROBE174_WIDTH = "1" *) 
   (* C_PROBE175_MU_CNT = "1" *) 
   (* C_PROBE175_WIDTH = "1" *) 
   (* C_PROBE176_MU_CNT = "1" *) 
   (* C_PROBE176_WIDTH = "1" *) 
   (* C_PROBE177_MU_CNT = "1" *) 
   (* C_PROBE177_WIDTH = "1" *) 
   (* C_PROBE178_MU_CNT = "1" *) 
   (* C_PROBE178_WIDTH = "1" *) 
   (* C_PROBE179_MU_CNT = "1" *) 
   (* C_PROBE179_WIDTH = "1" *) 
   (* C_PROBE17_MU_CNT = "1" *) 
   (* C_PROBE17_WIDTH = "1" *) 
   (* C_PROBE180_MU_CNT = "1" *) 
   (* C_PROBE180_WIDTH = "1" *) 
   (* C_PROBE181_MU_CNT = "1" *) 
   (* C_PROBE181_WIDTH = "1" *) 
   (* C_PROBE182_MU_CNT = "1" *) 
   (* C_PROBE182_WIDTH = "1" *) 
   (* C_PROBE183_MU_CNT = "1" *) 
   (* C_PROBE183_WIDTH = "1" *) 
   (* C_PROBE184_MU_CNT = "1" *) 
   (* C_PROBE184_WIDTH = "1" *) 
   (* C_PROBE185_MU_CNT = "1" *) 
   (* C_PROBE185_WIDTH = "1" *) 
   (* C_PROBE186_MU_CNT = "1" *) 
   (* C_PROBE186_WIDTH = "1" *) 
   (* C_PROBE187_MU_CNT = "1" *) 
   (* C_PROBE187_WIDTH = "1" *) 
   (* C_PROBE188_MU_CNT = "1" *) 
   (* C_PROBE188_WIDTH = "1" *) 
   (* C_PROBE189_MU_CNT = "1" *) 
   (* C_PROBE189_WIDTH = "1" *) 
   (* C_PROBE18_MU_CNT = "1" *) 
   (* C_PROBE18_WIDTH = "1" *) 
   (* C_PROBE190_MU_CNT = "1" *) 
   (* C_PROBE190_WIDTH = "1" *) 
   (* C_PROBE191_MU_CNT = "1" *) 
   (* C_PROBE191_WIDTH = "1" *) 
   (* C_PROBE192_MU_CNT = "1" *) 
   (* C_PROBE192_WIDTH = "1" *) 
   (* C_PROBE193_MU_CNT = "1" *) 
   (* C_PROBE193_WIDTH = "1" *) 
   (* C_PROBE194_MU_CNT = "1" *) 
   (* C_PROBE194_WIDTH = "1" *) 
   (* C_PROBE195_MU_CNT = "1" *) 
   (* C_PROBE195_WIDTH = "1" *) 
   (* C_PROBE196_MU_CNT = "1" *) 
   (* C_PROBE196_WIDTH = "1" *) 
   (* C_PROBE197_MU_CNT = "1" *) 
   (* C_PROBE197_WIDTH = "1" *) 
   (* C_PROBE198_MU_CNT = "1" *) 
   (* C_PROBE198_WIDTH = "1" *) 
   (* C_PROBE199_MU_CNT = "1" *) 
   (* C_PROBE199_WIDTH = "1" *) 
   (* C_PROBE19_MU_CNT = "1" *) 
   (* C_PROBE19_WIDTH = "1" *) 
   (* C_PROBE1_MU_CNT = "1" *) 
   (* C_PROBE1_WIDTH = "1" *) 
   (* C_PROBE200_MU_CNT = "1" *) 
   (* C_PROBE200_WIDTH = "1" *) 
   (* C_PROBE201_MU_CNT = "1" *) 
   (* C_PROBE201_WIDTH = "1" *) 
   (* C_PROBE202_MU_CNT = "1" *) 
   (* C_PROBE202_WIDTH = "1" *) 
   (* C_PROBE203_MU_CNT = "1" *) 
   (* C_PROBE203_WIDTH = "1" *) 
   (* C_PROBE204_MU_CNT = "1" *) 
   (* C_PROBE204_WIDTH = "1" *) 
   (* C_PROBE205_MU_CNT = "1" *) 
   (* C_PROBE205_WIDTH = "1" *) 
   (* C_PROBE206_MU_CNT = "1" *) 
   (* C_PROBE206_WIDTH = "1" *) 
   (* C_PROBE207_MU_CNT = "1" *) 
   (* C_PROBE207_WIDTH = "1" *) 
   (* C_PROBE208_MU_CNT = "1" *) 
   (* C_PROBE208_WIDTH = "1" *) 
   (* C_PROBE209_MU_CNT = "1" *) 
   (* C_PROBE209_WIDTH = "1" *) 
   (* C_PROBE20_MU_CNT = "1" *) 
   (* C_PROBE20_WIDTH = "1" *) 
   (* C_PROBE210_MU_CNT = "1" *) 
   (* C_PROBE210_WIDTH = "1" *) 
   (* C_PROBE211_MU_CNT = "1" *) 
   (* C_PROBE211_WIDTH = "1" *) 
   (* C_PROBE212_MU_CNT = "1" *) 
   (* C_PROBE212_WIDTH = "1" *) 
   (* C_PROBE213_MU_CNT = "1" *) 
   (* C_PROBE213_WIDTH = "1" *) 
   (* C_PROBE214_MU_CNT = "1" *) 
   (* C_PROBE214_WIDTH = "1" *) 
   (* C_PROBE215_MU_CNT = "1" *) 
   (* C_PROBE215_WIDTH = "1" *) 
   (* C_PROBE216_MU_CNT = "1" *) 
   (* C_PROBE216_WIDTH = "1" *) 
   (* C_PROBE217_MU_CNT = "1" *) 
   (* C_PROBE217_WIDTH = "1" *) 
   (* C_PROBE218_MU_CNT = "1" *) 
   (* C_PROBE218_WIDTH = "1" *) 
   (* C_PROBE219_MU_CNT = "1" *) 
   (* C_PROBE219_WIDTH = "1" *) 
   (* C_PROBE21_MU_CNT = "1" *) 
   (* C_PROBE21_WIDTH = "1" *) 
   (* C_PROBE220_MU_CNT = "1" *) 
   (* C_PROBE220_WIDTH = "1" *) 
   (* C_PROBE221_MU_CNT = "1" *) 
   (* C_PROBE221_WIDTH = "1" *) 
   (* C_PROBE222_MU_CNT = "1" *) 
   (* C_PROBE222_WIDTH = "1" *) 
   (* C_PROBE223_MU_CNT = "1" *) 
   (* C_PROBE223_WIDTH = "1" *) 
   (* C_PROBE224_MU_CNT = "1" *) 
   (* C_PROBE224_WIDTH = "1" *) 
   (* C_PROBE225_MU_CNT = "1" *) 
   (* C_PROBE225_WIDTH = "1" *) 
   (* C_PROBE226_MU_CNT = "1" *) 
   (* C_PROBE226_WIDTH = "1" *) 
   (* C_PROBE227_MU_CNT = "1" *) 
   (* C_PROBE227_WIDTH = "1" *) 
   (* C_PROBE228_MU_CNT = "1" *) 
   (* C_PROBE228_WIDTH = "1" *) 
   (* C_PROBE229_MU_CNT = "1" *) 
   (* C_PROBE229_WIDTH = "1" *) 
   (* C_PROBE22_MU_CNT = "1" *) 
   (* C_PROBE22_WIDTH = "1" *) 
   (* C_PROBE230_MU_CNT = "1" *) 
   (* C_PROBE230_WIDTH = "1" *) 
   (* C_PROBE231_MU_CNT = "1" *) 
   (* C_PROBE231_WIDTH = "1" *) 
   (* C_PROBE232_MU_CNT = "1" *) 
   (* C_PROBE232_WIDTH = "1" *) 
   (* C_PROBE233_MU_CNT = "1" *) 
   (* C_PROBE233_WIDTH = "1" *) 
   (* C_PROBE234_MU_CNT = "1" *) 
   (* C_PROBE234_WIDTH = "1" *) 
   (* C_PROBE235_MU_CNT = "1" *) 
   (* C_PROBE235_WIDTH = "1" *) 
   (* C_PROBE236_MU_CNT = "1" *) 
   (* C_PROBE236_WIDTH = "1" *) 
   (* C_PROBE237_MU_CNT = "1" *) 
   (* C_PROBE237_WIDTH = "1" *) 
   (* C_PROBE238_MU_CNT = "1" *) 
   (* C_PROBE238_WIDTH = "1" *) 
   (* C_PROBE239_MU_CNT = "1" *) 
   (* C_PROBE239_WIDTH = "1" *) 
   (* C_PROBE23_MU_CNT = "1" *) 
   (* C_PROBE23_WIDTH = "1" *) 
   (* C_PROBE240_MU_CNT = "1" *) 
   (* C_PROBE240_WIDTH = "1" *) 
   (* C_PROBE241_MU_CNT = "1" *) 
   (* C_PROBE241_WIDTH = "1" *) 
   (* C_PROBE242_MU_CNT = "1" *) 
   (* C_PROBE242_WIDTH = "1" *) 
   (* C_PROBE243_MU_CNT = "1" *) 
   (* C_PROBE243_WIDTH = "1" *) 
   (* C_PROBE244_MU_CNT = "1" *) 
   (* C_PROBE244_WIDTH = "1" *) 
   (* C_PROBE245_MU_CNT = "1" *) 
   (* C_PROBE245_WIDTH = "1" *) 
   (* C_PROBE246_MU_CNT = "1" *) 
   (* C_PROBE246_WIDTH = "1" *) 
   (* C_PROBE247_MU_CNT = "1" *) 
   (* C_PROBE247_WIDTH = "1" *) 
   (* C_PROBE248_MU_CNT = "1" *) 
   (* C_PROBE248_WIDTH = "1" *) 
   (* C_PROBE249_MU_CNT = "1" *) 
   (* C_PROBE249_WIDTH = "1" *) 
   (* C_PROBE24_MU_CNT = "1" *) 
   (* C_PROBE24_WIDTH = "1" *) 
   (* C_PROBE250_MU_CNT = "1" *) 
   (* C_PROBE250_WIDTH = "1" *) 
   (* C_PROBE251_MU_CNT = "1" *) 
   (* C_PROBE251_WIDTH = "1" *) 
   (* C_PROBE252_MU_CNT = "1" *) 
   (* C_PROBE252_WIDTH = "1" *) 
   (* C_PROBE253_MU_CNT = "1" *) 
   (* C_PROBE253_WIDTH = "1" *) 
   (* C_PROBE254_MU_CNT = "1" *) 
   (* C_PROBE254_WIDTH = "1" *) 
   (* C_PROBE255_MU_CNT = "1" *) 
   (* C_PROBE255_WIDTH = "1" *) 
   (* C_PROBE256_MU_CNT = "1" *) 
   (* C_PROBE256_WIDTH = "1" *) 
   (* C_PROBE257_MU_CNT = "1" *) 
   (* C_PROBE257_WIDTH = "1" *) 
   (* C_PROBE258_MU_CNT = "1" *) 
   (* C_PROBE258_WIDTH = "1" *) 
   (* C_PROBE259_MU_CNT = "1" *) 
   (* C_PROBE259_WIDTH = "1" *) 
   (* C_PROBE25_MU_CNT = "1" *) 
   (* C_PROBE25_WIDTH = "1" *) 
   (* C_PROBE260_MU_CNT = "1" *) 
   (* C_PROBE260_WIDTH = "1" *) 
   (* C_PROBE261_MU_CNT = "1" *) 
   (* C_PROBE261_WIDTH = "1" *) 
   (* C_PROBE262_MU_CNT = "1" *) 
   (* C_PROBE262_WIDTH = "1" *) 
   (* C_PROBE263_MU_CNT = "1" *) 
   (* C_PROBE263_WIDTH = "1" *) 
   (* C_PROBE264_MU_CNT = "1" *) 
   (* C_PROBE264_WIDTH = "1" *) 
   (* C_PROBE265_MU_CNT = "1" *) 
   (* C_PROBE265_WIDTH = "1" *) 
   (* C_PROBE266_MU_CNT = "1" *) 
   (* C_PROBE266_WIDTH = "1" *) 
   (* C_PROBE267_MU_CNT = "1" *) 
   (* C_PROBE267_WIDTH = "1" *) 
   (* C_PROBE268_MU_CNT = "1" *) 
   (* C_PROBE268_WIDTH = "1" *) 
   (* C_PROBE269_MU_CNT = "1" *) 
   (* C_PROBE269_WIDTH = "1" *) 
   (* C_PROBE26_MU_CNT = "1" *) 
   (* C_PROBE26_WIDTH = "1" *) 
   (* C_PROBE270_MU_CNT = "1" *) 
   (* C_PROBE270_WIDTH = "1" *) 
   (* C_PROBE271_MU_CNT = "1" *) 
   (* C_PROBE271_WIDTH = "1" *) 
   (* C_PROBE272_MU_CNT = "1" *) 
   (* C_PROBE272_WIDTH = "1" *) 
   (* C_PROBE273_MU_CNT = "1" *) 
   (* C_PROBE273_WIDTH = "1" *) 
   (* C_PROBE274_MU_CNT = "1" *) 
   (* C_PROBE274_WIDTH = "1" *) 
   (* C_PROBE275_MU_CNT = "1" *) 
   (* C_PROBE275_WIDTH = "1" *) 
   (* C_PROBE276_MU_CNT = "1" *) 
   (* C_PROBE276_WIDTH = "1" *) 
   (* C_PROBE277_MU_CNT = "1" *) 
   (* C_PROBE277_WIDTH = "1" *) 
   (* C_PROBE278_MU_CNT = "1" *) 
   (* C_PROBE278_WIDTH = "1" *) 
   (* C_PROBE279_MU_CNT = "1" *) 
   (* C_PROBE279_WIDTH = "1" *) 
   (* C_PROBE27_MU_CNT = "1" *) 
   (* C_PROBE27_WIDTH = "1" *) 
   (* C_PROBE280_MU_CNT = "1" *) 
   (* C_PROBE280_WIDTH = "1" *) 
   (* C_PROBE281_MU_CNT = "1" *) 
   (* C_PROBE281_WIDTH = "1" *) 
   (* C_PROBE282_MU_CNT = "1" *) 
   (* C_PROBE282_WIDTH = "1" *) 
   (* C_PROBE283_MU_CNT = "1" *) 
   (* C_PROBE283_WIDTH = "1" *) 
   (* C_PROBE284_MU_CNT = "1" *) 
   (* C_PROBE284_WIDTH = "1" *) 
   (* C_PROBE285_MU_CNT = "1" *) 
   (* C_PROBE285_WIDTH = "1" *) 
   (* C_PROBE286_MU_CNT = "1" *) 
   (* C_PROBE286_WIDTH = "1" *) 
   (* C_PROBE287_MU_CNT = "1" *) 
   (* C_PROBE287_WIDTH = "1" *) 
   (* C_PROBE288_MU_CNT = "1" *) 
   (* C_PROBE288_WIDTH = "1" *) 
   (* C_PROBE289_MU_CNT = "1" *) 
   (* C_PROBE289_WIDTH = "1" *) 
   (* C_PROBE28_MU_CNT = "1" *) 
   (* C_PROBE28_WIDTH = "1" *) 
   (* C_PROBE290_MU_CNT = "1" *) 
   (* C_PROBE290_WIDTH = "1" *) 
   (* C_PROBE291_MU_CNT = "1" *) 
   (* C_PROBE291_WIDTH = "1" *) 
   (* C_PROBE292_MU_CNT = "1" *) 
   (* C_PROBE292_WIDTH = "1" *) 
   (* C_PROBE293_MU_CNT = "1" *) 
   (* C_PROBE293_WIDTH = "1" *) 
   (* C_PROBE294_MU_CNT = "1" *) 
   (* C_PROBE294_WIDTH = "1" *) 
   (* C_PROBE295_MU_CNT = "1" *) 
   (* C_PROBE295_WIDTH = "1" *) 
   (* C_PROBE296_MU_CNT = "1" *) 
   (* C_PROBE296_WIDTH = "1" *) 
   (* C_PROBE297_MU_CNT = "1" *) 
   (* C_PROBE297_WIDTH = "1" *) 
   (* C_PROBE298_MU_CNT = "1" *) 
   (* C_PROBE298_WIDTH = "1" *) 
   (* C_PROBE299_MU_CNT = "1" *) 
   (* C_PROBE299_WIDTH = "1" *) 
   (* C_PROBE29_MU_CNT = "1" *) 
   (* C_PROBE29_WIDTH = "1" *) 
   (* C_PROBE2_MU_CNT = "1" *) 
   (* C_PROBE2_WIDTH = "1" *) 
   (* C_PROBE300_MU_CNT = "1" *) 
   (* C_PROBE300_WIDTH = "1" *) 
   (* C_PROBE301_MU_CNT = "1" *) 
   (* C_PROBE301_WIDTH = "1" *) 
   (* C_PROBE302_MU_CNT = "1" *) 
   (* C_PROBE302_WIDTH = "1" *) 
   (* C_PROBE303_MU_CNT = "1" *) 
   (* C_PROBE303_WIDTH = "1" *) 
   (* C_PROBE304_MU_CNT = "1" *) 
   (* C_PROBE304_WIDTH = "1" *) 
   (* C_PROBE305_MU_CNT = "1" *) 
   (* C_PROBE305_WIDTH = "1" *) 
   (* C_PROBE306_MU_CNT = "1" *) 
   (* C_PROBE306_WIDTH = "1" *) 
   (* C_PROBE307_MU_CNT = "1" *) 
   (* C_PROBE307_WIDTH = "1" *) 
   (* C_PROBE308_MU_CNT = "1" *) 
   (* C_PROBE308_WIDTH = "1" *) 
   (* C_PROBE309_MU_CNT = "1" *) 
   (* C_PROBE309_WIDTH = "1" *) 
   (* C_PROBE30_MU_CNT = "1" *) 
   (* C_PROBE30_WIDTH = "1" *) 
   (* C_PROBE310_MU_CNT = "1" *) 
   (* C_PROBE310_WIDTH = "1" *) 
   (* C_PROBE311_MU_CNT = "1" *) 
   (* C_PROBE311_WIDTH = "1" *) 
   (* C_PROBE312_MU_CNT = "1" *) 
   (* C_PROBE312_WIDTH = "1" *) 
   (* C_PROBE313_MU_CNT = "1" *) 
   (* C_PROBE313_WIDTH = "1" *) 
   (* C_PROBE314_MU_CNT = "1" *) 
   (* C_PROBE314_WIDTH = "1" *) 
   (* C_PROBE315_MU_CNT = "1" *) 
   (* C_PROBE315_WIDTH = "1" *) 
   (* C_PROBE316_MU_CNT = "1" *) 
   (* C_PROBE316_WIDTH = "1" *) 
   (* C_PROBE317_MU_CNT = "1" *) 
   (* C_PROBE317_WIDTH = "1" *) 
   (* C_PROBE318_MU_CNT = "1" *) 
   (* C_PROBE318_WIDTH = "1" *) 
   (* C_PROBE319_MU_CNT = "1" *) 
   (* C_PROBE319_WIDTH = "1" *) 
   (* C_PROBE31_MU_CNT = "1" *) 
   (* C_PROBE31_WIDTH = "1" *) 
   (* C_PROBE320_MU_CNT = "1" *) 
   (* C_PROBE320_WIDTH = "1" *) 
   (* C_PROBE321_MU_CNT = "1" *) 
   (* C_PROBE321_WIDTH = "1" *) 
   (* C_PROBE322_MU_CNT = "1" *) 
   (* C_PROBE322_WIDTH = "1" *) 
   (* C_PROBE323_MU_CNT = "1" *) 
   (* C_PROBE323_WIDTH = "1" *) 
   (* C_PROBE324_MU_CNT = "1" *) 
   (* C_PROBE324_WIDTH = "1" *) 
   (* C_PROBE325_MU_CNT = "1" *) 
   (* C_PROBE325_WIDTH = "1" *) 
   (* C_PROBE326_MU_CNT = "1" *) 
   (* C_PROBE326_WIDTH = "1" *) 
   (* C_PROBE327_MU_CNT = "1" *) 
   (* C_PROBE327_WIDTH = "1" *) 
   (* C_PROBE328_MU_CNT = "1" *) 
   (* C_PROBE328_WIDTH = "1" *) 
   (* C_PROBE329_MU_CNT = "1" *) 
   (* C_PROBE329_WIDTH = "1" *) 
   (* C_PROBE32_MU_CNT = "1" *) 
   (* C_PROBE32_WIDTH = "1" *) 
   (* C_PROBE330_MU_CNT = "1" *) 
   (* C_PROBE330_WIDTH = "1" *) 
   (* C_PROBE331_MU_CNT = "1" *) 
   (* C_PROBE331_WIDTH = "1" *) 
   (* C_PROBE332_MU_CNT = "1" *) 
   (* C_PROBE332_WIDTH = "1" *) 
   (* C_PROBE333_MU_CNT = "1" *) 
   (* C_PROBE333_WIDTH = "1" *) 
   (* C_PROBE334_MU_CNT = "1" *) 
   (* C_PROBE334_WIDTH = "1" *) 
   (* C_PROBE335_MU_CNT = "1" *) 
   (* C_PROBE335_WIDTH = "1" *) 
   (* C_PROBE336_MU_CNT = "1" *) 
   (* C_PROBE336_WIDTH = "1" *) 
   (* C_PROBE337_MU_CNT = "1" *) 
   (* C_PROBE337_WIDTH = "1" *) 
   (* C_PROBE338_MU_CNT = "1" *) 
   (* C_PROBE338_WIDTH = "1" *) 
   (* C_PROBE339_MU_CNT = "1" *) 
   (* C_PROBE339_WIDTH = "1" *) 
   (* C_PROBE33_MU_CNT = "1" *) 
   (* C_PROBE33_WIDTH = "1" *) 
   (* C_PROBE340_MU_CNT = "1" *) 
   (* C_PROBE340_WIDTH = "1" *) 
   (* C_PROBE341_MU_CNT = "1" *) 
   (* C_PROBE341_WIDTH = "1" *) 
   (* C_PROBE342_MU_CNT = "1" *) 
   (* C_PROBE342_WIDTH = "1" *) 
   (* C_PROBE343_MU_CNT = "1" *) 
   (* C_PROBE343_WIDTH = "1" *) 
   (* C_PROBE344_MU_CNT = "1" *) 
   (* C_PROBE344_WIDTH = "1" *) 
   (* C_PROBE345_MU_CNT = "1" *) 
   (* C_PROBE345_WIDTH = "1" *) 
   (* C_PROBE346_MU_CNT = "1" *) 
   (* C_PROBE346_WIDTH = "1" *) 
   (* C_PROBE347_MU_CNT = "1" *) 
   (* C_PROBE347_WIDTH = "1" *) 
   (* C_PROBE348_MU_CNT = "1" *) 
   (* C_PROBE348_WIDTH = "1" *) 
   (* C_PROBE349_MU_CNT = "1" *) 
   (* C_PROBE349_WIDTH = "1" *) 
   (* C_PROBE34_MU_CNT = "1" *) 
   (* C_PROBE34_WIDTH = "1" *) 
   (* C_PROBE350_MU_CNT = "1" *) 
   (* C_PROBE350_WIDTH = "1" *) 
   (* C_PROBE351_MU_CNT = "1" *) 
   (* C_PROBE351_WIDTH = "1" *) 
   (* C_PROBE352_MU_CNT = "1" *) 
   (* C_PROBE352_WIDTH = "1" *) 
   (* C_PROBE353_MU_CNT = "1" *) 
   (* C_PROBE353_WIDTH = "1" *) 
   (* C_PROBE354_MU_CNT = "1" *) 
   (* C_PROBE354_WIDTH = "1" *) 
   (* C_PROBE355_MU_CNT = "1" *) 
   (* C_PROBE355_WIDTH = "1" *) 
   (* C_PROBE356_MU_CNT = "1" *) 
   (* C_PROBE356_WIDTH = "1" *) 
   (* C_PROBE357_MU_CNT = "1" *) 
   (* C_PROBE357_WIDTH = "1" *) 
   (* C_PROBE358_MU_CNT = "1" *) 
   (* C_PROBE358_WIDTH = "1" *) 
   (* C_PROBE359_MU_CNT = "1" *) 
   (* C_PROBE359_WIDTH = "1" *) 
   (* C_PROBE35_MU_CNT = "1" *) 
   (* C_PROBE35_WIDTH = "1" *) 
   (* C_PROBE360_MU_CNT = "1" *) 
   (* C_PROBE360_WIDTH = "1" *) 
   (* C_PROBE361_MU_CNT = "1" *) 
   (* C_PROBE361_WIDTH = "1" *) 
   (* C_PROBE362_MU_CNT = "1" *) 
   (* C_PROBE362_WIDTH = "1" *) 
   (* C_PROBE363_MU_CNT = "1" *) 
   (* C_PROBE363_WIDTH = "1" *) 
   (* C_PROBE364_MU_CNT = "1" *) 
   (* C_PROBE364_WIDTH = "1" *) 
   (* C_PROBE365_MU_CNT = "1" *) 
   (* C_PROBE365_WIDTH = "1" *) 
   (* C_PROBE366_MU_CNT = "1" *) 
   (* C_PROBE366_WIDTH = "1" *) 
   (* C_PROBE367_MU_CNT = "1" *) 
   (* C_PROBE367_WIDTH = "1" *) 
   (* C_PROBE368_MU_CNT = "1" *) 
   (* C_PROBE368_WIDTH = "1" *) 
   (* C_PROBE369_MU_CNT = "1" *) 
   (* C_PROBE369_WIDTH = "1" *) 
   (* C_PROBE36_MU_CNT = "1" *) 
   (* C_PROBE36_WIDTH = "1" *) 
   (* C_PROBE370_MU_CNT = "1" *) 
   (* C_PROBE370_WIDTH = "1" *) 
   (* C_PROBE371_MU_CNT = "1" *) 
   (* C_PROBE371_WIDTH = "1" *) 
   (* C_PROBE372_MU_CNT = "1" *) 
   (* C_PROBE372_WIDTH = "1" *) 
   (* C_PROBE373_MU_CNT = "1" *) 
   (* C_PROBE373_WIDTH = "1" *) 
   (* C_PROBE374_MU_CNT = "1" *) 
   (* C_PROBE374_WIDTH = "1" *) 
   (* C_PROBE375_MU_CNT = "1" *) 
   (* C_PROBE375_WIDTH = "1" *) 
   (* C_PROBE376_MU_CNT = "1" *) 
   (* C_PROBE376_WIDTH = "1" *) 
   (* C_PROBE377_MU_CNT = "1" *) 
   (* C_PROBE377_WIDTH = "1" *) 
   (* C_PROBE378_MU_CNT = "1" *) 
   (* C_PROBE378_WIDTH = "1" *) 
   (* C_PROBE379_MU_CNT = "1" *) 
   (* C_PROBE379_WIDTH = "1" *) 
   (* C_PROBE37_MU_CNT = "1" *) 
   (* C_PROBE37_WIDTH = "1" *) 
   (* C_PROBE380_MU_CNT = "1" *) 
   (* C_PROBE380_WIDTH = "1" *) 
   (* C_PROBE381_MU_CNT = "1" *) 
   (* C_PROBE381_WIDTH = "1" *) 
   (* C_PROBE382_MU_CNT = "1" *) 
   (* C_PROBE382_WIDTH = "1" *) 
   (* C_PROBE383_MU_CNT = "1" *) 
   (* C_PROBE383_WIDTH = "1" *) 
   (* C_PROBE384_MU_CNT = "1" *) 
   (* C_PROBE384_WIDTH = "1" *) 
   (* C_PROBE385_MU_CNT = "1" *) 
   (* C_PROBE385_WIDTH = "1" *) 
   (* C_PROBE386_MU_CNT = "1" *) 
   (* C_PROBE386_WIDTH = "1" *) 
   (* C_PROBE387_MU_CNT = "1" *) 
   (* C_PROBE387_WIDTH = "1" *) 
   (* C_PROBE388_MU_CNT = "1" *) 
   (* C_PROBE388_WIDTH = "1" *) 
   (* C_PROBE389_MU_CNT = "1" *) 
   (* C_PROBE389_WIDTH = "1" *) 
   (* C_PROBE38_MU_CNT = "1" *) 
   (* C_PROBE38_WIDTH = "1" *) 
   (* C_PROBE390_MU_CNT = "1" *) 
   (* C_PROBE390_WIDTH = "1" *) 
   (* C_PROBE391_MU_CNT = "1" *) 
   (* C_PROBE391_WIDTH = "1" *) 
   (* C_PROBE392_MU_CNT = "1" *) 
   (* C_PROBE392_WIDTH = "1" *) 
   (* C_PROBE393_MU_CNT = "1" *) 
   (* C_PROBE393_WIDTH = "1" *) 
   (* C_PROBE394_MU_CNT = "1" *) 
   (* C_PROBE394_WIDTH = "1" *) 
   (* C_PROBE395_MU_CNT = "1" *) 
   (* C_PROBE395_WIDTH = "1" *) 
   (* C_PROBE396_MU_CNT = "1" *) 
   (* C_PROBE396_WIDTH = "1" *) 
   (* C_PROBE397_MU_CNT = "1" *) 
   (* C_PROBE397_WIDTH = "1" *) 
   (* C_PROBE398_MU_CNT = "1" *) 
   (* C_PROBE398_WIDTH = "1" *) 
   (* C_PROBE399_MU_CNT = "1" *) 
   (* C_PROBE399_WIDTH = "1" *) 
   (* C_PROBE39_MU_CNT = "1" *) 
   (* C_PROBE39_WIDTH = "1" *) 
   (* C_PROBE3_MU_CNT = "1" *) 
   (* C_PROBE3_WIDTH = "32" *) 
   (* C_PROBE400_MU_CNT = "1" *) 
   (* C_PROBE400_WIDTH = "1" *) 
   (* C_PROBE401_MU_CNT = "1" *) 
   (* C_PROBE401_WIDTH = "1" *) 
   (* C_PROBE402_MU_CNT = "1" *) 
   (* C_PROBE402_WIDTH = "1" *) 
   (* C_PROBE403_MU_CNT = "1" *) 
   (* C_PROBE403_WIDTH = "1" *) 
   (* C_PROBE404_MU_CNT = "1" *) 
   (* C_PROBE404_WIDTH = "1" *) 
   (* C_PROBE405_MU_CNT = "1" *) 
   (* C_PROBE405_WIDTH = "1" *) 
   (* C_PROBE406_MU_CNT = "1" *) 
   (* C_PROBE406_WIDTH = "1" *) 
   (* C_PROBE407_MU_CNT = "1" *) 
   (* C_PROBE407_WIDTH = "1" *) 
   (* C_PROBE408_MU_CNT = "1" *) 
   (* C_PROBE408_WIDTH = "1" *) 
   (* C_PROBE409_MU_CNT = "1" *) 
   (* C_PROBE409_WIDTH = "1" *) 
   (* C_PROBE40_MU_CNT = "1" *) 
   (* C_PROBE40_WIDTH = "1" *) 
   (* C_PROBE410_MU_CNT = "1" *) 
   (* C_PROBE410_WIDTH = "1" *) 
   (* C_PROBE411_MU_CNT = "1" *) 
   (* C_PROBE411_WIDTH = "1" *) 
   (* C_PROBE412_MU_CNT = "1" *) 
   (* C_PROBE412_WIDTH = "1" *) 
   (* C_PROBE413_MU_CNT = "1" *) 
   (* C_PROBE413_WIDTH = "1" *) 
   (* C_PROBE414_MU_CNT = "1" *) 
   (* C_PROBE414_WIDTH = "1" *) 
   (* C_PROBE415_MU_CNT = "1" *) 
   (* C_PROBE415_WIDTH = "1" *) 
   (* C_PROBE416_MU_CNT = "1" *) 
   (* C_PROBE416_WIDTH = "1" *) 
   (* C_PROBE417_MU_CNT = "1" *) 
   (* C_PROBE417_WIDTH = "1" *) 
   (* C_PROBE418_MU_CNT = "1" *) 
   (* C_PROBE418_WIDTH = "1" *) 
   (* C_PROBE419_MU_CNT = "1" *) 
   (* C_PROBE419_WIDTH = "1" *) 
   (* C_PROBE41_MU_CNT = "1" *) 
   (* C_PROBE41_WIDTH = "1" *) 
   (* C_PROBE420_MU_CNT = "1" *) 
   (* C_PROBE420_WIDTH = "1" *) 
   (* C_PROBE421_MU_CNT = "1" *) 
   (* C_PROBE421_WIDTH = "1" *) 
   (* C_PROBE422_MU_CNT = "1" *) 
   (* C_PROBE422_WIDTH = "1" *) 
   (* C_PROBE423_MU_CNT = "1" *) 
   (* C_PROBE423_WIDTH = "1" *) 
   (* C_PROBE424_MU_CNT = "1" *) 
   (* C_PROBE424_WIDTH = "1" *) 
   (* C_PROBE425_MU_CNT = "1" *) 
   (* C_PROBE425_WIDTH = "1" *) 
   (* C_PROBE426_MU_CNT = "1" *) 
   (* C_PROBE426_WIDTH = "1" *) 
   (* C_PROBE427_MU_CNT = "1" *) 
   (* C_PROBE427_WIDTH = "1" *) 
   (* C_PROBE428_MU_CNT = "1" *) 
   (* C_PROBE428_WIDTH = "1" *) 
   (* C_PROBE429_MU_CNT = "1" *) 
   (* C_PROBE429_WIDTH = "1" *) 
   (* C_PROBE42_MU_CNT = "1" *) 
   (* C_PROBE42_WIDTH = "1" *) 
   (* C_PROBE430_MU_CNT = "1" *) 
   (* C_PROBE430_WIDTH = "1" *) 
   (* C_PROBE431_MU_CNT = "1" *) 
   (* C_PROBE431_WIDTH = "1" *) 
   (* C_PROBE432_MU_CNT = "1" *) 
   (* C_PROBE432_WIDTH = "1" *) 
   (* C_PROBE433_MU_CNT = "1" *) 
   (* C_PROBE433_WIDTH = "1" *) 
   (* C_PROBE434_MU_CNT = "1" *) 
   (* C_PROBE434_WIDTH = "1" *) 
   (* C_PROBE435_MU_CNT = "1" *) 
   (* C_PROBE435_WIDTH = "1" *) 
   (* C_PROBE436_MU_CNT = "1" *) 
   (* C_PROBE436_WIDTH = "1" *) 
   (* C_PROBE437_MU_CNT = "1" *) 
   (* C_PROBE437_WIDTH = "1" *) 
   (* C_PROBE438_MU_CNT = "1" *) 
   (* C_PROBE438_WIDTH = "1" *) 
   (* C_PROBE439_MU_CNT = "1" *) 
   (* C_PROBE439_WIDTH = "1" *) 
   (* C_PROBE43_MU_CNT = "1" *) 
   (* C_PROBE43_WIDTH = "1" *) 
   (* C_PROBE440_MU_CNT = "1" *) 
   (* C_PROBE440_WIDTH = "1" *) 
   (* C_PROBE441_MU_CNT = "1" *) 
   (* C_PROBE441_WIDTH = "1" *) 
   (* C_PROBE442_MU_CNT = "1" *) 
   (* C_PROBE442_WIDTH = "1" *) 
   (* C_PROBE443_MU_CNT = "1" *) 
   (* C_PROBE443_WIDTH = "1" *) 
   (* C_PROBE444_MU_CNT = "1" *) 
   (* C_PROBE444_WIDTH = "1" *) 
   (* C_PROBE445_MU_CNT = "1" *) 
   (* C_PROBE445_WIDTH = "1" *) 
   (* C_PROBE446_MU_CNT = "1" *) 
   (* C_PROBE446_WIDTH = "1" *) 
   (* C_PROBE447_MU_CNT = "1" *) 
   (* C_PROBE447_WIDTH = "1" *) 
   (* C_PROBE448_MU_CNT = "1" *) 
   (* C_PROBE448_WIDTH = "1" *) 
   (* C_PROBE449_MU_CNT = "1" *) 
   (* C_PROBE449_WIDTH = "1" *) 
   (* C_PROBE44_MU_CNT = "1" *) 
   (* C_PROBE44_WIDTH = "1" *) 
   (* C_PROBE450_MU_CNT = "1" *) 
   (* C_PROBE450_WIDTH = "1" *) 
   (* C_PROBE451_MU_CNT = "1" *) 
   (* C_PROBE451_WIDTH = "1" *) 
   (* C_PROBE452_MU_CNT = "1" *) 
   (* C_PROBE452_WIDTH = "1" *) 
   (* C_PROBE453_MU_CNT = "1" *) 
   (* C_PROBE453_WIDTH = "1" *) 
   (* C_PROBE454_MU_CNT = "1" *) 
   (* C_PROBE454_WIDTH = "1" *) 
   (* C_PROBE455_MU_CNT = "1" *) 
   (* C_PROBE455_WIDTH = "1" *) 
   (* C_PROBE456_MU_CNT = "1" *) 
   (* C_PROBE456_WIDTH = "1" *) 
   (* C_PROBE457_MU_CNT = "1" *) 
   (* C_PROBE457_WIDTH = "1" *) 
   (* C_PROBE458_MU_CNT = "1" *) 
   (* C_PROBE458_WIDTH = "1" *) 
   (* C_PROBE459_MU_CNT = "1" *) 
   (* C_PROBE459_WIDTH = "1" *) 
   (* C_PROBE45_MU_CNT = "1" *) 
   (* C_PROBE45_WIDTH = "1" *) 
   (* C_PROBE460_MU_CNT = "1" *) 
   (* C_PROBE460_WIDTH = "1" *) 
   (* C_PROBE461_MU_CNT = "1" *) 
   (* C_PROBE461_WIDTH = "1" *) 
   (* C_PROBE462_MU_CNT = "1" *) 
   (* C_PROBE462_WIDTH = "1" *) 
   (* C_PROBE463_MU_CNT = "1" *) 
   (* C_PROBE463_WIDTH = "1" *) 
   (* C_PROBE464_MU_CNT = "1" *) 
   (* C_PROBE464_WIDTH = "1" *) 
   (* C_PROBE465_MU_CNT = "1" *) 
   (* C_PROBE465_WIDTH = "1" *) 
   (* C_PROBE466_MU_CNT = "1" *) 
   (* C_PROBE466_WIDTH = "1" *) 
   (* C_PROBE467_MU_CNT = "1" *) 
   (* C_PROBE467_WIDTH = "1" *) 
   (* C_PROBE468_MU_CNT = "1" *) 
   (* C_PROBE468_WIDTH = "1" *) 
   (* C_PROBE469_MU_CNT = "1" *) 
   (* C_PROBE469_WIDTH = "1" *) 
   (* C_PROBE46_MU_CNT = "1" *) 
   (* C_PROBE46_WIDTH = "1" *) 
   (* C_PROBE470_MU_CNT = "1" *) 
   (* C_PROBE470_WIDTH = "1" *) 
   (* C_PROBE471_MU_CNT = "1" *) 
   (* C_PROBE471_WIDTH = "1" *) 
   (* C_PROBE472_MU_CNT = "1" *) 
   (* C_PROBE472_WIDTH = "1" *) 
   (* C_PROBE473_MU_CNT = "1" *) 
   (* C_PROBE473_WIDTH = "1" *) 
   (* C_PROBE474_MU_CNT = "1" *) 
   (* C_PROBE474_WIDTH = "1" *) 
   (* C_PROBE475_MU_CNT = "1" *) 
   (* C_PROBE475_WIDTH = "1" *) 
   (* C_PROBE476_MU_CNT = "1" *) 
   (* C_PROBE476_WIDTH = "1" *) 
   (* C_PROBE477_MU_CNT = "1" *) 
   (* C_PROBE477_WIDTH = "1" *) 
   (* C_PROBE478_MU_CNT = "1" *) 
   (* C_PROBE478_WIDTH = "1" *) 
   (* C_PROBE479_MU_CNT = "1" *) 
   (* C_PROBE479_WIDTH = "1" *) 
   (* C_PROBE47_MU_CNT = "1" *) 
   (* C_PROBE47_WIDTH = "1" *) 
   (* C_PROBE480_MU_CNT = "1" *) 
   (* C_PROBE480_WIDTH = "1" *) 
   (* C_PROBE481_MU_CNT = "1" *) 
   (* C_PROBE481_WIDTH = "1" *) 
   (* C_PROBE482_MU_CNT = "1" *) 
   (* C_PROBE482_WIDTH = "1" *) 
   (* C_PROBE483_MU_CNT = "1" *) 
   (* C_PROBE483_WIDTH = "1" *) 
   (* C_PROBE484_MU_CNT = "1" *) 
   (* C_PROBE484_WIDTH = "1" *) 
   (* C_PROBE485_MU_CNT = "1" *) 
   (* C_PROBE485_WIDTH = "1" *) 
   (* C_PROBE486_MU_CNT = "1" *) 
   (* C_PROBE486_WIDTH = "1" *) 
   (* C_PROBE487_MU_CNT = "1" *) 
   (* C_PROBE487_WIDTH = "1" *) 
   (* C_PROBE488_MU_CNT = "1" *) 
   (* C_PROBE488_WIDTH = "1" *) 
   (* C_PROBE489_MU_CNT = "1" *) 
   (* C_PROBE489_WIDTH = "1" *) 
   (* C_PROBE48_MU_CNT = "1" *) 
   (* C_PROBE48_WIDTH = "1" *) 
   (* C_PROBE490_MU_CNT = "1" *) 
   (* C_PROBE490_WIDTH = "1" *) 
   (* C_PROBE491_MU_CNT = "1" *) 
   (* C_PROBE491_WIDTH = "1" *) 
   (* C_PROBE492_MU_CNT = "1" *) 
   (* C_PROBE492_WIDTH = "1" *) 
   (* C_PROBE493_MU_CNT = "1" *) 
   (* C_PROBE493_WIDTH = "1" *) 
   (* C_PROBE494_MU_CNT = "1" *) 
   (* C_PROBE494_WIDTH = "1" *) 
   (* C_PROBE495_MU_CNT = "1" *) 
   (* C_PROBE495_WIDTH = "1" *) 
   (* C_PROBE496_MU_CNT = "1" *) 
   (* C_PROBE496_WIDTH = "1" *) 
   (* C_PROBE497_MU_CNT = "1" *) 
   (* C_PROBE497_WIDTH = "1" *) 
   (* C_PROBE498_MU_CNT = "1" *) 
   (* C_PROBE498_WIDTH = "1" *) 
   (* C_PROBE499_MU_CNT = "1" *) 
   (* C_PROBE499_WIDTH = "1" *) 
   (* C_PROBE49_MU_CNT = "1" *) 
   (* C_PROBE49_WIDTH = "1" *) 
   (* C_PROBE4_MU_CNT = "1" *) 
   (* C_PROBE4_WIDTH = "1" *) 
   (* C_PROBE500_MU_CNT = "1" *) 
   (* C_PROBE500_WIDTH = "1" *) 
   (* C_PROBE501_MU_CNT = "1" *) 
   (* C_PROBE501_WIDTH = "1" *) 
   (* C_PROBE502_MU_CNT = "1" *) 
   (* C_PROBE502_WIDTH = "1" *) 
   (* C_PROBE503_MU_CNT = "1" *) 
   (* C_PROBE503_WIDTH = "1" *) 
   (* C_PROBE504_MU_CNT = "1" *) 
   (* C_PROBE504_WIDTH = "1" *) 
   (* C_PROBE505_MU_CNT = "1" *) 
   (* C_PROBE505_WIDTH = "1" *) 
   (* C_PROBE506_MU_CNT = "1" *) 
   (* C_PROBE506_WIDTH = "1" *) 
   (* C_PROBE507_MU_CNT = "1" *) 
   (* C_PROBE507_WIDTH = "1" *) 
   (* C_PROBE508_MU_CNT = "1" *) 
   (* C_PROBE508_WIDTH = "1" *) 
   (* C_PROBE509_MU_CNT = "1" *) 
   (* C_PROBE509_WIDTH = "1" *) 
   (* C_PROBE50_MU_CNT = "1" *) 
   (* C_PROBE50_WIDTH = "1" *) 
   (* C_PROBE510_MU_CNT = "1" *) 
   (* C_PROBE510_WIDTH = "1" *) 
   (* C_PROBE511_MU_CNT = "1" *) 
   (* C_PROBE511_WIDTH = "1" *) 
   (* C_PROBE512_MU_CNT = "1" *) 
   (* C_PROBE512_WIDTH = "1" *) 
   (* C_PROBE513_MU_CNT = "1" *) 
   (* C_PROBE513_WIDTH = "1" *) 
   (* C_PROBE514_MU_CNT = "1" *) 
   (* C_PROBE514_WIDTH = "1" *) 
   (* C_PROBE515_MU_CNT = "1" *) 
   (* C_PROBE515_WIDTH = "1" *) 
   (* C_PROBE516_MU_CNT = "1" *) 
   (* C_PROBE516_WIDTH = "1" *) 
   (* C_PROBE517_MU_CNT = "1" *) 
   (* C_PROBE517_WIDTH = "1" *) 
   (* C_PROBE518_MU_CNT = "1" *) 
   (* C_PROBE518_WIDTH = "1" *) 
   (* C_PROBE519_MU_CNT = "1" *) 
   (* C_PROBE519_WIDTH = "1" *) 
   (* C_PROBE51_MU_CNT = "1" *) 
   (* C_PROBE51_WIDTH = "1" *) 
   (* C_PROBE520_MU_CNT = "1" *) 
   (* C_PROBE520_WIDTH = "1" *) 
   (* C_PROBE521_MU_CNT = "1" *) 
   (* C_PROBE521_WIDTH = "1" *) 
   (* C_PROBE522_MU_CNT = "1" *) 
   (* C_PROBE522_WIDTH = "1" *) 
   (* C_PROBE523_MU_CNT = "1" *) 
   (* C_PROBE523_WIDTH = "1" *) 
   (* C_PROBE524_MU_CNT = "1" *) 
   (* C_PROBE524_WIDTH = "1" *) 
   (* C_PROBE525_MU_CNT = "1" *) 
   (* C_PROBE525_WIDTH = "1" *) 
   (* C_PROBE526_MU_CNT = "1" *) 
   (* C_PROBE526_WIDTH = "1" *) 
   (* C_PROBE527_MU_CNT = "1" *) 
   (* C_PROBE527_WIDTH = "1" *) 
   (* C_PROBE528_MU_CNT = "1" *) 
   (* C_PROBE528_WIDTH = "1" *) 
   (* C_PROBE529_MU_CNT = "1" *) 
   (* C_PROBE529_WIDTH = "1" *) 
   (* C_PROBE52_MU_CNT = "1" *) 
   (* C_PROBE52_WIDTH = "1" *) 
   (* C_PROBE530_MU_CNT = "1" *) 
   (* C_PROBE530_WIDTH = "1" *) 
   (* C_PROBE531_MU_CNT = "1" *) 
   (* C_PROBE531_WIDTH = "1" *) 
   (* C_PROBE532_MU_CNT = "1" *) 
   (* C_PROBE532_WIDTH = "1" *) 
   (* C_PROBE533_MU_CNT = "1" *) 
   (* C_PROBE533_WIDTH = "1" *) 
   (* C_PROBE534_MU_CNT = "1" *) 
   (* C_PROBE534_WIDTH = "1" *) 
   (* C_PROBE535_MU_CNT = "1" *) 
   (* C_PROBE535_WIDTH = "1" *) 
   (* C_PROBE536_MU_CNT = "1" *) 
   (* C_PROBE536_WIDTH = "1" *) 
   (* C_PROBE537_MU_CNT = "1" *) 
   (* C_PROBE537_WIDTH = "1" *) 
   (* C_PROBE538_MU_CNT = "1" *) 
   (* C_PROBE538_WIDTH = "1" *) 
   (* C_PROBE539_MU_CNT = "1" *) 
   (* C_PROBE539_WIDTH = "1" *) 
   (* C_PROBE53_MU_CNT = "1" *) 
   (* C_PROBE53_WIDTH = "1" *) 
   (* C_PROBE540_MU_CNT = "1" *) 
   (* C_PROBE540_WIDTH = "1" *) 
   (* C_PROBE541_MU_CNT = "1" *) 
   (* C_PROBE541_WIDTH = "1" *) 
   (* C_PROBE542_MU_CNT = "1" *) 
   (* C_PROBE542_WIDTH = "1" *) 
   (* C_PROBE543_MU_CNT = "1" *) 
   (* C_PROBE543_WIDTH = "1" *) 
   (* C_PROBE544_MU_CNT = "1" *) 
   (* C_PROBE544_WIDTH = "1" *) 
   (* C_PROBE545_MU_CNT = "1" *) 
   (* C_PROBE545_WIDTH = "1" *) 
   (* C_PROBE546_MU_CNT = "1" *) 
   (* C_PROBE546_WIDTH = "1" *) 
   (* C_PROBE547_MU_CNT = "1" *) 
   (* C_PROBE547_WIDTH = "1" *) 
   (* C_PROBE548_MU_CNT = "1" *) 
   (* C_PROBE548_WIDTH = "1" *) 
   (* C_PROBE549_MU_CNT = "1" *) 
   (* C_PROBE549_WIDTH = "1" *) 
   (* C_PROBE54_MU_CNT = "1" *) 
   (* C_PROBE54_WIDTH = "1" *) 
   (* C_PROBE550_MU_CNT = "1" *) 
   (* C_PROBE550_WIDTH = "1" *) 
   (* C_PROBE551_MU_CNT = "1" *) 
   (* C_PROBE551_WIDTH = "1" *) 
   (* C_PROBE552_MU_CNT = "1" *) 
   (* C_PROBE552_WIDTH = "1" *) 
   (* C_PROBE553_MU_CNT = "1" *) 
   (* C_PROBE553_WIDTH = "1" *) 
   (* C_PROBE554_MU_CNT = "1" *) 
   (* C_PROBE554_WIDTH = "1" *) 
   (* C_PROBE555_MU_CNT = "1" *) 
   (* C_PROBE555_WIDTH = "1" *) 
   (* C_PROBE556_MU_CNT = "1" *) 
   (* C_PROBE556_WIDTH = "1" *) 
   (* C_PROBE557_MU_CNT = "1" *) 
   (* C_PROBE557_WIDTH = "1" *) 
   (* C_PROBE558_MU_CNT = "1" *) 
   (* C_PROBE558_WIDTH = "1" *) 
   (* C_PROBE559_MU_CNT = "1" *) 
   (* C_PROBE559_WIDTH = "1" *) 
   (* C_PROBE55_MU_CNT = "1" *) 
   (* C_PROBE55_WIDTH = "1" *) 
   (* C_PROBE560_MU_CNT = "1" *) 
   (* C_PROBE560_WIDTH = "1" *) 
   (* C_PROBE561_MU_CNT = "1" *) 
   (* C_PROBE561_WIDTH = "1" *) 
   (* C_PROBE562_MU_CNT = "1" *) 
   (* C_PROBE562_WIDTH = "1" *) 
   (* C_PROBE563_MU_CNT = "1" *) 
   (* C_PROBE563_WIDTH = "1" *) 
   (* C_PROBE564_MU_CNT = "1" *) 
   (* C_PROBE564_WIDTH = "1" *) 
   (* C_PROBE565_MU_CNT = "1" *) 
   (* C_PROBE565_WIDTH = "1" *) 
   (* C_PROBE566_MU_CNT = "1" *) 
   (* C_PROBE566_WIDTH = "1" *) 
   (* C_PROBE567_MU_CNT = "1" *) 
   (* C_PROBE567_WIDTH = "1" *) 
   (* C_PROBE568_MU_CNT = "1" *) 
   (* C_PROBE568_WIDTH = "1" *) 
   (* C_PROBE569_MU_CNT = "1" *) 
   (* C_PROBE569_WIDTH = "1" *) 
   (* C_PROBE56_MU_CNT = "1" *) 
   (* C_PROBE56_WIDTH = "1" *) 
   (* C_PROBE570_MU_CNT = "1" *) 
   (* C_PROBE570_WIDTH = "1" *) 
   (* C_PROBE571_MU_CNT = "1" *) 
   (* C_PROBE571_WIDTH = "1" *) 
   (* C_PROBE572_MU_CNT = "1" *) 
   (* C_PROBE572_WIDTH = "1" *) 
   (* C_PROBE573_MU_CNT = "1" *) 
   (* C_PROBE573_WIDTH = "1" *) 
   (* C_PROBE574_MU_CNT = "1" *) 
   (* C_PROBE574_WIDTH = "1" *) 
   (* C_PROBE575_MU_CNT = "1" *) 
   (* C_PROBE575_WIDTH = "1" *) 
   (* C_PROBE576_MU_CNT = "1" *) 
   (* C_PROBE576_WIDTH = "1" *) 
   (* C_PROBE577_MU_CNT = "1" *) 
   (* C_PROBE577_WIDTH = "1" *) 
   (* C_PROBE578_MU_CNT = "1" *) 
   (* C_PROBE578_WIDTH = "1" *) 
   (* C_PROBE579_MU_CNT = "1" *) 
   (* C_PROBE579_WIDTH = "1" *) 
   (* C_PROBE57_MU_CNT = "1" *) 
   (* C_PROBE57_WIDTH = "1" *) 
   (* C_PROBE580_MU_CNT = "1" *) 
   (* C_PROBE580_WIDTH = "1" *) 
   (* C_PROBE581_MU_CNT = "1" *) 
   (* C_PROBE581_WIDTH = "1" *) 
   (* C_PROBE582_MU_CNT = "1" *) 
   (* C_PROBE582_WIDTH = "1" *) 
   (* C_PROBE583_MU_CNT = "1" *) 
   (* C_PROBE583_WIDTH = "1" *) 
   (* C_PROBE584_MU_CNT = "1" *) 
   (* C_PROBE584_WIDTH = "1" *) 
   (* C_PROBE585_MU_CNT = "1" *) 
   (* C_PROBE585_WIDTH = "1" *) 
   (* C_PROBE586_MU_CNT = "1" *) 
   (* C_PROBE586_WIDTH = "1" *) 
   (* C_PROBE587_MU_CNT = "1" *) 
   (* C_PROBE587_WIDTH = "1" *) 
   (* C_PROBE588_MU_CNT = "1" *) 
   (* C_PROBE588_WIDTH = "1" *) 
   (* C_PROBE589_MU_CNT = "1" *) 
   (* C_PROBE589_WIDTH = "1" *) 
   (* C_PROBE58_MU_CNT = "1" *) 
   (* C_PROBE58_WIDTH = "1" *) 
   (* C_PROBE590_MU_CNT = "1" *) 
   (* C_PROBE590_WIDTH = "1" *) 
   (* C_PROBE591_MU_CNT = "1" *) 
   (* C_PROBE591_WIDTH = "1" *) 
   (* C_PROBE592_MU_CNT = "1" *) 
   (* C_PROBE592_WIDTH = "1" *) 
   (* C_PROBE593_MU_CNT = "1" *) 
   (* C_PROBE593_WIDTH = "1" *) 
   (* C_PROBE594_MU_CNT = "1" *) 
   (* C_PROBE594_WIDTH = "1" *) 
   (* C_PROBE595_MU_CNT = "1" *) 
   (* C_PROBE595_WIDTH = "1" *) 
   (* C_PROBE596_MU_CNT = "1" *) 
   (* C_PROBE596_WIDTH = "1" *) 
   (* C_PROBE597_MU_CNT = "1" *) 
   (* C_PROBE597_WIDTH = "1" *) 
   (* C_PROBE598_MU_CNT = "1" *) 
   (* C_PROBE598_WIDTH = "1" *) 
   (* C_PROBE599_MU_CNT = "1" *) 
   (* C_PROBE599_WIDTH = "1" *) 
   (* C_PROBE59_MU_CNT = "1" *) 
   (* C_PROBE59_WIDTH = "1" *) 
   (* C_PROBE5_MU_CNT = "1" *) 
   (* C_PROBE5_WIDTH = "1" *) 
   (* C_PROBE600_MU_CNT = "1" *) 
   (* C_PROBE600_WIDTH = "1" *) 
   (* C_PROBE601_MU_CNT = "1" *) 
   (* C_PROBE601_WIDTH = "1" *) 
   (* C_PROBE602_MU_CNT = "1" *) 
   (* C_PROBE602_WIDTH = "1" *) 
   (* C_PROBE603_MU_CNT = "1" *) 
   (* C_PROBE603_WIDTH = "1" *) 
   (* C_PROBE604_MU_CNT = "1" *) 
   (* C_PROBE604_WIDTH = "1" *) 
   (* C_PROBE605_MU_CNT = "1" *) 
   (* C_PROBE605_WIDTH = "1" *) 
   (* C_PROBE606_MU_CNT = "1" *) 
   (* C_PROBE606_WIDTH = "1" *) 
   (* C_PROBE607_MU_CNT = "1" *) 
   (* C_PROBE607_WIDTH = "1" *) 
   (* C_PROBE608_MU_CNT = "1" *) 
   (* C_PROBE608_WIDTH = "1" *) 
   (* C_PROBE609_MU_CNT = "1" *) 
   (* C_PROBE609_WIDTH = "1" *) 
   (* C_PROBE60_MU_CNT = "1" *) 
   (* C_PROBE60_WIDTH = "1" *) 
   (* C_PROBE610_MU_CNT = "1" *) 
   (* C_PROBE610_WIDTH = "1" *) 
   (* C_PROBE611_MU_CNT = "1" *) 
   (* C_PROBE611_WIDTH = "1" *) 
   (* C_PROBE612_MU_CNT = "1" *) 
   (* C_PROBE612_WIDTH = "1" *) 
   (* C_PROBE613_MU_CNT = "1" *) 
   (* C_PROBE613_WIDTH = "1" *) 
   (* C_PROBE614_MU_CNT = "1" *) 
   (* C_PROBE614_WIDTH = "1" *) 
   (* C_PROBE615_MU_CNT = "1" *) 
   (* C_PROBE615_WIDTH = "1" *) 
   (* C_PROBE616_MU_CNT = "1" *) 
   (* C_PROBE616_WIDTH = "1" *) 
   (* C_PROBE617_MU_CNT = "1" *) 
   (* C_PROBE617_WIDTH = "1" *) 
   (* C_PROBE618_MU_CNT = "1" *) 
   (* C_PROBE618_WIDTH = "1" *) 
   (* C_PROBE619_MU_CNT = "1" *) 
   (* C_PROBE619_WIDTH = "1" *) 
   (* C_PROBE61_MU_CNT = "1" *) 
   (* C_PROBE61_WIDTH = "1" *) 
   (* C_PROBE620_MU_CNT = "1" *) 
   (* C_PROBE620_WIDTH = "1" *) 
   (* C_PROBE621_MU_CNT = "1" *) 
   (* C_PROBE621_WIDTH = "1" *) 
   (* C_PROBE622_MU_CNT = "1" *) 
   (* C_PROBE622_WIDTH = "1" *) 
   (* C_PROBE623_MU_CNT = "1" *) 
   (* C_PROBE623_WIDTH = "1" *) 
   (* C_PROBE624_MU_CNT = "1" *) 
   (* C_PROBE624_WIDTH = "1" *) 
   (* C_PROBE625_MU_CNT = "1" *) 
   (* C_PROBE625_WIDTH = "1" *) 
   (* C_PROBE626_MU_CNT = "1" *) 
   (* C_PROBE626_WIDTH = "1" *) 
   (* C_PROBE627_MU_CNT = "1" *) 
   (* C_PROBE627_WIDTH = "1" *) 
   (* C_PROBE628_MU_CNT = "1" *) 
   (* C_PROBE628_WIDTH = "1" *) 
   (* C_PROBE629_MU_CNT = "1" *) 
   (* C_PROBE629_WIDTH = "1" *) 
   (* C_PROBE62_MU_CNT = "1" *) 
   (* C_PROBE62_WIDTH = "1" *) 
   (* C_PROBE630_MU_CNT = "1" *) 
   (* C_PROBE630_WIDTH = "1" *) 
   (* C_PROBE631_MU_CNT = "1" *) 
   (* C_PROBE631_WIDTH = "1" *) 
   (* C_PROBE632_MU_CNT = "1" *) 
   (* C_PROBE632_WIDTH = "1" *) 
   (* C_PROBE633_MU_CNT = "1" *) 
   (* C_PROBE633_WIDTH = "1" *) 
   (* C_PROBE634_MU_CNT = "1" *) 
   (* C_PROBE634_WIDTH = "1" *) 
   (* C_PROBE635_MU_CNT = "1" *) 
   (* C_PROBE635_WIDTH = "1" *) 
   (* C_PROBE636_MU_CNT = "1" *) 
   (* C_PROBE636_WIDTH = "1" *) 
   (* C_PROBE637_MU_CNT = "1" *) 
   (* C_PROBE637_WIDTH = "1" *) 
   (* C_PROBE638_MU_CNT = "1" *) 
   (* C_PROBE638_WIDTH = "1" *) 
   (* C_PROBE639_MU_CNT = "1" *) 
   (* C_PROBE639_WIDTH = "1" *) 
   (* C_PROBE63_MU_CNT = "1" *) 
   (* C_PROBE63_WIDTH = "1" *) 
   (* C_PROBE640_MU_CNT = "1" *) 
   (* C_PROBE640_WIDTH = "1" *) 
   (* C_PROBE641_MU_CNT = "1" *) 
   (* C_PROBE641_WIDTH = "1" *) 
   (* C_PROBE642_MU_CNT = "1" *) 
   (* C_PROBE642_WIDTH = "1" *) 
   (* C_PROBE643_MU_CNT = "1" *) 
   (* C_PROBE643_WIDTH = "1" *) 
   (* C_PROBE644_MU_CNT = "1" *) 
   (* C_PROBE644_WIDTH = "1" *) 
   (* C_PROBE645_MU_CNT = "1" *) 
   (* C_PROBE645_WIDTH = "1" *) 
   (* C_PROBE646_MU_CNT = "1" *) 
   (* C_PROBE646_WIDTH = "1" *) 
   (* C_PROBE647_MU_CNT = "1" *) 
   (* C_PROBE647_WIDTH = "1" *) 
   (* C_PROBE648_MU_CNT = "1" *) 
   (* C_PROBE648_WIDTH = "1" *) 
   (* C_PROBE649_MU_CNT = "1" *) 
   (* C_PROBE649_WIDTH = "1" *) 
   (* C_PROBE64_MU_CNT = "1" *) 
   (* C_PROBE64_WIDTH = "1" *) 
   (* C_PROBE650_MU_CNT = "1" *) 
   (* C_PROBE650_WIDTH = "1" *) 
   (* C_PROBE651_MU_CNT = "1" *) 
   (* C_PROBE651_WIDTH = "1" *) 
   (* C_PROBE652_MU_CNT = "1" *) 
   (* C_PROBE652_WIDTH = "1" *) 
   (* C_PROBE653_MU_CNT = "1" *) 
   (* C_PROBE653_WIDTH = "1" *) 
   (* C_PROBE654_MU_CNT = "1" *) 
   (* C_PROBE654_WIDTH = "1" *) 
   (* C_PROBE655_MU_CNT = "1" *) 
   (* C_PROBE655_WIDTH = "1" *) 
   (* C_PROBE656_MU_CNT = "1" *) 
   (* C_PROBE656_WIDTH = "1" *) 
   (* C_PROBE657_MU_CNT = "1" *) 
   (* C_PROBE657_WIDTH = "1" *) 
   (* C_PROBE658_MU_CNT = "1" *) 
   (* C_PROBE658_WIDTH = "1" *) 
   (* C_PROBE659_MU_CNT = "1" *) 
   (* C_PROBE659_WIDTH = "1" *) 
   (* C_PROBE65_MU_CNT = "1" *) 
   (* C_PROBE65_WIDTH = "1" *) 
   (* C_PROBE660_MU_CNT = "1" *) 
   (* C_PROBE660_WIDTH = "1" *) 
   (* C_PROBE661_MU_CNT = "1" *) 
   (* C_PROBE661_WIDTH = "1" *) 
   (* C_PROBE662_MU_CNT = "1" *) 
   (* C_PROBE662_WIDTH = "1" *) 
   (* C_PROBE663_MU_CNT = "1" *) 
   (* C_PROBE663_WIDTH = "1" *) 
   (* C_PROBE664_MU_CNT = "1" *) 
   (* C_PROBE664_WIDTH = "1" *) 
   (* C_PROBE665_MU_CNT = "1" *) 
   (* C_PROBE665_WIDTH = "1" *) 
   (* C_PROBE666_MU_CNT = "1" *) 
   (* C_PROBE666_WIDTH = "1" *) 
   (* C_PROBE667_MU_CNT = "1" *) 
   (* C_PROBE667_WIDTH = "1" *) 
   (* C_PROBE668_MU_CNT = "1" *) 
   (* C_PROBE668_WIDTH = "1" *) 
   (* C_PROBE669_MU_CNT = "1" *) 
   (* C_PROBE669_WIDTH = "1" *) 
   (* C_PROBE66_MU_CNT = "1" *) 
   (* C_PROBE66_WIDTH = "1" *) 
   (* C_PROBE670_MU_CNT = "1" *) 
   (* C_PROBE670_WIDTH = "1" *) 
   (* C_PROBE671_MU_CNT = "1" *) 
   (* C_PROBE671_WIDTH = "1" *) 
   (* C_PROBE672_MU_CNT = "1" *) 
   (* C_PROBE672_WIDTH = "1" *) 
   (* C_PROBE673_MU_CNT = "1" *) 
   (* C_PROBE673_WIDTH = "1" *) 
   (* C_PROBE674_MU_CNT = "1" *) 
   (* C_PROBE674_WIDTH = "1" *) 
   (* C_PROBE675_MU_CNT = "1" *) 
   (* C_PROBE675_WIDTH = "1" *) 
   (* C_PROBE676_MU_CNT = "1" *) 
   (* C_PROBE676_WIDTH = "1" *) 
   (* C_PROBE677_MU_CNT = "1" *) 
   (* C_PROBE677_WIDTH = "1" *) 
   (* C_PROBE678_MU_CNT = "1" *) 
   (* C_PROBE678_WIDTH = "1" *) 
   (* C_PROBE679_MU_CNT = "1" *) 
   (* C_PROBE679_WIDTH = "1" *) 
   (* C_PROBE67_MU_CNT = "1" *) 
   (* C_PROBE67_WIDTH = "1" *) 
   (* C_PROBE680_MU_CNT = "1" *) 
   (* C_PROBE680_WIDTH = "1" *) 
   (* C_PROBE681_MU_CNT = "1" *) 
   (* C_PROBE681_WIDTH = "1" *) 
   (* C_PROBE682_MU_CNT = "1" *) 
   (* C_PROBE682_WIDTH = "1" *) 
   (* C_PROBE683_MU_CNT = "1" *) 
   (* C_PROBE683_WIDTH = "1" *) 
   (* C_PROBE684_MU_CNT = "1" *) 
   (* C_PROBE684_WIDTH = "1" *) 
   (* C_PROBE685_MU_CNT = "1" *) 
   (* C_PROBE685_WIDTH = "1" *) 
   (* C_PROBE686_MU_CNT = "1" *) 
   (* C_PROBE686_WIDTH = "1" *) 
   (* C_PROBE687_MU_CNT = "1" *) 
   (* C_PROBE687_WIDTH = "1" *) 
   (* C_PROBE688_MU_CNT = "1" *) 
   (* C_PROBE688_WIDTH = "1" *) 
   (* C_PROBE689_MU_CNT = "1" *) 
   (* C_PROBE689_WIDTH = "1" *) 
   (* C_PROBE68_MU_CNT = "1" *) 
   (* C_PROBE68_WIDTH = "1" *) 
   (* C_PROBE690_MU_CNT = "1" *) 
   (* C_PROBE690_WIDTH = "1" *) 
   (* C_PROBE691_MU_CNT = "1" *) 
   (* C_PROBE691_WIDTH = "1" *) 
   (* C_PROBE692_MU_CNT = "1" *) 
   (* C_PROBE692_WIDTH = "1" *) 
   (* C_PROBE693_MU_CNT = "1" *) 
   (* C_PROBE693_WIDTH = "1" *) 
   (* C_PROBE694_MU_CNT = "1" *) 
   (* C_PROBE694_WIDTH = "1" *) 
   (* C_PROBE695_MU_CNT = "1" *) 
   (* C_PROBE695_WIDTH = "1" *) 
   (* C_PROBE696_MU_CNT = "1" *) 
   (* C_PROBE696_WIDTH = "1" *) 
   (* C_PROBE697_MU_CNT = "1" *) 
   (* C_PROBE697_WIDTH = "1" *) 
   (* C_PROBE698_MU_CNT = "1" *) 
   (* C_PROBE698_WIDTH = "1" *) 
   (* C_PROBE699_MU_CNT = "1" *) 
   (* C_PROBE699_WIDTH = "1" *) 
   (* C_PROBE69_MU_CNT = "1" *) 
   (* C_PROBE69_WIDTH = "1" *) 
   (* C_PROBE6_MU_CNT = "1" *) 
   (* C_PROBE6_WIDTH = "32" *) 
   (* C_PROBE700_MU_CNT = "1" *) 
   (* C_PROBE700_WIDTH = "1" *) 
   (* C_PROBE701_MU_CNT = "1" *) 
   (* C_PROBE701_WIDTH = "1" *) 
   (* C_PROBE702_MU_CNT = "1" *) 
   (* C_PROBE702_WIDTH = "1" *) 
   (* C_PROBE703_MU_CNT = "1" *) 
   (* C_PROBE703_WIDTH = "1" *) 
   (* C_PROBE704_MU_CNT = "1" *) 
   (* C_PROBE704_WIDTH = "1" *) 
   (* C_PROBE705_MU_CNT = "1" *) 
   (* C_PROBE705_WIDTH = "1" *) 
   (* C_PROBE706_MU_CNT = "1" *) 
   (* C_PROBE706_WIDTH = "1" *) 
   (* C_PROBE707_MU_CNT = "1" *) 
   (* C_PROBE707_WIDTH = "1" *) 
   (* C_PROBE708_MU_CNT = "1" *) 
   (* C_PROBE708_WIDTH = "1" *) 
   (* C_PROBE709_MU_CNT = "1" *) 
   (* C_PROBE709_WIDTH = "1" *) 
   (* C_PROBE70_MU_CNT = "1" *) 
   (* C_PROBE70_WIDTH = "1" *) 
   (* C_PROBE710_MU_CNT = "1" *) 
   (* C_PROBE710_WIDTH = "1" *) 
   (* C_PROBE711_MU_CNT = "1" *) 
   (* C_PROBE711_WIDTH = "1" *) 
   (* C_PROBE712_MU_CNT = "1" *) 
   (* C_PROBE712_WIDTH = "1" *) 
   (* C_PROBE713_MU_CNT = "1" *) 
   (* C_PROBE713_WIDTH = "1" *) 
   (* C_PROBE714_MU_CNT = "1" *) 
   (* C_PROBE714_WIDTH = "1" *) 
   (* C_PROBE715_MU_CNT = "1" *) 
   (* C_PROBE715_WIDTH = "1" *) 
   (* C_PROBE716_MU_CNT = "1" *) 
   (* C_PROBE716_WIDTH = "1" *) 
   (* C_PROBE717_MU_CNT = "1" *) 
   (* C_PROBE717_WIDTH = "1" *) 
   (* C_PROBE718_MU_CNT = "1" *) 
   (* C_PROBE718_WIDTH = "1" *) 
   (* C_PROBE719_MU_CNT = "1" *) 
   (* C_PROBE719_WIDTH = "1" *) 
   (* C_PROBE71_MU_CNT = "1" *) 
   (* C_PROBE71_WIDTH = "1" *) 
   (* C_PROBE720_MU_CNT = "1" *) 
   (* C_PROBE720_WIDTH = "1" *) 
   (* C_PROBE721_MU_CNT = "1" *) 
   (* C_PROBE721_WIDTH = "1" *) 
   (* C_PROBE722_MU_CNT = "1" *) 
   (* C_PROBE722_WIDTH = "1" *) 
   (* C_PROBE723_MU_CNT = "1" *) 
   (* C_PROBE723_WIDTH = "1" *) 
   (* C_PROBE724_MU_CNT = "1" *) 
   (* C_PROBE724_WIDTH = "1" *) 
   (* C_PROBE725_MU_CNT = "1" *) 
   (* C_PROBE725_WIDTH = "1" *) 
   (* C_PROBE726_MU_CNT = "1" *) 
   (* C_PROBE726_WIDTH = "1" *) 
   (* C_PROBE727_MU_CNT = "1" *) 
   (* C_PROBE727_WIDTH = "1" *) 
   (* C_PROBE728_MU_CNT = "1" *) 
   (* C_PROBE728_WIDTH = "1" *) 
   (* C_PROBE729_MU_CNT = "1" *) 
   (* C_PROBE729_WIDTH = "1" *) 
   (* C_PROBE72_MU_CNT = "1" *) 
   (* C_PROBE72_WIDTH = "1" *) 
   (* C_PROBE730_MU_CNT = "1" *) 
   (* C_PROBE730_WIDTH = "1" *) 
   (* C_PROBE731_MU_CNT = "1" *) 
   (* C_PROBE731_WIDTH = "1" *) 
   (* C_PROBE732_MU_CNT = "1" *) 
   (* C_PROBE732_WIDTH = "1" *) 
   (* C_PROBE733_MU_CNT = "1" *) 
   (* C_PROBE733_WIDTH = "1" *) 
   (* C_PROBE734_MU_CNT = "1" *) 
   (* C_PROBE734_WIDTH = "1" *) 
   (* C_PROBE735_MU_CNT = "1" *) 
   (* C_PROBE735_WIDTH = "1" *) 
   (* C_PROBE736_MU_CNT = "1" *) 
   (* C_PROBE736_WIDTH = "1" *) 
   (* C_PROBE737_MU_CNT = "1" *) 
   (* C_PROBE737_WIDTH = "1" *) 
   (* C_PROBE738_MU_CNT = "1" *) 
   (* C_PROBE738_WIDTH = "1" *) 
   (* C_PROBE739_MU_CNT = "1" *) 
   (* C_PROBE739_WIDTH = "1" *) 
   (* C_PROBE73_MU_CNT = "1" *) 
   (* C_PROBE73_WIDTH = "1" *) 
   (* C_PROBE740_MU_CNT = "1" *) 
   (* C_PROBE740_WIDTH = "1" *) 
   (* C_PROBE741_MU_CNT = "1" *) 
   (* C_PROBE741_WIDTH = "1" *) 
   (* C_PROBE742_MU_CNT = "1" *) 
   (* C_PROBE742_WIDTH = "1" *) 
   (* C_PROBE743_MU_CNT = "1" *) 
   (* C_PROBE743_WIDTH = "1" *) 
   (* C_PROBE744_MU_CNT = "1" *) 
   (* C_PROBE744_WIDTH = "1" *) 
   (* C_PROBE745_MU_CNT = "1" *) 
   (* C_PROBE745_WIDTH = "1" *) 
   (* C_PROBE746_MU_CNT = "1" *) 
   (* C_PROBE746_WIDTH = "1" *) 
   (* C_PROBE747_MU_CNT = "1" *) 
   (* C_PROBE747_WIDTH = "1" *) 
   (* C_PROBE748_MU_CNT = "1" *) 
   (* C_PROBE748_WIDTH = "1" *) 
   (* C_PROBE749_MU_CNT = "1" *) 
   (* C_PROBE749_WIDTH = "1" *) 
   (* C_PROBE74_MU_CNT = "1" *) 
   (* C_PROBE74_WIDTH = "1" *) 
   (* C_PROBE750_MU_CNT = "1" *) 
   (* C_PROBE750_WIDTH = "1" *) 
   (* C_PROBE751_MU_CNT = "1" *) 
   (* C_PROBE751_WIDTH = "1" *) 
   (* C_PROBE752_MU_CNT = "1" *) 
   (* C_PROBE752_WIDTH = "1" *) 
   (* C_PROBE753_MU_CNT = "1" *) 
   (* C_PROBE753_WIDTH = "1" *) 
   (* C_PROBE754_MU_CNT = "1" *) 
   (* C_PROBE754_WIDTH = "1" *) 
   (* C_PROBE755_MU_CNT = "1" *) 
   (* C_PROBE755_WIDTH = "1" *) 
   (* C_PROBE756_MU_CNT = "1" *) 
   (* C_PROBE756_WIDTH = "1" *) 
   (* C_PROBE757_MU_CNT = "1" *) 
   (* C_PROBE757_WIDTH = "1" *) 
   (* C_PROBE758_MU_CNT = "1" *) 
   (* C_PROBE758_WIDTH = "1" *) 
   (* C_PROBE759_MU_CNT = "1" *) 
   (* C_PROBE759_WIDTH = "1" *) 
   (* C_PROBE75_MU_CNT = "1" *) 
   (* C_PROBE75_WIDTH = "1" *) 
   (* C_PROBE760_MU_CNT = "1" *) 
   (* C_PROBE760_WIDTH = "1" *) 
   (* C_PROBE761_MU_CNT = "1" *) 
   (* C_PROBE761_WIDTH = "1" *) 
   (* C_PROBE762_MU_CNT = "1" *) 
   (* C_PROBE762_WIDTH = "1" *) 
   (* C_PROBE763_MU_CNT = "1" *) 
   (* C_PROBE763_WIDTH = "1" *) 
   (* C_PROBE764_MU_CNT = "1" *) 
   (* C_PROBE764_WIDTH = "1" *) 
   (* C_PROBE765_MU_CNT = "1" *) 
   (* C_PROBE765_WIDTH = "1" *) 
   (* C_PROBE766_MU_CNT = "1" *) 
   (* C_PROBE766_WIDTH = "1" *) 
   (* C_PROBE767_MU_CNT = "1" *) 
   (* C_PROBE767_WIDTH = "1" *) 
   (* C_PROBE768_MU_CNT = "1" *) 
   (* C_PROBE768_WIDTH = "1" *) 
   (* C_PROBE769_MU_CNT = "1" *) 
   (* C_PROBE769_WIDTH = "1" *) 
   (* C_PROBE76_MU_CNT = "1" *) 
   (* C_PROBE76_WIDTH = "1" *) 
   (* C_PROBE770_MU_CNT = "1" *) 
   (* C_PROBE770_WIDTH = "1" *) 
   (* C_PROBE771_MU_CNT = "1" *) 
   (* C_PROBE771_WIDTH = "1" *) 
   (* C_PROBE772_MU_CNT = "1" *) 
   (* C_PROBE772_WIDTH = "1" *) 
   (* C_PROBE773_MU_CNT = "1" *) 
   (* C_PROBE773_WIDTH = "1" *) 
   (* C_PROBE774_MU_CNT = "1" *) 
   (* C_PROBE774_WIDTH = "1" *) 
   (* C_PROBE775_MU_CNT = "1" *) 
   (* C_PROBE775_WIDTH = "1" *) 
   (* C_PROBE776_MU_CNT = "1" *) 
   (* C_PROBE776_WIDTH = "1" *) 
   (* C_PROBE777_MU_CNT = "1" *) 
   (* C_PROBE777_WIDTH = "1" *) 
   (* C_PROBE778_MU_CNT = "1" *) 
   (* C_PROBE778_WIDTH = "1" *) 
   (* C_PROBE779_MU_CNT = "1" *) 
   (* C_PROBE779_WIDTH = "1" *) 
   (* C_PROBE77_MU_CNT = "1" *) 
   (* C_PROBE77_WIDTH = "1" *) 
   (* C_PROBE780_MU_CNT = "1" *) 
   (* C_PROBE780_WIDTH = "1" *) 
   (* C_PROBE781_MU_CNT = "1" *) 
   (* C_PROBE781_WIDTH = "1" *) 
   (* C_PROBE782_MU_CNT = "1" *) 
   (* C_PROBE782_WIDTH = "1" *) 
   (* C_PROBE783_MU_CNT = "1" *) 
   (* C_PROBE783_WIDTH = "1" *) 
   (* C_PROBE784_MU_CNT = "1" *) 
   (* C_PROBE784_WIDTH = "1" *) 
   (* C_PROBE785_MU_CNT = "1" *) 
   (* C_PROBE785_WIDTH = "1" *) 
   (* C_PROBE786_MU_CNT = "1" *) 
   (* C_PROBE786_WIDTH = "1" *) 
   (* C_PROBE787_MU_CNT = "1" *) 
   (* C_PROBE787_WIDTH = "1" *) 
   (* C_PROBE788_MU_CNT = "1" *) 
   (* C_PROBE788_WIDTH = "1" *) 
   (* C_PROBE789_MU_CNT = "1" *) 
   (* C_PROBE789_WIDTH = "1" *) 
   (* C_PROBE78_MU_CNT = "1" *) 
   (* C_PROBE78_WIDTH = "1" *) 
   (* C_PROBE790_MU_CNT = "1" *) 
   (* C_PROBE790_WIDTH = "1" *) 
   (* C_PROBE791_MU_CNT = "1" *) 
   (* C_PROBE791_WIDTH = "1" *) 
   (* C_PROBE792_MU_CNT = "1" *) 
   (* C_PROBE792_WIDTH = "1" *) 
   (* C_PROBE793_MU_CNT = "1" *) 
   (* C_PROBE793_WIDTH = "1" *) 
   (* C_PROBE794_MU_CNT = "1" *) 
   (* C_PROBE794_WIDTH = "1" *) 
   (* C_PROBE795_MU_CNT = "1" *) 
   (* C_PROBE795_WIDTH = "1" *) 
   (* C_PROBE796_MU_CNT = "1" *) 
   (* C_PROBE796_WIDTH = "1" *) 
   (* C_PROBE797_MU_CNT = "1" *) 
   (* C_PROBE797_WIDTH = "1" *) 
   (* C_PROBE798_MU_CNT = "1" *) 
   (* C_PROBE798_WIDTH = "1" *) 
   (* C_PROBE799_MU_CNT = "1" *) 
   (* C_PROBE799_WIDTH = "1" *) 
   (* C_PROBE79_MU_CNT = "1" *) 
   (* C_PROBE79_WIDTH = "1" *) 
   (* C_PROBE7_MU_CNT = "1" *) 
   (* C_PROBE7_WIDTH = "1" *) 
   (* C_PROBE800_MU_CNT = "1" *) 
   (* C_PROBE800_WIDTH = "1" *) 
   (* C_PROBE801_MU_CNT = "1" *) 
   (* C_PROBE801_WIDTH = "1" *) 
   (* C_PROBE802_MU_CNT = "1" *) 
   (* C_PROBE802_WIDTH = "1" *) 
   (* C_PROBE803_MU_CNT = "1" *) 
   (* C_PROBE803_WIDTH = "1" *) 
   (* C_PROBE804_MU_CNT = "1" *) 
   (* C_PROBE804_WIDTH = "1" *) 
   (* C_PROBE805_MU_CNT = "1" *) 
   (* C_PROBE805_WIDTH = "1" *) 
   (* C_PROBE806_MU_CNT = "1" *) 
   (* C_PROBE806_WIDTH = "1" *) 
   (* C_PROBE807_MU_CNT = "1" *) 
   (* C_PROBE807_WIDTH = "1" *) 
   (* C_PROBE808_MU_CNT = "1" *) 
   (* C_PROBE808_WIDTH = "1" *) 
   (* C_PROBE809_MU_CNT = "1" *) 
   (* C_PROBE809_WIDTH = "1" *) 
   (* C_PROBE80_MU_CNT = "1" *) 
   (* C_PROBE80_WIDTH = "1" *) 
   (* C_PROBE810_MU_CNT = "1" *) 
   (* C_PROBE810_WIDTH = "1" *) 
   (* C_PROBE811_MU_CNT = "1" *) 
   (* C_PROBE811_WIDTH = "1" *) 
   (* C_PROBE812_MU_CNT = "1" *) 
   (* C_PROBE812_WIDTH = "1" *) 
   (* C_PROBE813_MU_CNT = "1" *) 
   (* C_PROBE813_WIDTH = "1" *) 
   (* C_PROBE814_MU_CNT = "1" *) 
   (* C_PROBE814_WIDTH = "1" *) 
   (* C_PROBE815_MU_CNT = "1" *) 
   (* C_PROBE815_WIDTH = "1" *) 
   (* C_PROBE816_MU_CNT = "1" *) 
   (* C_PROBE816_WIDTH = "1" *) 
   (* C_PROBE817_MU_CNT = "1" *) 
   (* C_PROBE817_WIDTH = "1" *) 
   (* C_PROBE818_MU_CNT = "1" *) 
   (* C_PROBE818_WIDTH = "1" *) 
   (* C_PROBE819_MU_CNT = "1" *) 
   (* C_PROBE819_WIDTH = "1" *) 
   (* C_PROBE81_MU_CNT = "1" *) 
   (* C_PROBE81_WIDTH = "1" *) 
   (* C_PROBE820_MU_CNT = "1" *) 
   (* C_PROBE820_WIDTH = "1" *) 
   (* C_PROBE821_MU_CNT = "1" *) 
   (* C_PROBE821_WIDTH = "1" *) 
   (* C_PROBE822_MU_CNT = "1" *) 
   (* C_PROBE822_WIDTH = "1" *) 
   (* C_PROBE823_MU_CNT = "1" *) 
   (* C_PROBE823_WIDTH = "1" *) 
   (* C_PROBE824_MU_CNT = "1" *) 
   (* C_PROBE824_WIDTH = "1" *) 
   (* C_PROBE825_MU_CNT = "1" *) 
   (* C_PROBE825_WIDTH = "1" *) 
   (* C_PROBE826_MU_CNT = "1" *) 
   (* C_PROBE826_WIDTH = "1" *) 
   (* C_PROBE827_MU_CNT = "1" *) 
   (* C_PROBE827_WIDTH = "1" *) 
   (* C_PROBE828_MU_CNT = "1" *) 
   (* C_PROBE828_WIDTH = "1" *) 
   (* C_PROBE829_MU_CNT = "1" *) 
   (* C_PROBE829_WIDTH = "1" *) 
   (* C_PROBE82_MU_CNT = "1" *) 
   (* C_PROBE82_WIDTH = "1" *) 
   (* C_PROBE830_MU_CNT = "1" *) 
   (* C_PROBE830_WIDTH = "1" *) 
   (* C_PROBE831_MU_CNT = "1" *) 
   (* C_PROBE831_WIDTH = "1" *) 
   (* C_PROBE832_MU_CNT = "1" *) 
   (* C_PROBE832_WIDTH = "1" *) 
   (* C_PROBE833_MU_CNT = "1" *) 
   (* C_PROBE833_WIDTH = "1" *) 
   (* C_PROBE834_MU_CNT = "1" *) 
   (* C_PROBE834_WIDTH = "1" *) 
   (* C_PROBE835_MU_CNT = "1" *) 
   (* C_PROBE835_WIDTH = "1" *) 
   (* C_PROBE836_MU_CNT = "1" *) 
   (* C_PROBE836_WIDTH = "1" *) 
   (* C_PROBE837_MU_CNT = "1" *) 
   (* C_PROBE837_WIDTH = "1" *) 
   (* C_PROBE838_MU_CNT = "1" *) 
   (* C_PROBE838_WIDTH = "1" *) 
   (* C_PROBE839_MU_CNT = "1" *) 
   (* C_PROBE839_WIDTH = "1" *) 
   (* C_PROBE83_MU_CNT = "1" *) 
   (* C_PROBE83_WIDTH = "1" *) 
   (* C_PROBE840_MU_CNT = "1" *) 
   (* C_PROBE840_WIDTH = "1" *) 
   (* C_PROBE841_MU_CNT = "1" *) 
   (* C_PROBE841_WIDTH = "1" *) 
   (* C_PROBE842_MU_CNT = "1" *) 
   (* C_PROBE842_WIDTH = "1" *) 
   (* C_PROBE843_MU_CNT = "1" *) 
   (* C_PROBE843_WIDTH = "1" *) 
   (* C_PROBE844_MU_CNT = "1" *) 
   (* C_PROBE844_WIDTH = "1" *) 
   (* C_PROBE845_MU_CNT = "1" *) 
   (* C_PROBE845_WIDTH = "1" *) 
   (* C_PROBE846_MU_CNT = "1" *) 
   (* C_PROBE846_WIDTH = "1" *) 
   (* C_PROBE847_MU_CNT = "1" *) 
   (* C_PROBE847_WIDTH = "1" *) 
   (* C_PROBE848_MU_CNT = "1" *) 
   (* C_PROBE848_WIDTH = "1" *) 
   (* C_PROBE849_MU_CNT = "1" *) 
   (* C_PROBE849_WIDTH = "1" *) 
   (* C_PROBE84_MU_CNT = "1" *) 
   (* C_PROBE84_WIDTH = "1" *) 
   (* C_PROBE850_MU_CNT = "1" *) 
   (* C_PROBE850_WIDTH = "1" *) 
   (* C_PROBE851_MU_CNT = "1" *) 
   (* C_PROBE851_WIDTH = "1" *) 
   (* C_PROBE852_MU_CNT = "1" *) 
   (* C_PROBE852_WIDTH = "1" *) 
   (* C_PROBE853_MU_CNT = "1" *) 
   (* C_PROBE853_WIDTH = "1" *) 
   (* C_PROBE854_MU_CNT = "1" *) 
   (* C_PROBE854_WIDTH = "1" *) 
   (* C_PROBE855_MU_CNT = "1" *) 
   (* C_PROBE855_WIDTH = "1" *) 
   (* C_PROBE856_MU_CNT = "1" *) 
   (* C_PROBE856_WIDTH = "1" *) 
   (* C_PROBE857_MU_CNT = "1" *) 
   (* C_PROBE857_WIDTH = "1" *) 
   (* C_PROBE858_MU_CNT = "1" *) 
   (* C_PROBE858_WIDTH = "1" *) 
   (* C_PROBE859_MU_CNT = "1" *) 
   (* C_PROBE859_WIDTH = "1" *) 
   (* C_PROBE85_MU_CNT = "1" *) 
   (* C_PROBE85_WIDTH = "1" *) 
   (* C_PROBE860_MU_CNT = "1" *) 
   (* C_PROBE860_WIDTH = "1" *) 
   (* C_PROBE861_MU_CNT = "1" *) 
   (* C_PROBE861_WIDTH = "1" *) 
   (* C_PROBE862_MU_CNT = "1" *) 
   (* C_PROBE862_WIDTH = "1" *) 
   (* C_PROBE863_MU_CNT = "1" *) 
   (* C_PROBE863_WIDTH = "1" *) 
   (* C_PROBE864_MU_CNT = "1" *) 
   (* C_PROBE864_WIDTH = "1" *) 
   (* C_PROBE865_MU_CNT = "1" *) 
   (* C_PROBE865_WIDTH = "1" *) 
   (* C_PROBE866_MU_CNT = "1" *) 
   (* C_PROBE866_WIDTH = "1" *) 
   (* C_PROBE867_MU_CNT = "1" *) 
   (* C_PROBE867_WIDTH = "1" *) 
   (* C_PROBE868_MU_CNT = "1" *) 
   (* C_PROBE868_WIDTH = "1" *) 
   (* C_PROBE869_MU_CNT = "1" *) 
   (* C_PROBE869_WIDTH = "1" *) 
   (* C_PROBE86_MU_CNT = "1" *) 
   (* C_PROBE86_WIDTH = "1" *) 
   (* C_PROBE870_MU_CNT = "1" *) 
   (* C_PROBE870_WIDTH = "1" *) 
   (* C_PROBE871_MU_CNT = "1" *) 
   (* C_PROBE871_WIDTH = "1" *) 
   (* C_PROBE872_MU_CNT = "1" *) 
   (* C_PROBE872_WIDTH = "1" *) 
   (* C_PROBE873_MU_CNT = "1" *) 
   (* C_PROBE873_WIDTH = "1" *) 
   (* C_PROBE874_MU_CNT = "1" *) 
   (* C_PROBE874_WIDTH = "1" *) 
   (* C_PROBE875_MU_CNT = "1" *) 
   (* C_PROBE875_WIDTH = "1" *) 
   (* C_PROBE876_MU_CNT = "1" *) 
   (* C_PROBE876_WIDTH = "1" *) 
   (* C_PROBE877_MU_CNT = "1" *) 
   (* C_PROBE877_WIDTH = "1" *) 
   (* C_PROBE878_MU_CNT = "1" *) 
   (* C_PROBE878_WIDTH = "1" *) 
   (* C_PROBE879_MU_CNT = "1" *) 
   (* C_PROBE879_WIDTH = "1" *) 
   (* C_PROBE87_MU_CNT = "1" *) 
   (* C_PROBE87_WIDTH = "1" *) 
   (* C_PROBE880_MU_CNT = "1" *) 
   (* C_PROBE880_WIDTH = "1" *) 
   (* C_PROBE881_MU_CNT = "1" *) 
   (* C_PROBE881_WIDTH = "1" *) 
   (* C_PROBE882_MU_CNT = "1" *) 
   (* C_PROBE882_WIDTH = "1" *) 
   (* C_PROBE883_MU_CNT = "1" *) 
   (* C_PROBE883_WIDTH = "1" *) 
   (* C_PROBE884_MU_CNT = "1" *) 
   (* C_PROBE884_WIDTH = "1" *) 
   (* C_PROBE885_MU_CNT = "1" *) 
   (* C_PROBE885_WIDTH = "1" *) 
   (* C_PROBE886_MU_CNT = "1" *) 
   (* C_PROBE886_WIDTH = "1" *) 
   (* C_PROBE887_MU_CNT = "1" *) 
   (* C_PROBE887_WIDTH = "1" *) 
   (* C_PROBE888_MU_CNT = "1" *) 
   (* C_PROBE888_WIDTH = "1" *) 
   (* C_PROBE889_MU_CNT = "1" *) 
   (* C_PROBE889_WIDTH = "1" *) 
   (* C_PROBE88_MU_CNT = "1" *) 
   (* C_PROBE88_WIDTH = "1" *) 
   (* C_PROBE890_MU_CNT = "1" *) 
   (* C_PROBE890_WIDTH = "1" *) 
   (* C_PROBE891_MU_CNT = "1" *) 
   (* C_PROBE891_WIDTH = "1" *) 
   (* C_PROBE892_MU_CNT = "1" *) 
   (* C_PROBE892_WIDTH = "1" *) 
   (* C_PROBE893_MU_CNT = "1" *) 
   (* C_PROBE893_WIDTH = "1" *) 
   (* C_PROBE894_MU_CNT = "1" *) 
   (* C_PROBE894_WIDTH = "1" *) 
   (* C_PROBE895_MU_CNT = "1" *) 
   (* C_PROBE895_WIDTH = "1" *) 
   (* C_PROBE896_MU_CNT = "1" *) 
   (* C_PROBE896_WIDTH = "1" *) 
   (* C_PROBE897_MU_CNT = "1" *) 
   (* C_PROBE897_WIDTH = "1" *) 
   (* C_PROBE898_MU_CNT = "1" *) 
   (* C_PROBE898_WIDTH = "1" *) 
   (* C_PROBE899_MU_CNT = "1" *) 
   (* C_PROBE899_WIDTH = "1" *) 
   (* C_PROBE89_MU_CNT = "1" *) 
   (* C_PROBE89_WIDTH = "1" *) 
   (* C_PROBE8_MU_CNT = "1" *) 
   (* C_PROBE8_WIDTH = "1" *) 
   (* C_PROBE900_MU_CNT = "1" *) 
   (* C_PROBE900_WIDTH = "1" *) 
   (* C_PROBE901_MU_CNT = "1" *) 
   (* C_PROBE901_WIDTH = "1" *) 
   (* C_PROBE902_MU_CNT = "1" *) 
   (* C_PROBE902_WIDTH = "1" *) 
   (* C_PROBE903_MU_CNT = "1" *) 
   (* C_PROBE903_WIDTH = "1" *) 
   (* C_PROBE904_MU_CNT = "1" *) 
   (* C_PROBE904_WIDTH = "1" *) 
   (* C_PROBE905_MU_CNT = "1" *) 
   (* C_PROBE905_WIDTH = "1" *) 
   (* C_PROBE906_MU_CNT = "1" *) 
   (* C_PROBE906_WIDTH = "1" *) 
   (* C_PROBE907_MU_CNT = "1" *) 
   (* C_PROBE907_WIDTH = "1" *) 
   (* C_PROBE908_MU_CNT = "1" *) 
   (* C_PROBE908_WIDTH = "1" *) 
   (* C_PROBE909_MU_CNT = "1" *) 
   (* C_PROBE909_WIDTH = "1" *) 
   (* C_PROBE90_MU_CNT = "1" *) 
   (* C_PROBE90_WIDTH = "1" *) 
   (* C_PROBE910_MU_CNT = "1" *) 
   (* C_PROBE910_WIDTH = "1" *) 
   (* C_PROBE911_MU_CNT = "1" *) 
   (* C_PROBE911_WIDTH = "1" *) 
   (* C_PROBE912_MU_CNT = "1" *) 
   (* C_PROBE912_WIDTH = "1" *) 
   (* C_PROBE913_MU_CNT = "1" *) 
   (* C_PROBE913_WIDTH = "1" *) 
   (* C_PROBE914_MU_CNT = "1" *) 
   (* C_PROBE914_WIDTH = "1" *) 
   (* C_PROBE915_MU_CNT = "1" *) 
   (* C_PROBE915_WIDTH = "1" *) 
   (* C_PROBE916_MU_CNT = "1" *) 
   (* C_PROBE916_WIDTH = "1" *) 
   (* C_PROBE917_MU_CNT = "1" *) 
   (* C_PROBE917_WIDTH = "1" *) 
   (* C_PROBE918_MU_CNT = "1" *) 
   (* C_PROBE918_WIDTH = "1" *) 
   (* C_PROBE919_MU_CNT = "1" *) 
   (* C_PROBE919_WIDTH = "1" *) 
   (* C_PROBE91_MU_CNT = "1" *) 
   (* C_PROBE91_WIDTH = "1" *) 
   (* C_PROBE920_MU_CNT = "1" *) 
   (* C_PROBE920_WIDTH = "1" *) 
   (* C_PROBE921_MU_CNT = "1" *) 
   (* C_PROBE921_WIDTH = "1" *) 
   (* C_PROBE922_MU_CNT = "1" *) 
   (* C_PROBE922_WIDTH = "1" *) 
   (* C_PROBE923_MU_CNT = "1" *) 
   (* C_PROBE923_WIDTH = "1" *) 
   (* C_PROBE924_MU_CNT = "1" *) 
   (* C_PROBE924_WIDTH = "1" *) 
   (* C_PROBE925_MU_CNT = "1" *) 
   (* C_PROBE925_WIDTH = "1" *) 
   (* C_PROBE926_MU_CNT = "1" *) 
   (* C_PROBE926_WIDTH = "1" *) 
   (* C_PROBE927_MU_CNT = "1" *) 
   (* C_PROBE927_WIDTH = "1" *) 
   (* C_PROBE928_MU_CNT = "1" *) 
   (* C_PROBE928_WIDTH = "1" *) 
   (* C_PROBE929_MU_CNT = "1" *) 
   (* C_PROBE929_WIDTH = "1" *) 
   (* C_PROBE92_MU_CNT = "1" *) 
   (* C_PROBE92_WIDTH = "1" *) 
   (* C_PROBE930_MU_CNT = "1" *) 
   (* C_PROBE930_WIDTH = "1" *) 
   (* C_PROBE931_MU_CNT = "1" *) 
   (* C_PROBE931_WIDTH = "1" *) 
   (* C_PROBE932_MU_CNT = "1" *) 
   (* C_PROBE932_WIDTH = "1" *) 
   (* C_PROBE933_MU_CNT = "1" *) 
   (* C_PROBE933_WIDTH = "1" *) 
   (* C_PROBE934_MU_CNT = "1" *) 
   (* C_PROBE934_WIDTH = "1" *) 
   (* C_PROBE935_MU_CNT = "1" *) 
   (* C_PROBE935_WIDTH = "1" *) 
   (* C_PROBE936_MU_CNT = "1" *) 
   (* C_PROBE936_WIDTH = "1" *) 
   (* C_PROBE937_MU_CNT = "1" *) 
   (* C_PROBE937_WIDTH = "1" *) 
   (* C_PROBE938_MU_CNT = "1" *) 
   (* C_PROBE938_WIDTH = "1" *) 
   (* C_PROBE939_MU_CNT = "1" *) 
   (* C_PROBE939_WIDTH = "1" *) 
   (* C_PROBE93_MU_CNT = "1" *) 
   (* C_PROBE93_WIDTH = "1" *) 
   (* C_PROBE940_MU_CNT = "1" *) 
   (* C_PROBE940_WIDTH = "1" *) 
   (* C_PROBE941_MU_CNT = "1" *) 
   (* C_PROBE941_WIDTH = "1" *) 
   (* C_PROBE942_MU_CNT = "1" *) 
   (* C_PROBE942_WIDTH = "1" *) 
   (* C_PROBE943_MU_CNT = "1" *) 
   (* C_PROBE943_WIDTH = "1" *) 
   (* C_PROBE944_MU_CNT = "1" *) 
   (* C_PROBE944_WIDTH = "1" *) 
   (* C_PROBE945_MU_CNT = "1" *) 
   (* C_PROBE945_WIDTH = "1" *) 
   (* C_PROBE946_MU_CNT = "1" *) 
   (* C_PROBE946_WIDTH = "1" *) 
   (* C_PROBE947_MU_CNT = "1" *) 
   (* C_PROBE947_WIDTH = "1" *) 
   (* C_PROBE948_MU_CNT = "1" *) 
   (* C_PROBE948_WIDTH = "1" *) 
   (* C_PROBE949_MU_CNT = "1" *) 
   (* C_PROBE949_WIDTH = "1" *) 
   (* C_PROBE94_MU_CNT = "1" *) 
   (* C_PROBE94_WIDTH = "1" *) 
   (* C_PROBE950_MU_CNT = "1" *) 
   (* C_PROBE950_WIDTH = "1" *) 
   (* C_PROBE951_MU_CNT = "1" *) 
   (* C_PROBE951_WIDTH = "1" *) 
   (* C_PROBE952_MU_CNT = "1" *) 
   (* C_PROBE952_WIDTH = "1" *) 
   (* C_PROBE953_MU_CNT = "1" *) 
   (* C_PROBE953_WIDTH = "1" *) 
   (* C_PROBE954_MU_CNT = "1" *) 
   (* C_PROBE954_WIDTH = "1" *) 
   (* C_PROBE955_MU_CNT = "1" *) 
   (* C_PROBE955_WIDTH = "1" *) 
   (* C_PROBE956_MU_CNT = "1" *) 
   (* C_PROBE956_WIDTH = "1" *) 
   (* C_PROBE957_MU_CNT = "1" *) 
   (* C_PROBE957_WIDTH = "1" *) 
   (* C_PROBE958_MU_CNT = "1" *) 
   (* C_PROBE958_WIDTH = "1" *) 
   (* C_PROBE959_MU_CNT = "1" *) 
   (* C_PROBE959_WIDTH = "1" *) 
   (* C_PROBE95_MU_CNT = "1" *) 
   (* C_PROBE95_WIDTH = "1" *) 
   (* C_PROBE960_MU_CNT = "1" *) 
   (* C_PROBE960_WIDTH = "1" *) 
   (* C_PROBE961_MU_CNT = "1" *) 
   (* C_PROBE961_WIDTH = "1" *) 
   (* C_PROBE962_MU_CNT = "1" *) 
   (* C_PROBE962_WIDTH = "1" *) 
   (* C_PROBE963_MU_CNT = "1" *) 
   (* C_PROBE963_WIDTH = "1" *) 
   (* C_PROBE964_MU_CNT = "1" *) 
   (* C_PROBE964_WIDTH = "1" *) 
   (* C_PROBE965_MU_CNT = "1" *) 
   (* C_PROBE965_WIDTH = "1" *) 
   (* C_PROBE966_MU_CNT = "1" *) 
   (* C_PROBE966_WIDTH = "1" *) 
   (* C_PROBE967_MU_CNT = "1" *) 
   (* C_PROBE967_WIDTH = "1" *) 
   (* C_PROBE968_MU_CNT = "1" *) 
   (* C_PROBE968_WIDTH = "1" *) 
   (* C_PROBE969_MU_CNT = "1" *) 
   (* C_PROBE969_WIDTH = "1" *) 
   (* C_PROBE96_MU_CNT = "1" *) 
   (* C_PROBE96_WIDTH = "1" *) 
   (* C_PROBE970_MU_CNT = "1" *) 
   (* C_PROBE970_WIDTH = "1" *) 
   (* C_PROBE971_MU_CNT = "1" *) 
   (* C_PROBE971_WIDTH = "1" *) 
   (* C_PROBE972_MU_CNT = "1" *) 
   (* C_PROBE972_WIDTH = "1" *) 
   (* C_PROBE973_MU_CNT = "1" *) 
   (* C_PROBE973_WIDTH = "1" *) 
   (* C_PROBE974_MU_CNT = "1" *) 
   (* C_PROBE974_WIDTH = "1" *) 
   (* C_PROBE975_MU_CNT = "1" *) 
   (* C_PROBE975_WIDTH = "1" *) 
   (* C_PROBE976_MU_CNT = "1" *) 
   (* C_PROBE976_WIDTH = "1" *) 
   (* C_PROBE977_MU_CNT = "1" *) 
   (* C_PROBE977_WIDTH = "1" *) 
   (* C_PROBE978_MU_CNT = "1" *) 
   (* C_PROBE978_WIDTH = "1" *) 
   (* C_PROBE979_MU_CNT = "1" *) 
   (* C_PROBE979_WIDTH = "1" *) 
   (* C_PROBE97_MU_CNT = "1" *) 
   (* C_PROBE97_WIDTH = "1" *) 
   (* C_PROBE980_MU_CNT = "1" *) 
   (* C_PROBE980_WIDTH = "1" *) 
   (* C_PROBE981_MU_CNT = "1" *) 
   (* C_PROBE981_WIDTH = "1" *) 
   (* C_PROBE982_MU_CNT = "1" *) 
   (* C_PROBE982_WIDTH = "1" *) 
   (* C_PROBE983_MU_CNT = "1" *) 
   (* C_PROBE983_WIDTH = "1" *) 
   (* C_PROBE984_MU_CNT = "1" *) 
   (* C_PROBE984_WIDTH = "1" *) 
   (* C_PROBE985_MU_CNT = "1" *) 
   (* C_PROBE985_WIDTH = "1" *) 
   (* C_PROBE986_MU_CNT = "1" *) 
   (* C_PROBE986_WIDTH = "1" *) 
   (* C_PROBE987_MU_CNT = "1" *) 
   (* C_PROBE987_WIDTH = "1" *) 
   (* C_PROBE988_MU_CNT = "1" *) 
   (* C_PROBE988_WIDTH = "1" *) 
   (* C_PROBE989_MU_CNT = "1" *) 
   (* C_PROBE989_WIDTH = "1" *) 
   (* C_PROBE98_MU_CNT = "1" *) 
   (* C_PROBE98_WIDTH = "1" *) 
   (* C_PROBE990_MU_CNT = "1" *) 
   (* C_PROBE990_WIDTH = "1" *) 
   (* C_PROBE991_MU_CNT = "1" *) 
   (* C_PROBE991_WIDTH = "1" *) 
   (* C_PROBE992_MU_CNT = "1" *) 
   (* C_PROBE992_WIDTH = "1" *) 
   (* C_PROBE993_MU_CNT = "1" *) 
   (* C_PROBE993_WIDTH = "1" *) 
   (* C_PROBE994_MU_CNT = "1" *) 
   (* C_PROBE994_WIDTH = "1" *) 
   (* C_PROBE995_MU_CNT = "1" *) 
   (* C_PROBE995_WIDTH = "1" *) 
   (* C_PROBE996_MU_CNT = "1" *) 
   (* C_PROBE996_WIDTH = "1" *) 
   (* C_PROBE997_MU_CNT = "1" *) 
   (* C_PROBE997_WIDTH = "1" *) 
   (* C_PROBE998_MU_CNT = "1" *) 
   (* C_PROBE998_WIDTH = "1" *) 
   (* C_PROBE999_MU_CNT = "1" *) 
   (* C_PROBE999_WIDTH = "1" *) 
   (* C_PROBE99_MU_CNT = "1" *) 
   (* C_PROBE99_WIDTH = "1" *) 
   (* C_PROBE9_MU_CNT = "1" *) 
   (* C_PROBE9_WIDTH = "32" *) 
   (* C_RAM_STYLE = "SUBCORE" *) 
   (* C_SLOT_0_AXI_PROTOCOL = "AXI4" *) 
   (* C_TC_TYPE = "0" *) 
   (* C_TRIGIN_EN = "0" *) 
   (* C_TRIGOUT_EN = "0" *) 
   (* C_USE_TEST_REG = "1" *) 
   (* C_XDEVICEFAMILY = "artix7" *) 
   (* C_XLNX_HW_PROBE_INFO = "NUM_OF_PROBES=13,DATA_DEPTH=1024,PROBE0_WIDTH=32,PROBE0_MU_CNT=1,PROBE1_WIDTH=1,PROBE1_MU_CNT=1,PROBE2_WIDTH=1,PROBE2_MU_CNT=1,PROBE3_WIDTH=32,PROBE3_MU_CNT=1,PROBE4_WIDTH=1,PROBE4_MU_CNT=1,PROBE5_WIDTH=1,PROBE5_MU_CNT=1,PROBE6_WIDTH=32,PROBE6_MU_CNT=1,PROBE7_WIDTH=1,PROBE7_MU_CNT=1,PROBE8_WIDTH=1,PROBE8_MU_CNT=1,PROBE9_WIDTH=32,PROBE9_MU_CNT=1,PROBE10_WIDTH=1,PROBE10_MU_CNT=1,PROBE11_WIDTH=1,PROBE11_MU_CNT=1,PROBE12_WIDTH=4,PROBE12_MU_CNT=1,PROBE13_WIDTH=1,PROBE13_MU_CNT=1,PROBE14_WIDTH=1,PROBE14_MU_CNT=1,PROBE15_WIDTH=1,PROBE15_MU_CNT=1,PROBE16_WIDTH=1,PROBE16_MU_CNT=1,PROBE17_WIDTH=1,PROBE17_MU_CNT=1,PROBE18_WIDTH=1,PROBE18_MU_CNT=1,PROBE19_WIDTH=1,PROBE19_MU_CNT=1,PROBE20_WIDTH=1,PROBE20_MU_CNT=1,PROBE21_WIDTH=1,PROBE21_MU_CNT=1,PROBE22_WIDTH=1,PROBE22_MU_CNT=1,PROBE23_WIDTH=1,PROBE23_MU_CNT=1,PROBE24_WIDTH=1,PROBE24_MU_CNT=1,PROBE25_WIDTH=1,PROBE25_MU_CNT=1,PROBE26_WIDTH=1,PROBE26_MU_CNT=1,PROBE27_WIDTH=1,PROBE27_MU_CNT=1,PROBE28_WIDTH=1,PROBE28_MU_CNT=1,PROBE29_WIDTH=1,PROBE29_MU_CNT=1,PROBE30_WIDTH=1,PROBE30_MU_CNT=1,PROBE31_WIDTH=1,PROBE31_MU_CNT=1,PROBE32_WIDTH=1,PROBE32_MU_CNT=1,PROBE33_WIDTH=1,PROBE33_MU_CNT=1,PROBE34_WIDTH=1,PROBE34_MU_CNT=1,PROBE35_WIDTH=1,PROBE35_MU_CNT=1,PROBE36_WIDTH=1,PROBE36_MU_CNT=1,PROBE37_WIDTH=1,PROBE37_MU_CNT=1,PROBE38_WIDTH=1,PROBE38_MU_CNT=1,PROBE39_WIDTH=1,PROBE39_MU_CNT=1,PROBE40_WIDTH=1,PROBE40_MU_CNT=1,PROBE41_WIDTH=1,PROBE41_MU_CNT=1,PROBE42_WIDTH=1,PROBE42_MU_CNT=1,PROBE43_WIDTH=1,PROBE43_MU_CNT=1,PROBE44_WIDTH=1,PROBE44_MU_CNT=1,PROBE45_WIDTH=1,PROBE45_MU_CNT=1,PROBE46_WIDTH=1,PROBE46_MU_CNT=1,PROBE47_WIDTH=1,PROBE47_MU_CNT=1,PROBE48_WIDTH=1,PROBE48_MU_CNT=1,PROBE49_WIDTH=1,PROBE49_MU_CNT=1,PROBE50_WIDTH=1,PROBE50_MU_CNT=1,PROBE51_WIDTH=1,PROBE51_MU_CNT=1,PROBE52_WIDTH=1,PROBE52_MU_CNT=1,PROBE53_WIDTH=1,PROBE53_MU_CNT=1,PROBE54_WIDTH=1,PROBE54_MU_CNT=1,PROBE55_WIDTH=1,PROBE55_MU_CNT=1,PROBE56_WIDTH=1,PROBE56_MU_CNT=1,PROBE57_WIDTH=1,PROBE57_MU_CNT=1,PROBE58_WIDTH=1,PROBE58_MU_CNT=1,PROBE59_WIDTH=1,PROBE59_MU_CNT=1,PROBE60_WIDTH=1,PROBE60_MU_CNT=1,PROBE61_WIDTH=1,PROBE61_MU_CNT=1,PROBE62_WIDTH=1,PROBE62_MU_CNT=1,PROBE63_WIDTH=1,PROBE63_MU_CNT=1,PROBE64_WIDTH=1,PROBE64_MU_CNT=1,PROBE65_WIDTH=1,PROBE65_MU_CNT=1,PROBE66_WIDTH=1,PROBE66_MU_CNT=1,PROBE67_WIDTH=1,PROBE67_MU_CNT=1,PROBE68_WIDTH=1,PROBE68_MU_CNT=1,PROBE69_WIDTH=1,PROBE69_MU_CNT=1,PROBE70_WIDTH=1,PROBE70_MU_CNT=1,PROBE71_WIDTH=1,PROBE71_MU_CNT=1,PROBE72_WIDTH=1,PROBE72_MU_CNT=1,PROBE73_WIDTH=1,PROBE73_MU_CNT=1,PROBE74_WIDTH=1,PROBE74_MU_CNT=1,PROBE75_WIDTH=1,PROBE75_MU_CNT=1,PROBE76_WIDTH=1,PROBE76_MU_CNT=1,PROBE77_WIDTH=1,PROBE77_MU_CNT=1,PROBE78_WIDTH=1,PROBE78_MU_CNT=1,PROBE79_WIDTH=1,PROBE79_MU_CNT=1,PROBE80_WIDTH=1,PROBE80_MU_CNT=1,PROBE81_WIDTH=1,PROBE81_MU_CNT=1,PROBE82_WIDTH=1,PROBE82_MU_CNT=1,PROBE83_WIDTH=1,PROBE83_MU_CNT=1,PROBE84_WIDTH=1,PROBE84_MU_CNT=1,PROBE85_WIDTH=1,PROBE85_MU_CNT=1,PROBE86_WIDTH=1,PROBE86_MU_CNT=1,PROBE87_WIDTH=1,PROBE87_MU_CNT=1,PROBE88_WIDTH=1,PROBE88_MU_CNT=1,PROBE89_WIDTH=1,PROBE89_MU_CNT=1,PROBE90_WIDTH=1,PROBE90_MU_CNT=1,PROBE91_WIDTH=1,PROBE91_MU_CNT=1,PROBE92_WIDTH=1,PROBE92_MU_CNT=1,PROBE93_WIDTH=1,PROBE93_MU_CNT=1,PROBE94_WIDTH=1,PROBE94_MU_CNT=1,PROBE95_WIDTH=1,PROBE95_MU_CNT=1,PROBE96_WIDTH=1,PROBE96_MU_CNT=1,PROBE97_WIDTH=1,PROBE97_MU_CNT=1,PROBE98_WIDTH=1,PROBE98_MU_CNT=1,PROBE99_WIDTH=1,PROBE99_MU_CNT=1,PROBE100_WIDTH=1,PROBE100_MU_CNT=1,PROBE101_WIDTH=1,PROBE101_MU_CNT=1,PROBE102_WIDTH=1,PROBE102_MU_CNT=1,PROBE103_WIDTH=1,PROBE103_MU_CNT=1,PROBE104_WIDTH=1,PROBE104_MU_CNT=1,PROBE105_WIDTH=1,PROBE105_MU_CNT=1,PROBE106_WIDTH=1,PROBE106_MU_CNT=1,PROBE107_WIDTH=1,PROBE107_MU_CNT=1,PROBE108_WIDTH=1,PROBE108_MU_CNT=1,PROBE109_WIDTH=1,PROBE109_MU_CNT=1,PROBE110_WIDTH=1,PROBE110_MU_CNT=1,PROBE111_WIDTH=1,PROBE111_MU_CNT=1,PROBE112_WIDTH=1,PROBE112_MU_CNT=1,PROBE113_WIDTH=1,PROBE113_MU_CNT=1,PROBE114_WIDTH=1,PROBE114_MU_CNT=1,PROBE115_WIDTH=1,PROBE115_MU_CNT=1,PROBE116_WIDTH=1,PROBE116_MU_CNT=1,PROBE117_WIDTH=1,PROBE117_MU_CNT=1,PROBE118_WIDTH=1,PROBE118_MU_CNT=1,PROBE119_WIDTH=1,PROBE119_MU_CNT=1,PROBE120_WIDTH=1,PROBE120_MU_CNT=1,PROBE121_WIDTH=1,PROBE121_MU_CNT=1,PROBE122_WIDTH=1,PROBE122_MU_CNT=1,PROBE123_WIDTH=1,PROBE123_MU_CNT=1,PROBE124_WIDTH=1,PROBE124_MU_CNT=1,PROBE125_WIDTH=1,PROBE125_MU_CNT=1,PROBE126_WIDTH=1,PROBE126_MU_CNT=1,PROBE127_WIDTH=1,PROBE127_MU_CNT=1,PROBE128_WIDTH=1,PROBE128_MU_CNT=1,PROBE129_WIDTH=1,PROBE129_MU_CNT=1,PROBE130_WIDTH=1,PROBE130_MU_CNT=1,PROBE131_WIDTH=1,PROBE131_MU_CNT=1,PROBE132_WIDTH=1,PROBE132_MU_CNT=1,PROBE133_WIDTH=1,PROBE133_MU_CNT=1,PROBE134_WIDTH=1,PROBE134_MU_CNT=1,PROBE135_WIDTH=1,PROBE135_MU_CNT=1,PROBE136_WIDTH=1,PROBE136_MU_CNT=1,PROBE137_WIDTH=1,PROBE137_MU_CNT=1,PROBE138_WIDTH=1,PROBE138_MU_CNT=1,PROBE139_WIDTH=1,PROBE139_MU_CNT=1,PROBE140_WIDTH=1,PROBE140_MU_CNT=1,PROBE141_WIDTH=1,PROBE141_MU_CNT=1,PROBE142_WIDTH=1,PROBE142_MU_CNT=1,PROBE143_WIDTH=1,PROBE143_MU_CNT=1,PROBE144_WIDTH=1,PROBE144_MU_CNT=1,PROBE145_WIDTH=1,PROBE145_MU_CNT=1,PROBE146_WIDTH=1,PROBE146_MU_CNT=1,PROBE147_WIDTH=1,PROBE147_MU_CNT=1,PROBE148_WIDTH=1,PROBE148_MU_CNT=1,PROBE149_WIDTH=1,PROBE149_MU_CNT=1,PROBE150_WIDTH=1,PROBE150_MU_CNT=1,PROBE151_WIDTH=1,PROBE151_MU_CNT=1,PROBE152_WIDTH=1,PROBE152_MU_CNT=1,PROBE153_WIDTH=1,PROBE153_MU_CNT=1,PROBE154_WIDTH=1,PROBE154_MU_CNT=1,PROBE155_WIDTH=1,PROBE155_MU_CNT=1,PROBE156_WIDTH=1,PROBE156_MU_CNT=1,PROBE157_WIDTH=1,PROBE157_MU_CNT=1,PROBE158_WIDTH=1,PROBE158_MU_CNT=1,PROBE159_WIDTH=1,PROBE159_MU_CNT=1,PROBE160_WIDTH=1,PROBE160_MU_CNT=1,PROBE161_WIDTH=1,PROBE161_MU_CNT=1,PROBE162_WIDTH=1,PROBE162_MU_CNT=1,PROBE163_WIDTH=1,PROBE163_MU_CNT=1,PROBE164_WIDTH=1,PROBE164_MU_CNT=1,PROBE165_WIDTH=1,PROBE165_MU_CNT=1,PROBE166_WIDTH=1,PROBE166_MU_CNT=1,PROBE167_WIDTH=1,PROBE167_MU_CNT=1,PROBE168_WIDTH=1,PROBE168_MU_CNT=1,PROBE169_WIDTH=1,PROBE169_MU_CNT=1,PROBE170_WIDTH=1,PROBE170_MU_CNT=1,PROBE171_WIDTH=1,PROBE171_MU_CNT=1,PROBE172_WIDTH=1,PROBE172_MU_CNT=1,PROBE173_WIDTH=1,PROBE173_MU_CNT=1,PROBE174_WIDTH=1,PROBE174_MU_CNT=1,PROBE175_WIDTH=1,PROBE175_MU_CNT=1,PROBE176_WIDTH=1,PROBE176_MU_CNT=1,PROBE177_WIDTH=1,PROBE177_MU_CNT=1,PROBE178_WIDTH=1,PROBE178_MU_CNT=1,PROBE179_WIDTH=1,PROBE179_MU_CNT=1,PROBE180_WIDTH=1,PROBE180_MU_CNT=1,PROBE181_WIDTH=1,PROBE181_MU_CNT=1,PROBE182_WIDTH=1,PROBE182_MU_CNT=1,PROBE183_WIDTH=1,PROBE183_MU_CNT=1,PROBE184_WIDTH=1,PROBE184_MU_CNT=1,PROBE185_WIDTH=1,PROBE185_MU_CNT=1,PROBE186_WIDTH=1,PROBE186_MU_CNT=1,PROBE187_WIDTH=1,PROBE187_MU_CNT=1,PROBE188_WIDTH=1,PROBE188_MU_CNT=1,PROBE189_WIDTH=1,PROBE189_MU_CNT=1,PROBE190_WIDTH=1,PROBE190_MU_CNT=1,PROBE191_WIDTH=1,PROBE191_MU_CNT=1,PROBE192_WIDTH=1,PROBE192_MU_CNT=1,PROBE193_WIDTH=1,PROBE193_MU_CNT=1,PROBE194_WIDTH=1,PROBE194_MU_CNT=1,PROBE195_WIDTH=1,PROBE195_MU_CNT=1,PROBE196_WIDTH=1,PROBE196_MU_CNT=1,PROBE197_WIDTH=1,PROBE197_MU_CNT=1,PROBE198_WIDTH=1,PROBE198_MU_CNT=1,PROBE199_WIDTH=1,PROBE199_MU_CNT=1,PROBE200_WIDTH=1,PROBE200_MU_CNT=1,PROBE201_WIDTH=1,PROBE201_MU_CNT=1,PROBE202_WIDTH=1,PROBE202_MU_CNT=1,PROBE203_WIDTH=1,PROBE203_MU_CNT=1,PROBE204_WIDTH=1,PROBE204_MU_CNT=1,PROBE205_WIDTH=1,PROBE205_MU_CNT=1,PROBE206_WIDTH=1,PROBE206_MU_CNT=1,PROBE207_WIDTH=1,PROBE207_MU_CNT=1,PROBE208_WIDTH=1,PROBE208_MU_CNT=1,PROBE209_WIDTH=1,PROBE209_MU_CNT=1,PROBE210_WIDTH=1,PROBE210_MU_CNT=1,PROBE211_WIDTH=1,PROBE211_MU_CNT=1,PROBE212_WIDTH=1,PROBE212_MU_CNT=1,PROBE213_WIDTH=1,PROBE213_MU_CNT=1,PROBE214_WIDTH=1,PROBE214_MU_CNT=1,PROBE215_WIDTH=1,PROBE215_MU_CNT=1,PROBE216_WIDTH=1,PROBE216_MU_CNT=1,PROBE217_WIDTH=1,PROBE217_MU_CNT=1,PROBE218_WIDTH=1,PROBE218_MU_CNT=1,PROBE219_WIDTH=1,PROBE219_MU_CNT=1,PROBE220_WIDTH=1,PROBE220_MU_CNT=1,PROBE221_WIDTH=1,PROBE221_MU_CNT=1,PROBE222_WIDTH=1,PROBE222_MU_CNT=1,PROBE223_WIDTH=1,PROBE223_MU_CNT=1,PROBE224_WIDTH=1,PROBE224_MU_CNT=1,PROBE225_WIDTH=1,PROBE225_MU_CNT=1,PROBE226_WIDTH=1,PROBE226_MU_CNT=1,PROBE227_WIDTH=1,PROBE227_MU_CNT=1,PROBE228_WIDTH=1,PROBE228_MU_CNT=1,PROBE229_WIDTH=1,PROBE229_MU_CNT=1,PROBE230_WIDTH=1,PROBE230_MU_CNT=1,PROBE231_WIDTH=1,PROBE231_MU_CNT=1,PROBE232_WIDTH=1,PROBE232_MU_CNT=1,PROBE233_WIDTH=1,PROBE233_MU_CNT=1,PROBE234_WIDTH=1,PROBE234_MU_CNT=1,PROBE235_WIDTH=1,PROBE235_MU_CNT=1,PROBE236_WIDTH=1,PROBE236_MU_CNT=1,PROBE237_WIDTH=1,PROBE237_MU_CNT=1,PROBE238_WIDTH=1,PROBE238_MU_CNT=1,PROBE239_WIDTH=1,PROBE239_MU_CNT=1,PROBE240_WIDTH=1,PROBE240_MU_CNT=1,PROBE241_WIDTH=1,PROBE241_MU_CNT=1,PROBE242_WIDTH=1,PROBE242_MU_CNT=1,PROBE243_WIDTH=1,PROBE243_MU_CNT=1,PROBE244_WIDTH=1,PROBE244_MU_CNT=1,PROBE245_WIDTH=1,PROBE245_MU_CNT=1,PROBE246_WIDTH=1,PROBE246_MU_CNT=1,PROBE247_WIDTH=1,PROBE247_MU_CNT=1,PROBE248_WIDTH=1,PROBE248_MU_CNT=1,PROBE249_WIDTH=1,PROBE249_MU_CNT=1,PROBE250_WIDTH=1,PROBE250_MU_CNT=1,PROBE251_WIDTH=1,PROBE251_MU_CNT=1,PROBE252_WIDTH=1,PROBE252_MU_CNT=1,PROBE253_WIDTH=1,PROBE253_MU_CNT=1,PROBE254_WIDTH=1,PROBE254_MU_CNT=1,PROBE255_WIDTH=1,PROBE255_MU_CNT=1,PROBE256_WIDTH=1,PROBE256_MU_CNT=1,PROBE257_WIDTH=1,PROBE257_MU_CNT=1,PROBE258_WIDTH=1,PROBE258_MU_CNT=1,PROBE259_WIDTH=1,PROBE259_MU_CNT=1,PROBE260_WIDTH=1,PROBE260_MU_CNT=1,PROBE261_WIDTH=1,PROBE261_MU_CNT=1,PROBE262_WIDTH=1,PROBE262_MU_CNT=1,PROBE263_WIDTH=1,PROBE263_MU_CNT=1,PROBE264_WIDTH=1,PROBE264_MU_CNT=1,PROBE265_WIDTH=1,PROBE265_MU_CNT=1,PROBE266_WIDTH=1,PROBE266_MU_CNT=1,PROBE267_WIDTH=1,PROBE267_MU_CNT=1,PROBE268_WIDTH=1,PROBE268_MU_CNT=1,PROBE269_WIDTH=1,PROBE269_MU_CNT=1,PROBE270_WIDTH=1,PROBE270_MU_CNT=1,PROBE271_WIDTH=1,PROBE271_MU_CNT=1,PROBE272_WIDTH=1,PROBE272_MU_CNT=1,PROBE273_WIDTH=1,PROBE273_MU_CNT=1,PROBE274_WIDTH=1,PROBE274_MU_CNT=1,PROBE275_WIDTH=1,PROBE275_MU_CNT=1,PROBE276_WIDTH=1,PROBE276_MU_CNT=1,PROBE277_WIDTH=1,PROBE277_MU_CNT=1,PROBE278_WIDTH=1,PROBE278_MU_CNT=1,PROBE279_WIDTH=1,PROBE279_MU_CNT=1,PROBE280_WIDTH=1,PROBE280_MU_CNT=1,PROBE281_WIDTH=1,PROBE281_MU_CNT=1,PROBE282_WIDTH=1,PROBE282_MU_CNT=1,PROBE283_WIDTH=1,PROBE283_MU_CNT=1,PROBE284_WIDTH=1,PROBE284_MU_CNT=1,PROBE285_WIDTH=1,PROBE285_MU_CNT=1,PROBE286_WIDTH=1,PROBE286_MU_CNT=1,PROBE287_WIDTH=1,PROBE287_MU_CNT=1,PROBE288_WIDTH=1,PROBE288_MU_CNT=1,PROBE289_WIDTH=1,PROBE289_MU_CNT=1,PROBE290_WIDTH=1,PROBE290_MU_CNT=1,PROBE291_WIDTH=1,PROBE291_MU_CNT=1,PROBE292_WIDTH=1,PROBE292_MU_CNT=1,PROBE293_WIDTH=1,PROBE293_MU_CNT=1,PROBE294_WIDTH=1,PROBE294_MU_CNT=1,PROBE295_WIDTH=1,PROBE295_MU_CNT=1,PROBE296_WIDTH=1,PROBE296_MU_CNT=1,PROBE297_WIDTH=1,PROBE297_MU_CNT=1,PROBE298_WIDTH=1,PROBE298_MU_CNT=1,PROBE299_WIDTH=1,PROBE299_MU_CNT=1,PROBE300_WIDTH=1,PROBE300_MU_CNT=1,PROBE301_WIDTH=1,PROBE301_MU_CNT=1,PROBE302_WIDTH=1,PROBE302_MU_CNT=1,PROBE303_WIDTH=1,PROBE303_MU_CNT=1,PROBE304_WIDTH=1,PROBE304_MU_CNT=1,PROBE305_WIDTH=1,PROBE305_MU_CNT=1,PROBE306_WIDTH=1,PROBE306_MU_CNT=1,PROBE307_WIDTH=1,PROBE307_MU_CNT=1,PROBE308_WIDTH=1,PROBE308_MU_CNT=1,PROBE309_WIDTH=1,PROBE309_MU_CNT=1,PROBE310_WIDTH=1,PROBE310_MU_CNT=1,PROBE311_WIDTH=1,PROBE311_MU_CNT=1,PROBE312_WIDTH=1,PROBE312_MU_CNT=1,PROBE313_WIDTH=1,PROBE313_MU_CNT=1,PROBE314_WIDTH=1,PROBE314_MU_CNT=1,PROBE315_WIDTH=1,PROBE315_MU_CNT=1,PROBE316_WIDTH=1,PROBE316_MU_CNT=1,PROBE317_WIDTH=1,PROBE317_MU_CNT=1,PROBE318_WIDTH=1,PROBE318_MU_CNT=1,PROBE319_WIDTH=1,PROBE319_MU_CNT=1,PROBE320_WIDTH=1,PROBE320_MU_CNT=1,PROBE321_WIDTH=1,PROBE321_MU_CNT=1,PROBE322_WIDTH=1,PROBE322_MU_CNT=1,PROBE323_WIDTH=1,PROBE323_MU_CNT=1,PROBE324_WIDTH=1,PROBE324_MU_CNT=1,PROBE325_WIDTH=1,PROBE325_MU_CNT=1,PROBE326_WIDTH=1,PROBE326_MU_CNT=1,PROBE327_WIDTH=1,PROBE327_MU_CNT=1,PROBE328_WIDTH=1,PROBE328_MU_CNT=1,PROBE329_WIDTH=1,PROBE329_MU_CNT=1,PROBE330_WIDTH=1,PROBE330_MU_CNT=1,PROBE331_WIDTH=1,PROBE331_MU_CNT=1,PROBE332_WIDTH=1,PROBE332_MU_CNT=1,PROBE333_WIDTH=1,PROBE333_MU_CNT=1,PROBE334_WIDTH=1,PROBE334_MU_CNT=1,PROBE335_WIDTH=1,PROBE335_MU_CNT=1,PROBE336_WIDTH=1,PROBE336_MU_CNT=1,PROBE337_WIDTH=1,PROBE337_MU_CNT=1,PROBE338_WIDTH=1,PROBE338_MU_CNT=1,PROBE339_WIDTH=1,PROBE339_MU_CNT=1,PROBE340_WIDTH=1,PROBE340_MU_CNT=1,PROBE341_WIDTH=1,PROBE341_MU_CNT=1,PROBE342_WIDTH=1,PROBE342_MU_CNT=1,PROBE343_WIDTH=1,PROBE343_MU_CNT=1,PROBE344_WIDTH=1,PROBE344_MU_CNT=1,PROBE345_WIDTH=1,PROBE345_MU_CNT=1,PROBE346_WIDTH=1,PROBE346_MU_CNT=1,PROBE347_WIDTH=1,PROBE347_MU_CNT=1,PROBE348_WIDTH=1,PROBE348_MU_CNT=1,PROBE349_WIDTH=1,PROBE349_MU_CNT=1,PROBE350_WIDTH=1,PROBE350_MU_CNT=1,PROBE351_WIDTH=1,PROBE351_MU_CNT=1,PROBE352_WIDTH=1,PROBE352_MU_CNT=1,PROBE353_WIDTH=1,PROBE353_MU_CNT=1,PROBE354_WIDTH=1,PROBE354_MU_CNT=1,PROBE355_WIDTH=1,PROBE355_MU_CNT=1,PROBE356_WIDTH=1,PROBE356_MU_CNT=1,PROBE357_WIDTH=1,PROBE357_MU_CNT=1,PROBE358_WIDTH=1,PROBE358_MU_CNT=1,PROBE359_WIDTH=1,PROBE359_MU_CNT=1,PROBE360_WIDTH=1,PROBE360_MU_CNT=1,PROBE361_WIDTH=1,PROBE361_MU_CNT=1,PROBE362_WIDTH=1,PROBE362_MU_CNT=1,PROBE363_WIDTH=1,PROBE363_MU_CNT=1,PROBE364_WIDTH=1,PROBE364_MU_CNT=1,PROBE365_WIDTH=1,PROBE365_MU_CNT=1,PROBE366_WIDTH=1,PROBE366_MU_CNT=1,PROBE367_WIDTH=1,PROBE367_MU_CNT=1,PROBE368_WIDTH=1,PROBE368_MU_CNT=1,PROBE369_WIDTH=1,PROBE369_MU_CNT=1,PROBE370_WIDTH=1,PROBE370_MU_CNT=1,PROBE371_WIDTH=1,PROBE371_MU_CNT=1,PROBE372_WIDTH=1,PROBE372_MU_CNT=1,PROBE373_WIDTH=1,PROBE373_MU_CNT=1,PROBE374_WIDTH=1,PROBE374_MU_CNT=1,PROBE375_WIDTH=1,PROBE375_MU_CNT=1,PROBE376_WIDTH=1,PROBE376_MU_CNT=1,PROBE377_WIDTH=1,PROBE377_MU_CNT=1,PROBE378_WIDTH=1,PROBE378_MU_CNT=1,PROBE379_WIDTH=1,PROBE379_MU_CNT=1,PROBE380_WIDTH=1,PROBE380_MU_CNT=1,PROBE381_WIDTH=1,PROBE381_MU_CNT=1,PROBE382_WIDTH=1,PROBE382_MU_CNT=1,PROBE383_WIDTH=1,PROBE383_MU_CNT=1,PROBE384_WIDTH=1,PROBE384_MU_CNT=1,PROBE385_WIDTH=1,PROBE385_MU_CNT=1,PROBE386_WIDTH=1,PROBE386_MU_CNT=1,PROBE387_WIDTH=1,PROBE387_MU_CNT=1,PROBE388_WIDTH=1,PROBE388_MU_CNT=1,PROBE389_WIDTH=1,PROBE389_MU_CNT=1,PROBE390_WIDTH=1,PROBE390_MU_CNT=1,PROBE391_WIDTH=1,PROBE391_MU_CNT=1,PROBE392_WIDTH=1,PROBE392_MU_CNT=1,PROBE393_WIDTH=1,PROBE393_MU_CNT=1,PROBE394_WIDTH=1,PROBE394_MU_CNT=1,PROBE395_WIDTH=1,PROBE395_MU_CNT=1,PROBE396_WIDTH=1,PROBE396_MU_CNT=1,PROBE397_WIDTH=1,PROBE397_MU_CNT=1,PROBE398_WIDTH=1,PROBE398_MU_CNT=1,PROBE399_WIDTH=1,PROBE399_MU_CNT=1,PROBE400_WIDTH=1,PROBE400_MU_CNT=1,PROBE401_WIDTH=1,PROBE401_MU_CNT=1,PROBE402_WIDTH=1,PROBE402_MU_CNT=1,PROBE403_WIDTH=1,PROBE403_MU_CNT=1,PROBE404_WIDTH=1,PROBE404_MU_CNT=1,PROBE405_WIDTH=1,PROBE405_MU_CNT=1,PROBE406_WIDTH=1,PROBE406_MU_CNT=1,PROBE407_WIDTH=1,PROBE407_MU_CNT=1,PROBE408_WIDTH=1,PROBE408_MU_CNT=1,PROBE409_WIDTH=1,PROBE409_MU_CNT=1,PROBE410_WIDTH=1,PROBE410_MU_CNT=1,PROBE411_WIDTH=1,PROBE411_MU_CNT=1,PROBE412_WIDTH=1,PROBE412_MU_CNT=1,PROBE413_WIDTH=1,PROBE413_MU_CNT=1,PROBE414_WIDTH=1,PROBE414_MU_CNT=1,PROBE415_WIDTH=1,PROBE415_MU_CNT=1,PROBE416_WIDTH=1,PROBE416_MU_CNT=1,PROBE417_WIDTH=1,PROBE417_MU_CNT=1,PROBE418_WIDTH=1,PROBE418_MU_CNT=1,PROBE419_WIDTH=1,PROBE419_MU_CNT=1,PROBE420_WIDTH=1,PROBE420_MU_CNT=1,PROBE421_WIDTH=1,PROBE421_MU_CNT=1,PROBE422_WIDTH=1,PROBE422_MU_CNT=1,PROBE423_WIDTH=1,PROBE423_MU_CNT=1,PROBE424_WIDTH=1,PROBE424_MU_CNT=1,PROBE425_WIDTH=1,PROBE425_MU_CNT=1,PROBE426_WIDTH=1,PROBE426_MU_CNT=1,PROBE427_WIDTH=1,PROBE427_MU_CNT=1,PROBE428_WIDTH=1,PROBE428_MU_CNT=1,PROBE429_WIDTH=1,PROBE429_MU_CNT=1,PROBE430_WIDTH=1,PROBE430_MU_CNT=1,PROBE431_WIDTH=1,PROBE431_MU_CNT=1,PROBE432_WIDTH=1,PROBE432_MU_CNT=1,PROBE433_WIDTH=1,PROBE433_MU_CNT=1,PROBE434_WIDTH=1,PROBE434_MU_CNT=1,PROBE435_WIDTH=1,PROBE435_MU_CNT=1,PROBE436_WIDTH=1,PROBE436_MU_CNT=1,PROBE437_WIDTH=1,PROBE437_MU_CNT=1,PROBE438_WIDTH=1,PROBE438_MU_CNT=1,PROBE439_WIDTH=1,PROBE439_MU_CNT=1,PROBE440_WIDTH=1,PROBE440_MU_CNT=1,PROBE441_WIDTH=1,PROBE441_MU_CNT=1,PROBE442_WIDTH=1,PROBE442_MU_CNT=1,PROBE443_WIDTH=1,PROBE443_MU_CNT=1,PROBE444_WIDTH=1,PROBE444_MU_CNT=1,PROBE445_WIDTH=1,PROBE445_MU_CNT=1,PROBE446_WIDTH=1,PROBE446_MU_CNT=1,PROBE447_WIDTH=1,PROBE447_MU_CNT=1,PROBE448_WIDTH=1,PROBE448_MU_CNT=1,PROBE449_WIDTH=1,PROBE449_MU_CNT=1,PROBE450_WIDTH=1,PROBE450_MU_CNT=1,PROBE451_WIDTH=1,PROBE451_MU_CNT=1,PROBE452_WIDTH=1,PROBE452_MU_CNT=1,PROBE453_WIDTH=1,PROBE453_MU_CNT=1,PROBE454_WIDTH=1,PROBE454_MU_CNT=1,PROBE455_WIDTH=1,PROBE455_MU_CNT=1,PROBE456_WIDTH=1,PROBE456_MU_CNT=1,PROBE457_WIDTH=1,PROBE457_MU_CNT=1,PROBE458_WIDTH=1,PROBE458_MU_CNT=1,PROBE459_WIDTH=1,PROBE459_MU_CNT=1,PROBE460_WIDTH=1,PROBE460_MU_CNT=1,PROBE461_WIDTH=1,PROBE461_MU_CNT=1,PROBE462_WIDTH=1,PROBE462_MU_CNT=1,PROBE463_WIDTH=1,PROBE463_MU_CNT=1,PROBE464_WIDTH=1,PROBE464_MU_CNT=1,PROBE465_WIDTH=1,PROBE465_MU_CNT=1,PROBE466_WIDTH=1,PROBE466_MU_CNT=1,PROBE467_WIDTH=1,PROBE467_MU_CNT=1,PROBE468_WIDTH=1,PROBE468_MU_CNT=1,PROBE469_WIDTH=1,PROBE469_MU_CNT=1,PROBE470_WIDTH=1,PROBE470_MU_CNT=1,PROBE471_WIDTH=1,PROBE471_MU_CNT=1,PROBE472_WIDTH=1,PROBE472_MU_CNT=1,PROBE473_WIDTH=1,PROBE473_MU_CNT=1,PROBE474_WIDTH=1,PROBE474_MU_CNT=1,PROBE475_WIDTH=1,PROBE475_MU_CNT=1,PROBE476_WIDTH=1,PROBE476_MU_CNT=1,PROBE477_WIDTH=1,PROBE477_MU_CNT=1,PROBE478_WIDTH=1,PROBE478_MU_CNT=1,PROBE479_WIDTH=1,PROBE479_MU_CNT=1,PROBE480_WIDTH=1,PROBE480_MU_CNT=1,PROBE481_WIDTH=1,PROBE481_MU_CNT=1,PROBE482_WIDTH=1,PROBE482_MU_CNT=1,PROBE483_WIDTH=1,PROBE483_MU_CNT=1,PROBE484_WIDTH=1,PROBE484_MU_CNT=1,PROBE485_WIDTH=1,PROBE485_MU_CNT=1,PROBE486_WIDTH=1,PROBE486_MU_CNT=1,PROBE487_WIDTH=1,PROBE487_MU_CNT=1,PROBE488_WIDTH=1,PROBE488_MU_CNT=1,PROBE489_WIDTH=1,PROBE489_MU_CNT=1,PROBE490_WIDTH=1,PROBE490_MU_CNT=1,PROBE491_WIDTH=1,PROBE491_MU_CNT=1,PROBE492_WIDTH=1,PROBE492_MU_CNT=1,PROBE493_WIDTH=1,PROBE493_MU_CNT=1,PROBE494_WIDTH=1,PROBE494_MU_CNT=1,PROBE495_WIDTH=1,PROBE495_MU_CNT=1,PROBE496_WIDTH=1,PROBE496_MU_CNT=1,PROBE497_WIDTH=1,PROBE497_MU_CNT=1,PROBE498_WIDTH=1,PROBE498_MU_CNT=1,PROBE499_WIDTH=1,PROBE499_MU_CNT=1,PROBE500_WIDTH=1,PROBE500_MU_CNT=1,PROBE501_WIDTH=1,PROBE501_MU_CNT=1,PROBE502_WIDTH=1,PROBE502_MU_CNT=1,PROBE503_WIDTH=1,PROBE503_MU_CNT=1,PROBE504_WIDTH=1,PROBE504_MU_CNT=1,PROBE505_WIDTH=1,PROBE505_MU_CNT=1,PROBE506_WIDTH=1,PROBE506_MU_CNT=1,PROBE507_WIDTH=1,PROBE507_MU_CNT=1,PROBE508_WIDTH=1,PROBE508_MU_CNT=1,PROBE509_WIDTH=1,PROBE509_MU_CNT=1,PROBE510_WIDTH=1,PROBE510_MU_CNT=1,PROBE511_WIDTH=1,PROBE511_MU_CNT=1,PROBE512_WIDTH=1,PROBE512_MU_CNT=1,PROBE513_WIDTH=1,PROBE513_MU_CNT=1,PROBE514_WIDTH=1,PROBE514_MU_CNT=1,PROBE515_WIDTH=1,PROBE515_MU_CNT=1,PROBE516_WIDTH=1,PROBE516_MU_CNT=1,PROBE517_WIDTH=1,PROBE517_MU_CNT=1,PROBE518_WIDTH=1,PROBE518_MU_CNT=1,PROBE519_WIDTH=1,PROBE519_MU_CNT=1,PROBE520_WIDTH=1,PROBE520_MU_CNT=1,PROBE521_WIDTH=1,PROBE521_MU_CNT=1,PROBE522_WIDTH=1,PROBE522_MU_CNT=1,PROBE523_WIDTH=1,PROBE523_MU_CNT=1,PROBE524_WIDTH=1,PROBE524_MU_CNT=1,PROBE525_WIDTH=1,PROBE525_MU_CNT=1,PROBE526_WIDTH=1,PROBE526_MU_CNT=1,PROBE527_WIDTH=1,PROBE527_MU_CNT=1,PROBE528_WIDTH=1,PROBE528_MU_CNT=1,PROBE529_WIDTH=1,PROBE529_MU_CNT=1,PROBE530_WIDTH=1,PROBE530_MU_CNT=1,PROBE531_WIDTH=1,PROBE531_MU_CNT=1,PROBE532_WIDTH=1,PROBE532_MU_CNT=1,PROBE533_WIDTH=1,PROBE533_MU_CNT=1,PROBE534_WIDTH=1,PROBE534_MU_CNT=1,PROBE535_WIDTH=1,PROBE535_MU_CNT=1,PROBE536_WIDTH=1,PROBE536_MU_CNT=1,PROBE537_WIDTH=1,PROBE537_MU_CNT=1,PROBE538_WIDTH=1,PROBE538_MU_CNT=1,PROBE539_WIDTH=1,PROBE539_MU_CNT=1,PROBE540_WIDTH=1,PROBE540_MU_CNT=1,PROBE541_WIDTH=1,PROBE541_MU_CNT=1,PROBE542_WIDTH=1,PROBE542_MU_CNT=1,PROBE543_WIDTH=1,PROBE543_MU_CNT=1,PROBE544_WIDTH=1,PROBE544_MU_CNT=1,PROBE545_WIDTH=1,PROBE545_MU_CNT=1,PROBE546_WIDTH=1,PROBE546_MU_CNT=1,PROBE547_WIDTH=1,PROBE547_MU_CNT=1,PROBE548_WIDTH=1,PROBE548_MU_CNT=1,PROBE549_WIDTH=1,PROBE549_MU_CNT=1,PROBE550_WIDTH=1,PROBE550_MU_CNT=1,PROBE551_WIDTH=1,PROBE551_MU_CNT=1,PROBE552_WIDTH=1,PROBE552_MU_CNT=1,PROBE553_WIDTH=1,PROBE553_MU_CNT=1,PROBE554_WIDTH=1,PROBE554_MU_CNT=1,PROBE555_WIDTH=1,PROBE555_MU_CNT=1,PROBE556_WIDTH=1,PROBE556_MU_CNT=1,PROBE557_WIDTH=1,PROBE557_MU_CNT=1,PROBE558_WIDTH=1,PROBE558_MU_CNT=1,PROBE559_WIDTH=1,PROBE559_MU_CNT=1,PROBE560_WIDTH=1,PROBE560_MU_CNT=1,PROBE561_WIDTH=1,PROBE561_MU_CNT=1,PROBE562_WIDTH=1,PROBE562_MU_CNT=1,PROBE563_WIDTH=1,PROBE563_MU_CNT=1,PROBE564_WIDTH=1,PROBE564_MU_CNT=1,PROBE565_WIDTH=1,PROBE565_MU_CNT=1,PROBE566_WIDTH=1,PROBE566_MU_CNT=1,PROBE567_WIDTH=1,PROBE567_MU_CNT=1,PROBE568_WIDTH=1,PROBE568_MU_CNT=1,PROBE569_WIDTH=1,PROBE569_MU_CNT=1,PROBE570_WIDTH=1,PROBE570_MU_CNT=1,PROBE571_WIDTH=1,PROBE571_MU_CNT=1,PROBE572_WIDTH=1,PROBE572_MU_CNT=1,PROBE573_WIDTH=1,PROBE573_MU_CNT=1,PROBE574_WIDTH=1,PROBE574_MU_CNT=1,PROBE575_WIDTH=1,PROBE575_MU_CNT=1,PROBE576_WIDTH=1,PROBE576_MU_CNT=1,PROBE577_WIDTH=1,PROBE577_MU_CNT=1,PROBE578_WIDTH=1,PROBE578_MU_CNT=1,PROBE579_WIDTH=1,PROBE579_MU_CNT=1,PROBE580_WIDTH=1,PROBE580_MU_CNT=1,PROBE581_WIDTH=1,PROBE581_MU_CNT=1,PROBE582_WIDTH=1,PROBE582_MU_CNT=1,PROBE583_WIDTH=1,PROBE583_MU_CNT=1,PROBE584_WIDTH=1,PROBE584_MU_CNT=1,PROBE585_WIDTH=1,PROBE585_MU_CNT=1,PROBE586_WIDTH=1,PROBE586_MU_CNT=1,PROBE587_WIDTH=1,PROBE587_MU_CNT=1,PROBE588_WIDTH=1,PROBE588_MU_CNT=1,PROBE589_WIDTH=1,PROBE589_MU_CNT=1,PROBE590_WIDTH=1,PROBE590_MU_CNT=1,PROBE591_WIDTH=1,PROBE591_MU_CNT=1,PROBE592_WIDTH=1,PROBE592_MU_CNT=1,PROBE593_WIDTH=1,PROBE593_MU_CNT=1,PROBE594_WIDTH=1,PROBE594_MU_CNT=1,PROBE595_WIDTH=1,PROBE595_MU_CNT=1,PROBE596_WIDTH=1,PROBE596_MU_CNT=1,PROBE597_WIDTH=1,PROBE597_MU_CNT=1,PROBE598_WIDTH=1,PROBE598_MU_CNT=1,PROBE599_WIDTH=1,PROBE599_MU_CNT=1,PROBE600_WIDTH=1,PROBE600_MU_CNT=1,PROBE601_WIDTH=1,PROBE601_MU_CNT=1,PROBE602_WIDTH=1,PROBE602_MU_CNT=1,PROBE603_WIDTH=1,PROBE603_MU_CNT=1,PROBE604_WIDTH=1,PROBE604_MU_CNT=1,PROBE605_WIDTH=1,PROBE605_MU_CNT=1,PROBE606_WIDTH=1,PROBE606_MU_CNT=1,PROBE607_WIDTH=1,PROBE607_MU_CNT=1,PROBE608_WIDTH=1,PROBE608_MU_CNT=1,PROBE609_WIDTH=1,PROBE609_MU_CNT=1,PROBE610_WIDTH=1,PROBE610_MU_CNT=1,PROBE611_WIDTH=1,PROBE611_MU_CNT=1,PROBE612_WIDTH=1,PROBE612_MU_CNT=1,PROBE613_WIDTH=1,PROBE613_MU_CNT=1,PROBE614_WIDTH=1,PROBE614_MU_CNT=1,PROBE615_WIDTH=1,PROBE615_MU_CNT=1,PROBE616_WIDTH=1,PROBE616_MU_CNT=1,PROBE617_WIDTH=1,PROBE617_MU_CNT=1,PROBE618_WIDTH=1,PROBE618_MU_CNT=1,PROBE619_WIDTH=1,PROBE619_MU_CNT=1,PROBE620_WIDTH=1,PROBE620_MU_CNT=1,PROBE621_WIDTH=1,PROBE621_MU_CNT=1,PROBE622_WIDTH=1,PROBE622_MU_CNT=1,PROBE623_WIDTH=1,PROBE623_MU_CNT=1,PROBE624_WIDTH=1,PROBE624_MU_CNT=1,PROBE625_WIDTH=1,PROBE625_MU_CNT=1,PROBE626_WIDTH=1,PROBE626_MU_CNT=1,PROBE627_WIDTH=1,PROBE627_MU_CNT=1,PROBE628_WIDTH=1,PROBE628_MU_CNT=1,PROBE629_WIDTH=1,PROBE629_MU_CNT=1,PROBE630_WIDTH=1,PROBE630_MU_CNT=1,PROBE631_WIDTH=1,PROBE631_MU_CNT=1,PROBE632_WIDTH=1,PROBE632_MU_CNT=1,PROBE633_WIDTH=1,PROBE633_MU_CNT=1,PROBE634_WIDTH=1,PROBE634_MU_CNT=1,PROBE635_WIDTH=1,PROBE635_MU_CNT=1,PROBE636_WIDTH=1,PROBE636_MU_CNT=1,PROBE637_WIDTH=1,PROBE637_MU_CNT=1,PROBE638_WIDTH=1,PROBE638_MU_CNT=1,PROBE639_WIDTH=1,PROBE639_MU_CNT=1,PROBE640_WIDTH=1,PROBE640_MU_CNT=1,PROBE641_WIDTH=1,PROBE641_MU_CNT=1,PROBE642_WIDTH=1,PROBE642_MU_CNT=1,PROBE643_WIDTH=1,PROBE643_MU_CNT=1,PROBE644_WIDTH=1,PROBE644_MU_CNT=1,PROBE645_WIDTH=1,PROBE645_MU_CNT=1,PROBE646_WIDTH=1,PROBE646_MU_CNT=1,PROBE647_WIDTH=1,PROBE647_MU_CNT=1,PROBE648_WIDTH=1,PROBE648_MU_CNT=1,PROBE649_WIDTH=1,PROBE649_MU_CNT=1,PROBE650_WIDTH=1,PROBE650_MU_CNT=1,PROBE651_WIDTH=1,PROBE651_MU_CNT=1,PROBE652_WIDTH=1,PROBE652_MU_CNT=1,PROBE653_WIDTH=1,PROBE653_MU_CNT=1,PROBE654_WIDTH=1,PROBE654_MU_CNT=1,PROBE655_WIDTH=1,PROBE655_MU_CNT=1,PROBE656_WIDTH=1,PROBE656_MU_CNT=1,PROBE657_WIDTH=1,PROBE657_MU_CNT=1,PROBE658_WIDTH=1,PROBE658_MU_CNT=1,PROBE659_WIDTH=1,PROBE659_MU_CNT=1,PROBE660_WIDTH=1,PROBE660_MU_CNT=1,PROBE661_WIDTH=1,PROBE661_MU_CNT=1,PROBE662_WIDTH=1,PROBE662_MU_CNT=1,PROBE663_WIDTH=1,PROBE663_MU_CNT=1,PROBE664_WIDTH=1,PROBE664_MU_CNT=1,PROBE665_WIDTH=1,PROBE665_MU_CNT=1,PROBE666_WIDTH=1,PROBE666_MU_CNT=1,PROBE667_WIDTH=1,PROBE667_MU_CNT=1,PROBE668_WIDTH=1,PROBE668_MU_CNT=1,PROBE669_WIDTH=1,PROBE669_MU_CNT=1,PROBE670_WIDTH=1,PROBE670_MU_CNT=1,PROBE671_WIDTH=1,PROBE671_MU_CNT=1,PROBE672_WIDTH=1,PROBE672_MU_CNT=1,PROBE673_WIDTH=1,PROBE673_MU_CNT=1,PROBE674_WIDTH=1,PROBE674_MU_CNT=1,PROBE675_WIDTH=1,PROBE675_MU_CNT=1,PROBE676_WIDTH=1,PROBE676_MU_CNT=1,PROBE677_WIDTH=1,PROBE677_MU_CNT=1,PROBE678_WIDTH=1,PROBE678_MU_CNT=1,PROBE679_WIDTH=1,PROBE679_MU_CNT=1,PROBE680_WIDTH=1,PROBE680_MU_CNT=1,PROBE681_WIDTH=1,PROBE681_MU_CNT=1,PROBE682_WIDTH=1,PROBE682_MU_CNT=1,PROBE683_WIDTH=1,PROBE683_MU_CNT=1,PROBE684_WIDTH=1,PROBE684_MU_CNT=1,PROBE685_WIDTH=1,PROBE685_MU_CNT=1,PROBE686_WIDTH=1,PROBE686_MU_CNT=1,PROBE687_WIDTH=1,PROBE687_MU_CNT=1,PROBE688_WIDTH=1,PROBE688_MU_CNT=1,PROBE689_WIDTH=1,PROBE689_MU_CNT=1,PROBE690_WIDTH=1,PROBE690_MU_CNT=1,PROBE691_WIDTH=1,PROBE691_MU_CNT=1,PROBE692_WIDTH=1,PROBE692_MU_CNT=1,PROBE693_WIDTH=1,PROBE693_MU_CNT=1,PROBE694_WIDTH=1,PROBE694_MU_CNT=1,PROBE695_WIDTH=1,PROBE695_MU_CNT=1,PROBE696_WIDTH=1,PROBE696_MU_CNT=1,PROBE697_WIDTH=1,PROBE697_MU_CNT=1,PROBE698_WIDTH=1,PROBE698_MU_CNT=1,PROBE699_WIDTH=1,PROBE699_MU_CNT=1,PROBE700_WIDTH=1,PROBE700_MU_CNT=1,PROBE701_WIDTH=1,PROBE701_MU_CNT=1,PROBE702_WIDTH=1,PROBE702_MU_CNT=1,PROBE703_WIDTH=1,PROBE703_MU_CNT=1,PROBE704_WIDTH=1,PROBE704_MU_CNT=1,PROBE705_WIDTH=1,PROBE705_MU_CNT=1,PROBE706_WIDTH=1,PROBE706_MU_CNT=1,PROBE707_WIDTH=1,PROBE707_MU_CNT=1,PROBE708_WIDTH=1,PROBE708_MU_CNT=1,PROBE709_WIDTH=1,PROBE709_MU_CNT=1,PROBE710_WIDTH=1,PROBE710_MU_CNT=1,PROBE711_WIDTH=1,PROBE711_MU_CNT=1,PROBE712_WIDTH=1,PROBE712_MU_CNT=1,PROBE713_WIDTH=1,PROBE713_MU_CNT=1,PROBE714_WIDTH=1,PROBE714_MU_CNT=1,PROBE715_WIDTH=1,PROBE715_MU_CNT=1,PROBE716_WIDTH=1,PROBE716_MU_CNT=1,PROBE717_WIDTH=1,PROBE717_MU_CNT=1,PROBE718_WIDTH=1,PROBE718_MU_CNT=1,PROBE719_WIDTH=1,PROBE719_MU_CNT=1,PROBE720_WIDTH=1,PROBE720_MU_CNT=1,PROBE721_WIDTH=1,PROBE721_MU_CNT=1,PROBE722_WIDTH=1,PROBE722_MU_CNT=1,PROBE723_WIDTH=1,PROBE723_MU_CNT=1,PROBE724_WIDTH=1,PROBE724_MU_CNT=1,PROBE725_WIDTH=1,PROBE725_MU_CNT=1,PROBE726_WIDTH=1,PROBE726_MU_CNT=1,PROBE727_WIDTH=1,PROBE727_MU_CNT=1,PROBE728_WIDTH=1,PROBE728_MU_CNT=1,PROBE729_WIDTH=1,PROBE729_MU_CNT=1,PROBE730_WIDTH=1,PROBE730_MU_CNT=1,PROBE731_WIDTH=1,PROBE731_MU_CNT=1,PROBE732_WIDTH=1,PROBE732_MU_CNT=1,PROBE733_WIDTH=1,PROBE733_MU_CNT=1,PROBE734_WIDTH=1,PROBE734_MU_CNT=1,PROBE735_WIDTH=1,PROBE735_MU_CNT=1,PROBE736_WIDTH=1,PROBE736_MU_CNT=1,PROBE737_WIDTH=1,PROBE737_MU_CNT=1,PROBE738_WIDTH=1,PROBE738_MU_CNT=1,PROBE739_WIDTH=1,PROBE739_MU_CNT=1,PROBE740_WIDTH=1,PROBE740_MU_CNT=1,PROBE741_WIDTH=1,PROBE741_MU_CNT=1,PROBE742_WIDTH=1,PROBE742_MU_CNT=1,PROBE743_WIDTH=1,PROBE743_MU_CNT=1,PROBE744_WIDTH=1,PROBE744_MU_CNT=1,PROBE745_WIDTH=1,PROBE745_MU_CNT=1,PROBE746_WIDTH=1,PROBE746_MU_CNT=1,PROBE747_WIDTH=1,PROBE747_MU_CNT=1,PROBE748_WIDTH=1,PROBE748_MU_CNT=1,PROBE749_WIDTH=1,PROBE749_MU_CNT=1,PROBE750_WIDTH=1,PROBE750_MU_CNT=1,PROBE751_WIDTH=1,PROBE751_MU_CNT=1,PROBE752_WIDTH=1,PROBE752_MU_CNT=1,PROBE753_WIDTH=1,PROBE753_MU_CNT=1,PROBE754_WIDTH=1,PROBE754_MU_CNT=1,PROBE755_WIDTH=1,PROBE755_MU_CNT=1,PROBE756_WIDTH=1,PROBE756_MU_CNT=1,PROBE757_WIDTH=1,PROBE757_MU_CNT=1,PROBE758_WIDTH=1,PROBE758_MU_CNT=1,PROBE759_WIDTH=1,PROBE759_MU_CNT=1,PROBE760_WIDTH=1,PROBE760_MU_CNT=1,PROBE761_WIDTH=1,PROBE761_MU_CNT=1,PROBE762_WIDTH=1,PROBE762_MU_CNT=1,PROBE763_WIDTH=1,PROBE763_MU_CNT=1,PROBE764_WIDTH=1,PROBE764_MU_CNT=1,PROBE765_WIDTH=1,PROBE765_MU_CNT=1,PROBE766_WIDTH=1,PROBE766_MU_CNT=1,PROBE767_WIDTH=1,PROBE767_MU_CNT=1,PROBE768_WIDTH=1,PROBE768_MU_CNT=1,PROBE769_WIDTH=1,PROBE769_MU_CNT=1,PROBE770_WIDTH=1,PROBE770_MU_CNT=1,PROBE771_WIDTH=1,PROBE771_MU_CNT=1,PROBE772_WIDTH=1,PROBE772_MU_CNT=1,PROBE773_WIDTH=1,PROBE773_MU_CNT=1,PROBE774_WIDTH=1,PROBE774_MU_CNT=1,PROBE775_WIDTH=1,PROBE775_MU_CNT=1,PROBE776_WIDTH=1,PROBE776_MU_CNT=1,PROBE777_WIDTH=1,PROBE777_MU_CNT=1,PROBE778_WIDTH=1,PROBE778_MU_CNT=1,PROBE779_WIDTH=1,PROBE779_MU_CNT=1,PROBE780_WIDTH=1,PROBE780_MU_CNT=1,PROBE781_WIDTH=1,PROBE781_MU_CNT=1,PROBE782_WIDTH=1,PROBE782_MU_CNT=1,PROBE783_WIDTH=1,PROBE783_MU_CNT=1,PROBE784_WIDTH=1,PROBE784_MU_CNT=1,PROBE785_WIDTH=1,PROBE785_MU_CNT=1,PROBE786_WIDTH=1,PROBE786_MU_CNT=1,PROBE787_WIDTH=1,PROBE787_MU_CNT=1,PROBE788_WIDTH=1,PROBE788_MU_CNT=1,PROBE789_WIDTH=1,PROBE789_MU_CNT=1,PROBE790_WIDTH=1,PROBE790_MU_CNT=1,PROBE791_WIDTH=1,PROBE791_MU_CNT=1,PROBE792_WIDTH=1,PROBE792_MU_CNT=1,PROBE793_WIDTH=1,PROBE793_MU_CNT=1,PROBE794_WIDTH=1,PROBE794_MU_CNT=1,PROBE795_WIDTH=1,PROBE795_MU_CNT=1,PROBE796_WIDTH=1,PROBE796_MU_CNT=1,PROBE797_WIDTH=1,PROBE797_MU_CNT=1,PROBE798_WIDTH=1,PROBE798_MU_CNT=1,PROBE799_WIDTH=1,PROBE799_MU_CNT=1,PROBE800_WIDTH=1,PROBE800_MU_CNT=1,PROBE801_WIDTH=1,PROBE801_MU_CNT=1,PROBE802_WIDTH=1,PROBE802_MU_CNT=1,PROBE803_WIDTH=1,PROBE803_MU_CNT=1,PROBE804_WIDTH=1,PROBE804_MU_CNT=1,PROBE805_WIDTH=1,PROBE805_MU_CNT=1,PROBE806_WIDTH=1,PROBE806_MU_CNT=1,PROBE807_WIDTH=1,PROBE807_MU_CNT=1,PROBE808_WIDTH=1,PROBE808_MU_CNT=1,PROBE809_WIDTH=1,PROBE809_MU_CNT=1,PROBE810_WIDTH=1,PROBE810_MU_CNT=1,PROBE811_WIDTH=1,PROBE811_MU_CNT=1,PROBE812_WIDTH=1,PROBE812_MU_CNT=1,PROBE813_WIDTH=1,PROBE813_MU_CNT=1,PROBE814_WIDTH=1,PROBE814_MU_CNT=1,PROBE815_WIDTH=1,PROBE815_MU_CNT=1,PROBE816_WIDTH=1,PROBE816_MU_CNT=1,PROBE817_WIDTH=1,PROBE817_MU_CNT=1,PROBE818_WIDTH=1,PROBE818_MU_CNT=1,PROBE819_WIDTH=1,PROBE819_MU_CNT=1,PROBE820_WIDTH=1,PROBE820_MU_CNT=1,PROBE821_WIDTH=1,PROBE821_MU_CNT=1,PROBE822_WIDTH=1,PROBE822_MU_CNT=1,PROBE823_WIDTH=1,PROBE823_MU_CNT=1,PROBE824_WIDTH=1,PROBE824_MU_CNT=1,PROBE825_WIDTH=1,PROBE825_MU_CNT=1,PROBE826_WIDTH=1,PROBE826_MU_CNT=1,PROBE827_WIDTH=1,PROBE827_MU_CNT=1,PROBE828_WIDTH=1,PROBE828_MU_CNT=1,PROBE829_WIDTH=1,PROBE829_MU_CNT=1,PROBE830_WIDTH=1,PROBE830_MU_CNT=1,PROBE831_WIDTH=1,PROBE831_MU_CNT=1,PROBE832_WIDTH=1,PROBE832_MU_CNT=1,PROBE833_WIDTH=1,PROBE833_MU_CNT=1,PROBE834_WIDTH=1,PROBE834_MU_CNT=1,PROBE835_WIDTH=1,PROBE835_MU_CNT=1,PROBE836_WIDTH=1,PROBE836_MU_CNT=1,PROBE837_WIDTH=1,PROBE837_MU_CNT=1,PROBE838_WIDTH=1,PROBE838_MU_CNT=1,PROBE839_WIDTH=1,PROBE839_MU_CNT=1,PROBE840_WIDTH=1,PROBE840_MU_CNT=1,PROBE841_WIDTH=1,PROBE841_MU_CNT=1,PROBE842_WIDTH=1,PROBE842_MU_CNT=1,PROBE843_WIDTH=1,PROBE843_MU_CNT=1,PROBE844_WIDTH=1,PROBE844_MU_CNT=1,PROBE845_WIDTH=1,PROBE845_MU_CNT=1,PROBE846_WIDTH=1,PROBE846_MU_CNT=1,PROBE847_WIDTH=1,PROBE847_MU_CNT=1,PROBE848_WIDTH=1,PROBE848_MU_CNT=1,PROBE849_WIDTH=1,PROBE849_MU_CNT=1,PROBE850_WIDTH=1,PROBE850_MU_CNT=1,PROBE851_WIDTH=1,PROBE851_MU_CNT=1,PROBE852_WIDTH=1,PROBE852_MU_CNT=1,PROBE853_WIDTH=1,PROBE853_MU_CNT=1,PROBE854_WIDTH=1,PROBE854_MU_CNT=1,PROBE855_WIDTH=1,PROBE855_MU_CNT=1,PROBE856_WIDTH=1,PROBE856_MU_CNT=1,PROBE857_WIDTH=1,PROBE857_MU_CNT=1,PROBE858_WIDTH=1,PROBE858_MU_CNT=1,PROBE859_WIDTH=1,PROBE859_MU_CNT=1,PROBE860_WIDTH=1,PROBE860_MU_CNT=1,PROBE861_WIDTH=1,PROBE861_MU_CNT=1,PROBE862_WIDTH=1,PROBE862_MU_CNT=1,PROBE863_WIDTH=1,PROBE863_MU_CNT=1,PROBE864_WIDTH=1,PROBE864_MU_CNT=1,PROBE865_WIDTH=1,PROBE865_MU_CNT=1,PROBE866_WIDTH=1,PROBE866_MU_CNT=1,PROBE867_WIDTH=1,PROBE867_MU_CNT=1,PROBE868_WIDTH=1,PROBE868_MU_CNT=1,PROBE869_WIDTH=1,PROBE869_MU_CNT=1,PROBE870_WIDTH=1,PROBE870_MU_CNT=1,PROBE871_WIDTH=1,PROBE871_MU_CNT=1,PROBE872_WIDTH=1,PROBE872_MU_CNT=1,PROBE873_WIDTH=1,PROBE873_MU_CNT=1,PROBE874_WIDTH=1,PROBE874_MU_CNT=1,PROBE875_WIDTH=1,PROBE875_MU_CNT=1,PROBE876_WIDTH=1,PROBE876_MU_CNT=1,PROBE877_WIDTH=1,PROBE877_MU_CNT=1,PROBE878_WIDTH=1,PROBE878_MU_CNT=1,PROBE879_WIDTH=1,PROBE879_MU_CNT=1,PROBE880_WIDTH=1,PROBE880_MU_CNT=1,PROBE881_WIDTH=1,PROBE881_MU_CNT=1,PROBE882_WIDTH=1,PROBE882_MU_CNT=1,PROBE883_WIDTH=1,PROBE883_MU_CNT=1,PROBE884_WIDTH=1,PROBE884_MU_CNT=1,PROBE885_WIDTH=1,PROBE885_MU_CNT=1,PROBE886_WIDTH=1,PROBE886_MU_CNT=1,PROBE887_WIDTH=1,PROBE887_MU_CNT=1,PROBE888_WIDTH=1,PROBE888_MU_CNT=1,PROBE889_WIDTH=1,PROBE889_MU_CNT=1,PROBE890_WIDTH=1,PROBE890_MU_CNT=1,PROBE891_WIDTH=1,PROBE891_MU_CNT=1,PROBE892_WIDTH=1,PROBE892_MU_CNT=1,PROBE893_WIDTH=1,PROBE893_MU_CNT=1,PROBE894_WIDTH=1,PROBE894_MU_CNT=1,PROBE895_WIDTH=1,PROBE895_MU_CNT=1,PROBE896_WIDTH=1,PROBE896_MU_CNT=1,PROBE897_WIDTH=1,PROBE897_MU_CNT=1,PROBE898_WIDTH=1,PROBE898_MU_CNT=1,PROBE899_WIDTH=1,PROBE899_MU_CNT=1,PROBE900_WIDTH=1,PROBE900_MU_CNT=1,PROBE901_WIDTH=1,PROBE901_MU_CNT=1,PROBE902_WIDTH=1,PROBE902_MU_CNT=1,PROBE903_WIDTH=1,PROBE903_MU_CNT=1,PROBE904_WIDTH=1,PROBE904_MU_CNT=1,PROBE905_WIDTH=1,PROBE905_MU_CNT=1,PROBE906_WIDTH=1,PROBE906_MU_CNT=1,PROBE907_WIDTH=1,PROBE907_MU_CNT=1,PROBE908_WIDTH=1,PROBE908_MU_CNT=1,PROBE909_WIDTH=1,PROBE909_MU_CNT=1,PROBE910_WIDTH=1,PROBE910_MU_CNT=1,PROBE911_WIDTH=1,PROBE911_MU_CNT=1,PROBE912_WIDTH=1,PROBE912_MU_CNT=1,PROBE913_WIDTH=1,PROBE913_MU_CNT=1,PROBE914_WIDTH=1,PROBE914_MU_CNT=1,PROBE915_WIDTH=1,PROBE915_MU_CNT=1,PROBE916_WIDTH=1,PROBE916_MU_CNT=1,PROBE917_WIDTH=1,PROBE917_MU_CNT=1,PROBE918_WIDTH=1,PROBE918_MU_CNT=1,PROBE919_WIDTH=1,PROBE919_MU_CNT=1,PROBE920_WIDTH=1,PROBE920_MU_CNT=1,PROBE921_WIDTH=1,PROBE921_MU_CNT=1,PROBE922_WIDTH=1,PROBE922_MU_CNT=1,PROBE923_WIDTH=1,PROBE923_MU_CNT=1,PROBE924_WIDTH=1,PROBE924_MU_CNT=1,PROBE925_WIDTH=1,PROBE925_MU_CNT=1,PROBE926_WIDTH=1,PROBE926_MU_CNT=1,PROBE927_WIDTH=1,PROBE927_MU_CNT=1,PROBE928_WIDTH=1,PROBE928_MU_CNT=1,PROBE929_WIDTH=1,PROBE929_MU_CNT=1,PROBE930_WIDTH=1,PROBE930_MU_CNT=1,PROBE931_WIDTH=1,PROBE931_MU_CNT=1,PROBE932_WIDTH=1,PROBE932_MU_CNT=1,PROBE933_WIDTH=1,PROBE933_MU_CNT=1,PROBE934_WIDTH=1,PROBE934_MU_CNT=1,PROBE935_WIDTH=1,PROBE935_MU_CNT=1,PROBE936_WIDTH=1,PROBE936_MU_CNT=1,PROBE937_WIDTH=1,PROBE937_MU_CNT=1,PROBE938_WIDTH=1,PROBE938_MU_CNT=1,PROBE939_WIDTH=1,PROBE939_MU_CNT=1,PROBE940_WIDTH=1,PROBE940_MU_CNT=1,PROBE941_WIDTH=1,PROBE941_MU_CNT=1,PROBE942_WIDTH=1,PROBE942_MU_CNT=1,PROBE943_WIDTH=1,PROBE943_MU_CNT=1,PROBE944_WIDTH=1,PROBE944_MU_CNT=1,PROBE945_WIDTH=1,PROBE945_MU_CNT=1,PROBE946_WIDTH=1,PROBE946_MU_CNT=1,PROBE947_WIDTH=1,PROBE947_MU_CNT=1,PROBE948_WIDTH=1,PROBE948_MU_CNT=1,PROBE949_WIDTH=1,PROBE949_MU_CNT=1,PROBE950_WIDTH=1,PROBE950_MU_CNT=1,PROBE951_WIDTH=1,PROBE951_MU_CNT=1,PROBE952_WIDTH=1,PROBE952_MU_CNT=1,PROBE953_WIDTH=1,PROBE953_MU_CNT=1,PROBE954_WIDTH=1,PROBE954_MU_CNT=1,PROBE955_WIDTH=1,PROBE955_MU_CNT=1,PROBE956_WIDTH=1,PROBE956_MU_CNT=1,PROBE957_WIDTH=1,PROBE957_MU_CNT=1,PROBE958_WIDTH=1,PROBE958_MU_CNT=1,PROBE959_WIDTH=1,PROBE959_MU_CNT=1,PROBE960_WIDTH=1,PROBE960_MU_CNT=1,PROBE961_WIDTH=1,PROBE961_MU_CNT=1,PROBE962_WIDTH=1,PROBE962_MU_CNT=1,PROBE963_WIDTH=1,PROBE963_MU_CNT=1,PROBE964_WIDTH=1,PROBE964_MU_CNT=1,PROBE965_WIDTH=1,PROBE965_MU_CNT=1,PROBE966_WIDTH=1,PROBE966_MU_CNT=1,PROBE967_WIDTH=1,PROBE967_MU_CNT=1,PROBE968_WIDTH=1,PROBE968_MU_CNT=1,PROBE969_WIDTH=1,PROBE969_MU_CNT=1,PROBE970_WIDTH=1,PROBE970_MU_CNT=1,PROBE971_WIDTH=1,PROBE971_MU_CNT=1,PROBE972_WIDTH=1,PROBE972_MU_CNT=1,PROBE973_WIDTH=1,PROBE973_MU_CNT=1,PROBE974_WIDTH=1,PROBE974_MU_CNT=1,PROBE975_WIDTH=1,PROBE975_MU_CNT=1,PROBE976_WIDTH=1,PROBE976_MU_CNT=1,PROBE977_WIDTH=1,PROBE977_MU_CNT=1,PROBE978_WIDTH=1,PROBE978_MU_CNT=1,PROBE979_WIDTH=1,PROBE979_MU_CNT=1,PROBE980_WIDTH=1,PROBE980_MU_CNT=1,PROBE981_WIDTH=1,PROBE981_MU_CNT=1,PROBE982_WIDTH=1,PROBE982_MU_CNT=1,PROBE983_WIDTH=1,PROBE983_MU_CNT=1,PROBE984_WIDTH=1,PROBE984_MU_CNT=1,PROBE985_WIDTH=1,PROBE985_MU_CNT=1,PROBE986_WIDTH=1,PROBE986_MU_CNT=1,PROBE987_WIDTH=1,PROBE987_MU_CNT=1,PROBE988_WIDTH=1,PROBE988_MU_CNT=1,PROBE989_WIDTH=1,PROBE989_MU_CNT=1,PROBE990_WIDTH=1,PROBE990_MU_CNT=1,PROBE991_WIDTH=1,PROBE991_MU_CNT=1,PROBE992_WIDTH=1,PROBE992_MU_CNT=1,PROBE993_WIDTH=1,PROBE993_MU_CNT=1,PROBE994_WIDTH=1,PROBE994_MU_CNT=1,PROBE995_WIDTH=1,PROBE995_MU_CNT=1,PROBE996_WIDTH=1,PROBE996_MU_CNT=1,PROBE997_WIDTH=1,PROBE997_MU_CNT=1,PROBE998_WIDTH=1,PROBE998_MU_CNT=1,PROBE999_WIDTH=1,PROBE999_MU_CNT=1,PROBE1000_WIDTH=1,PROBE1000_MU_CNT=1,PROBE1001_WIDTH=1,PROBE1001_MU_CNT=1,PROBE1002_WIDTH=1,PROBE1002_MU_CNT=1,PROBE1003_WIDTH=1,PROBE1003_MU_CNT=1,PROBE1004_WIDTH=1,PROBE1004_MU_CNT=1,PROBE1005_WIDTH=1,PROBE1005_MU_CNT=1,PROBE1006_WIDTH=1,PROBE1006_MU_CNT=1,PROBE1007_WIDTH=1,PROBE1007_MU_CNT=1,PROBE1008_WIDTH=1,PROBE1008_MU_CNT=1,PROBE1009_WIDTH=1,PROBE1009_MU_CNT=1,PROBE1010_WIDTH=1,PROBE1010_MU_CNT=1,PROBE1011_WIDTH=1,PROBE1011_MU_CNT=1,PROBE1012_WIDTH=1,PROBE1012_MU_CNT=1,PROBE1013_WIDTH=1,PROBE1013_MU_CNT=1,PROBE1014_WIDTH=1,PROBE1014_MU_CNT=1,PROBE1015_WIDTH=1,PROBE1015_MU_CNT=1,PROBE1016_WIDTH=1,PROBE1016_MU_CNT=1,PROBE1017_WIDTH=1,PROBE1017_MU_CNT=1,PROBE1018_WIDTH=1,PROBE1018_MU_CNT=1,PROBE1019_WIDTH=1,PROBE1019_MU_CNT=1,PROBE1020_WIDTH=1,PROBE1020_MU_CNT=1,PROBE1021_WIDTH=1,PROBE1021_MU_CNT=1,PROBE1022_WIDTH=1,PROBE1022_MU_CNT=1,PROBE1023_WIDTH=1,PROBE1023_MU_CNT=1" *) 
   (* C_XSDB_SLAVE_TYPE = "17" *) 
   (* DONT_TOUCH *) 
   (* DowngradeIPIdentifiedWarnings = "yes" *) 
   (* IS_DEBUG_CORE = "true" *) 
   (* LC_MATCH_TPID_VEC = "208'b0000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) 
   (* LC_MU_CNT_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) 
   (* LC_MU_COUNT = "13" *) 
   (* LC_NUM_TRIG_EQS = "32" *) 
   (* LC_PROBE0_PID = "16'b0000000000000000" *) 
   (* LC_PROBE1000_PID = "16'b0000001111101000" *) 
   (* LC_PROBE1001_PID = "16'b0000001111101001" *) 
   (* LC_PROBE1002_PID = "16'b0000001111101010" *) 
   (* LC_PROBE1003_PID = "16'b0000001111101011" *) 
   (* LC_PROBE1004_PID = "16'b0000001111101100" *) 
   (* LC_PROBE1005_PID = "16'b0000001111101101" *) 
   (* LC_PROBE1006_PID = "16'b0000001111101110" *) 
   (* LC_PROBE1007_PID = "16'b0000001111101111" *) 
   (* LC_PROBE1008_PID = "16'b0000001111110000" *) 
   (* LC_PROBE1009_PID = "16'b0000001111110001" *) 
   (* LC_PROBE100_PID = "16'b0000000001100100" *) 
   (* LC_PROBE1010_PID = "16'b0000001111110010" *) 
   (* LC_PROBE1011_PID = "16'b0000001111110011" *) 
   (* LC_PROBE1012_PID = "16'b0000001111110100" *) 
   (* LC_PROBE1013_PID = "16'b0000001111110101" *) 
   (* LC_PROBE1014_PID = "16'b0000001111110110" *) 
   (* LC_PROBE1015_PID = "16'b0000001111110111" *) 
   (* LC_PROBE1016_PID = "16'b0000001111111000" *) 
   (* LC_PROBE1017_PID = "16'b0000001111111001" *) 
   (* LC_PROBE1018_PID = "16'b0000001111111010" *) 
   (* LC_PROBE1019_PID = "16'b0000001111111011" *) 
   (* LC_PROBE101_PID = "16'b0000000001100101" *) 
   (* LC_PROBE1020_PID = "16'b0000001111111100" *) 
   (* LC_PROBE1021_PID = "16'b0000001111111101" *) 
   (* LC_PROBE1022_PID = "16'b0000001111111110" *) 
   (* LC_PROBE1023_PID = "16'b0000001111111111" *) 
   (* LC_PROBE102_PID = "16'b0000000001100110" *) 
   (* LC_PROBE103_PID = "16'b0000000001100111" *) 
   (* LC_PROBE104_PID = "16'b0000000001101000" *) 
   (* LC_PROBE105_PID = "16'b0000000001101001" *) 
   (* LC_PROBE106_PID = "16'b0000000001101010" *) 
   (* LC_PROBE107_PID = "16'b0000000001101011" *) 
   (* LC_PROBE108_PID = "16'b0000000001101100" *) 
   (* LC_PROBE109_PID = "16'b0000000001101101" *) 
   (* LC_PROBE10_PID = "16'b0000000000001010" *) 
   (* LC_PROBE110_PID = "16'b0000000001101110" *) 
   (* LC_PROBE111_PID = "16'b0000000001101111" *) 
   (* LC_PROBE112_PID = "16'b0000000001110000" *) 
   (* LC_PROBE113_PID = "16'b0000000001110001" *) 
   (* LC_PROBE114_PID = "16'b0000000001110010" *) 
   (* LC_PROBE115_PID = "16'b0000000001110011" *) 
   (* LC_PROBE116_PID = "16'b0000000001110100" *) 
   (* LC_PROBE117_PID = "16'b0000000001110101" *) 
   (* LC_PROBE118_PID = "16'b0000000001110110" *) 
   (* LC_PROBE119_PID = "16'b0000000001110111" *) 
   (* LC_PROBE11_PID = "16'b0000000000001011" *) 
   (* LC_PROBE120_PID = "16'b0000000001111000" *) 
   (* LC_PROBE121_PID = "16'b0000000001111001" *) 
   (* LC_PROBE122_PID = "16'b0000000001111010" *) 
   (* LC_PROBE123_PID = "16'b0000000001111011" *) 
   (* LC_PROBE124_PID = "16'b0000000001111100" *) 
   (* LC_PROBE125_PID = "16'b0000000001111101" *) 
   (* LC_PROBE126_PID = "16'b0000000001111110" *) 
   (* LC_PROBE127_PID = "16'b0000000001111111" *) 
   (* LC_PROBE128_PID = "16'b0000000010000000" *) 
   (* LC_PROBE129_PID = "16'b0000000010000001" *) 
   (* LC_PROBE12_PID = "16'b0000000000001100" *) 
   (* LC_PROBE130_PID = "16'b0000000010000010" *) 
   (* LC_PROBE131_PID = "16'b0000000010000011" *) 
   (* LC_PROBE132_PID = "16'b0000000010000100" *) 
   (* LC_PROBE133_PID = "16'b0000000010000101" *) 
   (* LC_PROBE134_PID = "16'b0000000010000110" *) 
   (* LC_PROBE135_PID = "16'b0000000010000111" *) 
   (* LC_PROBE136_PID = "16'b0000000010001000" *) 
   (* LC_PROBE137_PID = "16'b0000000010001001" *) 
   (* LC_PROBE138_PID = "16'b0000000010001010" *) 
   (* LC_PROBE139_PID = "16'b0000000010001011" *) 
   (* LC_PROBE13_PID = "16'b0000000000001101" *) 
   (* LC_PROBE140_PID = "16'b0000000010001100" *) 
   (* LC_PROBE141_PID = "16'b0000000010001101" *) 
   (* LC_PROBE142_PID = "16'b0000000010001110" *) 
   (* LC_PROBE143_PID = "16'b0000000010001111" *) 
   (* LC_PROBE144_PID = "16'b0000000010010000" *) 
   (* LC_PROBE145_PID = "16'b0000000010010001" *) 
   (* LC_PROBE146_PID = "16'b0000000010010010" *) 
   (* LC_PROBE147_PID = "16'b0000000010010011" *) 
   (* LC_PROBE148_PID = "16'b0000000010010100" *) 
   (* LC_PROBE149_PID = "16'b0000000010010101" *) 
   (* LC_PROBE14_PID = "16'b0000000000001110" *) 
   (* LC_PROBE150_PID = "16'b0000000010010110" *) 
   (* LC_PROBE151_PID = "16'b0000000010010111" *) 
   (* LC_PROBE152_PID = "16'b0000000010011000" *) 
   (* LC_PROBE153_PID = "16'b0000000010011001" *) 
   (* LC_PROBE154_PID = "16'b0000000010011010" *) 
   (* LC_PROBE155_PID = "16'b0000000010011011" *) 
   (* LC_PROBE156_PID = "16'b0000000010011100" *) 
   (* LC_PROBE157_PID = "16'b0000000010011101" *) 
   (* LC_PROBE158_PID = "16'b0000000010011110" *) 
   (* LC_PROBE159_PID = "16'b0000000010011111" *) 
   (* LC_PROBE15_PID = "16'b0000000000001111" *) 
   (* LC_PROBE160_PID = "16'b0000000010100000" *) 
   (* LC_PROBE161_PID = "16'b0000000010100001" *) 
   (* LC_PROBE162_PID = "16'b0000000010100010" *) 
   (* LC_PROBE163_PID = "16'b0000000010100011" *) 
   (* LC_PROBE164_PID = "16'b0000000010100100" *) 
   (* LC_PROBE165_PID = "16'b0000000010100101" *) 
   (* LC_PROBE166_PID = "16'b0000000010100110" *) 
   (* LC_PROBE167_PID = "16'b0000000010100111" *) 
   (* LC_PROBE168_PID = "16'b0000000010101000" *) 
   (* LC_PROBE169_PID = "16'b0000000010101001" *) 
   (* LC_PROBE16_PID = "16'b0000000000010000" *) 
   (* LC_PROBE170_PID = "16'b0000000010101010" *) 
   (* LC_PROBE171_PID = "16'b0000000010101011" *) 
   (* LC_PROBE172_PID = "16'b0000000010101100" *) 
   (* LC_PROBE173_PID = "16'b0000000010101101" *) 
   (* LC_PROBE174_PID = "16'b0000000010101110" *) 
   (* LC_PROBE175_PID = "16'b0000000010101111" *) 
   (* LC_PROBE176_PID = "16'b0000000010110000" *) 
   (* LC_PROBE177_PID = "16'b0000000010110001" *) 
   (* LC_PROBE178_PID = "16'b0000000010110010" *) 
   (* LC_PROBE179_PID = "16'b0000000010110011" *) 
   (* LC_PROBE17_PID = "16'b0000000000010001" *) 
   (* LC_PROBE180_PID = "16'b0000000010110100" *) 
   (* LC_PROBE181_PID = "16'b0000000010110101" *) 
   (* LC_PROBE182_PID = "16'b0000000010110110" *) 
   (* LC_PROBE183_PID = "16'b0000000010110111" *) 
   (* LC_PROBE184_PID = "16'b0000000010111000" *) 
   (* LC_PROBE185_PID = "16'b0000000010111001" *) 
   (* LC_PROBE186_PID = "16'b0000000010111010" *) 
   (* LC_PROBE187_PID = "16'b0000000010111011" *) 
   (* LC_PROBE188_PID = "16'b0000000010111100" *) 
   (* LC_PROBE189_PID = "16'b0000000010111101" *) 
   (* LC_PROBE18_PID = "16'b0000000000010010" *) 
   (* LC_PROBE190_PID = "16'b0000000010111110" *) 
   (* LC_PROBE191_PID = "16'b0000000010111111" *) 
   (* LC_PROBE192_PID = "16'b0000000011000000" *) 
   (* LC_PROBE193_PID = "16'b0000000011000001" *) 
   (* LC_PROBE194_PID = "16'b0000000011000010" *) 
   (* LC_PROBE195_PID = "16'b0000000011000011" *) 
   (* LC_PROBE196_PID = "16'b0000000011000100" *) 
   (* LC_PROBE197_PID = "16'b0000000011000101" *) 
   (* LC_PROBE198_PID = "16'b0000000011000110" *) 
   (* LC_PROBE199_PID = "16'b0000000011000111" *) 
   (* LC_PROBE19_PID = "16'b0000000000010011" *) 
   (* LC_PROBE1_PID = "16'b0000000000000001" *) 
   (* LC_PROBE200_PID = "16'b0000000011001000" *) 
   (* LC_PROBE201_PID = "16'b0000000011001001" *) 
   (* LC_PROBE202_PID = "16'b0000000011001010" *) 
   (* LC_PROBE203_PID = "16'b0000000011001011" *) 
   (* LC_PROBE204_PID = "16'b0000000011001100" *) 
   (* LC_PROBE205_PID = "16'b0000000011001101" *) 
   (* LC_PROBE206_PID = "16'b0000000011001110" *) 
   (* LC_PROBE207_PID = "16'b0000000011001111" *) 
   (* LC_PROBE208_PID = "16'b0000000011010000" *) 
   (* LC_PROBE209_PID = "16'b0000000011010001" *) 
   (* LC_PROBE20_PID = "16'b0000000000010100" *) 
   (* LC_PROBE210_PID = "16'b0000000011010010" *) 
   (* LC_PROBE211_PID = "16'b0000000011010011" *) 
   (* LC_PROBE212_PID = "16'b0000000011010100" *) 
   (* LC_PROBE213_PID = "16'b0000000011010101" *) 
   (* LC_PROBE214_PID = "16'b0000000011010110" *) 
   (* LC_PROBE215_PID = "16'b0000000011010111" *) 
   (* LC_PROBE216_PID = "16'b0000000011011000" *) 
   (* LC_PROBE217_PID = "16'b0000000011011001" *) 
   (* LC_PROBE218_PID = "16'b0000000011011010" *) 
   (* LC_PROBE219_PID = "16'b0000000011011011" *) 
   (* LC_PROBE21_PID = "16'b0000000000010101" *) 
   (* LC_PROBE220_PID = "16'b0000000011011100" *) 
   (* LC_PROBE221_PID = "16'b0000000011011101" *) 
   (* LC_PROBE222_PID = "16'b0000000011011110" *) 
   (* LC_PROBE223_PID = "16'b0000000011011111" *) 
   (* LC_PROBE224_PID = "16'b0000000011100000" *) 
   (* LC_PROBE225_PID = "16'b0000000011100001" *) 
   (* LC_PROBE226_PID = "16'b0000000011100010" *) 
   (* LC_PROBE227_PID = "16'b0000000011100011" *) 
   (* LC_PROBE228_PID = "16'b0000000011100100" *) 
   (* LC_PROBE229_PID = "16'b0000000011100101" *) 
   (* LC_PROBE22_PID = "16'b0000000000010110" *) 
   (* LC_PROBE230_PID = "16'b0000000011100110" *) 
   (* LC_PROBE231_PID = "16'b0000000011100111" *) 
   (* LC_PROBE232_PID = "16'b0000000011101000" *) 
   (* LC_PROBE233_PID = "16'b0000000011101001" *) 
   (* LC_PROBE234_PID = "16'b0000000011101010" *) 
   (* LC_PROBE235_PID = "16'b0000000011101011" *) 
   (* LC_PROBE236_PID = "16'b0000000011101100" *) 
   (* LC_PROBE237_PID = "16'b0000000011101101" *) 
   (* LC_PROBE238_PID = "16'b0000000011101110" *) 
   (* LC_PROBE239_PID = "16'b0000000011101111" *) 
   (* LC_PROBE23_PID = "16'b0000000000010111" *) 
   (* LC_PROBE240_PID = "16'b0000000011110000" *) 
   (* LC_PROBE241_PID = "16'b0000000011110001" *) 
   (* LC_PROBE242_PID = "16'b0000000011110010" *) 
   (* LC_PROBE243_PID = "16'b0000000011110011" *) 
   (* LC_PROBE244_PID = "16'b0000000011110100" *) 
   (* LC_PROBE245_PID = "16'b0000000011110101" *) 
   (* LC_PROBE246_PID = "16'b0000000011110110" *) 
   (* LC_PROBE247_PID = "16'b0000000011110111" *) 
   (* LC_PROBE248_PID = "16'b0000000011111000" *) 
   (* LC_PROBE249_PID = "16'b0000000011111001" *) 
   (* LC_PROBE24_PID = "16'b0000000000011000" *) 
   (* LC_PROBE250_PID = "16'b0000000011111010" *) 
   (* LC_PROBE251_PID = "16'b0000000011111011" *) 
   (* LC_PROBE252_PID = "16'b0000000011111100" *) 
   (* LC_PROBE253_PID = "16'b0000000011111101" *) 
   (* LC_PROBE254_PID = "16'b0000000011111110" *) 
   (* LC_PROBE255_PID = "16'b0000000011111111" *) 
   (* LC_PROBE256_PID = "16'b0000000100000000" *) 
   (* LC_PROBE257_PID = "16'b0000000100000001" *) 
   (* LC_PROBE258_PID = "16'b0000000100000010" *) 
   (* LC_PROBE259_PID = "16'b0000000100000011" *) 
   (* LC_PROBE25_PID = "16'b0000000000011001" *) 
   (* LC_PROBE260_PID = "16'b0000000100000100" *) 
   (* LC_PROBE261_PID = "16'b0000000100000101" *) 
   (* LC_PROBE262_PID = "16'b0000000100000110" *) 
   (* LC_PROBE263_PID = "16'b0000000100000111" *) 
   (* LC_PROBE264_PID = "16'b0000000100001000" *) 
   (* LC_PROBE265_PID = "16'b0000000100001001" *) 
   (* LC_PROBE266_PID = "16'b0000000100001010" *) 
   (* LC_PROBE267_PID = "16'b0000000100001011" *) 
   (* LC_PROBE268_PID = "16'b0000000100001100" *) 
   (* LC_PROBE269_PID = "16'b0000000100001101" *) 
   (* LC_PROBE26_PID = "16'b0000000000011010" *) 
   (* LC_PROBE270_PID = "16'b0000000100001110" *) 
   (* LC_PROBE271_PID = "16'b0000000100001111" *) 
   (* LC_PROBE272_PID = "16'b0000000100010000" *) 
   (* LC_PROBE273_PID = "16'b0000000100010001" *) 
   (* LC_PROBE274_PID = "16'b0000000100010010" *) 
   (* LC_PROBE275_PID = "16'b0000000100010011" *) 
   (* LC_PROBE276_PID = "16'b0000000100010100" *) 
   (* LC_PROBE277_PID = "16'b0000000100010101" *) 
   (* LC_PROBE278_PID = "16'b0000000100010110" *) 
   (* LC_PROBE279_PID = "16'b0000000100010111" *) 
   (* LC_PROBE27_PID = "16'b0000000000011011" *) 
   (* LC_PROBE280_PID = "16'b0000000100011000" *) 
   (* LC_PROBE281_PID = "16'b0000000100011001" *) 
   (* LC_PROBE282_PID = "16'b0000000100011010" *) 
   (* LC_PROBE283_PID = "16'b0000000100011011" *) 
   (* LC_PROBE284_PID = "16'b0000000100011100" *) 
   (* LC_PROBE285_PID = "16'b0000000100011101" *) 
   (* LC_PROBE286_PID = "16'b0000000100011110" *) 
   (* LC_PROBE287_PID = "16'b0000000100011111" *) 
   (* LC_PROBE288_PID = "16'b0000000100100000" *) 
   (* LC_PROBE289_PID = "16'b0000000100100001" *) 
   (* LC_PROBE28_PID = "16'b0000000000011100" *) 
   (* LC_PROBE290_PID = "16'b0000000100100010" *) 
   (* LC_PROBE291_PID = "16'b0000000100100011" *) 
   (* LC_PROBE292_PID = "16'b0000000100100100" *) 
   (* LC_PROBE293_PID = "16'b0000000100100101" *) 
   (* LC_PROBE294_PID = "16'b0000000100100110" *) 
   (* LC_PROBE295_PID = "16'b0000000100100111" *) 
   (* LC_PROBE296_PID = "16'b0000000100101000" *) 
   (* LC_PROBE297_PID = "16'b0000000100101001" *) 
   (* LC_PROBE298_PID = "16'b0000000100101010" *) 
   (* LC_PROBE299_PID = "16'b0000000100101011" *) 
   (* LC_PROBE29_PID = "16'b0000000000011101" *) 
   (* LC_PROBE2_PID = "16'b0000000000000010" *) 
   (* LC_PROBE300_PID = "16'b0000000100101100" *) 
   (* LC_PROBE301_PID = "16'b0000000100101101" *) 
   (* LC_PROBE302_PID = "16'b0000000100101110" *) 
   (* LC_PROBE303_PID = "16'b0000000100101111" *) 
   (* LC_PROBE304_PID = "16'b0000000100110000" *) 
   (* LC_PROBE305_PID = "16'b0000000100110001" *) 
   (* LC_PROBE306_PID = "16'b0000000100110010" *) 
   (* LC_PROBE307_PID = "16'b0000000100110011" *) 
   (* LC_PROBE308_PID = "16'b0000000100110100" *) 
   (* LC_PROBE309_PID = "16'b0000000100110101" *) 
   (* LC_PROBE30_PID = "16'b0000000000011110" *) 
   (* LC_PROBE310_PID = "16'b0000000100110110" *) 
   (* LC_PROBE311_PID = "16'b0000000100110111" *) 
   (* LC_PROBE312_PID = "16'b0000000100111000" *) 
   (* LC_PROBE313_PID = "16'b0000000100111001" *) 
   (* LC_PROBE314_PID = "16'b0000000100111010" *) 
   (* LC_PROBE315_PID = "16'b0000000100111011" *) 
   (* LC_PROBE316_PID = "16'b0000000100111100" *) 
   (* LC_PROBE317_PID = "16'b0000000100111101" *) 
   (* LC_PROBE318_PID = "16'b0000000100111110" *) 
   (* LC_PROBE319_PID = "16'b0000000100111111" *) 
   (* LC_PROBE31_PID = "16'b0000000000011111" *) 
   (* LC_PROBE320_PID = "16'b0000000101000000" *) 
   (* LC_PROBE321_PID = "16'b0000000101000001" *) 
   (* LC_PROBE322_PID = "16'b0000000101000010" *) 
   (* LC_PROBE323_PID = "16'b0000000101000011" *) 
   (* LC_PROBE324_PID = "16'b0000000101000100" *) 
   (* LC_PROBE325_PID = "16'b0000000101000101" *) 
   (* LC_PROBE326_PID = "16'b0000000101000110" *) 
   (* LC_PROBE327_PID = "16'b0000000101000111" *) 
   (* LC_PROBE328_PID = "16'b0000000101001000" *) 
   (* LC_PROBE329_PID = "16'b0000000101001001" *) 
   (* LC_PROBE32_PID = "16'b0000000000100000" *) 
   (* LC_PROBE330_PID = "16'b0000000101001010" *) 
   (* LC_PROBE331_PID = "16'b0000000101001011" *) 
   (* LC_PROBE332_PID = "16'b0000000101001100" *) 
   (* LC_PROBE333_PID = "16'b0000000101001101" *) 
   (* LC_PROBE334_PID = "16'b0000000101001110" *) 
   (* LC_PROBE335_PID = "16'b0000000101001111" *) 
   (* LC_PROBE336_PID = "16'b0000000101010000" *) 
   (* LC_PROBE337_PID = "16'b0000000101010001" *) 
   (* LC_PROBE338_PID = "16'b0000000101010010" *) 
   (* LC_PROBE339_PID = "16'b0000000101010011" *) 
   (* LC_PROBE33_PID = "16'b0000000000100001" *) 
   (* LC_PROBE340_PID = "16'b0000000101010100" *) 
   (* LC_PROBE341_PID = "16'b0000000101010101" *) 
   (* LC_PROBE342_PID = "16'b0000000101010110" *) 
   (* LC_PROBE343_PID = "16'b0000000101010111" *) 
   (* LC_PROBE344_PID = "16'b0000000101011000" *) 
   (* LC_PROBE345_PID = "16'b0000000101011001" *) 
   (* LC_PROBE346_PID = "16'b0000000101011010" *) 
   (* LC_PROBE347_PID = "16'b0000000101011011" *) 
   (* LC_PROBE348_PID = "16'b0000000101011100" *) 
   (* LC_PROBE349_PID = "16'b0000000101011101" *) 
   (* LC_PROBE34_PID = "16'b0000000000100010" *) 
   (* LC_PROBE350_PID = "16'b0000000101011110" *) 
   (* LC_PROBE351_PID = "16'b0000000101011111" *) 
   (* LC_PROBE352_PID = "16'b0000000101100000" *) 
   (* LC_PROBE353_PID = "16'b0000000101100001" *) 
   (* LC_PROBE354_PID = "16'b0000000101100010" *) 
   (* LC_PROBE355_PID = "16'b0000000101100011" *) 
   (* LC_PROBE356_PID = "16'b0000000101100100" *) 
   (* LC_PROBE357_PID = "16'b0000000101100101" *) 
   (* LC_PROBE358_PID = "16'b0000000101100110" *) 
   (* LC_PROBE359_PID = "16'b0000000101100111" *) 
   (* LC_PROBE35_PID = "16'b0000000000100011" *) 
   (* LC_PROBE360_PID = "16'b0000000101101000" *) 
   (* LC_PROBE361_PID = "16'b0000000101101001" *) 
   (* LC_PROBE362_PID = "16'b0000000101101010" *) 
   (* LC_PROBE363_PID = "16'b0000000101101011" *) 
   (* LC_PROBE364_PID = "16'b0000000101101100" *) 
   (* LC_PROBE365_PID = "16'b0000000101101101" *) 
   (* LC_PROBE366_PID = "16'b0000000101101110" *) 
   (* LC_PROBE367_PID = "16'b0000000101101111" *) 
   (* LC_PROBE368_PID = "16'b0000000101110000" *) 
   (* LC_PROBE369_PID = "16'b0000000101110001" *) 
   (* LC_PROBE36_PID = "16'b0000000000100100" *) 
   (* LC_PROBE370_PID = "16'b0000000101110010" *) 
   (* LC_PROBE371_PID = "16'b0000000101110011" *) 
   (* LC_PROBE372_PID = "16'b0000000101110100" *) 
   (* LC_PROBE373_PID = "16'b0000000101110101" *) 
   (* LC_PROBE374_PID = "16'b0000000101110110" *) 
   (* LC_PROBE375_PID = "16'b0000000101110111" *) 
   (* LC_PROBE376_PID = "16'b0000000101111000" *) 
   (* LC_PROBE377_PID = "16'b0000000101111001" *) 
   (* LC_PROBE378_PID = "16'b0000000101111010" *) 
   (* LC_PROBE379_PID = "16'b0000000101111011" *) 
   (* LC_PROBE37_PID = "16'b0000000000100101" *) 
   (* LC_PROBE380_PID = "16'b0000000101111100" *) 
   (* LC_PROBE381_PID = "16'b0000000101111101" *) 
   (* LC_PROBE382_PID = "16'b0000000101111110" *) 
   (* LC_PROBE383_PID = "16'b0000000101111111" *) 
   (* LC_PROBE384_PID = "16'b0000000110000000" *) 
   (* LC_PROBE385_PID = "16'b0000000110000001" *) 
   (* LC_PROBE386_PID = "16'b0000000110000010" *) 
   (* LC_PROBE387_PID = "16'b0000000110000011" *) 
   (* LC_PROBE388_PID = "16'b0000000110000100" *) 
   (* LC_PROBE389_PID = "16'b0000000110000101" *) 
   (* LC_PROBE38_PID = "16'b0000000000100110" *) 
   (* LC_PROBE390_PID = "16'b0000000110000110" *) 
   (* LC_PROBE391_PID = "16'b0000000110000111" *) 
   (* LC_PROBE392_PID = "16'b0000000110001000" *) 
   (* LC_PROBE393_PID = "16'b0000000110001001" *) 
   (* LC_PROBE394_PID = "16'b0000000110001010" *) 
   (* LC_PROBE395_PID = "16'b0000000110001011" *) 
   (* LC_PROBE396_PID = "16'b0000000110001100" *) 
   (* LC_PROBE397_PID = "16'b0000000110001101" *) 
   (* LC_PROBE398_PID = "16'b0000000110001110" *) 
   (* LC_PROBE399_PID = "16'b0000000110001111" *) 
   (* LC_PROBE39_PID = "16'b0000000000100111" *) 
   (* LC_PROBE3_PID = "16'b0000000000000011" *) 
   (* LC_PROBE400_PID = "16'b0000000110010000" *) 
   (* LC_PROBE401_PID = "16'b0000000110010001" *) 
   (* LC_PROBE402_PID = "16'b0000000110010010" *) 
   (* LC_PROBE403_PID = "16'b0000000110010011" *) 
   (* LC_PROBE404_PID = "16'b0000000110010100" *) 
   (* LC_PROBE405_PID = "16'b0000000110010101" *) 
   (* LC_PROBE406_PID = "16'b0000000110010110" *) 
   (* LC_PROBE407_PID = "16'b0000000110010111" *) 
   (* LC_PROBE408_PID = "16'b0000000110011000" *) 
   (* LC_PROBE409_PID = "16'b0000000110011001" *) 
   (* LC_PROBE40_PID = "16'b0000000000101000" *) 
   (* LC_PROBE410_PID = "16'b0000000110011010" *) 
   (* LC_PROBE411_PID = "16'b0000000110011011" *) 
   (* LC_PROBE412_PID = "16'b0000000110011100" *) 
   (* LC_PROBE413_PID = "16'b0000000110011101" *) 
   (* LC_PROBE414_PID = "16'b0000000110011110" *) 
   (* LC_PROBE415_PID = "16'b0000000110011111" *) 
   (* LC_PROBE416_PID = "16'b0000000110100000" *) 
   (* LC_PROBE417_PID = "16'b0000000110100001" *) 
   (* LC_PROBE418_PID = "16'b0000000110100010" *) 
   (* LC_PROBE419_PID = "16'b0000000110100011" *) 
   (* LC_PROBE41_PID = "16'b0000000000101001" *) 
   (* LC_PROBE420_PID = "16'b0000000110100100" *) 
   (* LC_PROBE421_PID = "16'b0000000110100101" *) 
   (* LC_PROBE422_PID = "16'b0000000110100110" *) 
   (* LC_PROBE423_PID = "16'b0000000110100111" *) 
   (* LC_PROBE424_PID = "16'b0000000110101000" *) 
   (* LC_PROBE425_PID = "16'b0000000110101001" *) 
   (* LC_PROBE426_PID = "16'b0000000110101010" *) 
   (* LC_PROBE427_PID = "16'b0000000110101011" *) 
   (* LC_PROBE428_PID = "16'b0000000110101100" *) 
   (* LC_PROBE429_PID = "16'b0000000110101101" *) 
   (* LC_PROBE42_PID = "16'b0000000000101010" *) 
   (* LC_PROBE430_PID = "16'b0000000110101110" *) 
   (* LC_PROBE431_PID = "16'b0000000110101111" *) 
   (* LC_PROBE432_PID = "16'b0000000110110000" *) 
   (* LC_PROBE433_PID = "16'b0000000110110001" *) 
   (* LC_PROBE434_PID = "16'b0000000110110010" *) 
   (* LC_PROBE435_PID = "16'b0000000110110011" *) 
   (* LC_PROBE436_PID = "16'b0000000110110100" *) 
   (* LC_PROBE437_PID = "16'b0000000110110101" *) 
   (* LC_PROBE438_PID = "16'b0000000110110110" *) 
   (* LC_PROBE439_PID = "16'b0000000110110111" *) 
   (* LC_PROBE43_PID = "16'b0000000000101011" *) 
   (* LC_PROBE440_PID = "16'b0000000110111000" *) 
   (* LC_PROBE441_PID = "16'b0000000110111001" *) 
   (* LC_PROBE442_PID = "16'b0000000110111010" *) 
   (* LC_PROBE443_PID = "16'b0000000110111011" *) 
   (* LC_PROBE444_PID = "16'b0000000110111100" *) 
   (* LC_PROBE445_PID = "16'b0000000110111101" *) 
   (* LC_PROBE446_PID = "16'b0000000110111110" *) 
   (* LC_PROBE447_PID = "16'b0000000110111111" *) 
   (* LC_PROBE448_PID = "16'b0000000111000000" *) 
   (* LC_PROBE449_PID = "16'b0000000111000001" *) 
   (* LC_PROBE44_PID = "16'b0000000000101100" *) 
   (* LC_PROBE450_PID = "16'b0000000111000010" *) 
   (* LC_PROBE451_PID = "16'b0000000111000011" *) 
   (* LC_PROBE452_PID = "16'b0000000111000100" *) 
   (* LC_PROBE453_PID = "16'b0000000111000101" *) 
   (* LC_PROBE454_PID = "16'b0000000111000110" *) 
   (* LC_PROBE455_PID = "16'b0000000111000111" *) 
   (* LC_PROBE456_PID = "16'b0000000111001000" *) 
   (* LC_PROBE457_PID = "16'b0000000111001001" *) 
   (* LC_PROBE458_PID = "16'b0000000111001010" *) 
   (* LC_PROBE459_PID = "16'b0000000111001011" *) 
   (* LC_PROBE45_PID = "16'b0000000000101101" *) 
   (* LC_PROBE460_PID = "16'b0000000111001100" *) 
   (* LC_PROBE461_PID = "16'b0000000111001101" *) 
   (* LC_PROBE462_PID = "16'b0000000111001110" *) 
   (* LC_PROBE463_PID = "16'b0000000111001111" *) 
   (* LC_PROBE464_PID = "16'b0000000111010000" *) 
   (* LC_PROBE465_PID = "16'b0000000111010001" *) 
   (* LC_PROBE466_PID = "16'b0000000111010010" *) 
   (* LC_PROBE467_PID = "16'b0000000111010011" *) 
   (* LC_PROBE468_PID = "16'b0000000111010100" *) 
   (* LC_PROBE469_PID = "16'b0000000111010101" *) 
   (* LC_PROBE46_PID = "16'b0000000000101110" *) 
   (* LC_PROBE470_PID = "16'b0000000111010110" *) 
   (* LC_PROBE471_PID = "16'b0000000111010111" *) 
   (* LC_PROBE472_PID = "16'b0000000111011000" *) 
   (* LC_PROBE473_PID = "16'b0000000111011001" *) 
   (* LC_PROBE474_PID = "16'b0000000111011010" *) 
   (* LC_PROBE475_PID = "16'b0000000111011011" *) 
   (* LC_PROBE476_PID = "16'b0000000111011100" *) 
   (* LC_PROBE477_PID = "16'b0000000111011101" *) 
   (* LC_PROBE478_PID = "16'b0000000111011110" *) 
   (* LC_PROBE479_PID = "16'b0000000111011111" *) 
   (* LC_PROBE47_PID = "16'b0000000000101111" *) 
   (* LC_PROBE480_PID = "16'b0000000111100000" *) 
   (* LC_PROBE481_PID = "16'b0000000111100001" *) 
   (* LC_PROBE482_PID = "16'b0000000111100010" *) 
   (* LC_PROBE483_PID = "16'b0000000111100011" *) 
   (* LC_PROBE484_PID = "16'b0000000111100100" *) 
   (* LC_PROBE485_PID = "16'b0000000111100101" *) 
   (* LC_PROBE486_PID = "16'b0000000111100110" *) 
   (* LC_PROBE487_PID = "16'b0000000111100111" *) 
   (* LC_PROBE488_PID = "16'b0000000111101000" *) 
   (* LC_PROBE489_PID = "16'b0000000111101001" *) 
   (* LC_PROBE48_PID = "16'b0000000000110000" *) 
   (* LC_PROBE490_PID = "16'b0000000111101010" *) 
   (* LC_PROBE491_PID = "16'b0000000111101011" *) 
   (* LC_PROBE492_PID = "16'b0000000111101100" *) 
   (* LC_PROBE493_PID = "16'b0000000111101101" *) 
   (* LC_PROBE494_PID = "16'b0000000111101110" *) 
   (* LC_PROBE495_PID = "16'b0000000111101111" *) 
   (* LC_PROBE496_PID = "16'b0000000111110000" *) 
   (* LC_PROBE497_PID = "16'b0000000111110001" *) 
   (* LC_PROBE498_PID = "16'b0000000111110010" *) 
   (* LC_PROBE499_PID = "16'b0000000111110011" *) 
   (* LC_PROBE49_PID = "16'b0000000000110001" *) 
   (* LC_PROBE4_PID = "16'b0000000000000100" *) 
   (* LC_PROBE500_PID = "16'b0000000111110100" *) 
   (* LC_PROBE501_PID = "16'b0000000111110101" *) 
   (* LC_PROBE502_PID = "16'b0000000111110110" *) 
   (* LC_PROBE503_PID = "16'b0000000111110111" *) 
   (* LC_PROBE504_PID = "16'b0000000111111000" *) 
   (* LC_PROBE505_PID = "16'b0000000111111001" *) 
   (* LC_PROBE506_PID = "16'b0000000111111010" *) 
   (* LC_PROBE507_PID = "16'b0000000111111011" *) 
   (* LC_PROBE508_PID = "16'b0000000111111100" *) 
   (* LC_PROBE509_PID = "16'b0000000111111101" *) 
   (* LC_PROBE50_PID = "16'b0000000000110010" *) 
   (* LC_PROBE510_PID = "16'b0000000111111110" *) 
   (* LC_PROBE511_PID = "16'b0000000111111111" *) 
   (* LC_PROBE512_PID = "16'b0000001000000000" *) 
   (* LC_PROBE513_PID = "16'b0000001000000001" *) 
   (* LC_PROBE514_PID = "16'b0000001000000010" *) 
   (* LC_PROBE515_PID = "16'b0000001000000011" *) 
   (* LC_PROBE516_PID = "16'b0000001000000100" *) 
   (* LC_PROBE517_PID = "16'b0000001000000101" *) 
   (* LC_PROBE518_PID = "16'b0000001000000110" *) 
   (* LC_PROBE519_PID = "16'b0000001000000111" *) 
   (* LC_PROBE51_PID = "16'b0000000000110011" *) 
   (* LC_PROBE520_PID = "16'b0000001000001000" *) 
   (* LC_PROBE521_PID = "16'b0000001000001001" *) 
   (* LC_PROBE522_PID = "16'b0000001000001010" *) 
   (* LC_PROBE523_PID = "16'b0000001000001011" *) 
   (* LC_PROBE524_PID = "16'b0000001000001100" *) 
   (* LC_PROBE525_PID = "16'b0000001000001101" *) 
   (* LC_PROBE526_PID = "16'b0000001000001110" *) 
   (* LC_PROBE527_PID = "16'b0000001000001111" *) 
   (* LC_PROBE528_PID = "16'b0000001000010000" *) 
   (* LC_PROBE529_PID = "16'b0000001000010001" *) 
   (* LC_PROBE52_PID = "16'b0000000000110100" *) 
   (* LC_PROBE530_PID = "16'b0000001000010010" *) 
   (* LC_PROBE531_PID = "16'b0000001000010011" *) 
   (* LC_PROBE532_PID = "16'b0000001000010100" *) 
   (* LC_PROBE533_PID = "16'b0000001000010101" *) 
   (* LC_PROBE534_PID = "16'b0000001000010110" *) 
   (* LC_PROBE535_PID = "16'b0000001000010111" *) 
   (* LC_PROBE536_PID = "16'b0000001000011000" *) 
   (* LC_PROBE537_PID = "16'b0000001000011001" *) 
   (* LC_PROBE538_PID = "16'b0000001000011010" *) 
   (* LC_PROBE539_PID = "16'b0000001000011011" *) 
   (* LC_PROBE53_PID = "16'b0000000000110101" *) 
   (* LC_PROBE540_PID = "16'b0000001000011100" *) 
   (* LC_PROBE541_PID = "16'b0000001000011101" *) 
   (* LC_PROBE542_PID = "16'b0000001000011110" *) 
   (* LC_PROBE543_PID = "16'b0000001000011111" *) 
   (* LC_PROBE544_PID = "16'b0000001000100000" *) 
   (* LC_PROBE545_PID = "16'b0000001000100001" *) 
   (* LC_PROBE546_PID = "16'b0000001000100010" *) 
   (* LC_PROBE547_PID = "16'b0000001000100011" *) 
   (* LC_PROBE548_PID = "16'b0000001000100100" *) 
   (* LC_PROBE549_PID = "16'b0000001000100101" *) 
   (* LC_PROBE54_PID = "16'b0000000000110110" *) 
   (* LC_PROBE550_PID = "16'b0000001000100110" *) 
   (* LC_PROBE551_PID = "16'b0000001000100111" *) 
   (* LC_PROBE552_PID = "16'b0000001000101000" *) 
   (* LC_PROBE553_PID = "16'b0000001000101001" *) 
   (* LC_PROBE554_PID = "16'b0000001000101010" *) 
   (* LC_PROBE555_PID = "16'b0000001000101011" *) 
   (* LC_PROBE556_PID = "16'b0000001000101100" *) 
   (* LC_PROBE557_PID = "16'b0000001000101101" *) 
   (* LC_PROBE558_PID = "16'b0000001000101110" *) 
   (* LC_PROBE559_PID = "16'b0000001000101111" *) 
   (* LC_PROBE55_PID = "16'b0000000000110111" *) 
   (* LC_PROBE560_PID = "16'b0000001000110000" *) 
   (* LC_PROBE561_PID = "16'b0000001000110001" *) 
   (* LC_PROBE562_PID = "16'b0000001000110010" *) 
   (* LC_PROBE563_PID = "16'b0000001000110011" *) 
   (* LC_PROBE564_PID = "16'b0000001000110100" *) 
   (* LC_PROBE565_PID = "16'b0000001000110101" *) 
   (* LC_PROBE566_PID = "16'b0000001000110110" *) 
   (* LC_PROBE567_PID = "16'b0000001000110111" *) 
   (* LC_PROBE568_PID = "16'b0000001000111000" *) 
   (* LC_PROBE569_PID = "16'b0000001000111001" *) 
   (* LC_PROBE56_PID = "16'b0000000000111000" *) 
   (* LC_PROBE570_PID = "16'b0000001000111010" *) 
   (* LC_PROBE571_PID = "16'b0000001000111011" *) 
   (* LC_PROBE572_PID = "16'b0000001000111100" *) 
   (* LC_PROBE573_PID = "16'b0000001000111101" *) 
   (* LC_PROBE574_PID = "16'b0000001000111110" *) 
   (* LC_PROBE575_PID = "16'b0000001000111111" *) 
   (* LC_PROBE576_PID = "16'b0000001001000000" *) 
   (* LC_PROBE577_PID = "16'b0000001001000001" *) 
   (* LC_PROBE578_PID = "16'b0000001001000010" *) 
   (* LC_PROBE579_PID = "16'b0000001001000011" *) 
   (* LC_PROBE57_PID = "16'b0000000000111001" *) 
   (* LC_PROBE580_PID = "16'b0000001001000100" *) 
   (* LC_PROBE581_PID = "16'b0000001001000101" *) 
   (* LC_PROBE582_PID = "16'b0000001001000110" *) 
   (* LC_PROBE583_PID = "16'b0000001001000111" *) 
   (* LC_PROBE584_PID = "16'b0000001001001000" *) 
   (* LC_PROBE585_PID = "16'b0000001001001001" *) 
   (* LC_PROBE586_PID = "16'b0000001001001010" *) 
   (* LC_PROBE587_PID = "16'b0000001001001011" *) 
   (* LC_PROBE588_PID = "16'b0000001001001100" *) 
   (* LC_PROBE589_PID = "16'b0000001001001101" *) 
   (* LC_PROBE58_PID = "16'b0000000000111010" *) 
   (* LC_PROBE590_PID = "16'b0000001001001110" *) 
   (* LC_PROBE591_PID = "16'b0000001001001111" *) 
   (* LC_PROBE592_PID = "16'b0000001001010000" *) 
   (* LC_PROBE593_PID = "16'b0000001001010001" *) 
   (* LC_PROBE594_PID = "16'b0000001001010010" *) 
   (* LC_PROBE595_PID = "16'b0000001001010011" *) 
   (* LC_PROBE596_PID = "16'b0000001001010100" *) 
   (* LC_PROBE597_PID = "16'b0000001001010101" *) 
   (* LC_PROBE598_PID = "16'b0000001001010110" *) 
   (* LC_PROBE599_PID = "16'b0000001001010111" *) 
   (* LC_PROBE59_PID = "16'b0000000000111011" *) 
   (* LC_PROBE5_PID = "16'b0000000000000101" *) 
   (* LC_PROBE600_PID = "16'b0000001001011000" *) 
   (* LC_PROBE601_PID = "16'b0000001001011001" *) 
   (* LC_PROBE602_PID = "16'b0000001001011010" *) 
   (* LC_PROBE603_PID = "16'b0000001001011011" *) 
   (* LC_PROBE604_PID = "16'b0000001001011100" *) 
   (* LC_PROBE605_PID = "16'b0000001001011101" *) 
   (* LC_PROBE606_PID = "16'b0000001001011110" *) 
   (* LC_PROBE607_PID = "16'b0000001001011111" *) 
   (* LC_PROBE608_PID = "16'b0000001001100000" *) 
   (* LC_PROBE609_PID = "16'b0000001001100001" *) 
   (* LC_PROBE60_PID = "16'b0000000000111100" *) 
   (* LC_PROBE610_PID = "16'b0000001001100010" *) 
   (* LC_PROBE611_PID = "16'b0000001001100011" *) 
   (* LC_PROBE612_PID = "16'b0000001001100100" *) 
   (* LC_PROBE613_PID = "16'b0000001001100101" *) 
   (* LC_PROBE614_PID = "16'b0000001001100110" *) 
   (* LC_PROBE615_PID = "16'b0000001001100111" *) 
   (* LC_PROBE616_PID = "16'b0000001001101000" *) 
   (* LC_PROBE617_PID = "16'b0000001001101001" *) 
   (* LC_PROBE618_PID = "16'b0000001001101010" *) 
   (* LC_PROBE619_PID = "16'b0000001001101011" *) 
   (* LC_PROBE61_PID = "16'b0000000000111101" *) 
   (* LC_PROBE620_PID = "16'b0000001001101100" *) 
   (* LC_PROBE621_PID = "16'b0000001001101101" *) 
   (* LC_PROBE622_PID = "16'b0000001001101110" *) 
   (* LC_PROBE623_PID = "16'b0000001001101111" *) 
   (* LC_PROBE624_PID = "16'b0000001001110000" *) 
   (* LC_PROBE625_PID = "16'b0000001001110001" *) 
   (* LC_PROBE626_PID = "16'b0000001001110010" *) 
   (* LC_PROBE627_PID = "16'b0000001001110011" *) 
   (* LC_PROBE628_PID = "16'b0000001001110100" *) 
   (* LC_PROBE629_PID = "16'b0000001001110101" *) 
   (* LC_PROBE62_PID = "16'b0000000000111110" *) 
   (* LC_PROBE630_PID = "16'b0000001001110110" *) 
   (* LC_PROBE631_PID = "16'b0000001001110111" *) 
   (* LC_PROBE632_PID = "16'b0000001001111000" *) 
   (* LC_PROBE633_PID = "16'b0000001001111001" *) 
   (* LC_PROBE634_PID = "16'b0000001001111010" *) 
   (* LC_PROBE635_PID = "16'b0000001001111011" *) 
   (* LC_PROBE636_PID = "16'b0000001001111100" *) 
   (* LC_PROBE637_PID = "16'b0000001001111101" *) 
   (* LC_PROBE638_PID = "16'b0000001001111110" *) 
   (* LC_PROBE639_PID = "16'b0000001001111111" *) 
   (* LC_PROBE63_PID = "16'b0000000000111111" *) 
   (* LC_PROBE640_PID = "16'b0000001010000000" *) 
   (* LC_PROBE641_PID = "16'b0000001010000001" *) 
   (* LC_PROBE642_PID = "16'b0000001010000010" *) 
   (* LC_PROBE643_PID = "16'b0000001010000011" *) 
   (* LC_PROBE644_PID = "16'b0000001010000100" *) 
   (* LC_PROBE645_PID = "16'b0000001010000101" *) 
   (* LC_PROBE646_PID = "16'b0000001010000110" *) 
   (* LC_PROBE647_PID = "16'b0000001010000111" *) 
   (* LC_PROBE648_PID = "16'b0000001010001000" *) 
   (* LC_PROBE649_PID = "16'b0000001010001001" *) 
   (* LC_PROBE64_PID = "16'b0000000001000000" *) 
   (* LC_PROBE650_PID = "16'b0000001010001010" *) 
   (* LC_PROBE651_PID = "16'b0000001010001011" *) 
   (* LC_PROBE652_PID = "16'b0000001010001100" *) 
   (* LC_PROBE653_PID = "16'b0000001010001101" *) 
   (* LC_PROBE654_PID = "16'b0000001010001110" *) 
   (* LC_PROBE655_PID = "16'b0000001010001111" *) 
   (* LC_PROBE656_PID = "16'b0000001010010000" *) 
   (* LC_PROBE657_PID = "16'b0000001010010001" *) 
   (* LC_PROBE658_PID = "16'b0000001010010010" *) 
   (* LC_PROBE659_PID = "16'b0000001010010011" *) 
   (* LC_PROBE65_PID = "16'b0000000001000001" *) 
   (* LC_PROBE660_PID = "16'b0000001010010100" *) 
   (* LC_PROBE661_PID = "16'b0000001010010101" *) 
   (* LC_PROBE662_PID = "16'b0000001010010110" *) 
   (* LC_PROBE663_PID = "16'b0000001010010111" *) 
   (* LC_PROBE664_PID = "16'b0000001010011000" *) 
   (* LC_PROBE665_PID = "16'b0000001010011001" *) 
   (* LC_PROBE666_PID = "16'b0000001010011010" *) 
   (* LC_PROBE667_PID = "16'b0000001010011011" *) 
   (* LC_PROBE668_PID = "16'b0000001010011100" *) 
   (* LC_PROBE669_PID = "16'b0000001010011101" *) 
   (* LC_PROBE66_PID = "16'b0000000001000010" *) 
   (* LC_PROBE670_PID = "16'b0000001010011110" *) 
   (* LC_PROBE671_PID = "16'b0000001010011111" *) 
   (* LC_PROBE672_PID = "16'b0000001010100000" *) 
   (* LC_PROBE673_PID = "16'b0000001010100001" *) 
   (* LC_PROBE674_PID = "16'b0000001010100010" *) 
   (* LC_PROBE675_PID = "16'b0000001010100011" *) 
   (* LC_PROBE676_PID = "16'b0000001010100100" *) 
   (* LC_PROBE677_PID = "16'b0000001010100101" *) 
   (* LC_PROBE678_PID = "16'b0000001010100110" *) 
   (* LC_PROBE679_PID = "16'b0000001010100111" *) 
   (* LC_PROBE67_PID = "16'b0000000001000011" *) 
   (* LC_PROBE680_PID = "16'b0000001010101000" *) 
   (* LC_PROBE681_PID = "16'b0000001010101001" *) 
   (* LC_PROBE682_PID = "16'b0000001010101010" *) 
   (* LC_PROBE683_PID = "16'b0000001010101011" *) 
   (* LC_PROBE684_PID = "16'b0000001010101100" *) 
   (* LC_PROBE685_PID = "16'b0000001010101101" *) 
   (* LC_PROBE686_PID = "16'b0000001010101110" *) 
   (* LC_PROBE687_PID = "16'b0000001010101111" *) 
   (* LC_PROBE688_PID = "16'b0000001010110000" *) 
   (* LC_PROBE689_PID = "16'b0000001010110001" *) 
   (* LC_PROBE68_PID = "16'b0000000001000100" *) 
   (* LC_PROBE690_PID = "16'b0000001010110010" *) 
   (* LC_PROBE691_PID = "16'b0000001010110011" *) 
   (* LC_PROBE692_PID = "16'b0000001010110100" *) 
   (* LC_PROBE693_PID = "16'b0000001010110101" *) 
   (* LC_PROBE694_PID = "16'b0000001010110110" *) 
   (* LC_PROBE695_PID = "16'b0000001010110111" *) 
   (* LC_PROBE696_PID = "16'b0000001010111000" *) 
   (* LC_PROBE697_PID = "16'b0000001010111001" *) 
   (* LC_PROBE698_PID = "16'b0000001010111010" *) 
   (* LC_PROBE699_PID = "16'b0000001010111011" *) 
   (* LC_PROBE69_PID = "16'b0000000001000101" *) 
   (* LC_PROBE6_PID = "16'b0000000000000110" *) 
   (* LC_PROBE700_PID = "16'b0000001010111100" *) 
   (* LC_PROBE701_PID = "16'b0000001010111101" *) 
   (* LC_PROBE702_PID = "16'b0000001010111110" *) 
   (* LC_PROBE703_PID = "16'b0000001010111111" *) 
   (* LC_PROBE704_PID = "16'b0000001011000000" *) 
   (* LC_PROBE705_PID = "16'b0000001011000001" *) 
   (* LC_PROBE706_PID = "16'b0000001011000010" *) 
   (* LC_PROBE707_PID = "16'b0000001011000011" *) 
   (* LC_PROBE708_PID = "16'b0000001011000100" *) 
   (* LC_PROBE709_PID = "16'b0000001011000101" *) 
   (* LC_PROBE70_PID = "16'b0000000001000110" *) 
   (* LC_PROBE710_PID = "16'b0000001011000110" *) 
   (* LC_PROBE711_PID = "16'b0000001011000111" *) 
   (* LC_PROBE712_PID = "16'b0000001011001000" *) 
   (* LC_PROBE713_PID = "16'b0000001011001001" *) 
   (* LC_PROBE714_PID = "16'b0000001011001010" *) 
   (* LC_PROBE715_PID = "16'b0000001011001011" *) 
   (* LC_PROBE716_PID = "16'b0000001011001100" *) 
   (* LC_PROBE717_PID = "16'b0000001011001101" *) 
   (* LC_PROBE718_PID = "16'b0000001011001110" *) 
   (* LC_PROBE719_PID = "16'b0000001011001111" *) 
   (* LC_PROBE71_PID = "16'b0000000001000111" *) 
   (* LC_PROBE720_PID = "16'b0000001011010000" *) 
   (* LC_PROBE721_PID = "16'b0000001011010001" *) 
   (* LC_PROBE722_PID = "16'b0000001011010010" *) 
   (* LC_PROBE723_PID = "16'b0000001011010011" *) 
   (* LC_PROBE724_PID = "16'b0000001011010100" *) 
   (* LC_PROBE725_PID = "16'b0000001011010101" *) 
   (* LC_PROBE726_PID = "16'b0000001011010110" *) 
   (* LC_PROBE727_PID = "16'b0000001011010111" *) 
   (* LC_PROBE728_PID = "16'b0000001011011000" *) 
   (* LC_PROBE729_PID = "16'b0000001011011001" *) 
   (* LC_PROBE72_PID = "16'b0000000001001000" *) 
   (* LC_PROBE730_PID = "16'b0000001011011010" *) 
   (* LC_PROBE731_PID = "16'b0000001011011011" *) 
   (* LC_PROBE732_PID = "16'b0000001011011100" *) 
   (* LC_PROBE733_PID = "16'b0000001011011101" *) 
   (* LC_PROBE734_PID = "16'b0000001011011110" *) 
   (* LC_PROBE735_PID = "16'b0000001011011111" *) 
   (* LC_PROBE736_PID = "16'b0000001011100000" *) 
   (* LC_PROBE737_PID = "16'b0000001011100001" *) 
   (* LC_PROBE738_PID = "16'b0000001011100010" *) 
   (* LC_PROBE739_PID = "16'b0000001011100011" *) 
   (* LC_PROBE73_PID = "16'b0000000001001001" *) 
   (* LC_PROBE740_PID = "16'b0000001011100100" *) 
   (* LC_PROBE741_PID = "16'b0000001011100101" *) 
   (* LC_PROBE742_PID = "16'b0000001011100110" *) 
   (* LC_PROBE743_PID = "16'b0000001011100111" *) 
   (* LC_PROBE744_PID = "16'b0000001011101000" *) 
   (* LC_PROBE745_PID = "16'b0000001011101001" *) 
   (* LC_PROBE746_PID = "16'b0000001011101010" *) 
   (* LC_PROBE747_PID = "16'b0000001011101011" *) 
   (* LC_PROBE748_PID = "16'b0000001011101100" *) 
   (* LC_PROBE749_PID = "16'b0000001011101101" *) 
   (* LC_PROBE74_PID = "16'b0000000001001010" *) 
   (* LC_PROBE750_PID = "16'b0000001011101110" *) 
   (* LC_PROBE751_PID = "16'b0000001011101111" *) 
   (* LC_PROBE752_PID = "16'b0000001011110000" *) 
   (* LC_PROBE753_PID = "16'b0000001011110001" *) 
   (* LC_PROBE754_PID = "16'b0000001011110010" *) 
   (* LC_PROBE755_PID = "16'b0000001011110011" *) 
   (* LC_PROBE756_PID = "16'b0000001011110100" *) 
   (* LC_PROBE757_PID = "16'b0000001011110101" *) 
   (* LC_PROBE758_PID = "16'b0000001011110110" *) 
   (* LC_PROBE759_PID = "16'b0000001011110111" *) 
   (* LC_PROBE75_PID = "16'b0000000001001011" *) 
   (* LC_PROBE760_PID = "16'b0000001011111000" *) 
   (* LC_PROBE761_PID = "16'b0000001011111001" *) 
   (* LC_PROBE762_PID = "16'b0000001011111010" *) 
   (* LC_PROBE763_PID = "16'b0000001011111011" *) 
   (* LC_PROBE764_PID = "16'b0000001011111100" *) 
   (* LC_PROBE765_PID = "16'b0000001011111101" *) 
   (* LC_PROBE766_PID = "16'b0000001011111110" *) 
   (* LC_PROBE767_PID = "16'b0000001011111111" *) 
   (* LC_PROBE768_PID = "16'b0000001100000000" *) 
   (* LC_PROBE769_PID = "16'b0000001100000001" *) 
   (* LC_PROBE76_PID = "16'b0000000001001100" *) 
   (* LC_PROBE770_PID = "16'b0000001100000010" *) 
   (* LC_PROBE771_PID = "16'b0000001100000011" *) 
   (* LC_PROBE772_PID = "16'b0000001100000100" *) 
   (* LC_PROBE773_PID = "16'b0000001100000101" *) 
   (* LC_PROBE774_PID = "16'b0000001100000110" *) 
   (* LC_PROBE775_PID = "16'b0000001100000111" *) 
   (* LC_PROBE776_PID = "16'b0000001100001000" *) 
   (* LC_PROBE777_PID = "16'b0000001100001001" *) 
   (* LC_PROBE778_PID = "16'b0000001100001010" *) 
   (* LC_PROBE779_PID = "16'b0000001100001011" *) 
   (* LC_PROBE77_PID = "16'b0000000001001101" *) 
   (* LC_PROBE780_PID = "16'b0000001100001100" *) 
   (* LC_PROBE781_PID = "16'b0000001100001101" *) 
   (* LC_PROBE782_PID = "16'b0000001100001110" *) 
   (* LC_PROBE783_PID = "16'b0000001100001111" *) 
   (* LC_PROBE784_PID = "16'b0000001100010000" *) 
   (* LC_PROBE785_PID = "16'b0000001100010001" *) 
   (* LC_PROBE786_PID = "16'b0000001100010010" *) 
   (* LC_PROBE787_PID = "16'b0000001100010011" *) 
   (* LC_PROBE788_PID = "16'b0000001100010100" *) 
   (* LC_PROBE789_PID = "16'b0000001100010101" *) 
   (* LC_PROBE78_PID = "16'b0000000001001110" *) 
   (* LC_PROBE790_PID = "16'b0000001100010110" *) 
   (* LC_PROBE791_PID = "16'b0000001100010111" *) 
   (* LC_PROBE792_PID = "16'b0000001100011000" *) 
   (* LC_PROBE793_PID = "16'b0000001100011001" *) 
   (* LC_PROBE794_PID = "16'b0000001100011010" *) 
   (* LC_PROBE795_PID = "16'b0000001100011011" *) 
   (* LC_PROBE796_PID = "16'b0000001100011100" *) 
   (* LC_PROBE797_PID = "16'b0000001100011101" *) 
   (* LC_PROBE798_PID = "16'b0000001100011110" *) 
   (* LC_PROBE799_PID = "16'b0000001100011111" *) 
   (* LC_PROBE79_PID = "16'b0000000001001111" *) 
   (* LC_PROBE7_PID = "16'b0000000000000111" *) 
   (* LC_PROBE800_PID = "16'b0000001100100000" *) 
   (* LC_PROBE801_PID = "16'b0000001100100001" *) 
   (* LC_PROBE802_PID = "16'b0000001100100010" *) 
   (* LC_PROBE803_PID = "16'b0000001100100011" *) 
   (* LC_PROBE804_PID = "16'b0000001100100100" *) 
   (* LC_PROBE805_PID = "16'b0000001100100101" *) 
   (* LC_PROBE806_PID = "16'b0000001100100110" *) 
   (* LC_PROBE807_PID = "16'b0000001100100111" *) 
   (* LC_PROBE808_PID = "16'b0000001100101000" *) 
   (* LC_PROBE809_PID = "16'b0000001100101001" *) 
   (* LC_PROBE80_PID = "16'b0000000001010000" *) 
   (* LC_PROBE810_PID = "16'b0000001100101010" *) 
   (* LC_PROBE811_PID = "16'b0000001100101011" *) 
   (* LC_PROBE812_PID = "16'b0000001100101100" *) 
   (* LC_PROBE813_PID = "16'b0000001100101101" *) 
   (* LC_PROBE814_PID = "16'b0000001100101110" *) 
   (* LC_PROBE815_PID = "16'b0000001100101111" *) 
   (* LC_PROBE816_PID = "16'b0000001100110000" *) 
   (* LC_PROBE817_PID = "16'b0000001100110001" *) 
   (* LC_PROBE818_PID = "16'b0000001100110010" *) 
   (* LC_PROBE819_PID = "16'b0000001100110011" *) 
   (* LC_PROBE81_PID = "16'b0000000001010001" *) 
   (* LC_PROBE820_PID = "16'b0000001100110100" *) 
   (* LC_PROBE821_PID = "16'b0000001100110101" *) 
   (* LC_PROBE822_PID = "16'b0000001100110110" *) 
   (* LC_PROBE823_PID = "16'b0000001100110111" *) 
   (* LC_PROBE824_PID = "16'b0000001100111000" *) 
   (* LC_PROBE825_PID = "16'b0000001100111001" *) 
   (* LC_PROBE826_PID = "16'b0000001100111010" *) 
   (* LC_PROBE827_PID = "16'b0000001100111011" *) 
   (* LC_PROBE828_PID = "16'b0000001100111100" *) 
   (* LC_PROBE829_PID = "16'b0000001100111101" *) 
   (* LC_PROBE82_PID = "16'b0000000001010010" *) 
   (* LC_PROBE830_PID = "16'b0000001100111110" *) 
   (* LC_PROBE831_PID = "16'b0000001100111111" *) 
   (* LC_PROBE832_PID = "16'b0000001101000000" *) 
   (* LC_PROBE833_PID = "16'b0000001101000001" *) 
   (* LC_PROBE834_PID = "16'b0000001101000010" *) 
   (* LC_PROBE835_PID = "16'b0000001101000011" *) 
   (* LC_PROBE836_PID = "16'b0000001101000100" *) 
   (* LC_PROBE837_PID = "16'b0000001101000101" *) 
   (* LC_PROBE838_PID = "16'b0000001101000110" *) 
   (* LC_PROBE839_PID = "16'b0000001101000111" *) 
   (* LC_PROBE83_PID = "16'b0000000001010011" *) 
   (* LC_PROBE840_PID = "16'b0000001101001000" *) 
   (* LC_PROBE841_PID = "16'b0000001101001001" *) 
   (* LC_PROBE842_PID = "16'b0000001101001010" *) 
   (* LC_PROBE843_PID = "16'b0000001101001011" *) 
   (* LC_PROBE844_PID = "16'b0000001101001100" *) 
   (* LC_PROBE845_PID = "16'b0000001101001101" *) 
   (* LC_PROBE846_PID = "16'b0000001101001110" *) 
   (* LC_PROBE847_PID = "16'b0000001101001111" *) 
   (* LC_PROBE848_PID = "16'b0000001101010000" *) 
   (* LC_PROBE849_PID = "16'b0000001101010001" *) 
   (* LC_PROBE84_PID = "16'b0000000001010100" *) 
   (* LC_PROBE850_PID = "16'b0000001101010010" *) 
   (* LC_PROBE851_PID = "16'b0000001101010011" *) 
   (* LC_PROBE852_PID = "16'b0000001101010100" *) 
   (* LC_PROBE853_PID = "16'b0000001101010101" *) 
   (* LC_PROBE854_PID = "16'b0000001101010110" *) 
   (* LC_PROBE855_PID = "16'b0000001101010111" *) 
   (* LC_PROBE856_PID = "16'b0000001101011000" *) 
   (* LC_PROBE857_PID = "16'b0000001101011001" *) 
   (* LC_PROBE858_PID = "16'b0000001101011010" *) 
   (* LC_PROBE859_PID = "16'b0000001101011011" *) 
   (* LC_PROBE85_PID = "16'b0000000001010101" *) 
   (* LC_PROBE860_PID = "16'b0000001101011100" *) 
   (* LC_PROBE861_PID = "16'b0000001101011101" *) 
   (* LC_PROBE862_PID = "16'b0000001101011110" *) 
   (* LC_PROBE863_PID = "16'b0000001101011111" *) 
   (* LC_PROBE864_PID = "16'b0000001101100000" *) 
   (* LC_PROBE865_PID = "16'b0000001101100001" *) 
   (* LC_PROBE866_PID = "16'b0000001101100010" *) 
   (* LC_PROBE867_PID = "16'b0000001101100011" *) 
   (* LC_PROBE868_PID = "16'b0000001101100100" *) 
   (* LC_PROBE869_PID = "16'b0000001101100101" *) 
   (* LC_PROBE86_PID = "16'b0000000001010110" *) 
   (* LC_PROBE870_PID = "16'b0000001101100110" *) 
   (* LC_PROBE871_PID = "16'b0000001101100111" *) 
   (* LC_PROBE872_PID = "16'b0000001101101000" *) 
   (* LC_PROBE873_PID = "16'b0000001101101001" *) 
   (* LC_PROBE874_PID = "16'b0000001101101010" *) 
   (* LC_PROBE875_PID = "16'b0000001101101011" *) 
   (* LC_PROBE876_PID = "16'b0000001101101100" *) 
   (* LC_PROBE877_PID = "16'b0000001101101101" *) 
   (* LC_PROBE878_PID = "16'b0000001101101110" *) 
   (* LC_PROBE879_PID = "16'b0000001101101111" *) 
   (* LC_PROBE87_PID = "16'b0000000001010111" *) 
   (* LC_PROBE880_PID = "16'b0000001101110000" *) 
   (* LC_PROBE881_PID = "16'b0000001101110001" *) 
   (* LC_PROBE882_PID = "16'b0000001101110010" *) 
   (* LC_PROBE883_PID = "16'b0000001101110011" *) 
   (* LC_PROBE884_PID = "16'b0000001101110100" *) 
   (* LC_PROBE885_PID = "16'b0000001101110101" *) 
   (* LC_PROBE886_PID = "16'b0000001101110110" *) 
   (* LC_PROBE887_PID = "16'b0000001101110111" *) 
   (* LC_PROBE888_PID = "16'b0000001101111000" *) 
   (* LC_PROBE889_PID = "16'b0000001101111001" *) 
   (* LC_PROBE88_PID = "16'b0000000001011000" *) 
   (* LC_PROBE890_PID = "16'b0000001101111010" *) 
   (* LC_PROBE891_PID = "16'b0000001101111011" *) 
   (* LC_PROBE892_PID = "16'b0000001101111100" *) 
   (* LC_PROBE893_PID = "16'b0000001101111101" *) 
   (* LC_PROBE894_PID = "16'b0000001101111110" *) 
   (* LC_PROBE895_PID = "16'b0000001101111111" *) 
   (* LC_PROBE896_PID = "16'b0000001110000000" *) 
   (* LC_PROBE897_PID = "16'b0000001110000001" *) 
   (* LC_PROBE898_PID = "16'b0000001110000010" *) 
   (* LC_PROBE899_PID = "16'b0000001110000011" *) 
   (* LC_PROBE89_PID = "16'b0000000001011001" *) 
   (* LC_PROBE8_PID = "16'b0000000000001000" *) 
   (* LC_PROBE900_PID = "16'b0000001110000100" *) 
   (* LC_PROBE901_PID = "16'b0000001110000101" *) 
   (* LC_PROBE902_PID = "16'b0000001110000110" *) 
   (* LC_PROBE903_PID = "16'b0000001110000111" *) 
   (* LC_PROBE904_PID = "16'b0000001110001000" *) 
   (* LC_PROBE905_PID = "16'b0000001110001001" *) 
   (* LC_PROBE906_PID = "16'b0000001110001010" *) 
   (* LC_PROBE907_PID = "16'b0000001110001011" *) 
   (* LC_PROBE908_PID = "16'b0000001110001100" *) 
   (* LC_PROBE909_PID = "16'b0000001110001101" *) 
   (* LC_PROBE90_PID = "16'b0000000001011010" *) 
   (* LC_PROBE910_PID = "16'b0000001110001110" *) 
   (* LC_PROBE911_PID = "16'b0000001110001111" *) 
   (* LC_PROBE912_PID = "16'b0000001110010000" *) 
   (* LC_PROBE913_PID = "16'b0000001110010001" *) 
   (* LC_PROBE914_PID = "16'b0000001110010010" *) 
   (* LC_PROBE915_PID = "16'b0000001110010011" *) 
   (* LC_PROBE916_PID = "16'b0000001110010100" *) 
   (* LC_PROBE917_PID = "16'b0000001110010101" *) 
   (* LC_PROBE918_PID = "16'b0000001110010110" *) 
   (* LC_PROBE919_PID = "16'b0000001110010111" *) 
   (* LC_PROBE91_PID = "16'b0000000001011011" *) 
   (* LC_PROBE920_PID = "16'b0000001110011000" *) 
   (* LC_PROBE921_PID = "16'b0000001110011001" *) 
   (* LC_PROBE922_PID = "16'b0000001110011010" *) 
   (* LC_PROBE923_PID = "16'b0000001110011011" *) 
   (* LC_PROBE924_PID = "16'b0000001110011100" *) 
   (* LC_PROBE925_PID = "16'b0000001110011101" *) 
   (* LC_PROBE926_PID = "16'b0000001110011110" *) 
   (* LC_PROBE927_PID = "16'b0000001110011111" *) 
   (* LC_PROBE928_PID = "16'b0000001110100000" *) 
   (* LC_PROBE929_PID = "16'b0000001110100001" *) 
   (* LC_PROBE92_PID = "16'b0000000001011100" *) 
   (* LC_PROBE930_PID = "16'b0000001110100010" *) 
   (* LC_PROBE931_PID = "16'b0000001110100011" *) 
   (* LC_PROBE932_PID = "16'b0000001110100100" *) 
   (* LC_PROBE933_PID = "16'b0000001110100101" *) 
   (* LC_PROBE934_PID = "16'b0000001110100110" *) 
   (* LC_PROBE935_PID = "16'b0000001110100111" *) 
   (* LC_PROBE936_PID = "16'b0000001110101000" *) 
   (* LC_PROBE937_PID = "16'b0000001110101001" *) 
   (* LC_PROBE938_PID = "16'b0000001110101010" *) 
   (* LC_PROBE939_PID = "16'b0000001110101011" *) 
   (* LC_PROBE93_PID = "16'b0000000001011101" *) 
   (* LC_PROBE940_PID = "16'b0000001110101100" *) 
   (* LC_PROBE941_PID = "16'b0000001110101101" *) 
   (* LC_PROBE942_PID = "16'b0000001110101110" *) 
   (* LC_PROBE943_PID = "16'b0000001110101111" *) 
   (* LC_PROBE944_PID = "16'b0000001110110000" *) 
   (* LC_PROBE945_PID = "16'b0000001110110001" *) 
   (* LC_PROBE946_PID = "16'b0000001110110010" *) 
   (* LC_PROBE947_PID = "16'b0000001110110011" *) 
   (* LC_PROBE948_PID = "16'b0000001110110100" *) 
   (* LC_PROBE949_PID = "16'b0000001110110101" *) 
   (* LC_PROBE94_PID = "16'b0000000001011110" *) 
   (* LC_PROBE950_PID = "16'b0000001110110110" *) 
   (* LC_PROBE951_PID = "16'b0000001110110111" *) 
   (* LC_PROBE952_PID = "16'b0000001110111000" *) 
   (* LC_PROBE953_PID = "16'b0000001110111001" *) 
   (* LC_PROBE954_PID = "16'b0000001110111010" *) 
   (* LC_PROBE955_PID = "16'b0000001110111011" *) 
   (* LC_PROBE956_PID = "16'b0000001110111100" *) 
   (* LC_PROBE957_PID = "16'b0000001110111101" *) 
   (* LC_PROBE958_PID = "16'b0000001110111110" *) 
   (* LC_PROBE959_PID = "16'b0000001110111111" *) 
   (* LC_PROBE95_PID = "16'b0000000001011111" *) 
   (* LC_PROBE960_PID = "16'b0000001111000000" *) 
   (* LC_PROBE961_PID = "16'b0000001111000001" *) 
   (* LC_PROBE962_PID = "16'b0000001111000010" *) 
   (* LC_PROBE963_PID = "16'b0000001111000011" *) 
   (* LC_PROBE964_PID = "16'b0000001111000100" *) 
   (* LC_PROBE965_PID = "16'b0000001111000101" *) 
   (* LC_PROBE966_PID = "16'b0000001111000110" *) 
   (* LC_PROBE967_PID = "16'b0000001111000111" *) 
   (* LC_PROBE968_PID = "16'b0000001111001000" *) 
   (* LC_PROBE969_PID = "16'b0000001111001001" *) 
   (* LC_PROBE96_PID = "16'b0000000001100000" *) 
   (* LC_PROBE970_PID = "16'b0000001111001010" *) 
   (* LC_PROBE971_PID = "16'b0000001111001011" *) 
   (* LC_PROBE972_PID = "16'b0000001111001100" *) 
   (* LC_PROBE973_PID = "16'b0000001111001101" *) 
   (* LC_PROBE974_PID = "16'b0000001111001110" *) 
   (* LC_PROBE975_PID = "16'b0000001111001111" *) 
   (* LC_PROBE976_PID = "16'b0000001111010000" *) 
   (* LC_PROBE977_PID = "16'b0000001111010001" *) 
   (* LC_PROBE978_PID = "16'b0000001111010010" *) 
   (* LC_PROBE979_PID = "16'b0000001111010011" *) 
   (* LC_PROBE97_PID = "16'b0000000001100001" *) 
   (* LC_PROBE980_PID = "16'b0000001111010100" *) 
   (* LC_PROBE981_PID = "16'b0000001111010101" *) 
   (* LC_PROBE982_PID = "16'b0000001111010110" *) 
   (* LC_PROBE983_PID = "16'b0000001111010111" *) 
   (* LC_PROBE984_PID = "16'b0000001111011000" *) 
   (* LC_PROBE985_PID = "16'b0000001111011001" *) 
   (* LC_PROBE986_PID = "16'b0000001111011010" *) 
   (* LC_PROBE987_PID = "16'b0000001111011011" *) 
   (* LC_PROBE988_PID = "16'b0000001111011100" *) 
   (* LC_PROBE989_PID = "16'b0000001111011101" *) 
   (* LC_PROBE98_PID = "16'b0000000001100010" *) 
   (* LC_PROBE990_PID = "16'b0000001111011110" *) 
   (* LC_PROBE991_PID = "16'b0000001111011111" *) 
   (* LC_PROBE992_PID = "16'b0000001111100000" *) 
   (* LC_PROBE993_PID = "16'b0000001111100001" *) 
   (* LC_PROBE994_PID = "16'b0000001111100010" *) 
   (* LC_PROBE995_PID = "16'b0000001111100011" *) 
   (* LC_PROBE996_PID = "16'b0000001111100100" *) 
   (* LC_PROBE997_PID = "16'b0000001111100101" *) 
   (* LC_PROBE998_PID = "16'b0000001111100110" *) 
   (* LC_PROBE999_PID = "16'b0000001111100111" *) 
   (* LC_PROBE99_PID = "16'b0000000001100011" *) 
   (* LC_PROBE9_PID = "16'b0000000000001001" *) 
   (* LC_PROBES_WIDTH = "140" *) 
   (* LC_PROBE_WIDTH_STRING = "16384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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*) 
   (* syn_noprune = "TRUE" *) 
   ila_0_ila_v5_0_ila__parameterized0 U0
       (.clk(clk),
        .probe0(probe0),
        .probe1(probe1),
        .probe10(probe10),
        .probe100(1'b0),
        .probe1000(1'b0),
        .probe1001(1'b0),
        .probe1002(1'b0),
        .probe1003(1'b0),
        .probe1004(1'b0),
        .probe1005(1'b0),
        .probe1006(1'b0),
        .probe1007(1'b0),
        .probe1008(1'b0),
        .probe1009(1'b0),
        .probe101(1'b0),
        .probe1010(1'b0),
        .probe1011(1'b0),
        .probe1012(1'b0),
        .probe1013(1'b0),
        .probe1014(1'b0),
        .probe1015(1'b0),
        .probe1016(1'b0),
        .probe1017(1'b0),
        .probe1018(1'b0),
        .probe1019(1'b0),
        .probe102(1'b0),
        .probe1020(1'b0),
        .probe1021(1'b0),
        .probe1022(1'b0),
        .probe1023(1'b0),
        .probe103(1'b0),
        .probe104(1'b0),
        .probe105(1'b0),
        .probe106(1'b0),
        .probe107(1'b0),
        .probe108(1'b0),
        .probe109(1'b0),
        .probe11(probe11),
        .probe110(1'b0),
        .probe111(1'b0),
        .probe112(1'b0),
        .probe113(1'b0),
        .probe114(1'b0),
        .probe115(1'b0),
        .probe116(1'b0),
        .probe117(1'b0),
        .probe118(1'b0),
        .probe119(1'b0),
        .probe12(probe12),
        .probe120(1'b0),
        .probe121(1'b0),
        .probe122(1'b0),
        .probe123(1'b0),
        .probe124(1'b0),
        .probe125(1'b0),
        .probe126(1'b0),
        .probe127(1'b0),
        .probe128(1'b0),
        .probe129(1'b0),
        .probe13(1'b0),
        .probe130(1'b0),
        .probe131(1'b0),
        .probe132(1'b0),
        .probe133(1'b0),
        .probe134(1'b0),
        .probe135(1'b0),
        .probe136(1'b0),
        .probe137(1'b0),
        .probe138(1'b0),
        .probe139(1'b0),
        .probe14(1'b0),
        .probe140(1'b0),
        .probe141(1'b0),
        .probe142(1'b0),
        .probe143(1'b0),
        .probe144(1'b0),
        .probe145(1'b0),
        .probe146(1'b0),
        .probe147(1'b0),
        .probe148(1'b0),
        .probe149(1'b0),
        .probe15(1'b0),
        .probe150(1'b0),
        .probe151(1'b0),
        .probe152(1'b0),
        .probe153(1'b0),
        .probe154(1'b0),
        .probe155(1'b0),
        .probe156(1'b0),
        .probe157(1'b0),
        .probe158(1'b0),
        .probe159(1'b0),
        .probe16(1'b0),
        .probe160(1'b0),
        .probe161(1'b0),
        .probe162(1'b0),
        .probe163(1'b0),
        .probe164(1'b0),
        .probe165(1'b0),
        .probe166(1'b0),
        .probe167(1'b0),
        .probe168(1'b0),
        .probe169(1'b0),
        .probe17(1'b0),
        .probe170(1'b0),
        .probe171(1'b0),
        .probe172(1'b0),
        .probe173(1'b0),
        .probe174(1'b0),
        .probe175(1'b0),
        .probe176(1'b0),
        .probe177(1'b0),
        .probe178(1'b0),
        .probe179(1'b0),
        .probe18(1'b0),
        .probe180(1'b0),
        .probe181(1'b0),
        .probe182(1'b0),
        .probe183(1'b0),
        .probe184(1'b0),
        .probe185(1'b0),
        .probe186(1'b0),
        .probe187(1'b0),
        .probe188(1'b0),
        .probe189(1'b0),
        .probe19(1'b0),
        .probe190(1'b0),
        .probe191(1'b0),
        .probe192(1'b0),
        .probe193(1'b0),
        .probe194(1'b0),
        .probe195(1'b0),
        .probe196(1'b0),
        .probe197(1'b0),
        .probe198(1'b0),
        .probe199(1'b0),
        .probe2(probe2),
        .probe20(1'b0),
        .probe200(1'b0),
        .probe201(1'b0),
        .probe202(1'b0),
        .probe203(1'b0),
        .probe204(1'b0),
        .probe205(1'b0),
        .probe206(1'b0),
        .probe207(1'b0),
        .probe208(1'b0),
        .probe209(1'b0),
        .probe21(1'b0),
        .probe210(1'b0),
        .probe211(1'b0),
        .probe212(1'b0),
        .probe213(1'b0),
        .probe214(1'b0),
        .probe215(1'b0),
        .probe216(1'b0),
        .probe217(1'b0),
        .probe218(1'b0),
        .probe219(1'b0),
        .probe22(1'b0),
        .probe220(1'b0),
        .probe221(1'b0),
        .probe222(1'b0),
        .probe223(1'b0),
        .probe224(1'b0),
        .probe225(1'b0),
        .probe226(1'b0),
        .probe227(1'b0),
        .probe228(1'b0),
        .probe229(1'b0),
        .probe23(1'b0),
        .probe230(1'b0),
        .probe231(1'b0),
        .probe232(1'b0),
        .probe233(1'b0),
        .probe234(1'b0),
        .probe235(1'b0),
        .probe236(1'b0),
        .probe237(1'b0),
        .probe238(1'b0),
        .probe239(1'b0),
        .probe24(1'b0),
        .probe240(1'b0),
        .probe241(1'b0),
        .probe242(1'b0),
        .probe243(1'b0),
        .probe244(1'b0),
        .probe245(1'b0),
        .probe246(1'b0),
        .probe247(1'b0),
        .probe248(1'b0),
        .probe249(1'b0),
        .probe25(1'b0),
        .probe250(1'b0),
        .probe251(1'b0),
        .probe252(1'b0),
        .probe253(1'b0),
        .probe254(1'b0),
        .probe255(1'b0),
        .probe256(1'b0),
        .probe257(1'b0),
        .probe258(1'b0),
        .probe259(1'b0),
        .probe26(1'b0),
        .probe260(1'b0),
        .probe261(1'b0),
        .probe262(1'b0),
        .probe263(1'b0),
        .probe264(1'b0),
        .probe265(1'b0),
        .probe266(1'b0),
        .probe267(1'b0),
        .probe268(1'b0),
        .probe269(1'b0),
        .probe27(1'b0),
        .probe270(1'b0),
        .probe271(1'b0),
        .probe272(1'b0),
        .probe273(1'b0),
        .probe274(1'b0),
        .probe275(1'b0),
        .probe276(1'b0),
        .probe277(1'b0),
        .probe278(1'b0),
        .probe279(1'b0),
        .probe28(1'b0),
        .probe280(1'b0),
        .probe281(1'b0),
        .probe282(1'b0),
        .probe283(1'b0),
        .probe284(1'b0),
        .probe285(1'b0),
        .probe286(1'b0),
        .probe287(1'b0),
        .probe288(1'b0),
        .probe289(1'b0),
        .probe29(1'b0),
        .probe290(1'b0),
        .probe291(1'b0),
        .probe292(1'b0),
        .probe293(1'b0),
        .probe294(1'b0),
        .probe295(1'b0),
        .probe296(1'b0),
        .probe297(1'b0),
        .probe298(1'b0),
        .probe299(1'b0),
        .probe3(probe3),
        .probe30(1'b0),
        .probe300(1'b0),
        .probe301(1'b0),
        .probe302(1'b0),
        .probe303(1'b0),
        .probe304(1'b0),
        .probe305(1'b0),
        .probe306(1'b0),
        .probe307(1'b0),
        .probe308(1'b0),
        .probe309(1'b0),
        .probe31(1'b0),
        .probe310(1'b0),
        .probe311(1'b0),
        .probe312(1'b0),
        .probe313(1'b0),
        .probe314(1'b0),
        .probe315(1'b0),
        .probe316(1'b0),
        .probe317(1'b0),
        .probe318(1'b0),
        .probe319(1'b0),
        .probe32(1'b0),
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        .probe928(1'b0),
        .probe929(1'b0),
        .probe93(1'b0),
        .probe930(1'b0),
        .probe931(1'b0),
        .probe932(1'b0),
        .probe933(1'b0),
        .probe934(1'b0),
        .probe935(1'b0),
        .probe936(1'b0),
        .probe937(1'b0),
        .probe938(1'b0),
        .probe939(1'b0),
        .probe94(1'b0),
        .probe940(1'b0),
        .probe941(1'b0),
        .probe942(1'b0),
        .probe943(1'b0),
        .probe944(1'b0),
        .probe945(1'b0),
        .probe946(1'b0),
        .probe947(1'b0),
        .probe948(1'b0),
        .probe949(1'b0),
        .probe95(1'b0),
        .probe950(1'b0),
        .probe951(1'b0),
        .probe952(1'b0),
        .probe953(1'b0),
        .probe954(1'b0),
        .probe955(1'b0),
        .probe956(1'b0),
        .probe957(1'b0),
        .probe958(1'b0),
        .probe959(1'b0),
        .probe96(1'b0),
        .probe960(1'b0),
        .probe961(1'b0),
        .probe962(1'b0),
        .probe963(1'b0),
        .probe964(1'b0),
        .probe965(1'b0),
        .probe966(1'b0),
        .probe967(1'b0),
        .probe968(1'b0),
        .probe969(1'b0),
        .probe97(1'b0),
        .probe970(1'b0),
        .probe971(1'b0),
        .probe972(1'b0),
        .probe973(1'b0),
        .probe974(1'b0),
        .probe975(1'b0),
        .probe976(1'b0),
        .probe977(1'b0),
        .probe978(1'b0),
        .probe979(1'b0),
        .probe98(1'b0),
        .probe980(1'b0),
        .probe981(1'b0),
        .probe982(1'b0),
        .probe983(1'b0),
        .probe984(1'b0),
        .probe985(1'b0),
        .probe986(1'b0),
        .probe987(1'b0),
        .probe988(1'b0),
        .probe989(1'b0),
        .probe99(1'b0),
        .probe990(1'b0),
        .probe991(1'b0),
        .probe992(1'b0),
        .probe993(1'b0),
        .probe994(1'b0),
        .probe995(1'b0),
        .probe996(1'b0),
        .probe997(1'b0),
        .probe998(1'b0),
        .probe999(1'b0),
        .sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .sl_oport0(NLW_U0_sl_oport0_UNCONNECTED[16:0]),
        .trig_in(1'b0),
        .trig_in_ack(NLW_U0_trig_in_ack_UNCONNECTED),
        .trig_out(NLW_U0_trig_out_UNCONNECTED),
        .trig_out_ack(1'b0));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) 
module ila_0_blk_mem_gen_generic_cstr
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [140:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [140:0]DINA;

  wire [0:0]D;
  wire [140:0]DINA;
  wire [140:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_prim_width \ramloop[0].ram.r 
       (.D(D),
        .DINA(DINA[35:0]),
        .DOUTB(DOUTB[35:0]),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
ila_0_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r 
       (.D(D),
        .DINA(DINA[71:36]),
        .DOUTB(DOUTB[71:36]),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
ila_0_blk_mem_gen_prim_width__parameterized1 \ramloop[2].ram.r 
       (.D(D),
        .DINA(DINA[107:72]),
        .DOUTB(DOUTB[107:72]),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
ila_0_blk_mem_gen_prim_width__parameterized2 \ramloop[3].ram.r 
       (.D(D),
        .DINA(DINA[140:108]),
        .DOUTB(DOUTB[140:108]),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
module ila_0_blk_mem_gen_prim_width
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [35:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [35:0]DINA;

  wire [0:0]D;
  wire [35:0]DINA;
  wire [35:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_prim_wrapper \prim_noinit.ram 
       (.D(D),
        .DINA(DINA),
        .DOUTB(DOUTB),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
module ila_0_blk_mem_gen_prim_width__parameterized0
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [35:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [35:0]DINA;

  wire [0:0]D;
  wire [35:0]DINA;
  wire [35:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram 
       (.D(D),
        .DINA(DINA),
        .DOUTB(DOUTB),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
module ila_0_blk_mem_gen_prim_width__parameterized1
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [35:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [35:0]DINA;

  wire [0:0]D;
  wire [35:0]DINA;
  wire [35:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_prim_wrapper__parameterized1 \prim_noinit.ram 
       (.D(D),
        .DINA(DINA),
        .DOUTB(DOUTB),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
module ila_0_blk_mem_gen_prim_width__parameterized2
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [32:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [32:0]DINA;

  wire [0:0]D;
  wire [32:0]DINA;
  wire [32:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_prim_wrapper__parameterized2 \prim_noinit.ram 
       (.D(D),
        .DINA(DINA),
        .DOUTB(DOUTB),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) 
module ila_0_blk_mem_gen_prim_wrapper
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [35:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [35:0]DINA;

  wire [0:0]D;
  wire [35:0]DINA;
  wire [35:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
  wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
  wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
  wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;

(* BOX_TYPE = "PRIMITIVE" *) 
   RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(36),
    .RSTREG_PRIORITY_A("REGCE"),
    .RSTREG_PRIORITY_B("REGCE"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(36),
    .WRITE_WIDTH_B(36)) 
     \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram 
       (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,I1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(clk),
        .CLKBWRCLK(S_DCLK_O),
        .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
        .DIADI({DINA[34:27],DINA[25:18],DINA[16:9],DINA[7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({DINA[35],DINA[26],DINA[17],DINA[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
        .DOBDO({DOUTB[34:27],DOUTB[25:18],DOUTB[16:9],DOUTB[7:0]}),
        .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
        .DOPBDOP({DOUTB[35],DOUTB[26],DOUTB[17],DOUTB[8]}),
        .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(cap_wr_en),
        .ENBWREN(D),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(D),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) 
module ila_0_blk_mem_gen_prim_wrapper__parameterized0
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [35:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [35:0]DINA;

  wire [0:0]D;
  wire [35:0]DINA;
  wire [35:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
  wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
  wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
  wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;

(* BOX_TYPE = "PRIMITIVE" *) 
   RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(36),
    .RSTREG_PRIORITY_A("REGCE"),
    .RSTREG_PRIORITY_B("REGCE"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(36),
    .WRITE_WIDTH_B(36)) 
     \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram 
       (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,I1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(clk),
        .CLKBWRCLK(S_DCLK_O),
        .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
        .DIADI({DINA[34:27],DINA[25:18],DINA[16:9],DINA[7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({DINA[35],DINA[26],DINA[17],DINA[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
        .DOBDO({DOUTB[34:27],DOUTB[25:18],DOUTB[16:9],DOUTB[7:0]}),
        .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
        .DOPBDOP({DOUTB[35],DOUTB[26],DOUTB[17],DOUTB[8]}),
        .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(cap_wr_en),
        .ENBWREN(D),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(D),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) 
module ila_0_blk_mem_gen_prim_wrapper__parameterized1
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [35:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [35:0]DINA;

  wire [0:0]D;
  wire [35:0]DINA;
  wire [35:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
  wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
  wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
  wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;

(* BOX_TYPE = "PRIMITIVE" *) 
   RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(36),
    .RSTREG_PRIORITY_A("REGCE"),
    .RSTREG_PRIORITY_B("REGCE"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(36),
    .WRITE_WIDTH_B(36)) 
     \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram 
       (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,I1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(clk),
        .CLKBWRCLK(S_DCLK_O),
        .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
        .DIADI({DINA[34:27],DINA[25:18],DINA[16:9],DINA[7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({DINA[35],DINA[26],DINA[17],DINA[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
        .DOBDO({DOUTB[34:27],DOUTB[25:18],DOUTB[16:9],DOUTB[7:0]}),
        .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
        .DOPBDOP({DOUTB[35],DOUTB[26],DOUTB[17],DOUTB[8]}),
        .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(cap_wr_en),
        .ENBWREN(D),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(D),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *) 
module ila_0_blk_mem_gen_prim_wrapper__parameterized2
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [32:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [32:0]DINA;

  wire [0:0]D;
  wire [32:0]DINA;
  wire [32:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;
  wire \n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
  wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
  wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
  wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
  wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
  wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;

(* BOX_TYPE = "PRIMITIVE" *) 
   RAMB36E1 #(
    .DOA_REG(1),
    .DOB_REG(1),
    .EN_ECC_READ("FALSE"),
    .EN_ECC_WRITE("FALSE"),
    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_A(36'h000000000),
    .INIT_B(36'h000000000),
    .INIT_FILE("NONE"),
    .IS_CLKARDCLK_INVERTED(1'b0),
    .IS_CLKBWRCLK_INVERTED(1'b0),
    .IS_ENARDEN_INVERTED(1'b0),
    .IS_ENBWREN_INVERTED(1'b0),
    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
    .IS_RSTRAMB_INVERTED(1'b0),
    .IS_RSTREGARSTREG_INVERTED(1'b0),
    .IS_RSTREGB_INVERTED(1'b0),
    .RAM_EXTENSION_A("NONE"),
    .RAM_EXTENSION_B("NONE"),
    .RAM_MODE("TDP"),
    .RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
    .READ_WIDTH_A(36),
    .READ_WIDTH_B(36),
    .RSTREG_PRIORITY_A("REGCE"),
    .RSTREG_PRIORITY_B("REGCE"),
    .SIM_COLLISION_CHECK("ALL"),
    .SIM_DEVICE("7SERIES"),
    .SRVAL_A(36'h000000000),
    .SRVAL_B(36'h000000000),
    .WRITE_MODE_A("READ_FIRST"),
    .WRITE_MODE_B("READ_FIRST"),
    .WRITE_WIDTH_A(36),
    .WRITE_WIDTH_B(36)) 
     \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram 
       (.ADDRARDADDR({1'b1,Q,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .ADDRBWRADDR({1'b1,I1,1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CASCADEINA(1'b0),
        .CASCADEINB(1'b0),
        .CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
        .CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
        .CLKARDCLK(clk),
        .CLKBWRCLK(S_DCLK_O),
        .DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
        .DIADI({DINA[32:9],DINA[7:0]}),
        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DIPADIP({1'b0,1'b0,1'b0,DINA[8]}),
        .DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
        .DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
        .DOBDO({DOUTB[32:9],DOUTB[7:0]}),
        .DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
        .DOPBDOP({\n_72_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,\n_73_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,\n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,DOUTB[8]}),
        .ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
        .ENARDEN(cap_wr_en),
        .ENBWREN(D),
        .INJECTDBITERR(1'b0),
        .INJECTSBITERR(1'b0),
        .RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
        .REGCEAREGCE(1'b0),
        .REGCEB(D),
        .RSTRAMARSTRAM(1'b0),
        .RSTRAMB(1'b0),
        .RSTREGARSTREG(1'b0),
        .RSTREGB(1'b0),
        .SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
        .WEA({1'b1,1'b1,1'b1,1'b1}),
        .WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_top" *) 
module ila_0_blk_mem_gen_top
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [140:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [140:0]DINA;

  wire [0:0]D;
  wire [140:0]DINA;
  wire [140:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_generic_cstr \valid.cstr 
       (.D(D),
        .DINA(DINA),
        .DOUTB(DOUTB),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) 
module ila_0_blk_mem_gen_v8_2
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [140:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [140:0]DINA;

  wire [0:0]D;
  wire [140:0]DINA;
  wire [140:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_v8_2_synth inst_blk_mem_gen
       (.D(D),
        .DINA(DINA),
        .DOUTB(DOUTB),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *) 
module ila_0_blk_mem_gen_v8_2_synth
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [140:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [140:0]DINA;

  wire [0:0]D;
  wire [140:0]DINA;
  wire [140:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_top \gnativebmg.native_blk_mem_gen 
       (.D(D),
        .DINA(DINA),
        .DOUTB(DOUTB),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* DONT_TOUCH = "true" *) (* C_COUNTER_WIDTH = "17" *) (* CNT_MAX = "17'b10000000000000000" *) 
(* ORIG_REF_NAME = "ila_v5_0_generic_counter" *) 
module ila_0_ila_v5_0_generic_counter
   (CLK,
    CFG_CLK,
    RESET,
    SCNT_RESET,
    CNT_CTRL,
    CNT_LOAD_IN,
    CNT_LOAD_EN,
    CNT_LOAD_DOUT,
    COUNTER_MATCH);
  input CLK;
  input CFG_CLK;
  input [1:0]RESET;
  input SCNT_RESET;
  input [1:0]CNT_CTRL;
  input CNT_LOAD_IN;
  input CNT_LOAD_EN;
  output CNT_LOAD_DOUT;
  output COUNTER_MATCH;

  wire CFG_CLK;
  wire CLK;
  wire [1:0]CNT_CTRL;
  wire CNT_LOAD_DOUT;
  wire CNT_LOAD_EN;
  wire CNT_LOAD_IN;
  wire COUNTER_MATCH;
  wire [1:0]RESET;
  wire SCNT_RESET;
  wire [19:0]counter;
  wire [19:0]counter0;
  wire \n_0_counter[0]_i_1 ;
  wire \n_0_counter[10]_i_1 ;
  wire \n_0_counter[11]_i_1 ;
  wire \n_0_counter[11]_i_3 ;
  wire \n_0_counter[11]_i_4 ;
  wire \n_0_counter[11]_i_5 ;
  wire \n_0_counter[11]_i_6 ;
  wire \n_0_counter[12]_i_1 ;
  wire \n_0_counter[13]_i_1 ;
  wire \n_0_counter[14]_i_1 ;
  wire \n_0_counter[15]_i_1 ;
  wire \n_0_counter[15]_i_3 ;
  wire \n_0_counter[15]_i_4 ;
  wire \n_0_counter[15]_i_5 ;
  wire \n_0_counter[15]_i_6 ;
  wire \n_0_counter[16]_i_1 ;
  wire \n_0_counter[16]_i_2 ;
  wire \n_0_counter[16]_i_4 ;
  wire \n_0_counter[16]_i_5 ;
  wire \n_0_counter[16]_i_6 ;
  wire \n_0_counter[16]_i_7 ;
  wire \n_0_counter[16]_i_8 ;
  wire \n_0_counter[17]_i_1 ;
  wire \n_0_counter[18]_i_1 ;
  wire \n_0_counter[19]_i_1 ;
  wire \n_0_counter[1]_i_1 ;
  wire \n_0_counter[2]_i_1 ;
  wire \n_0_counter[3]_i_1 ;
  wire \n_0_counter[3]_i_3 ;
  wire \n_0_counter[3]_i_4 ;
  wire \n_0_counter[3]_i_5 ;
  wire \n_0_counter[3]_i_6 ;
  wire \n_0_counter[4]_i_1 ;
  wire \n_0_counter[5]_i_1 ;
  wire \n_0_counter[6]_i_1 ;
  wire \n_0_counter[7]_i_1 ;
  wire \n_0_counter[7]_i_3 ;
  wire \n_0_counter[7]_i_4 ;
  wire \n_0_counter[7]_i_5 ;
  wire \n_0_counter[7]_i_6 ;
  wire \n_0_counter[8]_i_1 ;
  wire \n_0_counter[9]_i_1 ;
  wire \n_0_counter_load_i_reg[20]_srl12 ;
  wire \n_0_counter_reg[11]_i_2 ;
  wire \n_0_counter_reg[15]_i_2 ;
  wire \n_0_counter_reg[16]_i_3 ;
  wire \n_0_counter_reg[3]_i_2 ;
  wire \n_0_counter_reg[7]_i_2 ;
  wire \n_1_counter_reg[11]_i_2 ;
  wire \n_1_counter_reg[15]_i_2 ;
  wire \n_1_counter_reg[16]_i_3 ;
  wire \n_1_counter_reg[3]_i_2 ;
  wire \n_1_counter_reg[7]_i_2 ;
  wire \n_2_counter_reg[11]_i_2 ;
  wire \n_2_counter_reg[15]_i_2 ;
  wire \n_2_counter_reg[16]_i_3 ;
  wire \n_2_counter_reg[3]_i_2 ;
  wire \n_2_counter_reg[7]_i_2 ;
  wire \n_3_counter_reg[11]_i_2 ;
  wire \n_3_counter_reg[15]_i_2 ;
  wire \n_3_counter_reg[16]_i_3 ;
  wire \n_3_counter_reg[3]_i_2 ;
  wire \n_3_counter_reg[7]_i_2 ;
  wire [18:0]p_1_in;

LUT4 #(
    .INIT(16'hBBB8)) 
     \counter[0]_i_1 
       (.I0(CNT_LOAD_DOUT),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(COUNTER_MATCH),
        .I3(counter0[0]),
        .O(\n_0_counter[0]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[10]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[10]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[9]),
        .O(\n_0_counter[10]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[11]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[11]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[10]),
        .O(\n_0_counter[11]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_3 
       (.I0(counter[11]),
        .O(\n_0_counter[11]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_4 
       (.I0(counter[10]),
        .O(\n_0_counter[11]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_5 
       (.I0(counter[9]),
        .O(\n_0_counter[11]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_6 
       (.I0(counter[8]),
        .O(\n_0_counter[11]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[12]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[12]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[11]),
        .O(\n_0_counter[12]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[13]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[13]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[12]),
        .O(\n_0_counter[13]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[14]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[14]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[13]),
        .O(\n_0_counter[14]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[15]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[15]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[14]),
        .O(\n_0_counter[15]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_3 
       (.I0(counter[15]),
        .O(\n_0_counter[15]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_4 
       (.I0(counter[14]),
        .O(\n_0_counter[15]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_5 
       (.I0(counter[13]),
        .O(\n_0_counter[15]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_6 
       (.I0(counter[12]),
        .O(\n_0_counter[15]_i_6 ));
LUT5 #(
    .INIT(32'hFEFEFFFE)) 
     \counter[16]_i_1 
       (.I0(CNT_CTRL[1]),
        .I1(SCNT_RESET),
        .I2(CNT_CTRL[0]),
        .I3(RESET[1]),
        .I4(RESET[0]),
        .O(\n_0_counter[16]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[16]_i_2 
       (.I0(COUNTER_MATCH),
        .I1(counter0[16]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[15]),
        .O(\n_0_counter[16]_i_2 ));
LUT4 #(
    .INIT(16'hFFF4)) 
     \counter[16]_i_4 
       (.I0(RESET[0]),
        .I1(RESET[1]),
        .I2(CNT_CTRL[0]),
        .I3(SCNT_RESET),
        .O(\n_0_counter[16]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_5 
       (.I0(counter[19]),
        .O(\n_0_counter[16]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_6 
       (.I0(counter[18]),
        .O(\n_0_counter[16]_i_6 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_7 
       (.I0(counter[17]),
        .O(\n_0_counter[16]_i_7 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_8 
       (.I0(COUNTER_MATCH),
        .O(\n_0_counter[16]_i_8 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[17]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[17]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[16]),
        .O(\n_0_counter[17]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[18]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[18]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[17]),
        .O(\n_0_counter[18]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[19]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[19]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[18]),
        .O(\n_0_counter[19]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[1]_i_1 
       (.I0(p_1_in[0]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[1]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[1]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[2]_i_1 
       (.I0(p_1_in[1]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[2]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[2]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[3]_i_1 
       (.I0(p_1_in[2]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[3]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[3]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_3 
       (.I0(counter[3]),
        .O(\n_0_counter[3]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_4 
       (.I0(counter[2]),
        .O(\n_0_counter[3]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_5 
       (.I0(counter[1]),
        .O(\n_0_counter[3]_i_5 ));
LUT1 #(
    .INIT(2'h1)) 
     \counter[3]_i_6 
       (.I0(counter[0]),
        .O(\n_0_counter[3]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[4]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[4]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[3]),
        .O(\n_0_counter[4]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[5]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[5]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[4]),
        .O(\n_0_counter[5]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[6]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[6]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[5]),
        .O(\n_0_counter[6]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[7]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[7]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[6]),
        .O(\n_0_counter[7]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_3 
       (.I0(counter[7]),
        .O(\n_0_counter[7]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_4 
       (.I0(counter[6]),
        .O(\n_0_counter[7]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_5 
       (.I0(counter[5]),
        .O(\n_0_counter[7]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_6 
       (.I0(counter[4]),
        .O(\n_0_counter[7]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[8]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[8]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[7]),
        .O(\n_0_counter[8]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[9]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[9]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[8]),
        .O(\n_0_counter[9]_i_1 ));
FDRE \counter_load_i_reg[0] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[0]),
        .Q(CNT_LOAD_DOUT),
        .R(1'b0));
FDRE \counter_load_i_reg[10] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[10]),
        .Q(p_1_in[9]),
        .R(1'b0));
FDRE \counter_load_i_reg[11] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[11]),
        .Q(p_1_in[10]),
        .R(1'b0));
FDRE \counter_load_i_reg[12] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[12]),
        .Q(p_1_in[11]),
        .R(1'b0));
FDRE \counter_load_i_reg[13] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[13]),
        .Q(p_1_in[12]),
        .R(1'b0));
FDRE \counter_load_i_reg[14] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[14]),
        .Q(p_1_in[13]),
        .R(1'b0));
FDRE \counter_load_i_reg[15] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[15]),
        .Q(p_1_in[14]),
        .R(1'b0));
FDRE \counter_load_i_reg[16] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[16]),
        .Q(p_1_in[15]),
        .R(1'b0));
FDRE \counter_load_i_reg[17] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[17]),
        .Q(p_1_in[16]),
        .R(1'b0));
FDRE \counter_load_i_reg[18] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[18]),
        .Q(p_1_in[17]),
        .R(1'b0));
FDRE \counter_load_i_reg[19] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(\n_0_counter_load_i_reg[20]_srl12 ),
        .Q(p_1_in[18]),
        .R(1'b0));
FDRE \counter_load_i_reg[1] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[1]),
        .Q(p_1_in[0]),
        .R(1'b0));
(* srl_bus_name = "U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER /\counter_load_i_reg " *) 
   (* srl_name = "U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER /\counter_load_i_reg[20]_srl12 " *) 
   SRL16E \counter_load_i_reg[20]_srl12 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(CNT_LOAD_EN),
        .CLK(CFG_CLK),
        .D(CNT_LOAD_IN),
        .Q(\n_0_counter_load_i_reg[20]_srl12 ));
FDRE \counter_load_i_reg[2] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[2]),
        .Q(p_1_in[1]),
        .R(1'b0));
FDRE \counter_load_i_reg[3] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[3]),
        .Q(p_1_in[2]),
        .R(1'b0));
FDRE \counter_load_i_reg[4] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[4]),
        .Q(p_1_in[3]),
        .R(1'b0));
FDRE \counter_load_i_reg[5] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[5]),
        .Q(p_1_in[4]),
        .R(1'b0));
FDRE \counter_load_i_reg[6] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[6]),
        .Q(p_1_in[5]),
        .R(1'b0));
FDRE \counter_load_i_reg[7] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[7]),
        .Q(p_1_in[6]),
        .R(1'b0));
FDRE \counter_load_i_reg[8] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[8]),
        .Q(p_1_in[7]),
        .R(1'b0));
FDRE \counter_load_i_reg[9] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[9]),
        .Q(p_1_in[8]),
        .R(1'b0));
FDRE \counter_reg[0] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[0]_i_1 ),
        .Q(counter[0]),
        .R(1'b0));
FDRE \counter_reg[10] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[10]_i_1 ),
        .Q(counter[10]),
        .R(1'b0));
FDRE \counter_reg[11] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[11]_i_1 ),
        .Q(counter[11]),
        .R(1'b0));
CARRY4 \counter_reg[11]_i_2 
       (.CI(\n_0_counter_reg[7]_i_2 ),
        .CO({\n_0_counter_reg[11]_i_2 ,\n_1_counter_reg[11]_i_2 ,\n_2_counter_reg[11]_i_2 ,\n_3_counter_reg[11]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[11:8]),
        .S({\n_0_counter[11]_i_3 ,\n_0_counter[11]_i_4 ,\n_0_counter[11]_i_5 ,\n_0_counter[11]_i_6 }));
FDRE \counter_reg[12] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[12]_i_1 ),
        .Q(counter[12]),
        .R(1'b0));
FDRE \counter_reg[13] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[13]_i_1 ),
        .Q(counter[13]),
        .R(1'b0));
FDRE \counter_reg[14] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[14]_i_1 ),
        .Q(counter[14]),
        .R(1'b0));
FDRE \counter_reg[15] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[15]_i_1 ),
        .Q(counter[15]),
        .R(1'b0));
CARRY4 \counter_reg[15]_i_2 
       (.CI(\n_0_counter_reg[11]_i_2 ),
        .CO({\n_0_counter_reg[15]_i_2 ,\n_1_counter_reg[15]_i_2 ,\n_2_counter_reg[15]_i_2 ,\n_3_counter_reg[15]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[15:12]),
        .S({\n_0_counter[15]_i_3 ,\n_0_counter[15]_i_4 ,\n_0_counter[15]_i_5 ,\n_0_counter[15]_i_6 }));
FDRE \counter_reg[16] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[16]_i_2 ),
        .Q(COUNTER_MATCH),
        .R(1'b0));
CARRY4 \counter_reg[16]_i_3 
       (.CI(\n_0_counter_reg[15]_i_2 ),
        .CO({\n_0_counter_reg[16]_i_3 ,\n_1_counter_reg[16]_i_3 ,\n_2_counter_reg[16]_i_3 ,\n_3_counter_reg[16]_i_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[19:16]),
        .S({\n_0_counter[16]_i_5 ,\n_0_counter[16]_i_6 ,\n_0_counter[16]_i_7 ,\n_0_counter[16]_i_8 }));
FDRE \counter_reg[17] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[17]_i_1 ),
        .Q(counter[17]),
        .R(1'b0));
FDRE \counter_reg[18] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[18]_i_1 ),
        .Q(counter[18]),
        .R(1'b0));
FDRE \counter_reg[19] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[19]_i_1 ),
        .Q(counter[19]),
        .R(1'b0));
FDRE \counter_reg[1] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[1]_i_1 ),
        .Q(counter[1]),
        .R(1'b0));
FDRE \counter_reg[2] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[2]_i_1 ),
        .Q(counter[2]),
        .R(1'b0));
FDRE \counter_reg[3] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[3]_i_1 ),
        .Q(counter[3]),
        .R(1'b0));
CARRY4 \counter_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\n_0_counter_reg[3]_i_2 ,\n_1_counter_reg[3]_i_2 ,\n_2_counter_reg[3]_i_2 ,\n_3_counter_reg[3]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,counter[0]}),
        .O(counter0[3:0]),
        .S({\n_0_counter[3]_i_3 ,\n_0_counter[3]_i_4 ,\n_0_counter[3]_i_5 ,\n_0_counter[3]_i_6 }));
FDRE \counter_reg[4] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[4]_i_1 ),
        .Q(counter[4]),
        .R(1'b0));
FDRE \counter_reg[5] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[5]_i_1 ),
        .Q(counter[5]),
        .R(1'b0));
FDRE \counter_reg[6] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[6]_i_1 ),
        .Q(counter[6]),
        .R(1'b0));
FDRE \counter_reg[7] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[7]_i_1 ),
        .Q(counter[7]),
        .R(1'b0));
CARRY4 \counter_reg[7]_i_2 
       (.CI(\n_0_counter_reg[3]_i_2 ),
        .CO({\n_0_counter_reg[7]_i_2 ,\n_1_counter_reg[7]_i_2 ,\n_2_counter_reg[7]_i_2 ,\n_3_counter_reg[7]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[7:4]),
        .S({\n_0_counter[7]_i_3 ,\n_0_counter[7]_i_4 ,\n_0_counter[7]_i_5 ,\n_0_counter[7]_i_6 }));
FDRE \counter_reg[8] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[8]_i_1 ),
        .Q(counter[8]),
        .R(1'b0));
FDRE \counter_reg[9] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[9]_i_1 ),
        .Q(counter[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_generic_counter" *) (* DONT_TOUCH = "true" *) (* C_COUNTER_WIDTH = "17" *) 
(* CNT_MAX = "17'b10000000000000000" *) 
module ila_0_ila_v5_0_generic_counter__4
   (CLK,
    CFG_CLK,
    RESET,
    SCNT_RESET,
    CNT_CTRL,
    CNT_LOAD_IN,
    CNT_LOAD_EN,
    CNT_LOAD_DOUT,
    COUNTER_MATCH);
  input CLK;
  input CFG_CLK;
  input [1:0]RESET;
  input SCNT_RESET;
  input [1:0]CNT_CTRL;
  input CNT_LOAD_IN;
  input CNT_LOAD_EN;
  output CNT_LOAD_DOUT;
  output COUNTER_MATCH;

  wire CFG_CLK;
  wire CLK;
  wire [1:0]CNT_CTRL;
  wire CNT_LOAD_DOUT;
  wire CNT_LOAD_EN;
  wire CNT_LOAD_IN;
  wire COUNTER_MATCH;
  wire [1:0]RESET;
  wire SCNT_RESET;
  wire [19:0]counter;
  wire [19:0]counter0;
  wire \n_0_counter[0]_i_1 ;
  wire \n_0_counter[10]_i_1 ;
  wire \n_0_counter[11]_i_1 ;
  wire \n_0_counter[11]_i_3 ;
  wire \n_0_counter[11]_i_4 ;
  wire \n_0_counter[11]_i_5 ;
  wire \n_0_counter[11]_i_6 ;
  wire \n_0_counter[12]_i_1 ;
  wire \n_0_counter[13]_i_1 ;
  wire \n_0_counter[14]_i_1 ;
  wire \n_0_counter[15]_i_1 ;
  wire \n_0_counter[15]_i_3 ;
  wire \n_0_counter[15]_i_4 ;
  wire \n_0_counter[15]_i_5 ;
  wire \n_0_counter[15]_i_6 ;
  wire \n_0_counter[16]_i_1 ;
  wire \n_0_counter[16]_i_2 ;
  wire \n_0_counter[16]_i_4 ;
  wire \n_0_counter[16]_i_5 ;
  wire \n_0_counter[16]_i_6 ;
  wire \n_0_counter[16]_i_7 ;
  wire \n_0_counter[16]_i_8 ;
  wire \n_0_counter[17]_i_1 ;
  wire \n_0_counter[18]_i_1 ;
  wire \n_0_counter[19]_i_1 ;
  wire \n_0_counter[1]_i_1 ;
  wire \n_0_counter[2]_i_1 ;
  wire \n_0_counter[3]_i_1 ;
  wire \n_0_counter[3]_i_3 ;
  wire \n_0_counter[3]_i_4 ;
  wire \n_0_counter[3]_i_5 ;
  wire \n_0_counter[3]_i_6 ;
  wire \n_0_counter[4]_i_1 ;
  wire \n_0_counter[5]_i_1 ;
  wire \n_0_counter[6]_i_1 ;
  wire \n_0_counter[7]_i_1 ;
  wire \n_0_counter[7]_i_3 ;
  wire \n_0_counter[7]_i_4 ;
  wire \n_0_counter[7]_i_5 ;
  wire \n_0_counter[7]_i_6 ;
  wire \n_0_counter[8]_i_1 ;
  wire \n_0_counter[9]_i_1 ;
  wire \n_0_counter_load_i_reg[20]_srl12 ;
  wire \n_0_counter_reg[11]_i_2 ;
  wire \n_0_counter_reg[15]_i_2 ;
  wire \n_0_counter_reg[16]_i_3 ;
  wire \n_0_counter_reg[3]_i_2 ;
  wire \n_0_counter_reg[7]_i_2 ;
  wire \n_1_counter_reg[11]_i_2 ;
  wire \n_1_counter_reg[15]_i_2 ;
  wire \n_1_counter_reg[16]_i_3 ;
  wire \n_1_counter_reg[3]_i_2 ;
  wire \n_1_counter_reg[7]_i_2 ;
  wire \n_2_counter_reg[11]_i_2 ;
  wire \n_2_counter_reg[15]_i_2 ;
  wire \n_2_counter_reg[16]_i_3 ;
  wire \n_2_counter_reg[3]_i_2 ;
  wire \n_2_counter_reg[7]_i_2 ;
  wire \n_3_counter_reg[11]_i_2 ;
  wire \n_3_counter_reg[15]_i_2 ;
  wire \n_3_counter_reg[16]_i_3 ;
  wire \n_3_counter_reg[3]_i_2 ;
  wire \n_3_counter_reg[7]_i_2 ;
  wire [18:0]p_1_in;

LUT4 #(
    .INIT(16'hBBB8)) 
     \counter[0]_i_1 
       (.I0(CNT_LOAD_DOUT),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(COUNTER_MATCH),
        .I3(counter0[0]),
        .O(\n_0_counter[0]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[10]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[10]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[9]),
        .O(\n_0_counter[10]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[11]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[11]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[10]),
        .O(\n_0_counter[11]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_3 
       (.I0(counter[11]),
        .O(\n_0_counter[11]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_4 
       (.I0(counter[10]),
        .O(\n_0_counter[11]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_5 
       (.I0(counter[9]),
        .O(\n_0_counter[11]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_6 
       (.I0(counter[8]),
        .O(\n_0_counter[11]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[12]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[12]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[11]),
        .O(\n_0_counter[12]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[13]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[13]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[12]),
        .O(\n_0_counter[13]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[14]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[14]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[13]),
        .O(\n_0_counter[14]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[15]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[15]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[14]),
        .O(\n_0_counter[15]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_3 
       (.I0(counter[15]),
        .O(\n_0_counter[15]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_4 
       (.I0(counter[14]),
        .O(\n_0_counter[15]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_5 
       (.I0(counter[13]),
        .O(\n_0_counter[15]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_6 
       (.I0(counter[12]),
        .O(\n_0_counter[15]_i_6 ));
LUT5 #(
    .INIT(32'hFEFEFFFE)) 
     \counter[16]_i_1 
       (.I0(CNT_CTRL[1]),
        .I1(SCNT_RESET),
        .I2(CNT_CTRL[0]),
        .I3(RESET[1]),
        .I4(RESET[0]),
        .O(\n_0_counter[16]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[16]_i_2 
       (.I0(COUNTER_MATCH),
        .I1(counter0[16]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[15]),
        .O(\n_0_counter[16]_i_2 ));
LUT4 #(
    .INIT(16'hFFF4)) 
     \counter[16]_i_4 
       (.I0(RESET[0]),
        .I1(RESET[1]),
        .I2(CNT_CTRL[0]),
        .I3(SCNT_RESET),
        .O(\n_0_counter[16]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_5 
       (.I0(counter[19]),
        .O(\n_0_counter[16]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_6 
       (.I0(counter[18]),
        .O(\n_0_counter[16]_i_6 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_7 
       (.I0(counter[17]),
        .O(\n_0_counter[16]_i_7 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_8 
       (.I0(COUNTER_MATCH),
        .O(\n_0_counter[16]_i_8 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[17]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[17]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[16]),
        .O(\n_0_counter[17]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[18]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[18]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[17]),
        .O(\n_0_counter[18]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[19]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[19]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[18]),
        .O(\n_0_counter[19]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[1]_i_1 
       (.I0(p_1_in[0]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[1]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[1]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[2]_i_1 
       (.I0(p_1_in[1]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[2]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[2]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[3]_i_1 
       (.I0(p_1_in[2]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[3]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[3]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_3 
       (.I0(counter[3]),
        .O(\n_0_counter[3]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_4 
       (.I0(counter[2]),
        .O(\n_0_counter[3]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_5 
       (.I0(counter[1]),
        .O(\n_0_counter[3]_i_5 ));
LUT1 #(
    .INIT(2'h1)) 
     \counter[3]_i_6 
       (.I0(counter[0]),
        .O(\n_0_counter[3]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[4]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[4]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[3]),
        .O(\n_0_counter[4]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[5]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[5]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[4]),
        .O(\n_0_counter[5]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[6]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[6]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[5]),
        .O(\n_0_counter[6]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[7]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[7]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[6]),
        .O(\n_0_counter[7]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_3 
       (.I0(counter[7]),
        .O(\n_0_counter[7]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_4 
       (.I0(counter[6]),
        .O(\n_0_counter[7]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_5 
       (.I0(counter[5]),
        .O(\n_0_counter[7]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_6 
       (.I0(counter[4]),
        .O(\n_0_counter[7]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[8]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[8]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[7]),
        .O(\n_0_counter[8]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[9]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[9]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[8]),
        .O(\n_0_counter[9]_i_1 ));
FDRE \counter_load_i_reg[0] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[0]),
        .Q(CNT_LOAD_DOUT),
        .R(1'b0));
FDRE \counter_load_i_reg[10] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[10]),
        .Q(p_1_in[9]),
        .R(1'b0));
FDRE \counter_load_i_reg[11] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[11]),
        .Q(p_1_in[10]),
        .R(1'b0));
FDRE \counter_load_i_reg[12] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[12]),
        .Q(p_1_in[11]),
        .R(1'b0));
FDRE \counter_load_i_reg[13] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[13]),
        .Q(p_1_in[12]),
        .R(1'b0));
FDRE \counter_load_i_reg[14] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[14]),
        .Q(p_1_in[13]),
        .R(1'b0));
FDRE \counter_load_i_reg[15] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[15]),
        .Q(p_1_in[14]),
        .R(1'b0));
FDRE \counter_load_i_reg[16] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[16]),
        .Q(p_1_in[15]),
        .R(1'b0));
FDRE \counter_load_i_reg[17] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[17]),
        .Q(p_1_in[16]),
        .R(1'b0));
FDRE \counter_load_i_reg[18] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[18]),
        .Q(p_1_in[17]),
        .R(1'b0));
FDRE \counter_load_i_reg[19] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(\n_0_counter_load_i_reg[20]_srl12 ),
        .Q(p_1_in[18]),
        .R(1'b0));
FDRE \counter_load_i_reg[1] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[1]),
        .Q(p_1_in[0]),
        .R(1'b0));
(* srl_bus_name = "U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER /\counter_load_i_reg " *) 
   (* srl_name = "U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER /\counter_load_i_reg[20]_srl12 " *) 
   SRL16E \counter_load_i_reg[20]_srl12 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(CNT_LOAD_EN),
        .CLK(CFG_CLK),
        .D(CNT_LOAD_IN),
        .Q(\n_0_counter_load_i_reg[20]_srl12 ));
FDRE \counter_load_i_reg[2] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[2]),
        .Q(p_1_in[1]),
        .R(1'b0));
FDRE \counter_load_i_reg[3] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[3]),
        .Q(p_1_in[2]),
        .R(1'b0));
FDRE \counter_load_i_reg[4] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[4]),
        .Q(p_1_in[3]),
        .R(1'b0));
FDRE \counter_load_i_reg[5] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[5]),
        .Q(p_1_in[4]),
        .R(1'b0));
FDRE \counter_load_i_reg[6] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[6]),
        .Q(p_1_in[5]),
        .R(1'b0));
FDRE \counter_load_i_reg[7] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[7]),
        .Q(p_1_in[6]),
        .R(1'b0));
FDRE \counter_load_i_reg[8] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[8]),
        .Q(p_1_in[7]),
        .R(1'b0));
FDRE \counter_load_i_reg[9] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[9]),
        .Q(p_1_in[8]),
        .R(1'b0));
FDRE \counter_reg[0] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[0]_i_1 ),
        .Q(counter[0]),
        .R(1'b0));
FDRE \counter_reg[10] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[10]_i_1 ),
        .Q(counter[10]),
        .R(1'b0));
FDRE \counter_reg[11] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[11]_i_1 ),
        .Q(counter[11]),
        .R(1'b0));
CARRY4 \counter_reg[11]_i_2 
       (.CI(\n_0_counter_reg[7]_i_2 ),
        .CO({\n_0_counter_reg[11]_i_2 ,\n_1_counter_reg[11]_i_2 ,\n_2_counter_reg[11]_i_2 ,\n_3_counter_reg[11]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[11:8]),
        .S({\n_0_counter[11]_i_3 ,\n_0_counter[11]_i_4 ,\n_0_counter[11]_i_5 ,\n_0_counter[11]_i_6 }));
FDRE \counter_reg[12] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[12]_i_1 ),
        .Q(counter[12]),
        .R(1'b0));
FDRE \counter_reg[13] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[13]_i_1 ),
        .Q(counter[13]),
        .R(1'b0));
FDRE \counter_reg[14] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[14]_i_1 ),
        .Q(counter[14]),
        .R(1'b0));
FDRE \counter_reg[15] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[15]_i_1 ),
        .Q(counter[15]),
        .R(1'b0));
CARRY4 \counter_reg[15]_i_2 
       (.CI(\n_0_counter_reg[11]_i_2 ),
        .CO({\n_0_counter_reg[15]_i_2 ,\n_1_counter_reg[15]_i_2 ,\n_2_counter_reg[15]_i_2 ,\n_3_counter_reg[15]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[15:12]),
        .S({\n_0_counter[15]_i_3 ,\n_0_counter[15]_i_4 ,\n_0_counter[15]_i_5 ,\n_0_counter[15]_i_6 }));
FDRE \counter_reg[16] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[16]_i_2 ),
        .Q(COUNTER_MATCH),
        .R(1'b0));
CARRY4 \counter_reg[16]_i_3 
       (.CI(\n_0_counter_reg[15]_i_2 ),
        .CO({\n_0_counter_reg[16]_i_3 ,\n_1_counter_reg[16]_i_3 ,\n_2_counter_reg[16]_i_3 ,\n_3_counter_reg[16]_i_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[19:16]),
        .S({\n_0_counter[16]_i_5 ,\n_0_counter[16]_i_6 ,\n_0_counter[16]_i_7 ,\n_0_counter[16]_i_8 }));
FDRE \counter_reg[17] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[17]_i_1 ),
        .Q(counter[17]),
        .R(1'b0));
FDRE \counter_reg[18] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[18]_i_1 ),
        .Q(counter[18]),
        .R(1'b0));
FDRE \counter_reg[19] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[19]_i_1 ),
        .Q(counter[19]),
        .R(1'b0));
FDRE \counter_reg[1] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[1]_i_1 ),
        .Q(counter[1]),
        .R(1'b0));
FDRE \counter_reg[2] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[2]_i_1 ),
        .Q(counter[2]),
        .R(1'b0));
FDRE \counter_reg[3] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[3]_i_1 ),
        .Q(counter[3]),
        .R(1'b0));
CARRY4 \counter_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\n_0_counter_reg[3]_i_2 ,\n_1_counter_reg[3]_i_2 ,\n_2_counter_reg[3]_i_2 ,\n_3_counter_reg[3]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,counter[0]}),
        .O(counter0[3:0]),
        .S({\n_0_counter[3]_i_3 ,\n_0_counter[3]_i_4 ,\n_0_counter[3]_i_5 ,\n_0_counter[3]_i_6 }));
FDRE \counter_reg[4] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[4]_i_1 ),
        .Q(counter[4]),
        .R(1'b0));
FDRE \counter_reg[5] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[5]_i_1 ),
        .Q(counter[5]),
        .R(1'b0));
FDRE \counter_reg[6] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[6]_i_1 ),
        .Q(counter[6]),
        .R(1'b0));
FDRE \counter_reg[7] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[7]_i_1 ),
        .Q(counter[7]),
        .R(1'b0));
CARRY4 \counter_reg[7]_i_2 
       (.CI(\n_0_counter_reg[3]_i_2 ),
        .CO({\n_0_counter_reg[7]_i_2 ,\n_1_counter_reg[7]_i_2 ,\n_2_counter_reg[7]_i_2 ,\n_3_counter_reg[7]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[7:4]),
        .S({\n_0_counter[7]_i_3 ,\n_0_counter[7]_i_4 ,\n_0_counter[7]_i_5 ,\n_0_counter[7]_i_6 }));
FDRE \counter_reg[8] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[8]_i_1 ),
        .Q(counter[8]),
        .R(1'b0));
FDRE \counter_reg[9] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[9]_i_1 ),
        .Q(counter[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_generic_counter" *) (* DONT_TOUCH = "true" *) (* C_COUNTER_WIDTH = "17" *) 
(* CNT_MAX = "17'b10000000000000000" *) 
module ila_0_ila_v5_0_generic_counter__5
   (CLK,
    CFG_CLK,
    RESET,
    SCNT_RESET,
    CNT_CTRL,
    CNT_LOAD_IN,
    CNT_LOAD_EN,
    CNT_LOAD_DOUT,
    COUNTER_MATCH);
  input CLK;
  input CFG_CLK;
  input [1:0]RESET;
  input SCNT_RESET;
  input [1:0]CNT_CTRL;
  input CNT_LOAD_IN;
  input CNT_LOAD_EN;
  output CNT_LOAD_DOUT;
  output COUNTER_MATCH;

  wire CFG_CLK;
  wire CLK;
  wire [1:0]CNT_CTRL;
  wire CNT_LOAD_DOUT;
  wire CNT_LOAD_EN;
  wire CNT_LOAD_IN;
  wire COUNTER_MATCH;
  wire [1:0]RESET;
  wire SCNT_RESET;
  wire [19:0]counter;
  wire [19:0]counter0;
  wire \n_0_counter[0]_i_1 ;
  wire \n_0_counter[10]_i_1 ;
  wire \n_0_counter[11]_i_1 ;
  wire \n_0_counter[11]_i_3 ;
  wire \n_0_counter[11]_i_4 ;
  wire \n_0_counter[11]_i_5 ;
  wire \n_0_counter[11]_i_6 ;
  wire \n_0_counter[12]_i_1 ;
  wire \n_0_counter[13]_i_1 ;
  wire \n_0_counter[14]_i_1 ;
  wire \n_0_counter[15]_i_1 ;
  wire \n_0_counter[15]_i_3 ;
  wire \n_0_counter[15]_i_4 ;
  wire \n_0_counter[15]_i_5 ;
  wire \n_0_counter[15]_i_6 ;
  wire \n_0_counter[16]_i_1 ;
  wire \n_0_counter[16]_i_2 ;
  wire \n_0_counter[16]_i_4 ;
  wire \n_0_counter[16]_i_5 ;
  wire \n_0_counter[16]_i_6 ;
  wire \n_0_counter[16]_i_7 ;
  wire \n_0_counter[16]_i_8 ;
  wire \n_0_counter[17]_i_1 ;
  wire \n_0_counter[18]_i_1 ;
  wire \n_0_counter[19]_i_1 ;
  wire \n_0_counter[1]_i_1 ;
  wire \n_0_counter[2]_i_1 ;
  wire \n_0_counter[3]_i_1 ;
  wire \n_0_counter[3]_i_3 ;
  wire \n_0_counter[3]_i_4 ;
  wire \n_0_counter[3]_i_5 ;
  wire \n_0_counter[3]_i_6 ;
  wire \n_0_counter[4]_i_1 ;
  wire \n_0_counter[5]_i_1 ;
  wire \n_0_counter[6]_i_1 ;
  wire \n_0_counter[7]_i_1 ;
  wire \n_0_counter[7]_i_3 ;
  wire \n_0_counter[7]_i_4 ;
  wire \n_0_counter[7]_i_5 ;
  wire \n_0_counter[7]_i_6 ;
  wire \n_0_counter[8]_i_1 ;
  wire \n_0_counter[9]_i_1 ;
  wire \n_0_counter_load_i_reg[20]_srl12 ;
  wire \n_0_counter_reg[11]_i_2 ;
  wire \n_0_counter_reg[15]_i_2 ;
  wire \n_0_counter_reg[16]_i_3 ;
  wire \n_0_counter_reg[3]_i_2 ;
  wire \n_0_counter_reg[7]_i_2 ;
  wire \n_1_counter_reg[11]_i_2 ;
  wire \n_1_counter_reg[15]_i_2 ;
  wire \n_1_counter_reg[16]_i_3 ;
  wire \n_1_counter_reg[3]_i_2 ;
  wire \n_1_counter_reg[7]_i_2 ;
  wire \n_2_counter_reg[11]_i_2 ;
  wire \n_2_counter_reg[15]_i_2 ;
  wire \n_2_counter_reg[16]_i_3 ;
  wire \n_2_counter_reg[3]_i_2 ;
  wire \n_2_counter_reg[7]_i_2 ;
  wire \n_3_counter_reg[11]_i_2 ;
  wire \n_3_counter_reg[15]_i_2 ;
  wire \n_3_counter_reg[16]_i_3 ;
  wire \n_3_counter_reg[3]_i_2 ;
  wire \n_3_counter_reg[7]_i_2 ;
  wire [18:0]p_1_in;

LUT4 #(
    .INIT(16'hBBB8)) 
     \counter[0]_i_1 
       (.I0(CNT_LOAD_DOUT),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(COUNTER_MATCH),
        .I3(counter0[0]),
        .O(\n_0_counter[0]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[10]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[10]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[9]),
        .O(\n_0_counter[10]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[11]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[11]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[10]),
        .O(\n_0_counter[11]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_3 
       (.I0(counter[11]),
        .O(\n_0_counter[11]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_4 
       (.I0(counter[10]),
        .O(\n_0_counter[11]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_5 
       (.I0(counter[9]),
        .O(\n_0_counter[11]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_6 
       (.I0(counter[8]),
        .O(\n_0_counter[11]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[12]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[12]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[11]),
        .O(\n_0_counter[12]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[13]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[13]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[12]),
        .O(\n_0_counter[13]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[14]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[14]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[13]),
        .O(\n_0_counter[14]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[15]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[15]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[14]),
        .O(\n_0_counter[15]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_3 
       (.I0(counter[15]),
        .O(\n_0_counter[15]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_4 
       (.I0(counter[14]),
        .O(\n_0_counter[15]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_5 
       (.I0(counter[13]),
        .O(\n_0_counter[15]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_6 
       (.I0(counter[12]),
        .O(\n_0_counter[15]_i_6 ));
LUT5 #(
    .INIT(32'hFEFEFFFE)) 
     \counter[16]_i_1 
       (.I0(CNT_CTRL[1]),
        .I1(SCNT_RESET),
        .I2(CNT_CTRL[0]),
        .I3(RESET[1]),
        .I4(RESET[0]),
        .O(\n_0_counter[16]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[16]_i_2 
       (.I0(COUNTER_MATCH),
        .I1(counter0[16]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[15]),
        .O(\n_0_counter[16]_i_2 ));
LUT4 #(
    .INIT(16'hFFF4)) 
     \counter[16]_i_4 
       (.I0(RESET[0]),
        .I1(RESET[1]),
        .I2(CNT_CTRL[0]),
        .I3(SCNT_RESET),
        .O(\n_0_counter[16]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_5 
       (.I0(counter[19]),
        .O(\n_0_counter[16]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_6 
       (.I0(counter[18]),
        .O(\n_0_counter[16]_i_6 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_7 
       (.I0(counter[17]),
        .O(\n_0_counter[16]_i_7 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_8 
       (.I0(COUNTER_MATCH),
        .O(\n_0_counter[16]_i_8 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[17]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[17]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[16]),
        .O(\n_0_counter[17]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[18]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[18]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[17]),
        .O(\n_0_counter[18]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[19]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[19]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[18]),
        .O(\n_0_counter[19]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[1]_i_1 
       (.I0(p_1_in[0]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[1]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[1]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[2]_i_1 
       (.I0(p_1_in[1]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[2]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[2]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[3]_i_1 
       (.I0(p_1_in[2]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[3]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[3]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_3 
       (.I0(counter[3]),
        .O(\n_0_counter[3]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_4 
       (.I0(counter[2]),
        .O(\n_0_counter[3]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_5 
       (.I0(counter[1]),
        .O(\n_0_counter[3]_i_5 ));
LUT1 #(
    .INIT(2'h1)) 
     \counter[3]_i_6 
       (.I0(counter[0]),
        .O(\n_0_counter[3]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[4]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[4]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[3]),
        .O(\n_0_counter[4]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[5]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[5]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[4]),
        .O(\n_0_counter[5]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[6]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[6]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[5]),
        .O(\n_0_counter[6]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[7]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[7]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[6]),
        .O(\n_0_counter[7]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_3 
       (.I0(counter[7]),
        .O(\n_0_counter[7]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_4 
       (.I0(counter[6]),
        .O(\n_0_counter[7]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_5 
       (.I0(counter[5]),
        .O(\n_0_counter[7]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_6 
       (.I0(counter[4]),
        .O(\n_0_counter[7]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[8]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[8]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[7]),
        .O(\n_0_counter[8]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[9]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[9]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[8]),
        .O(\n_0_counter[9]_i_1 ));
FDRE \counter_load_i_reg[0] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[0]),
        .Q(CNT_LOAD_DOUT),
        .R(1'b0));
FDRE \counter_load_i_reg[10] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[10]),
        .Q(p_1_in[9]),
        .R(1'b0));
FDRE \counter_load_i_reg[11] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[11]),
        .Q(p_1_in[10]),
        .R(1'b0));
FDRE \counter_load_i_reg[12] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[12]),
        .Q(p_1_in[11]),
        .R(1'b0));
FDRE \counter_load_i_reg[13] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[13]),
        .Q(p_1_in[12]),
        .R(1'b0));
FDRE \counter_load_i_reg[14] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[14]),
        .Q(p_1_in[13]),
        .R(1'b0));
FDRE \counter_load_i_reg[15] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[15]),
        .Q(p_1_in[14]),
        .R(1'b0));
FDRE \counter_load_i_reg[16] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[16]),
        .Q(p_1_in[15]),
        .R(1'b0));
FDRE \counter_load_i_reg[17] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[17]),
        .Q(p_1_in[16]),
        .R(1'b0));
FDRE \counter_load_i_reg[18] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[18]),
        .Q(p_1_in[17]),
        .R(1'b0));
FDRE \counter_load_i_reg[19] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(\n_0_counter_load_i_reg[20]_srl12 ),
        .Q(p_1_in[18]),
        .R(1'b0));
FDRE \counter_load_i_reg[1] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[1]),
        .Q(p_1_in[0]),
        .R(1'b0));
(* srl_bus_name = "U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER /\counter_load_i_reg " *) 
   (* srl_name = "U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER /\counter_load_i_reg[20]_srl12 " *) 
   SRL16E \counter_load_i_reg[20]_srl12 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(CNT_LOAD_EN),
        .CLK(CFG_CLK),
        .D(CNT_LOAD_IN),
        .Q(\n_0_counter_load_i_reg[20]_srl12 ));
FDRE \counter_load_i_reg[2] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[2]),
        .Q(p_1_in[1]),
        .R(1'b0));
FDRE \counter_load_i_reg[3] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[3]),
        .Q(p_1_in[2]),
        .R(1'b0));
FDRE \counter_load_i_reg[4] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[4]),
        .Q(p_1_in[3]),
        .R(1'b0));
FDRE \counter_load_i_reg[5] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[5]),
        .Q(p_1_in[4]),
        .R(1'b0));
FDRE \counter_load_i_reg[6] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[6]),
        .Q(p_1_in[5]),
        .R(1'b0));
FDRE \counter_load_i_reg[7] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[7]),
        .Q(p_1_in[6]),
        .R(1'b0));
FDRE \counter_load_i_reg[8] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[8]),
        .Q(p_1_in[7]),
        .R(1'b0));
FDRE \counter_load_i_reg[9] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[9]),
        .Q(p_1_in[8]),
        .R(1'b0));
FDRE \counter_reg[0] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[0]_i_1 ),
        .Q(counter[0]),
        .R(1'b0));
FDRE \counter_reg[10] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[10]_i_1 ),
        .Q(counter[10]),
        .R(1'b0));
FDRE \counter_reg[11] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[11]_i_1 ),
        .Q(counter[11]),
        .R(1'b0));
CARRY4 \counter_reg[11]_i_2 
       (.CI(\n_0_counter_reg[7]_i_2 ),
        .CO({\n_0_counter_reg[11]_i_2 ,\n_1_counter_reg[11]_i_2 ,\n_2_counter_reg[11]_i_2 ,\n_3_counter_reg[11]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[11:8]),
        .S({\n_0_counter[11]_i_3 ,\n_0_counter[11]_i_4 ,\n_0_counter[11]_i_5 ,\n_0_counter[11]_i_6 }));
FDRE \counter_reg[12] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[12]_i_1 ),
        .Q(counter[12]),
        .R(1'b0));
FDRE \counter_reg[13] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[13]_i_1 ),
        .Q(counter[13]),
        .R(1'b0));
FDRE \counter_reg[14] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[14]_i_1 ),
        .Q(counter[14]),
        .R(1'b0));
FDRE \counter_reg[15] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[15]_i_1 ),
        .Q(counter[15]),
        .R(1'b0));
CARRY4 \counter_reg[15]_i_2 
       (.CI(\n_0_counter_reg[11]_i_2 ),
        .CO({\n_0_counter_reg[15]_i_2 ,\n_1_counter_reg[15]_i_2 ,\n_2_counter_reg[15]_i_2 ,\n_3_counter_reg[15]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[15:12]),
        .S({\n_0_counter[15]_i_3 ,\n_0_counter[15]_i_4 ,\n_0_counter[15]_i_5 ,\n_0_counter[15]_i_6 }));
FDRE \counter_reg[16] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[16]_i_2 ),
        .Q(COUNTER_MATCH),
        .R(1'b0));
CARRY4 \counter_reg[16]_i_3 
       (.CI(\n_0_counter_reg[15]_i_2 ),
        .CO({\n_0_counter_reg[16]_i_3 ,\n_1_counter_reg[16]_i_3 ,\n_2_counter_reg[16]_i_3 ,\n_3_counter_reg[16]_i_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[19:16]),
        .S({\n_0_counter[16]_i_5 ,\n_0_counter[16]_i_6 ,\n_0_counter[16]_i_7 ,\n_0_counter[16]_i_8 }));
FDRE \counter_reg[17] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[17]_i_1 ),
        .Q(counter[17]),
        .R(1'b0));
FDRE \counter_reg[18] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[18]_i_1 ),
        .Q(counter[18]),
        .R(1'b0));
FDRE \counter_reg[19] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[19]_i_1 ),
        .Q(counter[19]),
        .R(1'b0));
FDRE \counter_reg[1] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[1]_i_1 ),
        .Q(counter[1]),
        .R(1'b0));
FDRE \counter_reg[2] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[2]_i_1 ),
        .Q(counter[2]),
        .R(1'b0));
FDRE \counter_reg[3] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[3]_i_1 ),
        .Q(counter[3]),
        .R(1'b0));
CARRY4 \counter_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\n_0_counter_reg[3]_i_2 ,\n_1_counter_reg[3]_i_2 ,\n_2_counter_reg[3]_i_2 ,\n_3_counter_reg[3]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,counter[0]}),
        .O(counter0[3:0]),
        .S({\n_0_counter[3]_i_3 ,\n_0_counter[3]_i_4 ,\n_0_counter[3]_i_5 ,\n_0_counter[3]_i_6 }));
FDRE \counter_reg[4] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[4]_i_1 ),
        .Q(counter[4]),
        .R(1'b0));
FDRE \counter_reg[5] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[5]_i_1 ),
        .Q(counter[5]),
        .R(1'b0));
FDRE \counter_reg[6] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[6]_i_1 ),
        .Q(counter[6]),
        .R(1'b0));
FDRE \counter_reg[7] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[7]_i_1 ),
        .Q(counter[7]),
        .R(1'b0));
CARRY4 \counter_reg[7]_i_2 
       (.CI(\n_0_counter_reg[3]_i_2 ),
        .CO({\n_0_counter_reg[7]_i_2 ,\n_1_counter_reg[7]_i_2 ,\n_2_counter_reg[7]_i_2 ,\n_3_counter_reg[7]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[7:4]),
        .S({\n_0_counter[7]_i_3 ,\n_0_counter[7]_i_4 ,\n_0_counter[7]_i_5 ,\n_0_counter[7]_i_6 }));
FDRE \counter_reg[8] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[8]_i_1 ),
        .Q(counter[8]),
        .R(1'b0));
FDRE \counter_reg[9] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[9]_i_1 ),
        .Q(counter[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_generic_counter" *) (* DONT_TOUCH = "true" *) (* C_COUNTER_WIDTH = "17" *) 
(* CNT_MAX = "17'b10000000000000000" *) 
module ila_0_ila_v5_0_generic_counter__6
   (CLK,
    CFG_CLK,
    RESET,
    SCNT_RESET,
    CNT_CTRL,
    CNT_LOAD_IN,
    CNT_LOAD_EN,
    CNT_LOAD_DOUT,
    COUNTER_MATCH);
  input CLK;
  input CFG_CLK;
  input [1:0]RESET;
  input SCNT_RESET;
  input [1:0]CNT_CTRL;
  input CNT_LOAD_IN;
  input CNT_LOAD_EN;
  output CNT_LOAD_DOUT;
  output COUNTER_MATCH;

  wire CFG_CLK;
  wire CLK;
  wire [1:0]CNT_CTRL;
  wire CNT_LOAD_DOUT;
  wire CNT_LOAD_EN;
  wire CNT_LOAD_IN;
  wire COUNTER_MATCH;
  wire [1:0]RESET;
  wire SCNT_RESET;
  wire [19:0]counter;
  wire [19:0]counter0;
  wire \n_0_counter[0]_i_1 ;
  wire \n_0_counter[10]_i_1 ;
  wire \n_0_counter[11]_i_1 ;
  wire \n_0_counter[11]_i_3 ;
  wire \n_0_counter[11]_i_4 ;
  wire \n_0_counter[11]_i_5 ;
  wire \n_0_counter[11]_i_6 ;
  wire \n_0_counter[12]_i_1 ;
  wire \n_0_counter[13]_i_1 ;
  wire \n_0_counter[14]_i_1 ;
  wire \n_0_counter[15]_i_1 ;
  wire \n_0_counter[15]_i_3 ;
  wire \n_0_counter[15]_i_4 ;
  wire \n_0_counter[15]_i_5 ;
  wire \n_0_counter[15]_i_6 ;
  wire \n_0_counter[16]_i_1 ;
  wire \n_0_counter[16]_i_2 ;
  wire \n_0_counter[16]_i_4 ;
  wire \n_0_counter[16]_i_5 ;
  wire \n_0_counter[16]_i_6 ;
  wire \n_0_counter[16]_i_7 ;
  wire \n_0_counter[16]_i_8 ;
  wire \n_0_counter[17]_i_1 ;
  wire \n_0_counter[18]_i_1 ;
  wire \n_0_counter[19]_i_1 ;
  wire \n_0_counter[1]_i_1 ;
  wire \n_0_counter[2]_i_1 ;
  wire \n_0_counter[3]_i_1 ;
  wire \n_0_counter[3]_i_3 ;
  wire \n_0_counter[3]_i_4 ;
  wire \n_0_counter[3]_i_5 ;
  wire \n_0_counter[3]_i_6 ;
  wire \n_0_counter[4]_i_1 ;
  wire \n_0_counter[5]_i_1 ;
  wire \n_0_counter[6]_i_1 ;
  wire \n_0_counter[7]_i_1 ;
  wire \n_0_counter[7]_i_3 ;
  wire \n_0_counter[7]_i_4 ;
  wire \n_0_counter[7]_i_5 ;
  wire \n_0_counter[7]_i_6 ;
  wire \n_0_counter[8]_i_1 ;
  wire \n_0_counter[9]_i_1 ;
  wire \n_0_counter_load_i_reg[20]_srl12 ;
  wire \n_0_counter_reg[11]_i_2 ;
  wire \n_0_counter_reg[15]_i_2 ;
  wire \n_0_counter_reg[16]_i_3 ;
  wire \n_0_counter_reg[3]_i_2 ;
  wire \n_0_counter_reg[7]_i_2 ;
  wire \n_1_counter_reg[11]_i_2 ;
  wire \n_1_counter_reg[15]_i_2 ;
  wire \n_1_counter_reg[16]_i_3 ;
  wire \n_1_counter_reg[3]_i_2 ;
  wire \n_1_counter_reg[7]_i_2 ;
  wire \n_2_counter_reg[11]_i_2 ;
  wire \n_2_counter_reg[15]_i_2 ;
  wire \n_2_counter_reg[16]_i_3 ;
  wire \n_2_counter_reg[3]_i_2 ;
  wire \n_2_counter_reg[7]_i_2 ;
  wire \n_3_counter_reg[11]_i_2 ;
  wire \n_3_counter_reg[15]_i_2 ;
  wire \n_3_counter_reg[16]_i_3 ;
  wire \n_3_counter_reg[3]_i_2 ;
  wire \n_3_counter_reg[7]_i_2 ;
  wire [18:0]p_1_in;

LUT4 #(
    .INIT(16'hBBB8)) 
     \counter[0]_i_1 
       (.I0(CNT_LOAD_DOUT),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(COUNTER_MATCH),
        .I3(counter0[0]),
        .O(\n_0_counter[0]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[10]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[10]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[9]),
        .O(\n_0_counter[10]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[11]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[11]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[10]),
        .O(\n_0_counter[11]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_3 
       (.I0(counter[11]),
        .O(\n_0_counter[11]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_4 
       (.I0(counter[10]),
        .O(\n_0_counter[11]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_5 
       (.I0(counter[9]),
        .O(\n_0_counter[11]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[11]_i_6 
       (.I0(counter[8]),
        .O(\n_0_counter[11]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[12]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[12]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[11]),
        .O(\n_0_counter[12]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[13]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[13]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[12]),
        .O(\n_0_counter[13]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[14]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[14]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[13]),
        .O(\n_0_counter[14]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[15]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[15]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[14]),
        .O(\n_0_counter[15]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_3 
       (.I0(counter[15]),
        .O(\n_0_counter[15]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_4 
       (.I0(counter[14]),
        .O(\n_0_counter[15]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_5 
       (.I0(counter[13]),
        .O(\n_0_counter[15]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[15]_i_6 
       (.I0(counter[12]),
        .O(\n_0_counter[15]_i_6 ));
LUT5 #(
    .INIT(32'hFEFEFFFE)) 
     \counter[16]_i_1 
       (.I0(CNT_CTRL[1]),
        .I1(SCNT_RESET),
        .I2(CNT_CTRL[0]),
        .I3(RESET[1]),
        .I4(RESET[0]),
        .O(\n_0_counter[16]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[16]_i_2 
       (.I0(COUNTER_MATCH),
        .I1(counter0[16]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[15]),
        .O(\n_0_counter[16]_i_2 ));
LUT4 #(
    .INIT(16'hFFF4)) 
     \counter[16]_i_4 
       (.I0(RESET[0]),
        .I1(RESET[1]),
        .I2(CNT_CTRL[0]),
        .I3(SCNT_RESET),
        .O(\n_0_counter[16]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_5 
       (.I0(counter[19]),
        .O(\n_0_counter[16]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_6 
       (.I0(counter[18]),
        .O(\n_0_counter[16]_i_6 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_7 
       (.I0(counter[17]),
        .O(\n_0_counter[16]_i_7 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[16]_i_8 
       (.I0(COUNTER_MATCH),
        .O(\n_0_counter[16]_i_8 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[17]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[17]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[16]),
        .O(\n_0_counter[17]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[18]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[18]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[17]),
        .O(\n_0_counter[18]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[19]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[19]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[18]),
        .O(\n_0_counter[19]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[1]_i_1 
       (.I0(p_1_in[0]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[1]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[1]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[2]_i_1 
       (.I0(p_1_in[1]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[2]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[2]_i_1 ));
LUT4 #(
    .INIT(16'h88B8)) 
     \counter[3]_i_1 
       (.I0(p_1_in[2]),
        .I1(\n_0_counter[16]_i_4 ),
        .I2(counter0[3]),
        .I3(COUNTER_MATCH),
        .O(\n_0_counter[3]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_3 
       (.I0(counter[3]),
        .O(\n_0_counter[3]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_4 
       (.I0(counter[2]),
        .O(\n_0_counter[3]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[3]_i_5 
       (.I0(counter[1]),
        .O(\n_0_counter[3]_i_5 ));
LUT1 #(
    .INIT(2'h1)) 
     \counter[3]_i_6 
       (.I0(counter[0]),
        .O(\n_0_counter[3]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[4]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[4]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[3]),
        .O(\n_0_counter[4]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[5]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[5]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[4]),
        .O(\n_0_counter[5]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[6]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[6]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[5]),
        .O(\n_0_counter[6]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[7]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[7]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[6]),
        .O(\n_0_counter[7]_i_1 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_3 
       (.I0(counter[7]),
        .O(\n_0_counter[7]_i_3 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_4 
       (.I0(counter[6]),
        .O(\n_0_counter[7]_i_4 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_5 
       (.I0(counter[5]),
        .O(\n_0_counter[7]_i_5 ));
LUT1 #(
    .INIT(2'h2)) 
     \counter[7]_i_6 
       (.I0(counter[4]),
        .O(\n_0_counter[7]_i_6 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[8]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[8]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[7]),
        .O(\n_0_counter[8]_i_1 ));
LUT4 #(
    .INIT(16'hF404)) 
     \counter[9]_i_1 
       (.I0(COUNTER_MATCH),
        .I1(counter0[9]),
        .I2(\n_0_counter[16]_i_4 ),
        .I3(p_1_in[8]),
        .O(\n_0_counter[9]_i_1 ));
FDRE \counter_load_i_reg[0] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[0]),
        .Q(CNT_LOAD_DOUT),
        .R(1'b0));
FDRE \counter_load_i_reg[10] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[10]),
        .Q(p_1_in[9]),
        .R(1'b0));
FDRE \counter_load_i_reg[11] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[11]),
        .Q(p_1_in[10]),
        .R(1'b0));
FDRE \counter_load_i_reg[12] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[12]),
        .Q(p_1_in[11]),
        .R(1'b0));
FDRE \counter_load_i_reg[13] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[13]),
        .Q(p_1_in[12]),
        .R(1'b0));
FDRE \counter_load_i_reg[14] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[14]),
        .Q(p_1_in[13]),
        .R(1'b0));
FDRE \counter_load_i_reg[15] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[15]),
        .Q(p_1_in[14]),
        .R(1'b0));
FDRE \counter_load_i_reg[16] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[16]),
        .Q(p_1_in[15]),
        .R(1'b0));
FDRE \counter_load_i_reg[17] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[17]),
        .Q(p_1_in[16]),
        .R(1'b0));
FDRE \counter_load_i_reg[18] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[18]),
        .Q(p_1_in[17]),
        .R(1'b0));
FDRE \counter_load_i_reg[19] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(\n_0_counter_load_i_reg[20]_srl12 ),
        .Q(p_1_in[18]),
        .R(1'b0));
FDRE \counter_load_i_reg[1] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[1]),
        .Q(p_1_in[0]),
        .R(1'b0));
(* srl_bus_name = "U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER /\counter_load_i_reg " *) 
   (* srl_name = "U0/\ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER /\counter_load_i_reg[20]_srl12 " *) 
   SRL16E \counter_load_i_reg[20]_srl12 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(CNT_LOAD_EN),
        .CLK(CFG_CLK),
        .D(CNT_LOAD_IN),
        .Q(\n_0_counter_load_i_reg[20]_srl12 ));
FDRE \counter_load_i_reg[2] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[2]),
        .Q(p_1_in[1]),
        .R(1'b0));
FDRE \counter_load_i_reg[3] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[3]),
        .Q(p_1_in[2]),
        .R(1'b0));
FDRE \counter_load_i_reg[4] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[4]),
        .Q(p_1_in[3]),
        .R(1'b0));
FDRE \counter_load_i_reg[5] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[5]),
        .Q(p_1_in[4]),
        .R(1'b0));
FDRE \counter_load_i_reg[6] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[6]),
        .Q(p_1_in[5]),
        .R(1'b0));
FDRE \counter_load_i_reg[7] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[7]),
        .Q(p_1_in[6]),
        .R(1'b0));
FDRE \counter_load_i_reg[8] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[8]),
        .Q(p_1_in[7]),
        .R(1'b0));
FDRE \counter_load_i_reg[9] 
       (.C(CFG_CLK),
        .CE(CNT_LOAD_EN),
        .D(p_1_in[9]),
        .Q(p_1_in[8]),
        .R(1'b0));
FDRE \counter_reg[0] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[0]_i_1 ),
        .Q(counter[0]),
        .R(1'b0));
FDRE \counter_reg[10] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[10]_i_1 ),
        .Q(counter[10]),
        .R(1'b0));
FDRE \counter_reg[11] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[11]_i_1 ),
        .Q(counter[11]),
        .R(1'b0));
CARRY4 \counter_reg[11]_i_2 
       (.CI(\n_0_counter_reg[7]_i_2 ),
        .CO({\n_0_counter_reg[11]_i_2 ,\n_1_counter_reg[11]_i_2 ,\n_2_counter_reg[11]_i_2 ,\n_3_counter_reg[11]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[11:8]),
        .S({\n_0_counter[11]_i_3 ,\n_0_counter[11]_i_4 ,\n_0_counter[11]_i_5 ,\n_0_counter[11]_i_6 }));
FDRE \counter_reg[12] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[12]_i_1 ),
        .Q(counter[12]),
        .R(1'b0));
FDRE \counter_reg[13] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[13]_i_1 ),
        .Q(counter[13]),
        .R(1'b0));
FDRE \counter_reg[14] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[14]_i_1 ),
        .Q(counter[14]),
        .R(1'b0));
FDRE \counter_reg[15] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[15]_i_1 ),
        .Q(counter[15]),
        .R(1'b0));
CARRY4 \counter_reg[15]_i_2 
       (.CI(\n_0_counter_reg[11]_i_2 ),
        .CO({\n_0_counter_reg[15]_i_2 ,\n_1_counter_reg[15]_i_2 ,\n_2_counter_reg[15]_i_2 ,\n_3_counter_reg[15]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[15:12]),
        .S({\n_0_counter[15]_i_3 ,\n_0_counter[15]_i_4 ,\n_0_counter[15]_i_5 ,\n_0_counter[15]_i_6 }));
FDRE \counter_reg[16] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[16]_i_2 ),
        .Q(COUNTER_MATCH),
        .R(1'b0));
CARRY4 \counter_reg[16]_i_3 
       (.CI(\n_0_counter_reg[15]_i_2 ),
        .CO({\n_0_counter_reg[16]_i_3 ,\n_1_counter_reg[16]_i_3 ,\n_2_counter_reg[16]_i_3 ,\n_3_counter_reg[16]_i_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[19:16]),
        .S({\n_0_counter[16]_i_5 ,\n_0_counter[16]_i_6 ,\n_0_counter[16]_i_7 ,\n_0_counter[16]_i_8 }));
FDRE \counter_reg[17] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[17]_i_1 ),
        .Q(counter[17]),
        .R(1'b0));
FDRE \counter_reg[18] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[18]_i_1 ),
        .Q(counter[18]),
        .R(1'b0));
FDRE \counter_reg[19] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[19]_i_1 ),
        .Q(counter[19]),
        .R(1'b0));
FDRE \counter_reg[1] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[1]_i_1 ),
        .Q(counter[1]),
        .R(1'b0));
FDRE \counter_reg[2] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[2]_i_1 ),
        .Q(counter[2]),
        .R(1'b0));
FDRE \counter_reg[3] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[3]_i_1 ),
        .Q(counter[3]),
        .R(1'b0));
CARRY4 \counter_reg[3]_i_2 
       (.CI(1'b0),
        .CO({\n_0_counter_reg[3]_i_2 ,\n_1_counter_reg[3]_i_2 ,\n_2_counter_reg[3]_i_2 ,\n_3_counter_reg[3]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,counter[0]}),
        .O(counter0[3:0]),
        .S({\n_0_counter[3]_i_3 ,\n_0_counter[3]_i_4 ,\n_0_counter[3]_i_5 ,\n_0_counter[3]_i_6 }));
FDRE \counter_reg[4] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[4]_i_1 ),
        .Q(counter[4]),
        .R(1'b0));
FDRE \counter_reg[5] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[5]_i_1 ),
        .Q(counter[5]),
        .R(1'b0));
FDRE \counter_reg[6] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[6]_i_1 ),
        .Q(counter[6]),
        .R(1'b0));
FDRE \counter_reg[7] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[7]_i_1 ),
        .Q(counter[7]),
        .R(1'b0));
CARRY4 \counter_reg[7]_i_2 
       (.CI(\n_0_counter_reg[3]_i_2 ),
        .CO({\n_0_counter_reg[7]_i_2 ,\n_1_counter_reg[7]_i_2 ,\n_2_counter_reg[7]_i_2 ,\n_3_counter_reg[7]_i_2 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(counter0[7:4]),
        .S({\n_0_counter[7]_i_3 ,\n_0_counter[7]_i_4 ,\n_0_counter[7]_i_5 ,\n_0_counter[7]_i_6 }));
FDRE \counter_reg[8] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[8]_i_1 ),
        .Q(counter[8]),
        .R(1'b0));
FDRE \counter_reg[9] 
       (.C(CLK),
        .CE(\n_0_counter[16]_i_1 ),
        .D(\n_0_counter[9]_i_1 ),
        .Q(counter[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila" *) (* downgradeipidentifiedwarnings = "yes" *) (* IS_DEBUG_CORE = "true" *) 
(* DONT_TOUCH = "true" *) (* C_ENABLE_ILA_AXI_MON = "0" *) (* C_SLOT_0_AXI_PROTOCOL = "AXI4" *) 
(* C_NUM_MONITOR_SLOTS = "1" *) (* C_XLNX_HW_PROBE_INFO = "NUM_OF_PROBES=13,DATA_DEPTH=1024,PROBE0_WIDTH=32,PROBE0_MU_CNT=1,PROBE1_WIDTH=1,PROBE1_MU_CNT=1,PROBE2_WIDTH=1,PROBE2_MU_CNT=1,PROBE3_WIDTH=32,PROBE3_MU_CNT=1,PROBE4_WIDTH=1,PROBE4_MU_CNT=1,PROBE5_WIDTH=1,PROBE5_MU_CNT=1,PROBE6_WIDTH=32,PROBE6_MU_CNT=1,PROBE7_WIDTH=1,PROBE7_MU_CNT=1,PROBE8_WIDTH=1,PROBE8_MU_CNT=1,PROBE9_WIDTH=32,PROBE9_MU_CNT=1,PROBE10_WIDTH=1,PROBE10_MU_CNT=1,PROBE11_WIDTH=1,PROBE11_MU_CNT=1,PROBE12_WIDTH=4,PROBE12_MU_CNT=1,PROBE13_WIDTH=1,PROBE13_MU_CNT=1,PROBE14_WIDTH=1,PROBE14_MU_CNT=1,PROBE15_WIDTH=1,PROBE15_MU_CNT=1,PROBE16_WIDTH=1,PROBE16_MU_CNT=1,PROBE17_WIDTH=1,PROBE17_MU_CNT=1,PROBE18_WIDTH=1,PROBE18_MU_CNT=1,PROBE19_WIDTH=1,PROBE19_MU_CNT=1,PROBE20_WIDTH=1,PROBE20_MU_CNT=1,PROBE21_WIDTH=1,PROBE21_MU_CNT=1,PROBE22_WIDTH=1,PROBE22_MU_CNT=1,PROBE23_WIDTH=1,PROBE23_MU_CNT=1,PROBE24_WIDTH=1,PROBE24_MU_CNT=1,PROBE25_WIDTH=1,PROBE25_MU_CNT=1,PROBE26_WIDTH=1,PROBE26_MU_CNT=1,PROBE27_WIDTH=1,PROBE27_MU_CNT=1,PROBE28_WIDTH=1,PROBE28_MU_CNT=1,PROBE29_WIDTH=1,PROBE29_MU_CNT=1,PROBE30_WIDTH=1,PROBE30_MU_CNT=1,PROBE31_WIDTH=1,PROBE31_MU_CNT=1,PROBE32_WIDTH=1,PROBE32_MU_CNT=1,PROBE33_WIDTH=1,PROBE33_MU_CNT=1,PROBE34_WIDTH=1,PROBE34_MU_CNT=1,PROBE35_WIDTH=1,PROBE35_MU_CNT=1,PROBE36_WIDTH=1,PROBE36_MU_CNT=1,PROBE37_WIDTH=1,PROBE37_MU_CNT=1,PROBE38_WIDTH=1,PROBE38_MU_CNT=1,PROBE39_WIDTH=1,PROBE39_MU_CNT=1,PROBE40_WIDTH=1,PROBE40_MU_CNT=1,PROBE41_WIDTH=1,PROBE41_MU_CNT=1,PROBE42_WIDTH=1,PROBE42_MU_CNT=1,PROBE43_WIDTH=1,PROBE43_MU_CNT=1,PROBE44_WIDTH=1,PROBE44_MU_CNT=1,PROBE45_WIDTH=1,PROBE45_MU_CNT=1,PROBE46_WIDTH=1,PROBE46_MU_CNT=1,PROBE47_WIDTH=1,PROBE47_MU_CNT=1,PROBE48_WIDTH=1,PROBE48_MU_CNT=1,PROBE49_WIDTH=1,PROBE49_MU_CNT=1,PROBE50_WIDTH=1,PROBE50_MU_CNT=1,PROBE51_WIDTH=1,PROBE51_MU_CNT=1,PROBE52_WIDTH=1,PROBE52_MU_CNT=1,PROBE53_WIDTH=1,PROBE53_MU_CNT=1,PROBE54_WIDTH=1,PROBE54_MU_CNT=1,PROBE55_WIDTH=1,PROBE55_MU_CNT=1,PROBE56_WIDTH=1,PROBE56_MU_CNT=1,PROBE57_WIDTH=1,PROBE57_MU_CNT=1,PROBE58_WIDTH=1,PROBE58_MU_CNT=1,PROBE59_WIDTH=1,PROBE59_MU_CNT=1,PROBE60_WIDTH=1,PROBE60_MU_CNT=1,PROBE61_WIDTH=1,PROBE61_MU_CNT=1,PROBE62_WIDTH=1,PROBE62_MU_CNT=1,PROBE63_WIDTH=1,PROBE63_MU_CNT=1,PROBE64_WIDTH=1,PROBE64_MU_CNT=1,PROBE65_WIDTH=1,PROBE65_MU_CNT=1,PROBE66_WIDTH=1,PROBE66_MU_CNT=1,PROBE67_WIDTH=1,PROBE67_MU_CNT=1,PROBE68_WIDTH=1,PROBE68_MU_CNT=1,PROBE69_WIDTH=1,PROBE69_MU_CNT=1,PROBE70_WIDTH=1,PROBE70_MU_CNT=1,PROBE71_WIDTH=1,PROBE71_MU_CNT=1,PROBE72_WIDTH=1,PROBE72_MU_CNT=1,PROBE73_WIDTH=1,PROBE73_MU_CNT=1,PROBE74_WIDTH=1,PROBE74_MU_CNT=1,PROBE75_WIDTH=1,PROBE75_MU_CNT=1,PROBE76_WIDTH=1,PROBE76_MU_CNT=1,PROBE77_WIDTH=1,PROBE77_MU_CNT=1,PROBE78_WIDTH=1,PROBE78_MU_CNT=1,PROBE79_WIDTH=1,PROBE79_MU_CNT=1,PROBE80_WIDTH=1,PROBE80_MU_CNT=1,PROBE81_WIDTH=1,PROBE81_MU_CNT=1,PROBE82_WIDTH=1,PROBE82_MU_CNT=1,PROBE83_WIDTH=1,PROBE83_MU_CNT=1,PROBE84_WIDTH=1,PROBE84_MU_CNT=1,PROBE85_WIDTH=1,PROBE85_MU_CNT=1,PROBE86_WIDTH=1,PROBE86_MU_CNT=1,PROBE87_WIDTH=1,PROBE87_MU_CNT=1,PROBE88_WIDTH=1,PROBE88_MU_CNT=1,PROBE89_WIDTH=1,PROBE89_MU_CNT=1,PROBE90_WIDTH=1,PROBE90_MU_CNT=1,PROBE91_WIDTH=1,PROBE91_MU_CNT=1,PROBE92_WIDTH=1,PROBE92_MU_CNT=1,PROBE93_WIDTH=1,PROBE93_MU_CNT=1,PROBE94_WIDTH=1,PROBE94_MU_CNT=1,PROBE95_WIDTH=1,PROBE95_MU_CNT=1,PROBE96_WIDTH=1,PROBE96_MU_CNT=1,PROBE97_WIDTH=1,PROBE97_MU_CNT=1,PROBE98_WIDTH=1,PROBE98_MU_CNT=1,PROBE99_WIDTH=1,PROBE99_MU_CNT=1,PROBE100_WIDTH=1,PROBE100_MU_CNT=1,PROBE101_WIDTH=1,PROBE101_MU_CNT=1,PROBE102_WIDTH=1,PROBE102_MU_CNT=1,PROBE103_WIDTH=1,PROBE103_MU_CNT=1,PROBE104_WIDTH=1,PROBE104_MU_CNT=1,PROBE105_WIDTH=1,PROBE105_MU_CNT=1,PROBE106_WIDTH=1,PROBE106_MU_CNT=1,PROBE107_WIDTH=1,PROBE107_MU_CNT=1,PROBE108_WIDTH=1,PROBE108_MU_CNT=1,PROBE109_WIDTH=1,PROBE109_MU_CNT=1,PROBE110_WIDTH=1,PROBE110_MU_CNT=1,PROBE111_WIDTH=1,PROBE111_MU_CNT=1,PROBE112_WIDTH=1,PROBE112_MU_CNT=1,PROBE113_WIDTH=1,PROBE113_MU_CNT=1,PROBE114_WIDTH=1,PROBE114_MU_CNT=1,PROBE115_WIDTH=1,PROBE115_MU_CNT=1,PROBE116_WIDTH=1,PROBE116_MU_CNT=1,PROBE117_WIDTH=1,PROBE117_MU_CNT=1,PROBE118_WIDTH=1,PROBE118_MU_CNT=1,PROBE119_WIDTH=1,PROBE119_MU_CNT=1,PROBE120_WIDTH=1,PROBE120_MU_CNT=1,PROBE121_WIDTH=1,PROBE121_MU_CNT=1,PROBE122_WIDTH=1,PROBE122_MU_CNT=1,PROBE123_WIDTH=1,PROBE123_MU_CNT=1,PROBE124_WIDTH=1,PROBE124_MU_CNT=1,PROBE125_WIDTH=1,PROBE125_MU_CNT=1,PROBE126_WIDTH=1,PROBE126_MU_CNT=1,PROBE127_WIDTH=1,PROBE127_MU_CNT=1,PROBE128_WIDTH=1,PROBE128_MU_CNT=1,PROBE129_WIDTH=1,PROBE129_MU_CNT=1,PROBE130_WIDTH=1,PROBE130_MU_CNT=1,PROBE131_WIDTH=1,PROBE131_MU_CNT=1,PROBE132_WIDTH=1,PROBE132_MU_CNT=1,PROBE133_WIDTH=1,PROBE133_MU_CNT=1,PROBE134_WIDTH=1,PROBE134_MU_CNT=1,PROBE135_WIDTH=1,PROBE135_MU_CNT=1,PROBE136_WIDTH=1,PROBE136_MU_CNT=1,PROBE137_WIDTH=1,PROBE137_MU_CNT=1,PROBE138_WIDTH=1,PROBE138_MU_CNT=1,PROBE139_WIDTH=1,PROBE139_MU_CNT=1,PROBE140_WIDTH=1,PROBE140_MU_CNT=1,PROBE141_WIDTH=1,PROBE141_MU_CNT=1,PROBE142_WIDTH=1,PROBE142_MU_CNT=1,PROBE143_WIDTH=1,PROBE143_MU_CNT=1,PROBE144_WIDTH=1,PROBE144_MU_CNT=1,PROBE145_WIDTH=1,PROBE145_MU_CNT=1,PROBE146_WIDTH=1,PROBE146_MU_CNT=1,PROBE147_WIDTH=1,PROBE147_MU_CNT=1,PROBE148_WIDTH=1,PROBE148_MU_CNT=1,PROBE149_WIDTH=1,PROBE149_MU_CNT=1,PROBE150_WIDTH=1,PROBE150_MU_CNT=1,PROBE151_WIDTH=1,PROBE151_MU_CNT=1,PROBE152_WIDTH=1,PROBE152_MU_CNT=1,PROBE153_WIDTH=1,PROBE153_MU_CNT=1,PROBE154_WIDTH=1,PROBE154_MU_CNT=1,PROBE155_WIDTH=1,PROBE155_MU_CNT=1,PROBE156_WIDTH=1,PROBE156_MU_CNT=1,PROBE157_WIDTH=1,PROBE157_MU_CNT=1,PROBE158_WIDTH=1,PROBE158_MU_CNT=1,PROBE159_WIDTH=1,PROBE159_MU_CNT=1,PROBE160_WIDTH=1,PROBE160_MU_CNT=1,PROBE161_WIDTH=1,PROBE161_MU_CNT=1,PROBE162_WIDTH=1,PROBE162_MU_CNT=1,PROBE163_WIDTH=1,PROBE163_MU_CNT=1,PROBE164_WIDTH=1,PROBE164_MU_CNT=1,PROBE165_WIDTH=1,PROBE165_MU_CNT=1,PROBE166_WIDTH=1,PROBE166_MU_CNT=1,PROBE167_WIDTH=1,PROBE167_MU_CNT=1,PROBE168_WIDTH=1,PROBE168_MU_CNT=1,PROBE169_WIDTH=1,PROBE169_MU_CNT=1,PROBE170_WIDTH=1,PROBE170_MU_CNT=1,PROBE171_WIDTH=1,PROBE171_MU_CNT=1,PROBE172_WIDTH=1,PROBE172_MU_CNT=1,PROBE173_WIDTH=1,PROBE173_MU_CNT=1,PROBE174_WIDTH=1,PROBE174_MU_CNT=1,PROBE175_WIDTH=1,PROBE175_MU_CNT=1,PROBE176_WIDTH=1,PROBE176_MU_CNT=1,PROBE177_WIDTH=1,PROBE177_MU_CNT=1,PROBE178_WIDTH=1,PROBE178_MU_CNT=1,PROBE179_WIDTH=1,PROBE179_MU_CNT=1,PROBE180_WIDTH=1,PROBE180_MU_CNT=1,PROBE181_WIDTH=1,PROBE181_MU_CNT=1,PROBE182_WIDTH=1,PROBE182_MU_CNT=1,PROBE183_WIDTH=1,PROBE183_MU_CNT=1,PROBE184_WIDTH=1,PROBE184_MU_CNT=1,PROBE185_WIDTH=1,PROBE185_MU_CNT=1,PROBE186_WIDTH=1,PROBE186_MU_CNT=1,PROBE187_WIDTH=1,PROBE187_MU_CNT=1,PROBE188_WIDTH=1,PROBE188_MU_CNT=1,PROBE189_WIDTH=1,PROBE189_MU_CNT=1,PROBE190_WIDTH=1,PROBE190_MU_CNT=1,PROBE191_WIDTH=1,PROBE191_MU_CNT=1,PROBE192_WIDTH=1,PROBE192_MU_CNT=1,PROBE193_WIDTH=1,PROBE193_MU_CNT=1,PROBE194_WIDTH=1,PROBE194_MU_CNT=1,PROBE195_WIDTH=1,PROBE195_MU_CNT=1,PROBE196_WIDTH=1,PROBE196_MU_CNT=1,PROBE197_WIDTH=1,PROBE197_MU_CNT=1,PROBE198_WIDTH=1,PROBE198_MU_CNT=1,PROBE199_WIDTH=1,PROBE199_MU_CNT=1,PROBE200_WIDTH=1,PROBE200_MU_CNT=1,PROBE201_WIDTH=1,PROBE201_MU_CNT=1,PROBE202_WIDTH=1,PROBE202_MU_CNT=1,PROBE203_WIDTH=1,PROBE203_MU_CNT=1,PROBE204_WIDTH=1,PROBE204_MU_CNT=1,PROBE205_WIDTH=1,PROBE205_MU_CNT=1,PROBE206_WIDTH=1,PROBE206_MU_CNT=1,PROBE207_WIDTH=1,PROBE207_MU_CNT=1,PROBE208_WIDTH=1,PROBE208_MU_CNT=1,PROBE209_WIDTH=1,PROBE209_MU_CNT=1,PROBE210_WIDTH=1,PROBE210_MU_CNT=1,PROBE211_WIDTH=1,PROBE211_MU_CNT=1,PROBE212_WIDTH=1,PROBE212_MU_CNT=1,PROBE213_WIDTH=1,PROBE213_MU_CNT=1,PROBE214_WIDTH=1,PROBE214_MU_CNT=1,PROBE215_WIDTH=1,PROBE215_MU_CNT=1,PROBE216_WIDTH=1,PROBE216_MU_CNT=1,PROBE217_WIDTH=1,PROBE217_MU_CNT=1,PROBE218_WIDTH=1,PROBE218_MU_CNT=1,PROBE219_WIDTH=1,PROBE219_MU_CNT=1,PROBE220_WIDTH=1,PROBE220_MU_CNT=1,PROBE221_WIDTH=1,PROBE221_MU_CNT=1,PROBE222_WIDTH=1,PROBE222_MU_CNT=1,PROBE223_WIDTH=1,PROBE223_MU_CNT=1,PROBE224_WIDTH=1,PROBE224_MU_CNT=1,PROBE225_WIDTH=1,PROBE225_MU_CNT=1,PROBE226_WIDTH=1,PROBE226_MU_CNT=1,PROBE227_WIDTH=1,PROBE227_MU_CNT=1,PROBE228_WIDTH=1,PROBE228_MU_CNT=1,PROBE229_WIDTH=1,PROBE229_MU_CNT=1,PROBE230_WIDTH=1,PROBE230_MU_CNT=1,PROBE231_WIDTH=1,PROBE231_MU_CNT=1,PROBE232_WIDTH=1,PROBE232_MU_CNT=1,PROBE233_WIDTH=1,PROBE233_MU_CNT=1,PROBE234_WIDTH=1,PROBE234_MU_CNT=1,PROBE235_WIDTH=1,PROBE235_MU_CNT=1,PROBE236_WIDTH=1,PROBE236_MU_CNT=1,PROBE237_WIDTH=1,PROBE237_MU_CNT=1,PROBE238_WIDTH=1,PROBE238_MU_CNT=1,PROBE239_WIDTH=1,PROBE239_MU_CNT=1,PROBE240_WIDTH=1,PROBE240_MU_CNT=1,PROBE241_WIDTH=1,PROBE241_MU_CNT=1,PROBE242_WIDTH=1,PROBE242_MU_CNT=1,PROBE243_WIDTH=1,PROBE243_MU_CNT=1,PROBE244_WIDTH=1,PROBE244_MU_CNT=1,PROBE245_WIDTH=1,PROBE245_MU_CNT=1,PROBE246_WIDTH=1,PROBE246_MU_CNT=1,PROBE247_WIDTH=1,PROBE247_MU_CNT=1,PROBE248_WIDTH=1,PROBE248_MU_CNT=1,PROBE249_WIDTH=1,PROBE249_MU_CNT=1,PROBE250_WIDTH=1,PROBE250_MU_CNT=1,PROBE251_WIDTH=1,PROBE251_MU_CNT=1,PROBE252_WIDTH=1,PROBE252_MU_CNT=1,PROBE253_WIDTH=1,PROBE253_MU_CNT=1,PROBE254_WIDTH=1,PROBE254_MU_CNT=1,PROBE255_WIDTH=1,PROBE255_MU_CNT=1,PROBE256_WIDTH=1,PROBE256_MU_CNT=1,PROBE257_WIDTH=1,PROBE257_MU_CNT=1,PROBE258_WIDTH=1,PROBE258_MU_CNT=1,PROBE259_WIDTH=1,PROBE259_MU_CNT=1,PROBE260_WIDTH=1,PROBE260_MU_CNT=1,PROBE261_WIDTH=1,PROBE261_MU_CNT=1,PROBE262_WIDTH=1,PROBE262_MU_CNT=1,PROBE263_WIDTH=1,PROBE263_MU_CNT=1,PROBE264_WIDTH=1,PROBE264_MU_CNT=1,PROBE265_WIDTH=1,PROBE265_MU_CNT=1,PROBE266_WIDTH=1,PROBE266_MU_CNT=1,PROBE267_WIDTH=1,PROBE267_MU_CNT=1,PROBE268_WIDTH=1,PROBE268_MU_CNT=1,PROBE269_WIDTH=1,PROBE269_MU_CNT=1,PROBE270_WIDTH=1,PROBE270_MU_CNT=1,PROBE271_WIDTH=1,PROBE271_MU_CNT=1,PROBE272_WIDTH=1,PROBE272_MU_CNT=1,PROBE273_WIDTH=1,PROBE273_MU_CNT=1,PROBE274_WIDTH=1,PROBE274_MU_CNT=1,PROBE275_WIDTH=1,PROBE275_MU_CNT=1,PROBE276_WIDTH=1,PROBE276_MU_CNT=1,PROBE277_WIDTH=1,PROBE277_MU_CNT=1,PROBE278_WIDTH=1,PROBE278_MU_CNT=1,PROBE279_WIDTH=1,PROBE279_MU_CNT=1,PROBE280_WIDTH=1,PROBE280_MU_CNT=1,PROBE281_WIDTH=1,PROBE281_MU_CNT=1,PROBE282_WIDTH=1,PROBE282_MU_CNT=1,PROBE283_WIDTH=1,PROBE283_MU_CNT=1,PROBE284_WIDTH=1,PROBE284_MU_CNT=1,PROBE285_WIDTH=1,PROBE285_MU_CNT=1,PROBE286_WIDTH=1,PROBE286_MU_CNT=1,PROBE287_WIDTH=1,PROBE287_MU_CNT=1,PROBE288_WIDTH=1,PROBE288_MU_CNT=1,PROBE289_WIDTH=1,PROBE289_MU_CNT=1,PROBE290_WIDTH=1,PROBE290_MU_CNT=1,PROBE291_WIDTH=1,PROBE291_MU_CNT=1,PROBE292_WIDTH=1,PROBE292_MU_CNT=1,PROBE293_WIDTH=1,PROBE293_MU_CNT=1,PROBE294_WIDTH=1,PROBE294_MU_CNT=1,PROBE295_WIDTH=1,PROBE295_MU_CNT=1,PROBE296_WIDTH=1,PROBE296_MU_CNT=1,PROBE297_WIDTH=1,PROBE297_MU_CNT=1,PROBE298_WIDTH=1,PROBE298_MU_CNT=1,PROBE299_WIDTH=1,PROBE299_MU_CNT=1,PROBE300_WIDTH=1,PROBE300_MU_CNT=1,PROBE301_WIDTH=1,PROBE301_MU_CNT=1,PROBE302_WIDTH=1,PROBE302_MU_CNT=1,PROBE303_WIDTH=1,PROBE303_MU_CNT=1,PROBE304_WIDTH=1,PROBE304_MU_CNT=1,PROBE305_WIDTH=1,PROBE305_MU_CNT=1,PROBE306_WIDTH=1,PROBE306_MU_CNT=1,PROBE307_WIDTH=1,PROBE307_MU_CNT=1,PROBE308_WIDTH=1,PROBE308_MU_CNT=1,PROBE309_WIDTH=1,PROBE309_MU_CNT=1,PROBE310_WIDTH=1,PROBE310_MU_CNT=1,PROBE311_WIDTH=1,PROBE311_MU_CNT=1,PROBE312_WIDTH=1,PROBE312_MU_CNT=1,PROBE313_WIDTH=1,PROBE313_MU_CNT=1,PROBE314_WIDTH=1,PROBE314_MU_CNT=1,PROBE315_WIDTH=1,PROBE315_MU_CNT=1,PROBE316_WIDTH=1,PROBE316_MU_CNT=1,PROBE317_WIDTH=1,PROBE317_MU_CNT=1,PROBE318_WIDTH=1,PROBE318_MU_CNT=1,PROBE319_WIDTH=1,PROBE319_MU_CNT=1,PROBE320_WIDTH=1,PROBE320_MU_CNT=1,PROBE321_WIDTH=1,PROBE321_MU_CNT=1,PROBE322_WIDTH=1,PROBE322_MU_CNT=1,PROBE323_WIDTH=1,PROBE323_MU_CNT=1,PROBE324_WIDTH=1,PROBE324_MU_CNT=1,PROBE325_WIDTH=1,PROBE325_MU_CNT=1,PROBE326_WIDTH=1,PROBE326_MU_CNT=1,PROBE327_WIDTH=1,PROBE327_MU_CNT=1,PROBE328_WIDTH=1,PROBE328_MU_CNT=1,PROBE329_WIDTH=1,PROBE329_MU_CNT=1,PROBE330_WIDTH=1,PROBE330_MU_CNT=1,PROBE331_WIDTH=1,PROBE331_MU_CNT=1,PROBE332_WIDTH=1,PROBE332_MU_CNT=1,PROBE333_WIDTH=1,PROBE333_MU_CNT=1,PROBE334_WIDTH=1,PROBE334_MU_CNT=1,PROBE335_WIDTH=1,PROBE335_MU_CNT=1,PROBE336_WIDTH=1,PROBE336_MU_CNT=1,PROBE337_WIDTH=1,PROBE337_MU_CNT=1,PROBE338_WIDTH=1,PROBE338_MU_CNT=1,PROBE339_WIDTH=1,PROBE339_MU_CNT=1,PROBE340_WIDTH=1,PROBE340_MU_CNT=1,PROBE341_WIDTH=1,PROBE341_MU_CNT=1,PROBE342_WIDTH=1,PROBE342_MU_CNT=1,PROBE343_WIDTH=1,PROBE343_MU_CNT=1,PROBE344_WIDTH=1,PROBE344_MU_CNT=1,PROBE345_WIDTH=1,PROBE345_MU_CNT=1,PROBE346_WIDTH=1,PROBE346_MU_CNT=1,PROBE347_WIDTH=1,PROBE347_MU_CNT=1,PROBE348_WIDTH=1,PROBE348_MU_CNT=1,PROBE349_WIDTH=1,PROBE349_MU_CNT=1,PROBE350_WIDTH=1,PROBE350_MU_CNT=1,PROBE351_WIDTH=1,PROBE351_MU_CNT=1,PROBE352_WIDTH=1,PROBE352_MU_CNT=1,PROBE353_WIDTH=1,PROBE353_MU_CNT=1,PROBE354_WIDTH=1,PROBE354_MU_CNT=1,PROBE355_WIDTH=1,PROBE355_MU_CNT=1,PROBE356_WIDTH=1,PROBE356_MU_CNT=1,PROBE357_WIDTH=1,PROBE357_MU_CNT=1,PROBE358_WIDTH=1,PROBE358_MU_CNT=1,PROBE359_WIDTH=1,PROBE359_MU_CNT=1,PROBE360_WIDTH=1,PROBE360_MU_CNT=1,PROBE361_WIDTH=1,PROBE361_MU_CNT=1,PROBE362_WIDTH=1,PROBE362_MU_CNT=1,PROBE363_WIDTH=1,PROBE363_MU_CNT=1,PROBE364_WIDTH=1,PROBE364_MU_CNT=1,PROBE365_WIDTH=1,PROBE365_MU_CNT=1,PROBE366_WIDTH=1,PROBE366_MU_CNT=1,PROBE367_WIDTH=1,PROBE367_MU_CNT=1,PROBE368_WIDTH=1,PROBE368_MU_CNT=1,PROBE369_WIDTH=1,PROBE369_MU_CNT=1,PROBE370_WIDTH=1,PROBE370_MU_CNT=1,PROBE371_WIDTH=1,PROBE371_MU_CNT=1,PROBE372_WIDTH=1,PROBE372_MU_CNT=1,PROBE373_WIDTH=1,PROBE373_MU_CNT=1,PROBE374_WIDTH=1,PROBE374_MU_CNT=1,PROBE375_WIDTH=1,PROBE375_MU_CNT=1,PROBE376_WIDTH=1,PROBE376_MU_CNT=1,PROBE377_WIDTH=1,PROBE377_MU_CNT=1,PROBE378_WIDTH=1,PROBE378_MU_CNT=1,PROBE379_WIDTH=1,PROBE379_MU_CNT=1,PROBE380_WIDTH=1,PROBE380_MU_CNT=1,PROBE381_WIDTH=1,PROBE381_MU_CNT=1,PROBE382_WIDTH=1,PROBE382_MU_CNT=1,PROBE383_WIDTH=1,PROBE383_MU_CNT=1,PROBE384_WIDTH=1,PROBE384_MU_CNT=1,PROBE385_WIDTH=1,PROBE385_MU_CNT=1,PROBE386_WIDTH=1,PROBE386_MU_CNT=1,PROBE387_WIDTH=1,PROBE387_MU_CNT=1,PROBE388_WIDTH=1,PROBE388_MU_CNT=1,PROBE389_WIDTH=1,PROBE389_MU_CNT=1,PROBE390_WIDTH=1,PROBE390_MU_CNT=1,PROBE391_WIDTH=1,PROBE391_MU_CNT=1,PROBE392_WIDTH=1,PROBE392_MU_CNT=1,PROBE393_WIDTH=1,PROBE393_MU_CNT=1,PROBE394_WIDTH=1,PROBE394_MU_CNT=1,PROBE395_WIDTH=1,PROBE395_MU_CNT=1,PROBE396_WIDTH=1,PROBE396_MU_CNT=1,PROBE397_WIDTH=1,PROBE397_MU_CNT=1,PROBE398_WIDTH=1,PROBE398_MU_CNT=1,PROBE399_WIDTH=1,PROBE399_MU_CNT=1,PROBE400_WIDTH=1,PROBE400_MU_CNT=1,PROBE401_WIDTH=1,PROBE401_MU_CNT=1,PROBE402_WIDTH=1,PROBE402_MU_CNT=1,PROBE403_WIDTH=1,PROBE403_MU_CNT=1,PROBE404_WIDTH=1,PROBE404_MU_CNT=1,PROBE405_WIDTH=1,PROBE405_MU_CNT=1,PROBE406_WIDTH=1,PROBE406_MU_CNT=1,PROBE407_WIDTH=1,PROBE407_MU_CNT=1,PROBE408_WIDTH=1,PROBE408_MU_CNT=1,PROBE409_WIDTH=1,PROBE409_MU_CNT=1,PROBE410_WIDTH=1,PROBE410_MU_CNT=1,PROBE411_WIDTH=1,PROBE411_MU_CNT=1,PROBE412_WIDTH=1,PROBE412_MU_CNT=1,PROBE413_WIDTH=1,PROBE413_MU_CNT=1,PROBE414_WIDTH=1,PROBE414_MU_CNT=1,PROBE415_WIDTH=1,PROBE415_MU_CNT=1,PROBE416_WIDTH=1,PROBE416_MU_CNT=1,PROBE417_WIDTH=1,PROBE417_MU_CNT=1,PROBE418_WIDTH=1,PROBE418_MU_CNT=1,PROBE419_WIDTH=1,PROBE419_MU_CNT=1,PROBE420_WIDTH=1,PROBE420_MU_CNT=1,PROBE421_WIDTH=1,PROBE421_MU_CNT=1,PROBE422_WIDTH=1,PROBE422_MU_CNT=1,PROBE423_WIDTH=1,PROBE423_MU_CNT=1,PROBE424_WIDTH=1,PROBE424_MU_CNT=1,PROBE425_WIDTH=1,PROBE425_MU_CNT=1,PROBE426_WIDTH=1,PROBE426_MU_CNT=1,PROBE427_WIDTH=1,PROBE427_MU_CNT=1,PROBE428_WIDTH=1,PROBE428_MU_CNT=1,PROBE429_WIDTH=1,PROBE429_MU_CNT=1,PROBE430_WIDTH=1,PROBE430_MU_CNT=1,PROBE431_WIDTH=1,PROBE431_MU_CNT=1,PROBE432_WIDTH=1,PROBE432_MU_CNT=1,PROBE433_WIDTH=1,PROBE433_MU_CNT=1,PROBE434_WIDTH=1,PROBE434_MU_CNT=1,PROBE435_WIDTH=1,PROBE435_MU_CNT=1,PROBE436_WIDTH=1,PROBE436_MU_CNT=1,PROBE437_WIDTH=1,PROBE437_MU_CNT=1,PROBE438_WIDTH=1,PROBE438_MU_CNT=1,PROBE439_WIDTH=1,PROBE439_MU_CNT=1,PROBE440_WIDTH=1,PROBE440_MU_CNT=1,PROBE441_WIDTH=1,PROBE441_MU_CNT=1,PROBE442_WIDTH=1,PROBE442_MU_CNT=1,PROBE443_WIDTH=1,PROBE443_MU_CNT=1,PROBE444_WIDTH=1,PROBE444_MU_CNT=1,PROBE445_WIDTH=1,PROBE445_MU_CNT=1,PROBE446_WIDTH=1,PROBE446_MU_CNT=1,PROBE447_WIDTH=1,PROBE447_MU_CNT=1,PROBE448_WIDTH=1,PROBE448_MU_CNT=1,PROBE449_WIDTH=1,PROBE449_MU_CNT=1,PROBE450_WIDTH=1,PROBE450_MU_CNT=1,PROBE451_WIDTH=1,PROBE451_MU_CNT=1,PROBE452_WIDTH=1,PROBE452_MU_CNT=1,PROBE453_WIDTH=1,PROBE453_MU_CNT=1,PROBE454_WIDTH=1,PROBE454_MU_CNT=1,PROBE455_WIDTH=1,PROBE455_MU_CNT=1,PROBE456_WIDTH=1,PROBE456_MU_CNT=1,PROBE457_WIDTH=1,PROBE457_MU_CNT=1,PROBE458_WIDTH=1,PROBE458_MU_CNT=1,PROBE459_WIDTH=1,PROBE459_MU_CNT=1,PROBE460_WIDTH=1,PROBE460_MU_CNT=1,PROBE461_WIDTH=1,PROBE461_MU_CNT=1,PROBE462_WIDTH=1,PROBE462_MU_CNT=1,PROBE463_WIDTH=1,PROBE463_MU_CNT=1,PROBE464_WIDTH=1,PROBE464_MU_CNT=1,PROBE465_WIDTH=1,PROBE465_MU_CNT=1,PROBE466_WIDTH=1,PROBE466_MU_CNT=1,PROBE467_WIDTH=1,PROBE467_MU_CNT=1,PROBE468_WIDTH=1,PROBE468_MU_CNT=1,PROBE469_WIDTH=1,PROBE469_MU_CNT=1,PROBE470_WIDTH=1,PROBE470_MU_CNT=1,PROBE471_WIDTH=1,PROBE471_MU_CNT=1,PROBE472_WIDTH=1,PROBE472_MU_CNT=1,PROBE473_WIDTH=1,PROBE473_MU_CNT=1,PROBE474_WIDTH=1,PROBE474_MU_CNT=1,PROBE475_WIDTH=1,PROBE475_MU_CNT=1,PROBE476_WIDTH=1,PROBE476_MU_CNT=1,PROBE477_WIDTH=1,PROBE477_MU_CNT=1,PROBE478_WIDTH=1,PROBE478_MU_CNT=1,PROBE479_WIDTH=1,PROBE479_MU_CNT=1,PROBE480_WIDTH=1,PROBE480_MU_CNT=1,PROBE481_WIDTH=1,PROBE481_MU_CNT=1,PROBE482_WIDTH=1,PROBE482_MU_CNT=1,PROBE483_WIDTH=1,PROBE483_MU_CNT=1,PROBE484_WIDTH=1,PROBE484_MU_CNT=1,PROBE485_WIDTH=1,PROBE485_MU_CNT=1,PROBE486_WIDTH=1,PROBE486_MU_CNT=1,PROBE487_WIDTH=1,PROBE487_MU_CNT=1,PROBE488_WIDTH=1,PROBE488_MU_CNT=1,PROBE489_WIDTH=1,PROBE489_MU_CNT=1,PROBE490_WIDTH=1,PROBE490_MU_CNT=1,PROBE491_WIDTH=1,PROBE491_MU_CNT=1,PROBE492_WIDTH=1,PROBE492_MU_CNT=1,PROBE493_WIDTH=1,PROBE493_MU_CNT=1,PROBE494_WIDTH=1,PROBE494_MU_CNT=1,PROBE495_WIDTH=1,PROBE495_MU_CNT=1,PROBE496_WIDTH=1,PROBE496_MU_CNT=1,PROBE497_WIDTH=1,PROBE497_MU_CNT=1,PROBE498_WIDTH=1,PROBE498_MU_CNT=1,PROBE499_WIDTH=1,PROBE499_MU_CNT=1,PROBE500_WIDTH=1,PROBE500_MU_CNT=1,PROBE501_WIDTH=1,PROBE501_MU_CNT=1,PROBE502_WIDTH=1,PROBE502_MU_CNT=1,PROBE503_WIDTH=1,PROBE503_MU_CNT=1,PROBE504_WIDTH=1,PROBE504_MU_CNT=1,PROBE505_WIDTH=1,PROBE505_MU_CNT=1,PROBE506_WIDTH=1,PROBE506_MU_CNT=1,PROBE507_WIDTH=1,PROBE507_MU_CNT=1,PROBE508_WIDTH=1,PROBE508_MU_CNT=1,PROBE509_WIDTH=1,PROBE509_MU_CNT=1,PROBE510_WIDTH=1,PROBE510_MU_CNT=1,PROBE511_WIDTH=1,PROBE511_MU_CNT=1,PROBE512_WIDTH=1,PROBE512_MU_CNT=1,PROBE513_WIDTH=1,PROBE513_MU_CNT=1,PROBE514_WIDTH=1,PROBE514_MU_CNT=1,PROBE515_WIDTH=1,PROBE515_MU_CNT=1,PROBE516_WIDTH=1,PROBE516_MU_CNT=1,PROBE517_WIDTH=1,PROBE517_MU_CNT=1,PROBE518_WIDTH=1,PROBE518_MU_CNT=1,PROBE519_WIDTH=1,PROBE519_MU_CNT=1,PROBE520_WIDTH=1,PROBE520_MU_CNT=1,PROBE521_WIDTH=1,PROBE521_MU_CNT=1,PROBE522_WIDTH=1,PROBE522_MU_CNT=1,PROBE523_WIDTH=1,PROBE523_MU_CNT=1,PROBE524_WIDTH=1,PROBE524_MU_CNT=1,PROBE525_WIDTH=1,PROBE525_MU_CNT=1,PROBE526_WIDTH=1,PROBE526_MU_CNT=1,PROBE527_WIDTH=1,PROBE527_MU_CNT=1,PROBE528_WIDTH=1,PROBE528_MU_CNT=1,PROBE529_WIDTH=1,PROBE529_MU_CNT=1,PROBE530_WIDTH=1,PROBE530_MU_CNT=1,PROBE531_WIDTH=1,PROBE531_MU_CNT=1,PROBE532_WIDTH=1,PROBE532_MU_CNT=1,PROBE533_WIDTH=1,PROBE533_MU_CNT=1,PROBE534_WIDTH=1,PROBE534_MU_CNT=1,PROBE535_WIDTH=1,PROBE535_MU_CNT=1,PROBE536_WIDTH=1,PROBE536_MU_CNT=1,PROBE537_WIDTH=1,PROBE537_MU_CNT=1,PROBE538_WIDTH=1,PROBE538_MU_CNT=1,PROBE539_WIDTH=1,PROBE539_MU_CNT=1,PROBE540_WIDTH=1,PROBE540_MU_CNT=1,PROBE541_WIDTH=1,PROBE541_MU_CNT=1,PROBE542_WIDTH=1,PROBE542_MU_CNT=1,PROBE543_WIDTH=1,PROBE543_MU_CNT=1,PROBE544_WIDTH=1,PROBE544_MU_CNT=1,PROBE545_WIDTH=1,PROBE545_MU_CNT=1,PROBE546_WIDTH=1,PROBE546_MU_CNT=1,PROBE547_WIDTH=1,PROBE547_MU_CNT=1,PROBE548_WIDTH=1,PROBE548_MU_CNT=1,PROBE549_WIDTH=1,PROBE549_MU_CNT=1,PROBE550_WIDTH=1,PROBE550_MU_CNT=1,PROBE551_WIDTH=1,PROBE551_MU_CNT=1,PROBE552_WIDTH=1,PROBE552_MU_CNT=1,PROBE553_WIDTH=1,PROBE553_MU_CNT=1,PROBE554_WIDTH=1,PROBE554_MU_CNT=1,PROBE555_WIDTH=1,PROBE555_MU_CNT=1,PROBE556_WIDTH=1,PROBE556_MU_CNT=1,PROBE557_WIDTH=1,PROBE557_MU_CNT=1,PROBE558_WIDTH=1,PROBE558_MU_CNT=1,PROBE559_WIDTH=1,PROBE559_MU_CNT=1,PROBE560_WIDTH=1,PROBE560_MU_CNT=1,PROBE561_WIDTH=1,PROBE561_MU_CNT=1,PROBE562_WIDTH=1,PROBE562_MU_CNT=1,PROBE563_WIDTH=1,PROBE563_MU_CNT=1,PROBE564_WIDTH=1,PROBE564_MU_CNT=1,PROBE565_WIDTH=1,PROBE565_MU_CNT=1,PROBE566_WIDTH=1,PROBE566_MU_CNT=1,PROBE567_WIDTH=1,PROBE567_MU_CNT=1,PROBE568_WIDTH=1,PROBE568_MU_CNT=1,PROBE569_WIDTH=1,PROBE569_MU_CNT=1,PROBE570_WIDTH=1,PROBE570_MU_CNT=1,PROBE571_WIDTH=1,PROBE571_MU_CNT=1,PROBE572_WIDTH=1,PROBE572_MU_CNT=1,PROBE573_WIDTH=1,PROBE573_MU_CNT=1,PROBE574_WIDTH=1,PROBE574_MU_CNT=1,PROBE575_WIDTH=1,PROBE575_MU_CNT=1,PROBE576_WIDTH=1,PROBE576_MU_CNT=1,PROBE577_WIDTH=1,PROBE577_MU_CNT=1,PROBE578_WIDTH=1,PROBE578_MU_CNT=1,PROBE579_WIDTH=1,PROBE579_MU_CNT=1,PROBE580_WIDTH=1,PROBE580_MU_CNT=1,PROBE581_WIDTH=1,PROBE581_MU_CNT=1,PROBE582_WIDTH=1,PROBE582_MU_CNT=1,PROBE583_WIDTH=1,PROBE583_MU_CNT=1,PROBE584_WIDTH=1,PROBE584_MU_CNT=1,PROBE585_WIDTH=1,PROBE585_MU_CNT=1,PROBE586_WIDTH=1,PROBE586_MU_CNT=1,PROBE587_WIDTH=1,PROBE587_MU_CNT=1,PROBE588_WIDTH=1,PROBE588_MU_CNT=1,PROBE589_WIDTH=1,PROBE589_MU_CNT=1,PROBE590_WIDTH=1,PROBE590_MU_CNT=1,PROBE591_WIDTH=1,PROBE591_MU_CNT=1,PROBE592_WIDTH=1,PROBE592_MU_CNT=1,PROBE593_WIDTH=1,PROBE593_MU_CNT=1,PROBE594_WIDTH=1,PROBE594_MU_CNT=1,PROBE595_WIDTH=1,PROBE595_MU_CNT=1,PROBE596_WIDTH=1,PROBE596_MU_CNT=1,PROBE597_WIDTH=1,PROBE597_MU_CNT=1,PROBE598_WIDTH=1,PROBE598_MU_CNT=1,PROBE599_WIDTH=1,PROBE599_MU_CNT=1,PROBE600_WIDTH=1,PROBE600_MU_CNT=1,PROBE601_WIDTH=1,PROBE601_MU_CNT=1,PROBE602_WIDTH=1,PROBE602_MU_CNT=1,PROBE603_WIDTH=1,PROBE603_MU_CNT=1,PROBE604_WIDTH=1,PROBE604_MU_CNT=1,PROBE605_WIDTH=1,PROBE605_MU_CNT=1,PROBE606_WIDTH=1,PROBE606_MU_CNT=1,PROBE607_WIDTH=1,PROBE607_MU_CNT=1,PROBE608_WIDTH=1,PROBE608_MU_CNT=1,PROBE609_WIDTH=1,PROBE609_MU_CNT=1,PROBE610_WIDTH=1,PROBE610_MU_CNT=1,PROBE611_WIDTH=1,PROBE611_MU_CNT=1,PROBE612_WIDTH=1,PROBE612_MU_CNT=1,PROBE613_WIDTH=1,PROBE613_MU_CNT=1,PROBE614_WIDTH=1,PROBE614_MU_CNT=1,PROBE615_WIDTH=1,PROBE615_MU_CNT=1,PROBE616_WIDTH=1,PROBE616_MU_CNT=1,PROBE617_WIDTH=1,PROBE617_MU_CNT=1,PROBE618_WIDTH=1,PROBE618_MU_CNT=1,PROBE619_WIDTH=1,PROBE619_MU_CNT=1,PROBE620_WIDTH=1,PROBE620_MU_CNT=1,PROBE621_WIDTH=1,PROBE621_MU_CNT=1,PROBE622_WIDTH=1,PROBE622_MU_CNT=1,PROBE623_WIDTH=1,PROBE623_MU_CNT=1,PROBE624_WIDTH=1,PROBE624_MU_CNT=1,PROBE625_WIDTH=1,PROBE625_MU_CNT=1,PROBE626_WIDTH=1,PROBE626_MU_CNT=1,PROBE627_WIDTH=1,PROBE627_MU_CNT=1,PROBE628_WIDTH=1,PROBE628_MU_CNT=1,PROBE629_WIDTH=1,PROBE629_MU_CNT=1,PROBE630_WIDTH=1,PROBE630_MU_CNT=1,PROBE631_WIDTH=1,PROBE631_MU_CNT=1,PROBE632_WIDTH=1,PROBE632_MU_CNT=1,PROBE633_WIDTH=1,PROBE633_MU_CNT=1,PROBE634_WIDTH=1,PROBE634_MU_CNT=1,PROBE635_WIDTH=1,PROBE635_MU_CNT=1,PROBE636_WIDTH=1,PROBE636_MU_CNT=1,PROBE637_WIDTH=1,PROBE637_MU_CNT=1,PROBE638_WIDTH=1,PROBE638_MU_CNT=1,PROBE639_WIDTH=1,PROBE639_MU_CNT=1,PROBE640_WIDTH=1,PROBE640_MU_CNT=1,PROBE641_WIDTH=1,PROBE641_MU_CNT=1,PROBE642_WIDTH=1,PROBE642_MU_CNT=1,PROBE643_WIDTH=1,PROBE643_MU_CNT=1,PROBE644_WIDTH=1,PROBE644_MU_CNT=1,PROBE645_WIDTH=1,PROBE645_MU_CNT=1,PROBE646_WIDTH=1,PROBE646_MU_CNT=1,PROBE647_WIDTH=1,PROBE647_MU_CNT=1,PROBE648_WIDTH=1,PROBE648_MU_CNT=1,PROBE649_WIDTH=1,PROBE649_MU_CNT=1,PROBE650_WIDTH=1,PROBE650_MU_CNT=1,PROBE651_WIDTH=1,PROBE651_MU_CNT=1,PROBE652_WIDTH=1,PROBE652_MU_CNT=1,PROBE653_WIDTH=1,PROBE653_MU_CNT=1,PROBE654_WIDTH=1,PROBE654_MU_CNT=1,PROBE655_WIDTH=1,PROBE655_MU_CNT=1,PROBE656_WIDTH=1,PROBE656_MU_CNT=1,PROBE657_WIDTH=1,PROBE657_MU_CNT=1,PROBE658_WIDTH=1,PROBE658_MU_CNT=1,PROBE659_WIDTH=1,PROBE659_MU_CNT=1,PROBE660_WIDTH=1,PROBE660_MU_CNT=1,PROBE661_WIDTH=1,PROBE661_MU_CNT=1,PROBE662_WIDTH=1,PROBE662_MU_CNT=1,PROBE663_WIDTH=1,PROBE663_MU_CNT=1,PROBE664_WIDTH=1,PROBE664_MU_CNT=1,PROBE665_WIDTH=1,PROBE665_MU_CNT=1,PROBE666_WIDTH=1,PROBE666_MU_CNT=1,PROBE667_WIDTH=1,PROBE667_MU_CNT=1,PROBE668_WIDTH=1,PROBE668_MU_CNT=1,PROBE669_WIDTH=1,PROBE669_MU_CNT=1,PROBE670_WIDTH=1,PROBE670_MU_CNT=1,PROBE671_WIDTH=1,PROBE671_MU_CNT=1,PROBE672_WIDTH=1,PROBE672_MU_CNT=1,PROBE673_WIDTH=1,PROBE673_MU_CNT=1,PROBE674_WIDTH=1,PROBE674_MU_CNT=1,PROBE675_WIDTH=1,PROBE675_MU_CNT=1,PROBE676_WIDTH=1,PROBE676_MU_CNT=1,PROBE677_WIDTH=1,PROBE677_MU_CNT=1,PROBE678_WIDTH=1,PROBE678_MU_CNT=1,PROBE679_WIDTH=1,PROBE679_MU_CNT=1,PROBE680_WIDTH=1,PROBE680_MU_CNT=1,PROBE681_WIDTH=1,PROBE681_MU_CNT=1,PROBE682_WIDTH=1,PROBE682_MU_CNT=1,PROBE683_WIDTH=1,PROBE683_MU_CNT=1,PROBE684_WIDTH=1,PROBE684_MU_CNT=1,PROBE685_WIDTH=1,PROBE685_MU_CNT=1,PROBE686_WIDTH=1,PROBE686_MU_CNT=1,PROBE687_WIDTH=1,PROBE687_MU_CNT=1,PROBE688_WIDTH=1,PROBE688_MU_CNT=1,PROBE689_WIDTH=1,PROBE689_MU_CNT=1,PROBE690_WIDTH=1,PROBE690_MU_CNT=1,PROBE691_WIDTH=1,PROBE691_MU_CNT=1,PROBE692_WIDTH=1,PROBE692_MU_CNT=1,PROBE693_WIDTH=1,PROBE693_MU_CNT=1,PROBE694_WIDTH=1,PROBE694_MU_CNT=1,PROBE695_WIDTH=1,PROBE695_MU_CNT=1,PROBE696_WIDTH=1,PROBE696_MU_CNT=1,PROBE697_WIDTH=1,PROBE697_MU_CNT=1,PROBE698_WIDTH=1,PROBE698_MU_CNT=1,PROBE699_WIDTH=1,PROBE699_MU_CNT=1,PROBE700_WIDTH=1,PROBE700_MU_CNT=1,PROBE701_WIDTH=1,PROBE701_MU_CNT=1,PROBE702_WIDTH=1,PROBE702_MU_CNT=1,PROBE703_WIDTH=1,PROBE703_MU_CNT=1,PROBE704_WIDTH=1,PROBE704_MU_CNT=1,PROBE705_WIDTH=1,PROBE705_MU_CNT=1,PROBE706_WIDTH=1,PROBE706_MU_CNT=1,PROBE707_WIDTH=1,PROBE707_MU_CNT=1,PROBE708_WIDTH=1,PROBE708_MU_CNT=1,PROBE709_WIDTH=1,PROBE709_MU_CNT=1,PROBE710_WIDTH=1,PROBE710_MU_CNT=1,PROBE711_WIDTH=1,PROBE711_MU_CNT=1,PROBE712_WIDTH=1,PROBE712_MU_CNT=1,PROBE713_WIDTH=1,PROBE713_MU_CNT=1,PROBE714_WIDTH=1,PROBE714_MU_CNT=1,PROBE715_WIDTH=1,PROBE715_MU_CNT=1,PROBE716_WIDTH=1,PROBE716_MU_CNT=1,PROBE717_WIDTH=1,PROBE717_MU_CNT=1,PROBE718_WIDTH=1,PROBE718_MU_CNT=1,PROBE719_WIDTH=1,PROBE719_MU_CNT=1,PROBE720_WIDTH=1,PROBE720_MU_CNT=1,PROBE721_WIDTH=1,PROBE721_MU_CNT=1,PROBE722_WIDTH=1,PROBE722_MU_CNT=1,PROBE723_WIDTH=1,PROBE723_MU_CNT=1,PROBE724_WIDTH=1,PROBE724_MU_CNT=1,PROBE725_WIDTH=1,PROBE725_MU_CNT=1,PROBE726_WIDTH=1,PROBE726_MU_CNT=1,PROBE727_WIDTH=1,PROBE727_MU_CNT=1,PROBE728_WIDTH=1,PROBE728_MU_CNT=1,PROBE729_WIDTH=1,PROBE729_MU_CNT=1,PROBE730_WIDTH=1,PROBE730_MU_CNT=1,PROBE731_WIDTH=1,PROBE731_MU_CNT=1,PROBE732_WIDTH=1,PROBE732_MU_CNT=1,PROBE733_WIDTH=1,PROBE733_MU_CNT=1,PROBE734_WIDTH=1,PROBE734_MU_CNT=1,PROBE735_WIDTH=1,PROBE735_MU_CNT=1,PROBE736_WIDTH=1,PROBE736_MU_CNT=1,PROBE737_WIDTH=1,PROBE737_MU_CNT=1,PROBE738_WIDTH=1,PROBE738_MU_CNT=1,PROBE739_WIDTH=1,PROBE739_MU_CNT=1,PROBE740_WIDTH=1,PROBE740_MU_CNT=1,PROBE741_WIDTH=1,PROBE741_MU_CNT=1,PROBE742_WIDTH=1,PROBE742_MU_CNT=1,PROBE743_WIDTH=1,PROBE743_MU_CNT=1,PROBE744_WIDTH=1,PROBE744_MU_CNT=1,PROBE745_WIDTH=1,PROBE745_MU_CNT=1,PROBE746_WIDTH=1,PROBE746_MU_CNT=1,PROBE747_WIDTH=1,PROBE747_MU_CNT=1,PROBE748_WIDTH=1,PROBE748_MU_CNT=1,PROBE749_WIDTH=1,PROBE749_MU_CNT=1,PROBE750_WIDTH=1,PROBE750_MU_CNT=1,PROBE751_WIDTH=1,PROBE751_MU_CNT=1,PROBE752_WIDTH=1,PROBE752_MU_CNT=1,PROBE753_WIDTH=1,PROBE753_MU_CNT=1,PROBE754_WIDTH=1,PROBE754_MU_CNT=1,PROBE755_WIDTH=1,PROBE755_MU_CNT=1,PROBE756_WIDTH=1,PROBE756_MU_CNT=1,PROBE757_WIDTH=1,PROBE757_MU_CNT=1,PROBE758_WIDTH=1,PROBE758_MU_CNT=1,PROBE759_WIDTH=1,PROBE759_MU_CNT=1,PROBE760_WIDTH=1,PROBE760_MU_CNT=1,PROBE761_WIDTH=1,PROBE761_MU_CNT=1,PROBE762_WIDTH=1,PROBE762_MU_CNT=1,PROBE763_WIDTH=1,PROBE763_MU_CNT=1,PROBE764_WIDTH=1,PROBE764_MU_CNT=1,PROBE765_WIDTH=1,PROBE765_MU_CNT=1,PROBE766_WIDTH=1,PROBE766_MU_CNT=1,PROBE767_WIDTH=1,PROBE767_MU_CNT=1,PROBE768_WIDTH=1,PROBE768_MU_CNT=1,PROBE769_WIDTH=1,PROBE769_MU_CNT=1,PROBE770_WIDTH=1,PROBE770_MU_CNT=1,PROBE771_WIDTH=1,PROBE771_MU_CNT=1,PROBE772_WIDTH=1,PROBE772_MU_CNT=1,PROBE773_WIDTH=1,PROBE773_MU_CNT=1,PROBE774_WIDTH=1,PROBE774_MU_CNT=1,PROBE775_WIDTH=1,PROBE775_MU_CNT=1,PROBE776_WIDTH=1,PROBE776_MU_CNT=1,PROBE777_WIDTH=1,PROBE777_MU_CNT=1,PROBE778_WIDTH=1,PROBE778_MU_CNT=1,PROBE779_WIDTH=1,PROBE779_MU_CNT=1,PROBE780_WIDTH=1,PROBE780_MU_CNT=1,PROBE781_WIDTH=1,PROBE781_MU_CNT=1,PROBE782_WIDTH=1,PROBE782_MU_CNT=1,PROBE783_WIDTH=1,PROBE783_MU_CNT=1,PROBE784_WIDTH=1,PROBE784_MU_CNT=1,PROBE785_WIDTH=1,PROBE785_MU_CNT=1,PROBE786_WIDTH=1,PROBE786_MU_CNT=1,PROBE787_WIDTH=1,PROBE787_MU_CNT=1,PROBE788_WIDTH=1,PROBE788_MU_CNT=1,PROBE789_WIDTH=1,PROBE789_MU_CNT=1,PROBE790_WIDTH=1,PROBE790_MU_CNT=1,PROBE791_WIDTH=1,PROBE791_MU_CNT=1,PROBE792_WIDTH=1,PROBE792_MU_CNT=1,PROBE793_WIDTH=1,PROBE793_MU_CNT=1,PROBE794_WIDTH=1,PROBE794_MU_CNT=1,PROBE795_WIDTH=1,PROBE795_MU_CNT=1,PROBE796_WIDTH=1,PROBE796_MU_CNT=1,PROBE797_WIDTH=1,PROBE797_MU_CNT=1,PROBE798_WIDTH=1,PROBE798_MU_CNT=1,PROBE799_WIDTH=1,PROBE799_MU_CNT=1,PROBE800_WIDTH=1,PROBE800_MU_CNT=1,PROBE801_WIDTH=1,PROBE801_MU_CNT=1,PROBE802_WIDTH=1,PROBE802_MU_CNT=1,PROBE803_WIDTH=1,PROBE803_MU_CNT=1,PROBE804_WIDTH=1,PROBE804_MU_CNT=1,PROBE805_WIDTH=1,PROBE805_MU_CNT=1,PROBE806_WIDTH=1,PROBE806_MU_CNT=1,PROBE807_WIDTH=1,PROBE807_MU_CNT=1,PROBE808_WIDTH=1,PROBE808_MU_CNT=1,PROBE809_WIDTH=1,PROBE809_MU_CNT=1,PROBE810_WIDTH=1,PROBE810_MU_CNT=1,PROBE811_WIDTH=1,PROBE811_MU_CNT=1,PROBE812_WIDTH=1,PROBE812_MU_CNT=1,PROBE813_WIDTH=1,PROBE813_MU_CNT=1,PROBE814_WIDTH=1,PROBE814_MU_CNT=1,PROBE815_WIDTH=1,PROBE815_MU_CNT=1,PROBE816_WIDTH=1,PROBE816_MU_CNT=1,PROBE817_WIDTH=1,PROBE817_MU_CNT=1,PROBE818_WIDTH=1,PROBE818_MU_CNT=1,PROBE819_WIDTH=1,PROBE819_MU_CNT=1,PROBE820_WIDTH=1,PROBE820_MU_CNT=1,PROBE821_WIDTH=1,PROBE821_MU_CNT=1,PROBE822_WIDTH=1,PROBE822_MU_CNT=1,PROBE823_WIDTH=1,PROBE823_MU_CNT=1,PROBE824_WIDTH=1,PROBE824_MU_CNT=1,PROBE825_WIDTH=1,PROBE825_MU_CNT=1,PROBE826_WIDTH=1,PROBE826_MU_CNT=1,PROBE827_WIDTH=1,PROBE827_MU_CNT=1,PROBE828_WIDTH=1,PROBE828_MU_CNT=1,PROBE829_WIDTH=1,PROBE829_MU_CNT=1,PROBE830_WIDTH=1,PROBE830_MU_CNT=1,PROBE831_WIDTH=1,PROBE831_MU_CNT=1,PROBE832_WIDTH=1,PROBE832_MU_CNT=1,PROBE833_WIDTH=1,PROBE833_MU_CNT=1,PROBE834_WIDTH=1,PROBE834_MU_CNT=1,PROBE835_WIDTH=1,PROBE835_MU_CNT=1,PROBE836_WIDTH=1,PROBE836_MU_CNT=1,PROBE837_WIDTH=1,PROBE837_MU_CNT=1,PROBE838_WIDTH=1,PROBE838_MU_CNT=1,PROBE839_WIDTH=1,PROBE839_MU_CNT=1,PROBE840_WIDTH=1,PROBE840_MU_CNT=1,PROBE841_WIDTH=1,PROBE841_MU_CNT=1,PROBE842_WIDTH=1,PROBE842_MU_CNT=1,PROBE843_WIDTH=1,PROBE843_MU_CNT=1,PROBE844_WIDTH=1,PROBE844_MU_CNT=1,PROBE845_WIDTH=1,PROBE845_MU_CNT=1,PROBE846_WIDTH=1,PROBE846_MU_CNT=1,PROBE847_WIDTH=1,PROBE847_MU_CNT=1,PROBE848_WIDTH=1,PROBE848_MU_CNT=1,PROBE849_WIDTH=1,PROBE849_MU_CNT=1,PROBE850_WIDTH=1,PROBE850_MU_CNT=1,PROBE851_WIDTH=1,PROBE851_MU_CNT=1,PROBE852_WIDTH=1,PROBE852_MU_CNT=1,PROBE853_WIDTH=1,PROBE853_MU_CNT=1,PROBE854_WIDTH=1,PROBE854_MU_CNT=1,PROBE855_WIDTH=1,PROBE855_MU_CNT=1,PROBE856_WIDTH=1,PROBE856_MU_CNT=1,PROBE857_WIDTH=1,PROBE857_MU_CNT=1,PROBE858_WIDTH=1,PROBE858_MU_CNT=1,PROBE859_WIDTH=1,PROBE859_MU_CNT=1,PROBE860_WIDTH=1,PROBE860_MU_CNT=1,PROBE861_WIDTH=1,PROBE861_MU_CNT=1,PROBE862_WIDTH=1,PROBE862_MU_CNT=1,PROBE863_WIDTH=1,PROBE863_MU_CNT=1,PROBE864_WIDTH=1,PROBE864_MU_CNT=1,PROBE865_WIDTH=1,PROBE865_MU_CNT=1,PROBE866_WIDTH=1,PROBE866_MU_CNT=1,PROBE867_WIDTH=1,PROBE867_MU_CNT=1,PROBE868_WIDTH=1,PROBE868_MU_CNT=1,PROBE869_WIDTH=1,PROBE869_MU_CNT=1,PROBE870_WIDTH=1,PROBE870_MU_CNT=1,PROBE871_WIDTH=1,PROBE871_MU_CNT=1,PROBE872_WIDTH=1,PROBE872_MU_CNT=1,PROBE873_WIDTH=1,PROBE873_MU_CNT=1,PROBE874_WIDTH=1,PROBE874_MU_CNT=1,PROBE875_WIDTH=1,PROBE875_MU_CNT=1,PROBE876_WIDTH=1,PROBE876_MU_CNT=1,PROBE877_WIDTH=1,PROBE877_MU_CNT=1,PROBE878_WIDTH=1,PROBE878_MU_CNT=1,PROBE879_WIDTH=1,PROBE879_MU_CNT=1,PROBE880_WIDTH=1,PROBE880_MU_CNT=1,PROBE881_WIDTH=1,PROBE881_MU_CNT=1,PROBE882_WIDTH=1,PROBE882_MU_CNT=1,PROBE883_WIDTH=1,PROBE883_MU_CNT=1,PROBE884_WIDTH=1,PROBE884_MU_CNT=1,PROBE885_WIDTH=1,PROBE885_MU_CNT=1,PROBE886_WIDTH=1,PROBE886_MU_CNT=1,PROBE887_WIDTH=1,PROBE887_MU_CNT=1,PROBE888_WIDTH=1,PROBE888_MU_CNT=1,PROBE889_WIDTH=1,PROBE889_MU_CNT=1,PROBE890_WIDTH=1,PROBE890_MU_CNT=1,PROBE891_WIDTH=1,PROBE891_MU_CNT=1,PROBE892_WIDTH=1,PROBE892_MU_CNT=1,PROBE893_WIDTH=1,PROBE893_MU_CNT=1,PROBE894_WIDTH=1,PROBE894_MU_CNT=1,PROBE895_WIDTH=1,PROBE895_MU_CNT=1,PROBE896_WIDTH=1,PROBE896_MU_CNT=1,PROBE897_WIDTH=1,PROBE897_MU_CNT=1,PROBE898_WIDTH=1,PROBE898_MU_CNT=1,PROBE899_WIDTH=1,PROBE899_MU_CNT=1,PROBE900_WIDTH=1,PROBE900_MU_CNT=1,PROBE901_WIDTH=1,PROBE901_MU_CNT=1,PROBE902_WIDTH=1,PROBE902_MU_CNT=1,PROBE903_WIDTH=1,PROBE903_MU_CNT=1,PROBE904_WIDTH=1,PROBE904_MU_CNT=1,PROBE905_WIDTH=1,PROBE905_MU_CNT=1,PROBE906_WIDTH=1,PROBE906_MU_CNT=1,PROBE907_WIDTH=1,PROBE907_MU_CNT=1,PROBE908_WIDTH=1,PROBE908_MU_CNT=1,PROBE909_WIDTH=1,PROBE909_MU_CNT=1,PROBE910_WIDTH=1,PROBE910_MU_CNT=1,PROBE911_WIDTH=1,PROBE911_MU_CNT=1,PROBE912_WIDTH=1,PROBE912_MU_CNT=1,PROBE913_WIDTH=1,PROBE913_MU_CNT=1,PROBE914_WIDTH=1,PROBE914_MU_CNT=1,PROBE915_WIDTH=1,PROBE915_MU_CNT=1,PROBE916_WIDTH=1,PROBE916_MU_CNT=1,PROBE917_WIDTH=1,PROBE917_MU_CNT=1,PROBE918_WIDTH=1,PROBE918_MU_CNT=1,PROBE919_WIDTH=1,PROBE919_MU_CNT=1,PROBE920_WIDTH=1,PROBE920_MU_CNT=1,PROBE921_WIDTH=1,PROBE921_MU_CNT=1,PROBE922_WIDTH=1,PROBE922_MU_CNT=1,PROBE923_WIDTH=1,PROBE923_MU_CNT=1,PROBE924_WIDTH=1,PROBE924_MU_CNT=1,PROBE925_WIDTH=1,PROBE925_MU_CNT=1,PROBE926_WIDTH=1,PROBE926_MU_CNT=1,PROBE927_WIDTH=1,PROBE927_MU_CNT=1,PROBE928_WIDTH=1,PROBE928_MU_CNT=1,PROBE929_WIDTH=1,PROBE929_MU_CNT=1,PROBE930_WIDTH=1,PROBE930_MU_CNT=1,PROBE931_WIDTH=1,PROBE931_MU_CNT=1,PROBE932_WIDTH=1,PROBE932_MU_CNT=1,PROBE933_WIDTH=1,PROBE933_MU_CNT=1,PROBE934_WIDTH=1,PROBE934_MU_CNT=1,PROBE935_WIDTH=1,PROBE935_MU_CNT=1,PROBE936_WIDTH=1,PROBE936_MU_CNT=1,PROBE937_WIDTH=1,PROBE937_MU_CNT=1,PROBE938_WIDTH=1,PROBE938_MU_CNT=1,PROBE939_WIDTH=1,PROBE939_MU_CNT=1,PROBE940_WIDTH=1,PROBE940_MU_CNT=1,PROBE941_WIDTH=1,PROBE941_MU_CNT=1,PROBE942_WIDTH=1,PROBE942_MU_CNT=1,PROBE943_WIDTH=1,PROBE943_MU_CNT=1,PROBE944_WIDTH=1,PROBE944_MU_CNT=1,PROBE945_WIDTH=1,PROBE945_MU_CNT=1,PROBE946_WIDTH=1,PROBE946_MU_CNT=1,PROBE947_WIDTH=1,PROBE947_MU_CNT=1,PROBE948_WIDTH=1,PROBE948_MU_CNT=1,PROBE949_WIDTH=1,PROBE949_MU_CNT=1,PROBE950_WIDTH=1,PROBE950_MU_CNT=1,PROBE951_WIDTH=1,PROBE951_MU_CNT=1,PROBE952_WIDTH=1,PROBE952_MU_CNT=1,PROBE953_WIDTH=1,PROBE953_MU_CNT=1,PROBE954_WIDTH=1,PROBE954_MU_CNT=1,PROBE955_WIDTH=1,PROBE955_MU_CNT=1,PROBE956_WIDTH=1,PROBE956_MU_CNT=1,PROBE957_WIDTH=1,PROBE957_MU_CNT=1,PROBE958_WIDTH=1,PROBE958_MU_CNT=1,PROBE959_WIDTH=1,PROBE959_MU_CNT=1,PROBE960_WIDTH=1,PROBE960_MU_CNT=1,PROBE961_WIDTH=1,PROBE961_MU_CNT=1,PROBE962_WIDTH=1,PROBE962_MU_CNT=1,PROBE963_WIDTH=1,PROBE963_MU_CNT=1,PROBE964_WIDTH=1,PROBE964_MU_CNT=1,PROBE965_WIDTH=1,PROBE965_MU_CNT=1,PROBE966_WIDTH=1,PROBE966_MU_CNT=1,PROBE967_WIDTH=1,PROBE967_MU_CNT=1,PROBE968_WIDTH=1,PROBE968_MU_CNT=1,PROBE969_WIDTH=1,PROBE969_MU_CNT=1,PROBE970_WIDTH=1,PROBE970_MU_CNT=1,PROBE971_WIDTH=1,PROBE971_MU_CNT=1,PROBE972_WIDTH=1,PROBE972_MU_CNT=1,PROBE973_WIDTH=1,PROBE973_MU_CNT=1,PROBE974_WIDTH=1,PROBE974_MU_CNT=1,PROBE975_WIDTH=1,PROBE975_MU_CNT=1,PROBE976_WIDTH=1,PROBE976_MU_CNT=1,PROBE977_WIDTH=1,PROBE977_MU_CNT=1,PROBE978_WIDTH=1,PROBE978_MU_CNT=1,PROBE979_WIDTH=1,PROBE979_MU_CNT=1,PROBE980_WIDTH=1,PROBE980_MU_CNT=1,PROBE981_WIDTH=1,PROBE981_MU_CNT=1,PROBE982_WIDTH=1,PROBE982_MU_CNT=1,PROBE983_WIDTH=1,PROBE983_MU_CNT=1,PROBE984_WIDTH=1,PROBE984_MU_CNT=1,PROBE985_WIDTH=1,PROBE985_MU_CNT=1,PROBE986_WIDTH=1,PROBE986_MU_CNT=1,PROBE987_WIDTH=1,PROBE987_MU_CNT=1,PROBE988_WIDTH=1,PROBE988_MU_CNT=1,PROBE989_WIDTH=1,PROBE989_MU_CNT=1,PROBE990_WIDTH=1,PROBE990_MU_CNT=1,PROBE991_WIDTH=1,PROBE991_MU_CNT=1,PROBE992_WIDTH=1,PROBE992_MU_CNT=1,PROBE993_WIDTH=1,PROBE993_MU_CNT=1,PROBE994_WIDTH=1,PROBE994_MU_CNT=1,PROBE995_WIDTH=1,PROBE995_MU_CNT=1,PROBE996_WIDTH=1,PROBE996_MU_CNT=1,PROBE997_WIDTH=1,PROBE997_MU_CNT=1,PROBE998_WIDTH=1,PROBE998_MU_CNT=1,PROBE999_WIDTH=1,PROBE999_MU_CNT=1,PROBE1000_WIDTH=1,PROBE1000_MU_CNT=1,PROBE1001_WIDTH=1,PROBE1001_MU_CNT=1,PROBE1002_WIDTH=1,PROBE1002_MU_CNT=1,PROBE1003_WIDTH=1,PROBE1003_MU_CNT=1,PROBE1004_WIDTH=1,PROBE1004_MU_CNT=1,PROBE1005_WIDTH=1,PROBE1005_MU_CNT=1,PROBE1006_WIDTH=1,PROBE1006_MU_CNT=1,PROBE1007_WIDTH=1,PROBE1007_MU_CNT=1,PROBE1008_WIDTH=1,PROBE1008_MU_CNT=1,PROBE1009_WIDTH=1,PROBE1009_MU_CNT=1,PROBE1010_WIDTH=1,PROBE1010_MU_CNT=1,PROBE1011_WIDTH=1,PROBE1011_MU_CNT=1,PROBE1012_WIDTH=1,PROBE1012_MU_CNT=1,PROBE1013_WIDTH=1,PROBE1013_MU_CNT=1,PROBE1014_WIDTH=1,PROBE1014_MU_CNT=1,PROBE1015_WIDTH=1,PROBE1015_MU_CNT=1,PROBE1016_WIDTH=1,PROBE1016_MU_CNT=1,PROBE1017_WIDTH=1,PROBE1017_MU_CNT=1,PROBE1018_WIDTH=1,PROBE1018_MU_CNT=1,PROBE1019_WIDTH=1,PROBE1019_MU_CNT=1,PROBE1020_WIDTH=1,PROBE1020_MU_CNT=1,PROBE1021_WIDTH=1,PROBE1021_MU_CNT=1,PROBE1022_WIDTH=1,PROBE1022_MU_CNT=1,PROBE1023_WIDTH=1,PROBE1023_MU_CNT=1" *) (* C_XDEVICEFAMILY = "artix7" *) 
(* C_CORE_TYPE = "1" *) (* C_CORE_INFO1 = "0" *) (* C_CORE_INFO2 = "0" *) 
(* C_CAPTURE_TYPE = "0" *) (* C_MU_TYPE = "0" *) (* C_TC_TYPE = "0" *) 
(* C_NUM_OF_PROBES = "13" *) (* C_DATA_DEPTH = "1024" *) (* C_MAJOR_VERSION = "2013" *) 
(* C_MINOR_VERSION = "3" *) (* C_BUILD_REVISION = "0" *) (* C_CORE_MAJOR_VER = "4" *) 
(* C_CORE_MINOR_VER = "0" *) (* C_XSDB_SLAVE_TYPE = "17" *) (* C_NEXT_SLAVE = "0" *) 
(* C_CSE_DRV_VER = "1" *) (* C_USE_TEST_REG = "1" *) (* C_PIPE_IFACE = "1" *) 
(* C_RAM_STYLE = "SUBCORE" *) (* C_TRIGOUT_EN = "0" *) (* C_TRIGIN_EN = "0" *) 
(* C_PROBE0_WIDTH = "32" *) (* C_PROBE1_WIDTH = "1" *) (* C_PROBE2_WIDTH = "1" *) 
(* C_PROBE3_WIDTH = "32" *) (* C_PROBE4_WIDTH = "1" *) (* C_PROBE5_WIDTH = "1" *) 
(* C_PROBE6_WIDTH = "32" *) (* C_PROBE7_WIDTH = "1" *) (* C_PROBE8_WIDTH = "1" *) 
(* C_PROBE9_WIDTH = "32" *) (* C_PROBE10_WIDTH = "1" *) (* C_PROBE11_WIDTH = "1" *) 
(* C_PROBE12_WIDTH = "4" *) (* C_PROBE13_WIDTH = "1" *) (* C_PROBE14_WIDTH = "1" *) 
(* C_PROBE15_WIDTH = "1" *) (* C_PROBE16_WIDTH = "1" *) (* C_PROBE17_WIDTH = "1" *) 
(* C_PROBE18_WIDTH = "1" *) (* C_PROBE19_WIDTH = "1" *) (* C_PROBE20_WIDTH = "1" *) 
(* C_PROBE21_WIDTH = "1" *) (* C_PROBE22_WIDTH = "1" *) (* C_PROBE23_WIDTH = "1" *) 
(* C_PROBE24_WIDTH = "1" *) (* C_PROBE25_WIDTH = "1" *) (* C_PROBE26_WIDTH = "1" *) 
(* C_PROBE27_WIDTH = "1" *) (* C_PROBE28_WIDTH = "1" *) (* C_PROBE29_WIDTH = "1" *) 
(* C_PROBE30_WIDTH = "1" *) (* C_PROBE31_WIDTH = "1" *) (* C_PROBE32_WIDTH = "1" *) 
(* C_PROBE33_WIDTH = "1" *) (* C_PROBE34_WIDTH = "1" *) (* C_PROBE35_WIDTH = "1" *) 
(* C_PROBE36_WIDTH = "1" *) (* C_PROBE37_WIDTH = "1" *) (* C_PROBE38_WIDTH = "1" *) 
(* C_PROBE39_WIDTH = "1" *) (* C_PROBE40_WIDTH = "1" *) (* C_PROBE41_WIDTH = "1" *) 
(* C_PROBE42_WIDTH = "1" *) (* C_PROBE43_WIDTH = "1" *) (* C_PROBE44_WIDTH = "1" *) 
(* C_PROBE45_WIDTH = "1" *) (* C_PROBE46_WIDTH = "1" *) (* C_PROBE47_WIDTH = "1" *) 
(* C_PROBE48_WIDTH = "1" *) (* C_PROBE49_WIDTH = "1" *) (* C_PROBE50_WIDTH = "1" *) 
(* C_PROBE51_WIDTH = "1" *) (* C_PROBE52_WIDTH = "1" *) (* C_PROBE53_WIDTH = "1" *) 
(* C_PROBE54_WIDTH = "1" *) (* C_PROBE55_WIDTH = "1" *) (* C_PROBE56_WIDTH = "1" *) 
(* C_PROBE57_WIDTH = "1" *) (* C_PROBE58_WIDTH = "1" *) (* C_PROBE59_WIDTH = "1" *) 
(* C_PROBE60_WIDTH = "1" *) (* C_PROBE61_WIDTH = "1" *) (* C_PROBE62_WIDTH = "1" *) 
(* C_PROBE63_WIDTH = "1" *) (* C_PROBE64_WIDTH = "1" *) (* C_PROBE65_WIDTH = "1" *) 
(* C_PROBE66_WIDTH = "1" *) (* C_PROBE67_WIDTH = "1" *) (* C_PROBE68_WIDTH = "1" *) 
(* C_PROBE69_WIDTH = "1" *) (* C_PROBE70_WIDTH = "1" *) (* C_PROBE71_WIDTH = "1" *) 
(* C_PROBE72_WIDTH = "1" *) (* C_PROBE73_WIDTH = "1" *) (* C_PROBE74_WIDTH = "1" *) 
(* C_PROBE75_WIDTH = "1" *) (* C_PROBE76_WIDTH = "1" *) (* C_PROBE77_WIDTH = "1" *) 
(* C_PROBE78_WIDTH = "1" *) (* C_PROBE79_WIDTH = "1" *) (* C_PROBE80_WIDTH = "1" *) 
(* C_PROBE81_WIDTH = "1" *) (* C_PROBE82_WIDTH = "1" *) (* C_PROBE83_WIDTH = "1" *) 
(* C_PROBE84_WIDTH = "1" *) (* C_PROBE85_WIDTH = "1" *) (* C_PROBE86_WIDTH = "1" *) 
(* C_PROBE87_WIDTH = "1" *) (* C_PROBE88_WIDTH = "1" *) (* C_PROBE89_WIDTH = "1" *) 
(* C_PROBE90_WIDTH = "1" *) (* C_PROBE91_WIDTH = "1" *) (* C_PROBE92_WIDTH = "1" *) 
(* C_PROBE93_WIDTH = "1" *) (* C_PROBE94_WIDTH = "1" *) (* C_PROBE95_WIDTH = "1" *) 
(* C_PROBE96_WIDTH = "1" *) (* C_PROBE97_WIDTH = "1" *) (* C_PROBE98_WIDTH = "1" *) 
(* C_PROBE99_WIDTH = "1" *) (* C_PROBE100_WIDTH = "1" *) (* C_PROBE101_WIDTH = "1" *) 
(* C_PROBE102_WIDTH = "1" *) (* C_PROBE103_WIDTH = "1" *) (* C_PROBE104_WIDTH = "1" *) 
(* C_PROBE105_WIDTH = "1" *) (* C_PROBE106_WIDTH = "1" *) (* C_PROBE107_WIDTH = "1" *) 
(* C_PROBE108_WIDTH = "1" *) (* C_PROBE109_WIDTH = "1" *) (* C_PROBE110_WIDTH = "1" *) 
(* C_PROBE111_WIDTH = "1" *) (* C_PROBE112_WIDTH = "1" *) (* C_PROBE113_WIDTH = "1" *) 
(* C_PROBE114_WIDTH = "1" *) (* C_PROBE115_WIDTH = "1" *) (* C_PROBE116_WIDTH = "1" *) 
(* C_PROBE117_WIDTH = "1" *) (* C_PROBE118_WIDTH = "1" *) (* C_PROBE119_WIDTH = "1" *) 
(* C_PROBE120_WIDTH = "1" *) (* C_PROBE121_WIDTH = "1" *) (* C_PROBE122_WIDTH = "1" *) 
(* C_PROBE123_WIDTH = "1" *) (* C_PROBE124_WIDTH = "1" *) (* C_PROBE125_WIDTH = "1" *) 
(* C_PROBE126_WIDTH = "1" *) (* C_PROBE127_WIDTH = "1" *) (* C_PROBE128_WIDTH = "1" *) 
(* C_PROBE129_WIDTH = "1" *) (* C_PROBE130_WIDTH = "1" *) (* C_PROBE131_WIDTH = "1" *) 
(* C_PROBE132_WIDTH = "1" *) (* C_PROBE133_WIDTH = "1" *) (* C_PROBE134_WIDTH = "1" *) 
(* C_PROBE135_WIDTH = "1" *) (* C_PROBE136_WIDTH = "1" *) (* C_PROBE137_WIDTH = "1" *) 
(* C_PROBE138_WIDTH = "1" *) (* C_PROBE139_WIDTH = "1" *) (* C_PROBE140_WIDTH = "1" *) 
(* C_PROBE141_WIDTH = "1" *) (* C_PROBE142_WIDTH = "1" *) (* C_PROBE143_WIDTH = "1" *) 
(* C_PROBE144_WIDTH = "1" *) (* C_PROBE145_WIDTH = "1" *) (* C_PROBE146_WIDTH = "1" *) 
(* C_PROBE147_WIDTH = "1" *) (* C_PROBE148_WIDTH = "1" *) (* C_PROBE149_WIDTH = "1" *) 
(* C_PROBE150_WIDTH = "1" *) (* C_PROBE151_WIDTH = "1" *) (* C_PROBE152_WIDTH = "1" *) 
(* C_PROBE153_WIDTH = "1" *) (* C_PROBE154_WIDTH = "1" *) (* C_PROBE155_WIDTH = "1" *) 
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(* C_PROBE741_WIDTH = "1" *) (* C_PROBE742_WIDTH = "1" *) (* C_PROBE743_WIDTH = "1" *) 
(* C_PROBE744_WIDTH = "1" *) (* C_PROBE745_WIDTH = "1" *) (* C_PROBE746_WIDTH = "1" *) 
(* C_PROBE747_WIDTH = "1" *) (* C_PROBE748_WIDTH = "1" *) (* C_PROBE749_WIDTH = "1" *) 
(* C_PROBE750_WIDTH = "1" *) (* C_PROBE751_WIDTH = "1" *) (* C_PROBE752_WIDTH = "1" *) 
(* C_PROBE753_WIDTH = "1" *) (* C_PROBE754_WIDTH = "1" *) (* C_PROBE755_WIDTH = "1" *) 
(* C_PROBE756_WIDTH = "1" *) (* C_PROBE757_WIDTH = "1" *) (* C_PROBE758_WIDTH = "1" *) 
(* C_PROBE759_WIDTH = "1" *) (* C_PROBE760_WIDTH = "1" *) (* C_PROBE761_WIDTH = "1" *) 
(* C_PROBE762_WIDTH = "1" *) (* C_PROBE763_WIDTH = "1" *) (* C_PROBE764_WIDTH = "1" *) 
(* C_PROBE765_WIDTH = "1" *) (* C_PROBE766_WIDTH = "1" *) (* C_PROBE767_WIDTH = "1" *) 
(* C_PROBE768_WIDTH = "1" *) (* C_PROBE769_WIDTH = "1" *) (* C_PROBE770_WIDTH = "1" *) 
(* C_PROBE771_WIDTH = "1" *) (* C_PROBE772_WIDTH = "1" *) (* C_PROBE773_WIDTH = "1" *) 
(* C_PROBE774_WIDTH = "1" *) (* C_PROBE775_WIDTH = "1" *) (* C_PROBE776_WIDTH = "1" *) 
(* C_PROBE777_WIDTH = "1" *) (* C_PROBE778_WIDTH = "1" *) (* C_PROBE779_WIDTH = "1" *) 
(* C_PROBE780_WIDTH = "1" *) (* C_PROBE781_WIDTH = "1" *) (* C_PROBE782_WIDTH = "1" *) 
(* C_PROBE783_WIDTH = "1" *) (* C_PROBE784_WIDTH = "1" *) (* C_PROBE785_WIDTH = "1" *) 
(* C_PROBE786_WIDTH = "1" *) (* C_PROBE787_WIDTH = "1" *) (* C_PROBE788_WIDTH = "1" *) 
(* C_PROBE789_WIDTH = "1" *) (* C_PROBE790_WIDTH = "1" *) (* C_PROBE791_WIDTH = "1" *) 
(* C_PROBE792_WIDTH = "1" *) (* C_PROBE793_WIDTH = "1" *) (* C_PROBE794_WIDTH = "1" *) 
(* C_PROBE795_WIDTH = "1" *) (* C_PROBE796_WIDTH = "1" *) (* C_PROBE797_WIDTH = "1" *) 
(* C_PROBE798_WIDTH = "1" *) (* C_PROBE799_WIDTH = "1" *) (* C_PROBE800_WIDTH = "1" *) 
(* C_PROBE801_WIDTH = "1" *) (* C_PROBE802_WIDTH = "1" *) (* C_PROBE803_WIDTH = "1" *) 
(* C_PROBE804_WIDTH = "1" *) (* C_PROBE805_WIDTH = "1" *) (* C_PROBE806_WIDTH = "1" *) 
(* C_PROBE807_WIDTH = "1" *) (* C_PROBE808_WIDTH = "1" *) (* C_PROBE809_WIDTH = "1" *) 
(* C_PROBE810_WIDTH = "1" *) (* C_PROBE811_WIDTH = "1" *) (* C_PROBE812_WIDTH = "1" *) 
(* C_PROBE813_WIDTH = "1" *) (* C_PROBE814_WIDTH = "1" *) (* C_PROBE815_WIDTH = "1" *) 
(* C_PROBE816_WIDTH = "1" *) (* C_PROBE817_WIDTH = "1" *) (* C_PROBE818_WIDTH = "1" *) 
(* C_PROBE819_WIDTH = "1" *) (* C_PROBE820_WIDTH = "1" *) (* C_PROBE821_WIDTH = "1" *) 
(* C_PROBE822_WIDTH = "1" *) (* C_PROBE823_WIDTH = "1" *) (* C_PROBE824_WIDTH = "1" *) 
(* C_PROBE825_WIDTH = "1" *) (* C_PROBE826_WIDTH = "1" *) (* C_PROBE827_WIDTH = "1" *) 
(* C_PROBE828_WIDTH = "1" *) (* C_PROBE829_WIDTH = "1" *) (* C_PROBE830_WIDTH = "1" *) 
(* C_PROBE831_WIDTH = "1" *) (* C_PROBE832_WIDTH = "1" *) (* C_PROBE833_WIDTH = "1" *) 
(* C_PROBE834_WIDTH = "1" *) (* C_PROBE835_WIDTH = "1" *) (* C_PROBE836_WIDTH = "1" *) 
(* C_PROBE837_WIDTH = "1" *) (* C_PROBE838_WIDTH = "1" *) (* C_PROBE839_WIDTH = "1" *) 
(* C_PROBE840_WIDTH = "1" *) (* C_PROBE841_WIDTH = "1" *) (* C_PROBE842_WIDTH = "1" *) 
(* C_PROBE843_WIDTH = "1" *) (* C_PROBE844_WIDTH = "1" *) (* C_PROBE845_WIDTH = "1" *) 
(* C_PROBE846_WIDTH = "1" *) (* C_PROBE847_WIDTH = "1" *) (* C_PROBE848_WIDTH = "1" *) 
(* C_PROBE849_WIDTH = "1" *) (* C_PROBE850_WIDTH = "1" *) (* C_PROBE851_WIDTH = "1" *) 
(* C_PROBE852_WIDTH = "1" *) (* C_PROBE853_WIDTH = "1" *) (* C_PROBE854_WIDTH = "1" *) 
(* C_PROBE855_WIDTH = "1" *) (* C_PROBE856_WIDTH = "1" *) (* C_PROBE857_WIDTH = "1" *) 
(* C_PROBE858_WIDTH = "1" *) (* C_PROBE859_WIDTH = "1" *) (* C_PROBE860_WIDTH = "1" *) 
(* C_PROBE861_WIDTH = "1" *) (* C_PROBE862_WIDTH = "1" *) (* C_PROBE863_WIDTH = "1" *) 
(* C_PROBE864_WIDTH = "1" *) (* C_PROBE865_WIDTH = "1" *) (* C_PROBE866_WIDTH = "1" *) 
(* C_PROBE867_WIDTH = "1" *) (* C_PROBE868_WIDTH = "1" *) (* C_PROBE869_WIDTH = "1" *) 
(* C_PROBE870_WIDTH = "1" *) (* C_PROBE871_WIDTH = "1" *) (* C_PROBE872_WIDTH = "1" *) 
(* C_PROBE873_WIDTH = "1" *) (* C_PROBE874_WIDTH = "1" *) (* C_PROBE875_WIDTH = "1" *) 
(* C_PROBE876_WIDTH = "1" *) (* C_PROBE877_WIDTH = "1" *) (* C_PROBE878_WIDTH = "1" *) 
(* C_PROBE879_WIDTH = "1" *) (* C_PROBE880_WIDTH = "1" *) (* C_PROBE881_WIDTH = "1" *) 
(* C_PROBE882_WIDTH = "1" *) (* C_PROBE883_WIDTH = "1" *) (* C_PROBE884_WIDTH = "1" *) 
(* C_PROBE885_WIDTH = "1" *) (* C_PROBE886_WIDTH = "1" *) (* C_PROBE887_WIDTH = "1" *) 
(* C_PROBE888_WIDTH = "1" *) (* C_PROBE889_WIDTH = "1" *) (* C_PROBE890_WIDTH = "1" *) 
(* C_PROBE891_WIDTH = "1" *) (* C_PROBE892_WIDTH = "1" *) (* C_PROBE893_WIDTH = "1" *) 
(* C_PROBE894_WIDTH = "1" *) (* C_PROBE895_WIDTH = "1" *) (* C_PROBE896_WIDTH = "1" *) 
(* C_PROBE897_WIDTH = "1" *) (* C_PROBE898_WIDTH = "1" *) (* C_PROBE899_WIDTH = "1" *) 
(* C_PROBE900_WIDTH = "1" *) (* C_PROBE901_WIDTH = "1" *) (* C_PROBE902_WIDTH = "1" *) 
(* C_PROBE903_WIDTH = "1" *) (* C_PROBE904_WIDTH = "1" *) (* C_PROBE905_WIDTH = "1" *) 
(* C_PROBE906_WIDTH = "1" *) (* C_PROBE907_WIDTH = "1" *) (* C_PROBE908_WIDTH = "1" *) 
(* C_PROBE909_WIDTH = "1" *) (* C_PROBE910_WIDTH = "1" *) (* C_PROBE911_WIDTH = "1" *) 
(* C_PROBE912_WIDTH = "1" *) (* C_PROBE913_WIDTH = "1" *) (* C_PROBE914_WIDTH = "1" *) 
(* C_PROBE915_WIDTH = "1" *) (* C_PROBE916_WIDTH = "1" *) (* C_PROBE917_WIDTH = "1" *) 
(* C_PROBE918_WIDTH = "1" *) (* C_PROBE919_WIDTH = "1" *) (* C_PROBE920_WIDTH = "1" *) 
(* C_PROBE921_WIDTH = "1" *) (* C_PROBE922_WIDTH = "1" *) (* C_PROBE923_WIDTH = "1" *) 
(* C_PROBE924_WIDTH = "1" *) (* C_PROBE925_WIDTH = "1" *) (* C_PROBE926_WIDTH = "1" *) 
(* C_PROBE927_WIDTH = "1" *) (* C_PROBE928_WIDTH = "1" *) (* C_PROBE929_WIDTH = "1" *) 
(* C_PROBE930_WIDTH = "1" *) (* C_PROBE931_WIDTH = "1" *) (* C_PROBE932_WIDTH = "1" *) 
(* C_PROBE933_WIDTH = "1" *) (* C_PROBE934_WIDTH = "1" *) (* C_PROBE935_WIDTH = "1" *) 
(* C_PROBE936_WIDTH = "1" *) (* C_PROBE937_WIDTH = "1" *) (* C_PROBE938_WIDTH = "1" *) 
(* C_PROBE939_WIDTH = "1" *) (* C_PROBE940_WIDTH = "1" *) (* C_PROBE941_WIDTH = "1" *) 
(* C_PROBE942_WIDTH = "1" *) (* C_PROBE943_WIDTH = "1" *) (* C_PROBE944_WIDTH = "1" *) 
(* C_PROBE945_WIDTH = "1" *) (* C_PROBE946_WIDTH = "1" *) (* C_PROBE947_WIDTH = "1" *) 
(* C_PROBE948_WIDTH = "1" *) (* C_PROBE949_WIDTH = "1" *) (* C_PROBE950_WIDTH = "1" *) 
(* C_PROBE951_WIDTH = "1" *) (* C_PROBE952_WIDTH = "1" *) (* C_PROBE953_WIDTH = "1" *) 
(* C_PROBE954_WIDTH = "1" *) (* C_PROBE955_WIDTH = "1" *) (* C_PROBE956_WIDTH = "1" *) 
(* C_PROBE957_WIDTH = "1" *) (* C_PROBE958_WIDTH = "1" *) (* C_PROBE959_WIDTH = "1" *) 
(* C_PROBE960_WIDTH = "1" *) (* C_PROBE961_WIDTH = "1" *) (* C_PROBE962_WIDTH = "1" *) 
(* C_PROBE963_WIDTH = "1" *) (* C_PROBE964_WIDTH = "1" *) (* C_PROBE965_WIDTH = "1" *) 
(* C_PROBE966_WIDTH = "1" *) (* C_PROBE967_WIDTH = "1" *) (* C_PROBE968_WIDTH = "1" *) 
(* C_PROBE969_WIDTH = "1" *) (* C_PROBE970_WIDTH = "1" *) (* C_PROBE971_WIDTH = "1" *) 
(* C_PROBE972_WIDTH = "1" *) (* C_PROBE973_WIDTH = "1" *) (* C_PROBE974_WIDTH = "1" *) 
(* C_PROBE975_WIDTH = "1" *) (* C_PROBE976_WIDTH = "1" *) (* C_PROBE977_WIDTH = "1" *) 
(* C_PROBE978_WIDTH = "1" *) (* C_PROBE979_WIDTH = "1" *) (* C_PROBE980_WIDTH = "1" *) 
(* C_PROBE981_WIDTH = "1" *) (* C_PROBE982_WIDTH = "1" *) (* C_PROBE983_WIDTH = "1" *) 
(* C_PROBE984_WIDTH = "1" *) (* C_PROBE985_WIDTH = "1" *) (* C_PROBE986_WIDTH = "1" *) 
(* C_PROBE987_WIDTH = "1" *) (* C_PROBE988_WIDTH = "1" *) (* C_PROBE989_WIDTH = "1" *) 
(* C_PROBE990_WIDTH = "1" *) (* C_PROBE991_WIDTH = "1" *) (* C_PROBE992_WIDTH = "1" *) 
(* C_PROBE993_WIDTH = "1" *) (* C_PROBE994_WIDTH = "1" *) (* C_PROBE995_WIDTH = "1" *) 
(* C_PROBE996_WIDTH = "1" *) (* C_PROBE997_WIDTH = "1" *) (* C_PROBE998_WIDTH = "1" *) 
(* C_PROBE999_WIDTH = "1" *) (* C_PROBE1000_WIDTH = "1" *) (* C_PROBE1001_WIDTH = "1" *) 
(* C_PROBE1002_WIDTH = "1" *) (* C_PROBE1003_WIDTH = "1" *) (* C_PROBE1004_WIDTH = "1" *) 
(* C_PROBE1005_WIDTH = "1" *) (* C_PROBE1006_WIDTH = "1" *) (* C_PROBE1007_WIDTH = "1" *) 
(* C_PROBE1008_WIDTH = "1" *) (* C_PROBE1009_WIDTH = "1" *) (* C_PROBE1010_WIDTH = "1" *) 
(* C_PROBE1011_WIDTH = "1" *) (* C_PROBE1012_WIDTH = "1" *) (* C_PROBE1013_WIDTH = "1" *) 
(* C_PROBE1014_WIDTH = "1" *) (* C_PROBE1015_WIDTH = "1" *) (* C_PROBE1016_WIDTH = "1" *) 
(* C_PROBE1017_WIDTH = "1" *) (* C_PROBE1018_WIDTH = "1" *) (* C_PROBE1019_WIDTH = "1" *) 
(* C_PROBE1020_WIDTH = "1" *) (* C_PROBE1021_WIDTH = "1" *) (* C_PROBE1022_WIDTH = "1" *) 
(* C_PROBE1023_WIDTH = "1" *) (* C_ADV_TRIGGER = "1" *) (* C_EN_STRG_QUAL = "0" *) 
(* C_INPUT_PIPE_STAGES = "0" *) (* C_PROBE0_MU_CNT = "1" *) (* C_PROBE1_MU_CNT = "1" *) 
(* C_PROBE2_MU_CNT = "1" *) (* C_PROBE3_MU_CNT = "1" *) (* C_PROBE4_MU_CNT = "1" *) 
(* C_PROBE5_MU_CNT = "1" *) (* C_PROBE6_MU_CNT = "1" *) (* C_PROBE7_MU_CNT = "1" *) 
(* C_PROBE8_MU_CNT = "1" *) (* C_PROBE9_MU_CNT = "1" *) (* C_PROBE10_MU_CNT = "1" *) 
(* C_PROBE11_MU_CNT = "1" *) (* C_PROBE12_MU_CNT = "1" *) (* C_PROBE13_MU_CNT = "1" *) 
(* C_PROBE14_MU_CNT = "1" *) (* C_PROBE15_MU_CNT = "1" *) (* C_PROBE16_MU_CNT = "1" *) 
(* C_PROBE17_MU_CNT = "1" *) (* C_PROBE18_MU_CNT = "1" *) (* C_PROBE19_MU_CNT = "1" *) 
(* C_PROBE20_MU_CNT = "1" *) (* C_PROBE21_MU_CNT = "1" *) (* C_PROBE22_MU_CNT = "1" *) 
(* C_PROBE23_MU_CNT = "1" *) (* C_PROBE24_MU_CNT = "1" *) (* C_PROBE25_MU_CNT = "1" *) 
(* C_PROBE26_MU_CNT = "1" *) (* C_PROBE27_MU_CNT = "1" *) (* C_PROBE28_MU_CNT = "1" *) 
(* C_PROBE29_MU_CNT = "1" *) (* C_PROBE30_MU_CNT = "1" *) (* C_PROBE31_MU_CNT = "1" *) 
(* C_PROBE32_MU_CNT = "1" *) (* C_PROBE33_MU_CNT = "1" *) (* C_PROBE34_MU_CNT = "1" *) 
(* C_PROBE35_MU_CNT = "1" *) (* C_PROBE36_MU_CNT = "1" *) (* C_PROBE37_MU_CNT = "1" *) 
(* C_PROBE38_MU_CNT = "1" *) (* C_PROBE39_MU_CNT = "1" *) (* C_PROBE40_MU_CNT = "1" *) 
(* C_PROBE41_MU_CNT = "1" *) (* C_PROBE42_MU_CNT = "1" *) (* C_PROBE43_MU_CNT = "1" *) 
(* C_PROBE44_MU_CNT = "1" *) (* C_PROBE45_MU_CNT = "1" *) (* C_PROBE46_MU_CNT = "1" *) 
(* C_PROBE47_MU_CNT = "1" *) (* C_PROBE48_MU_CNT = "1" *) (* C_PROBE49_MU_CNT = "1" *) 
(* C_PROBE50_MU_CNT = "1" *) (* C_PROBE51_MU_CNT = "1" *) (* C_PROBE52_MU_CNT = "1" *) 
(* C_PROBE53_MU_CNT = "1" *) (* C_PROBE54_MU_CNT = "1" *) (* C_PROBE55_MU_CNT = "1" *) 
(* C_PROBE56_MU_CNT = "1" *) (* C_PROBE57_MU_CNT = "1" *) (* C_PROBE58_MU_CNT = "1" *) 
(* C_PROBE59_MU_CNT = "1" *) (* C_PROBE60_MU_CNT = "1" *) (* C_PROBE61_MU_CNT = "1" *) 
(* C_PROBE62_MU_CNT = "1" *) (* C_PROBE63_MU_CNT = "1" *) (* C_PROBE64_MU_CNT = "1" *) 
(* C_PROBE65_MU_CNT = "1" *) (* C_PROBE66_MU_CNT = "1" *) (* C_PROBE67_MU_CNT = "1" *) 
(* C_PROBE68_MU_CNT = "1" *) (* C_PROBE69_MU_CNT = "1" *) (* C_PROBE70_MU_CNT = "1" *) 
(* C_PROBE71_MU_CNT = "1" *) (* C_PROBE72_MU_CNT = "1" *) (* C_PROBE73_MU_CNT = "1" *) 
(* C_PROBE74_MU_CNT = "1" *) (* C_PROBE75_MU_CNT = "1" *) (* C_PROBE76_MU_CNT = "1" *) 
(* C_PROBE77_MU_CNT = "1" *) (* C_PROBE78_MU_CNT = "1" *) (* C_PROBE79_MU_CNT = "1" *) 
(* C_PROBE80_MU_CNT = "1" *) (* C_PROBE81_MU_CNT = "1" *) (* C_PROBE82_MU_CNT = "1" *) 
(* C_PROBE83_MU_CNT = "1" *) (* C_PROBE84_MU_CNT = "1" *) (* C_PROBE85_MU_CNT = "1" *) 
(* C_PROBE86_MU_CNT = "1" *) (* C_PROBE87_MU_CNT = "1" *) (* C_PROBE88_MU_CNT = "1" *) 
(* C_PROBE89_MU_CNT = "1" *) (* C_PROBE90_MU_CNT = "1" *) (* C_PROBE91_MU_CNT = "1" *) 
(* C_PROBE92_MU_CNT = "1" *) (* C_PROBE93_MU_CNT = "1" *) (* C_PROBE94_MU_CNT = "1" *) 
(* C_PROBE95_MU_CNT = "1" *) (* C_PROBE96_MU_CNT = "1" *) (* C_PROBE97_MU_CNT = "1" *) 
(* C_PROBE98_MU_CNT = "1" *) (* C_PROBE99_MU_CNT = "1" *) (* C_PROBE100_MU_CNT = "1" *) 
(* C_PROBE101_MU_CNT = "1" *) (* C_PROBE102_MU_CNT = "1" *) (* C_PROBE103_MU_CNT = "1" *) 
(* C_PROBE104_MU_CNT = "1" *) (* C_PROBE105_MU_CNT = "1" *) (* C_PROBE106_MU_CNT = "1" *) 
(* C_PROBE107_MU_CNT = "1" *) (* C_PROBE108_MU_CNT = "1" *) (* C_PROBE109_MU_CNT = "1" *) 
(* C_PROBE110_MU_CNT = "1" *) (* C_PROBE111_MU_CNT = "1" *) (* C_PROBE112_MU_CNT = "1" *) 
(* C_PROBE113_MU_CNT = "1" *) (* C_PROBE114_MU_CNT = "1" *) (* C_PROBE115_MU_CNT = "1" *) 
(* C_PROBE116_MU_CNT = "1" *) (* C_PROBE117_MU_CNT = "1" *) (* C_PROBE118_MU_CNT = "1" *) 
(* C_PROBE119_MU_CNT = "1" *) (* C_PROBE120_MU_CNT = "1" *) (* C_PROBE121_MU_CNT = "1" *) 
(* C_PROBE122_MU_CNT = "1" *) (* C_PROBE123_MU_CNT = "1" *) (* C_PROBE124_MU_CNT = "1" *) 
(* C_PROBE125_MU_CNT = "1" *) (* C_PROBE126_MU_CNT = "1" *) (* C_PROBE127_MU_CNT = "1" *) 
(* C_PROBE128_MU_CNT = "1" *) (* C_PROBE129_MU_CNT = "1" *) (* C_PROBE130_MU_CNT = "1" *) 
(* C_PROBE131_MU_CNT = "1" *) (* C_PROBE132_MU_CNT = "1" *) (* C_PROBE133_MU_CNT = "1" *) 
(* C_PROBE134_MU_CNT = "1" *) (* C_PROBE135_MU_CNT = "1" *) (* C_PROBE136_MU_CNT = "1" *) 
(* C_PROBE137_MU_CNT = "1" *) (* C_PROBE138_MU_CNT = "1" *) (* C_PROBE139_MU_CNT = "1" *) 
(* C_PROBE140_MU_CNT = "1" *) (* C_PROBE141_MU_CNT = "1" *) (* C_PROBE142_MU_CNT = "1" *) 
(* C_PROBE143_MU_CNT = "1" *) (* C_PROBE144_MU_CNT = "1" *) (* C_PROBE145_MU_CNT = "1" *) 
(* C_PROBE146_MU_CNT = "1" *) (* C_PROBE147_MU_CNT = "1" *) (* C_PROBE148_MU_CNT = "1" *) 
(* C_PROBE149_MU_CNT = "1" *) (* C_PROBE150_MU_CNT = "1" *) (* C_PROBE151_MU_CNT = "1" *) 
(* C_PROBE152_MU_CNT = "1" *) (* C_PROBE153_MU_CNT = "1" *) (* C_PROBE154_MU_CNT = "1" *) 
(* C_PROBE155_MU_CNT = "1" *) (* C_PROBE156_MU_CNT = "1" *) (* C_PROBE157_MU_CNT = "1" *) 
(* C_PROBE158_MU_CNT = "1" *) (* C_PROBE159_MU_CNT = "1" *) (* C_PROBE160_MU_CNT = "1" *) 
(* C_PROBE161_MU_CNT = "1" *) (* C_PROBE162_MU_CNT = "1" *) (* C_PROBE163_MU_CNT = "1" *) 
(* C_PROBE164_MU_CNT = "1" *) (* C_PROBE165_MU_CNT = "1" *) (* C_PROBE166_MU_CNT = "1" *) 
(* C_PROBE167_MU_CNT = "1" *) (* C_PROBE168_MU_CNT = "1" *) (* C_PROBE169_MU_CNT = "1" *) 
(* C_PROBE170_MU_CNT = "1" *) (* C_PROBE171_MU_CNT = "1" *) (* C_PROBE172_MU_CNT = "1" *) 
(* C_PROBE173_MU_CNT = "1" *) (* C_PROBE174_MU_CNT = "1" *) (* C_PROBE175_MU_CNT = "1" *) 
(* C_PROBE176_MU_CNT = "1" *) (* C_PROBE177_MU_CNT = "1" *) (* C_PROBE178_MU_CNT = "1" *) 
(* C_PROBE179_MU_CNT = "1" *) (* C_PROBE180_MU_CNT = "1" *) (* C_PROBE181_MU_CNT = "1" *) 
(* C_PROBE182_MU_CNT = "1" *) (* C_PROBE183_MU_CNT = "1" *) (* C_PROBE184_MU_CNT = "1" *) 
(* C_PROBE185_MU_CNT = "1" *) (* C_PROBE186_MU_CNT = "1" *) (* C_PROBE187_MU_CNT = "1" *) 
(* C_PROBE188_MU_CNT = "1" *) (* C_PROBE189_MU_CNT = "1" *) (* C_PROBE190_MU_CNT = "1" *) 
(* C_PROBE191_MU_CNT = "1" *) (* C_PROBE192_MU_CNT = "1" *) (* C_PROBE193_MU_CNT = "1" *) 
(* C_PROBE194_MU_CNT = "1" *) (* C_PROBE195_MU_CNT = "1" *) (* C_PROBE196_MU_CNT = "1" *) 
(* C_PROBE197_MU_CNT = "1" *) (* C_PROBE198_MU_CNT = "1" *) (* C_PROBE199_MU_CNT = "1" *) 
(* C_PROBE200_MU_CNT = "1" *) (* C_PROBE201_MU_CNT = "1" *) (* C_PROBE202_MU_CNT = "1" *) 
(* C_PROBE203_MU_CNT = "1" *) (* C_PROBE204_MU_CNT = "1" *) (* C_PROBE205_MU_CNT = "1" *) 
(* C_PROBE206_MU_CNT = "1" *) (* C_PROBE207_MU_CNT = "1" *) (* C_PROBE208_MU_CNT = "1" *) 
(* C_PROBE209_MU_CNT = "1" *) (* C_PROBE210_MU_CNT = "1" *) (* C_PROBE211_MU_CNT = "1" *) 
(* C_PROBE212_MU_CNT = "1" *) (* C_PROBE213_MU_CNT = "1" *) (* C_PROBE214_MU_CNT = "1" *) 
(* C_PROBE215_MU_CNT = "1" *) (* C_PROBE216_MU_CNT = "1" *) (* C_PROBE217_MU_CNT = "1" *) 
(* C_PROBE218_MU_CNT = "1" *) (* C_PROBE219_MU_CNT = "1" *) (* C_PROBE220_MU_CNT = "1" *) 
(* C_PROBE221_MU_CNT = "1" *) (* C_PROBE222_MU_CNT = "1" *) (* C_PROBE223_MU_CNT = "1" *) 
(* C_PROBE224_MU_CNT = "1" *) (* C_PROBE225_MU_CNT = "1" *) (* C_PROBE226_MU_CNT = "1" *) 
(* C_PROBE227_MU_CNT = "1" *) (* C_PROBE228_MU_CNT = "1" *) (* C_PROBE229_MU_CNT = "1" *) 
(* C_PROBE230_MU_CNT = "1" *) (* C_PROBE231_MU_CNT = "1" *) (* C_PROBE232_MU_CNT = "1" *) 
(* C_PROBE233_MU_CNT = "1" *) (* C_PROBE234_MU_CNT = "1" *) (* C_PROBE235_MU_CNT = "1" *) 
(* C_PROBE236_MU_CNT = "1" *) (* C_PROBE237_MU_CNT = "1" *) (* C_PROBE238_MU_CNT = "1" *) 
(* C_PROBE239_MU_CNT = "1" *) (* C_PROBE240_MU_CNT = "1" *) (* C_PROBE241_MU_CNT = "1" *) 
(* C_PROBE242_MU_CNT = "1" *) (* C_PROBE243_MU_CNT = "1" *) (* C_PROBE244_MU_CNT = "1" *) 
(* C_PROBE245_MU_CNT = "1" *) (* C_PROBE246_MU_CNT = "1" *) (* C_PROBE247_MU_CNT = "1" *) 
(* C_PROBE248_MU_CNT = "1" *) (* C_PROBE249_MU_CNT = "1" *) (* C_PROBE250_MU_CNT = "1" *) 
(* C_PROBE251_MU_CNT = "1" *) (* C_PROBE252_MU_CNT = "1" *) (* C_PROBE253_MU_CNT = "1" *) 
(* C_PROBE254_MU_CNT = "1" *) (* C_PROBE255_MU_CNT = "1" *) (* C_PROBE256_MU_CNT = "1" *) 
(* C_PROBE257_MU_CNT = "1" *) (* C_PROBE258_MU_CNT = "1" *) (* C_PROBE259_MU_CNT = "1" *) 
(* C_PROBE260_MU_CNT = "1" *) (* C_PROBE261_MU_CNT = "1" *) (* C_PROBE262_MU_CNT = "1" *) 
(* C_PROBE263_MU_CNT = "1" *) (* C_PROBE264_MU_CNT = "1" *) (* C_PROBE265_MU_CNT = "1" *) 
(* C_PROBE266_MU_CNT = "1" *) (* C_PROBE267_MU_CNT = "1" *) (* C_PROBE268_MU_CNT = "1" *) 
(* C_PROBE269_MU_CNT = "1" *) (* C_PROBE270_MU_CNT = "1" *) (* C_PROBE271_MU_CNT = "1" *) 
(* C_PROBE272_MU_CNT = "1" *) (* C_PROBE273_MU_CNT = "1" *) (* C_PROBE274_MU_CNT = "1" *) 
(* C_PROBE275_MU_CNT = "1" *) (* C_PROBE276_MU_CNT = "1" *) (* C_PROBE277_MU_CNT = "1" *) 
(* C_PROBE278_MU_CNT = "1" *) (* C_PROBE279_MU_CNT = "1" *) (* C_PROBE280_MU_CNT = "1" *) 
(* C_PROBE281_MU_CNT = "1" *) (* C_PROBE282_MU_CNT = "1" *) (* C_PROBE283_MU_CNT = "1" *) 
(* C_PROBE284_MU_CNT = "1" *) (* C_PROBE285_MU_CNT = "1" *) (* C_PROBE286_MU_CNT = "1" *) 
(* C_PROBE287_MU_CNT = "1" *) (* C_PROBE288_MU_CNT = "1" *) (* C_PROBE289_MU_CNT = "1" *) 
(* C_PROBE290_MU_CNT = "1" *) (* C_PROBE291_MU_CNT = "1" *) (* C_PROBE292_MU_CNT = "1" *) 
(* C_PROBE293_MU_CNT = "1" *) (* C_PROBE294_MU_CNT = "1" *) (* C_PROBE295_MU_CNT = "1" *) 
(* C_PROBE296_MU_CNT = "1" *) (* C_PROBE297_MU_CNT = "1" *) (* C_PROBE298_MU_CNT = "1" *) 
(* C_PROBE299_MU_CNT = "1" *) (* C_PROBE300_MU_CNT = "1" *) (* C_PROBE301_MU_CNT = "1" *) 
(* C_PROBE302_MU_CNT = "1" *) (* C_PROBE303_MU_CNT = "1" *) (* C_PROBE304_MU_CNT = "1" *) 
(* C_PROBE305_MU_CNT = "1" *) (* C_PROBE306_MU_CNT = "1" *) (* C_PROBE307_MU_CNT = "1" *) 
(* C_PROBE308_MU_CNT = "1" *) (* C_PROBE309_MU_CNT = "1" *) (* C_PROBE310_MU_CNT = "1" *) 
(* C_PROBE311_MU_CNT = "1" *) (* C_PROBE312_MU_CNT = "1" *) (* C_PROBE313_MU_CNT = "1" *) 
(* C_PROBE314_MU_CNT = "1" *) (* C_PROBE315_MU_CNT = "1" *) (* C_PROBE316_MU_CNT = "1" *) 
(* C_PROBE317_MU_CNT = "1" *) (* C_PROBE318_MU_CNT = "1" *) (* C_PROBE319_MU_CNT = "1" *) 
(* C_PROBE320_MU_CNT = "1" *) (* C_PROBE321_MU_CNT = "1" *) (* C_PROBE322_MU_CNT = "1" *) 
(* C_PROBE323_MU_CNT = "1" *) (* C_PROBE324_MU_CNT = "1" *) (* C_PROBE325_MU_CNT = "1" *) 
(* C_PROBE326_MU_CNT = "1" *) (* C_PROBE327_MU_CNT = "1" *) (* C_PROBE328_MU_CNT = "1" *) 
(* C_PROBE329_MU_CNT = "1" *) (* C_PROBE330_MU_CNT = "1" *) (* C_PROBE331_MU_CNT = "1" *) 
(* C_PROBE332_MU_CNT = "1" *) (* C_PROBE333_MU_CNT = "1" *) (* C_PROBE334_MU_CNT = "1" *) 
(* C_PROBE335_MU_CNT = "1" *) (* C_PROBE336_MU_CNT = "1" *) (* C_PROBE337_MU_CNT = "1" *) 
(* C_PROBE338_MU_CNT = "1" *) (* C_PROBE339_MU_CNT = "1" *) (* C_PROBE340_MU_CNT = "1" *) 
(* C_PROBE341_MU_CNT = "1" *) (* C_PROBE342_MU_CNT = "1" *) (* C_PROBE343_MU_CNT = "1" *) 
(* C_PROBE344_MU_CNT = "1" *) (* C_PROBE345_MU_CNT = "1" *) (* C_PROBE346_MU_CNT = "1" *) 
(* C_PROBE347_MU_CNT = "1" *) (* C_PROBE348_MU_CNT = "1" *) (* C_PROBE349_MU_CNT = "1" *) 
(* C_PROBE350_MU_CNT = "1" *) (* C_PROBE351_MU_CNT = "1" *) (* C_PROBE352_MU_CNT = "1" *) 
(* C_PROBE353_MU_CNT = "1" *) (* C_PROBE354_MU_CNT = "1" *) (* C_PROBE355_MU_CNT = "1" *) 
(* C_PROBE356_MU_CNT = "1" *) (* C_PROBE357_MU_CNT = "1" *) (* C_PROBE358_MU_CNT = "1" *) 
(* C_PROBE359_MU_CNT = "1" *) (* C_PROBE360_MU_CNT = "1" *) (* C_PROBE361_MU_CNT = "1" *) 
(* C_PROBE362_MU_CNT = "1" *) (* C_PROBE363_MU_CNT = "1" *) (* C_PROBE364_MU_CNT = "1" *) 
(* C_PROBE365_MU_CNT = "1" *) (* C_PROBE366_MU_CNT = "1" *) (* C_PROBE367_MU_CNT = "1" *) 
(* C_PROBE368_MU_CNT = "1" *) (* C_PROBE369_MU_CNT = "1" *) (* C_PROBE370_MU_CNT = "1" *) 
(* C_PROBE371_MU_CNT = "1" *) (* C_PROBE372_MU_CNT = "1" *) (* C_PROBE373_MU_CNT = "1" *) 
(* C_PROBE374_MU_CNT = "1" *) (* C_PROBE375_MU_CNT = "1" *) (* C_PROBE376_MU_CNT = "1" *) 
(* C_PROBE377_MU_CNT = "1" *) (* C_PROBE378_MU_CNT = "1" *) (* C_PROBE379_MU_CNT = "1" *) 
(* C_PROBE380_MU_CNT = "1" *) (* C_PROBE381_MU_CNT = "1" *) (* C_PROBE382_MU_CNT = "1" *) 
(* C_PROBE383_MU_CNT = "1" *) (* C_PROBE384_MU_CNT = "1" *) (* C_PROBE385_MU_CNT = "1" *) 
(* C_PROBE386_MU_CNT = "1" *) (* C_PROBE387_MU_CNT = "1" *) (* C_PROBE388_MU_CNT = "1" *) 
(* C_PROBE389_MU_CNT = "1" *) (* C_PROBE390_MU_CNT = "1" *) (* C_PROBE391_MU_CNT = "1" *) 
(* C_PROBE392_MU_CNT = "1" *) (* C_PROBE393_MU_CNT = "1" *) (* C_PROBE394_MU_CNT = "1" *) 
(* C_PROBE395_MU_CNT = "1" *) (* C_PROBE396_MU_CNT = "1" *) (* C_PROBE397_MU_CNT = "1" *) 
(* C_PROBE398_MU_CNT = "1" *) (* C_PROBE399_MU_CNT = "1" *) (* C_PROBE400_MU_CNT = "1" *) 
(* C_PROBE401_MU_CNT = "1" *) (* C_PROBE402_MU_CNT = "1" *) (* C_PROBE403_MU_CNT = "1" *) 
(* C_PROBE404_MU_CNT = "1" *) (* C_PROBE405_MU_CNT = "1" *) (* C_PROBE406_MU_CNT = "1" *) 
(* C_PROBE407_MU_CNT = "1" *) (* C_PROBE408_MU_CNT = "1" *) (* C_PROBE409_MU_CNT = "1" *) 
(* C_PROBE410_MU_CNT = "1" *) (* C_PROBE411_MU_CNT = "1" *) (* C_PROBE412_MU_CNT = "1" *) 
(* C_PROBE413_MU_CNT = "1" *) (* C_PROBE414_MU_CNT = "1" *) (* C_PROBE415_MU_CNT = "1" *) 
(* C_PROBE416_MU_CNT = "1" *) (* C_PROBE417_MU_CNT = "1" *) (* C_PROBE418_MU_CNT = "1" *) 
(* C_PROBE419_MU_CNT = "1" *) (* C_PROBE420_MU_CNT = "1" *) (* C_PROBE421_MU_CNT = "1" *) 
(* C_PROBE422_MU_CNT = "1" *) (* C_PROBE423_MU_CNT = "1" *) (* C_PROBE424_MU_CNT = "1" *) 
(* C_PROBE425_MU_CNT = "1" *) (* C_PROBE426_MU_CNT = "1" *) (* C_PROBE427_MU_CNT = "1" *) 
(* C_PROBE428_MU_CNT = "1" *) (* C_PROBE429_MU_CNT = "1" *) (* C_PROBE430_MU_CNT = "1" *) 
(* C_PROBE431_MU_CNT = "1" *) (* C_PROBE432_MU_CNT = "1" *) (* C_PROBE433_MU_CNT = "1" *) 
(* C_PROBE434_MU_CNT = "1" *) (* C_PROBE435_MU_CNT = "1" *) (* C_PROBE436_MU_CNT = "1" *) 
(* C_PROBE437_MU_CNT = "1" *) (* C_PROBE438_MU_CNT = "1" *) (* C_PROBE439_MU_CNT = "1" *) 
(* C_PROBE440_MU_CNT = "1" *) (* C_PROBE441_MU_CNT = "1" *) (* C_PROBE442_MU_CNT = "1" *) 
(* C_PROBE443_MU_CNT = "1" *) (* C_PROBE444_MU_CNT = "1" *) (* C_PROBE445_MU_CNT = "1" *) 
(* C_PROBE446_MU_CNT = "1" *) (* C_PROBE447_MU_CNT = "1" *) (* C_PROBE448_MU_CNT = "1" *) 
(* C_PROBE449_MU_CNT = "1" *) (* C_PROBE450_MU_CNT = "1" *) (* C_PROBE451_MU_CNT = "1" *) 
(* C_PROBE452_MU_CNT = "1" *) (* C_PROBE453_MU_CNT = "1" *) (* C_PROBE454_MU_CNT = "1" *) 
(* C_PROBE455_MU_CNT = "1" *) (* C_PROBE456_MU_CNT = "1" *) (* C_PROBE457_MU_CNT = "1" *) 
(* C_PROBE458_MU_CNT = "1" *) (* C_PROBE459_MU_CNT = "1" *) (* C_PROBE460_MU_CNT = "1" *) 
(* C_PROBE461_MU_CNT = "1" *) (* C_PROBE462_MU_CNT = "1" *) (* C_PROBE463_MU_CNT = "1" *) 
(* C_PROBE464_MU_CNT = "1" *) (* C_PROBE465_MU_CNT = "1" *) (* C_PROBE466_MU_CNT = "1" *) 
(* C_PROBE467_MU_CNT = "1" *) (* C_PROBE468_MU_CNT = "1" *) (* C_PROBE469_MU_CNT = "1" *) 
(* C_PROBE470_MU_CNT = "1" *) (* C_PROBE471_MU_CNT = "1" *) (* C_PROBE472_MU_CNT = "1" *) 
(* C_PROBE473_MU_CNT = "1" *) (* C_PROBE474_MU_CNT = "1" *) (* C_PROBE475_MU_CNT = "1" *) 
(* C_PROBE476_MU_CNT = "1" *) (* C_PROBE477_MU_CNT = "1" *) (* C_PROBE478_MU_CNT = "1" *) 
(* C_PROBE479_MU_CNT = "1" *) (* C_PROBE480_MU_CNT = "1" *) (* C_PROBE481_MU_CNT = "1" *) 
(* C_PROBE482_MU_CNT = "1" *) (* C_PROBE483_MU_CNT = "1" *) (* C_PROBE484_MU_CNT = "1" *) 
(* C_PROBE485_MU_CNT = "1" *) (* C_PROBE486_MU_CNT = "1" *) (* C_PROBE487_MU_CNT = "1" *) 
(* C_PROBE488_MU_CNT = "1" *) (* C_PROBE489_MU_CNT = "1" *) (* C_PROBE490_MU_CNT = "1" *) 
(* C_PROBE491_MU_CNT = "1" *) (* C_PROBE492_MU_CNT = "1" *) (* C_PROBE493_MU_CNT = "1" *) 
(* C_PROBE494_MU_CNT = "1" *) (* C_PROBE495_MU_CNT = "1" *) (* C_PROBE496_MU_CNT = "1" *) 
(* C_PROBE497_MU_CNT = "1" *) (* C_PROBE498_MU_CNT = "1" *) (* C_PROBE499_MU_CNT = "1" *) 
(* C_PROBE500_MU_CNT = "1" *) (* C_PROBE501_MU_CNT = "1" *) (* C_PROBE502_MU_CNT = "1" *) 
(* C_PROBE503_MU_CNT = "1" *) (* C_PROBE504_MU_CNT = "1" *) (* C_PROBE505_MU_CNT = "1" *) 
(* C_PROBE506_MU_CNT = "1" *) (* C_PROBE507_MU_CNT = "1" *) (* C_PROBE508_MU_CNT = "1" *) 
(* C_PROBE509_MU_CNT = "1" *) (* C_PROBE510_MU_CNT = "1" *) (* C_PROBE511_MU_CNT = "1" *) 
(* C_PROBE512_MU_CNT = "1" *) (* C_PROBE513_MU_CNT = "1" *) (* C_PROBE514_MU_CNT = "1" *) 
(* C_PROBE515_MU_CNT = "1" *) (* C_PROBE516_MU_CNT = "1" *) (* C_PROBE517_MU_CNT = "1" *) 
(* C_PROBE518_MU_CNT = "1" *) (* C_PROBE519_MU_CNT = "1" *) (* C_PROBE520_MU_CNT = "1" *) 
(* C_PROBE521_MU_CNT = "1" *) (* C_PROBE522_MU_CNT = "1" *) (* C_PROBE523_MU_CNT = "1" *) 
(* C_PROBE524_MU_CNT = "1" *) (* C_PROBE525_MU_CNT = "1" *) (* C_PROBE526_MU_CNT = "1" *) 
(* C_PROBE527_MU_CNT = "1" *) (* C_PROBE528_MU_CNT = "1" *) (* C_PROBE529_MU_CNT = "1" *) 
(* C_PROBE530_MU_CNT = "1" *) (* C_PROBE531_MU_CNT = "1" *) (* C_PROBE532_MU_CNT = "1" *) 
(* C_PROBE533_MU_CNT = "1" *) (* C_PROBE534_MU_CNT = "1" *) (* C_PROBE535_MU_CNT = "1" *) 
(* C_PROBE536_MU_CNT = "1" *) (* C_PROBE537_MU_CNT = "1" *) (* C_PROBE538_MU_CNT = "1" *) 
(* C_PROBE539_MU_CNT = "1" *) (* C_PROBE540_MU_CNT = "1" *) (* C_PROBE541_MU_CNT = "1" *) 
(* C_PROBE542_MU_CNT = "1" *) (* C_PROBE543_MU_CNT = "1" *) (* C_PROBE544_MU_CNT = "1" *) 
(* C_PROBE545_MU_CNT = "1" *) (* C_PROBE546_MU_CNT = "1" *) (* C_PROBE547_MU_CNT = "1" *) 
(* C_PROBE548_MU_CNT = "1" *) (* C_PROBE549_MU_CNT = "1" *) (* C_PROBE550_MU_CNT = "1" *) 
(* C_PROBE551_MU_CNT = "1" *) (* C_PROBE552_MU_CNT = "1" *) (* C_PROBE553_MU_CNT = "1" *) 
(* C_PROBE554_MU_CNT = "1" *) (* C_PROBE555_MU_CNT = "1" *) (* C_PROBE556_MU_CNT = "1" *) 
(* C_PROBE557_MU_CNT = "1" *) (* C_PROBE558_MU_CNT = "1" *) (* C_PROBE559_MU_CNT = "1" *) 
(* C_PROBE560_MU_CNT = "1" *) (* C_PROBE561_MU_CNT = "1" *) (* C_PROBE562_MU_CNT = "1" *) 
(* C_PROBE563_MU_CNT = "1" *) (* C_PROBE564_MU_CNT = "1" *) (* C_PROBE565_MU_CNT = "1" *) 
(* C_PROBE566_MU_CNT = "1" *) (* C_PROBE567_MU_CNT = "1" *) (* C_PROBE568_MU_CNT = "1" *) 
(* C_PROBE569_MU_CNT = "1" *) (* C_PROBE570_MU_CNT = "1" *) (* C_PROBE571_MU_CNT = "1" *) 
(* C_PROBE572_MU_CNT = "1" *) (* C_PROBE573_MU_CNT = "1" *) (* C_PROBE574_MU_CNT = "1" *) 
(* C_PROBE575_MU_CNT = "1" *) (* C_PROBE576_MU_CNT = "1" *) (* C_PROBE577_MU_CNT = "1" *) 
(* C_PROBE578_MU_CNT = "1" *) (* C_PROBE579_MU_CNT = "1" *) (* C_PROBE580_MU_CNT = "1" *) 
(* C_PROBE581_MU_CNT = "1" *) (* C_PROBE582_MU_CNT = "1" *) (* C_PROBE583_MU_CNT = "1" *) 
(* C_PROBE584_MU_CNT = "1" *) (* C_PROBE585_MU_CNT = "1" *) (* C_PROBE586_MU_CNT = "1" *) 
(* C_PROBE587_MU_CNT = "1" *) (* C_PROBE588_MU_CNT = "1" *) (* C_PROBE589_MU_CNT = "1" *) 
(* C_PROBE590_MU_CNT = "1" *) (* C_PROBE591_MU_CNT = "1" *) (* C_PROBE592_MU_CNT = "1" *) 
(* C_PROBE593_MU_CNT = "1" *) (* C_PROBE594_MU_CNT = "1" *) (* C_PROBE595_MU_CNT = "1" *) 
(* C_PROBE596_MU_CNT = "1" *) (* C_PROBE597_MU_CNT = "1" *) (* C_PROBE598_MU_CNT = "1" *) 
(* C_PROBE599_MU_CNT = "1" *) (* C_PROBE600_MU_CNT = "1" *) (* C_PROBE601_MU_CNT = "1" *) 
(* C_PROBE602_MU_CNT = "1" *) (* C_PROBE603_MU_CNT = "1" *) (* C_PROBE604_MU_CNT = "1" *) 
(* C_PROBE605_MU_CNT = "1" *) (* C_PROBE606_MU_CNT = "1" *) (* C_PROBE607_MU_CNT = "1" *) 
(* C_PROBE608_MU_CNT = "1" *) (* C_PROBE609_MU_CNT = "1" *) (* C_PROBE610_MU_CNT = "1" *) 
(* C_PROBE611_MU_CNT = "1" *) (* C_PROBE612_MU_CNT = "1" *) (* C_PROBE613_MU_CNT = "1" *) 
(* C_PROBE614_MU_CNT = "1" *) (* C_PROBE615_MU_CNT = "1" *) (* C_PROBE616_MU_CNT = "1" *) 
(* C_PROBE617_MU_CNT = "1" *) (* C_PROBE618_MU_CNT = "1" *) (* C_PROBE619_MU_CNT = "1" *) 
(* C_PROBE620_MU_CNT = "1" *) (* C_PROBE621_MU_CNT = "1" *) (* C_PROBE622_MU_CNT = "1" *) 
(* C_PROBE623_MU_CNT = "1" *) (* C_PROBE624_MU_CNT = "1" *) (* C_PROBE625_MU_CNT = "1" *) 
(* C_PROBE626_MU_CNT = "1" *) (* C_PROBE627_MU_CNT = "1" *) (* C_PROBE628_MU_CNT = "1" *) 
(* C_PROBE629_MU_CNT = "1" *) (* C_PROBE630_MU_CNT = "1" *) (* C_PROBE631_MU_CNT = "1" *) 
(* C_PROBE632_MU_CNT = "1" *) (* C_PROBE633_MU_CNT = "1" *) (* C_PROBE634_MU_CNT = "1" *) 
(* C_PROBE635_MU_CNT = "1" *) (* C_PROBE636_MU_CNT = "1" *) (* C_PROBE637_MU_CNT = "1" *) 
(* C_PROBE638_MU_CNT = "1" *) (* C_PROBE639_MU_CNT = "1" *) (* C_PROBE640_MU_CNT = "1" *) 
(* C_PROBE641_MU_CNT = "1" *) (* C_PROBE642_MU_CNT = "1" *) (* C_PROBE643_MU_CNT = "1" *) 
(* C_PROBE644_MU_CNT = "1" *) (* C_PROBE645_MU_CNT = "1" *) (* C_PROBE646_MU_CNT = "1" *) 
(* C_PROBE647_MU_CNT = "1" *) (* C_PROBE648_MU_CNT = "1" *) (* C_PROBE649_MU_CNT = "1" *) 
(* C_PROBE650_MU_CNT = "1" *) (* C_PROBE651_MU_CNT = "1" *) (* C_PROBE652_MU_CNT = "1" *) 
(* C_PROBE653_MU_CNT = "1" *) (* C_PROBE654_MU_CNT = "1" *) (* C_PROBE655_MU_CNT = "1" *) 
(* C_PROBE656_MU_CNT = "1" *) (* C_PROBE657_MU_CNT = "1" *) (* C_PROBE658_MU_CNT = "1" *) 
(* C_PROBE659_MU_CNT = "1" *) (* C_PROBE660_MU_CNT = "1" *) (* C_PROBE661_MU_CNT = "1" *) 
(* C_PROBE662_MU_CNT = "1" *) (* C_PROBE663_MU_CNT = "1" *) (* C_PROBE664_MU_CNT = "1" *) 
(* C_PROBE665_MU_CNT = "1" *) (* C_PROBE666_MU_CNT = "1" *) (* C_PROBE667_MU_CNT = "1" *) 
(* C_PROBE668_MU_CNT = "1" *) (* C_PROBE669_MU_CNT = "1" *) (* C_PROBE670_MU_CNT = "1" *) 
(* C_PROBE671_MU_CNT = "1" *) (* C_PROBE672_MU_CNT = "1" *) (* C_PROBE673_MU_CNT = "1" *) 
(* C_PROBE674_MU_CNT = "1" *) (* C_PROBE675_MU_CNT = "1" *) (* C_PROBE676_MU_CNT = "1" *) 
(* C_PROBE677_MU_CNT = "1" *) (* C_PROBE678_MU_CNT = "1" *) (* C_PROBE679_MU_CNT = "1" *) 
(* C_PROBE680_MU_CNT = "1" *) (* C_PROBE681_MU_CNT = "1" *) (* C_PROBE682_MU_CNT = "1" *) 
(* C_PROBE683_MU_CNT = "1" *) (* C_PROBE684_MU_CNT = "1" *) (* C_PROBE685_MU_CNT = "1" *) 
(* C_PROBE686_MU_CNT = "1" *) (* C_PROBE687_MU_CNT = "1" *) (* C_PROBE688_MU_CNT = "1" *) 
(* C_PROBE689_MU_CNT = "1" *) (* C_PROBE690_MU_CNT = "1" *) (* C_PROBE691_MU_CNT = "1" *) 
(* C_PROBE692_MU_CNT = "1" *) (* C_PROBE693_MU_CNT = "1" *) (* C_PROBE694_MU_CNT = "1" *) 
(* C_PROBE695_MU_CNT = "1" *) (* C_PROBE696_MU_CNT = "1" *) (* C_PROBE697_MU_CNT = "1" *) 
(* C_PROBE698_MU_CNT = "1" *) (* C_PROBE699_MU_CNT = "1" *) (* C_PROBE700_MU_CNT = "1" *) 
(* C_PROBE701_MU_CNT = "1" *) (* C_PROBE702_MU_CNT = "1" *) (* C_PROBE703_MU_CNT = "1" *) 
(* C_PROBE704_MU_CNT = "1" *) (* C_PROBE705_MU_CNT = "1" *) (* C_PROBE706_MU_CNT = "1" *) 
(* C_PROBE707_MU_CNT = "1" *) (* C_PROBE708_MU_CNT = "1" *) (* C_PROBE709_MU_CNT = "1" *) 
(* C_PROBE710_MU_CNT = "1" *) (* C_PROBE711_MU_CNT = "1" *) (* C_PROBE712_MU_CNT = "1" *) 
(* C_PROBE713_MU_CNT = "1" *) (* C_PROBE714_MU_CNT = "1" *) (* C_PROBE715_MU_CNT = "1" *) 
(* C_PROBE716_MU_CNT = "1" *) (* C_PROBE717_MU_CNT = "1" *) (* C_PROBE718_MU_CNT = "1" *) 
(* C_PROBE719_MU_CNT = "1" *) (* C_PROBE720_MU_CNT = "1" *) (* C_PROBE721_MU_CNT = "1" *) 
(* C_PROBE722_MU_CNT = "1" *) (* C_PROBE723_MU_CNT = "1" *) (* C_PROBE724_MU_CNT = "1" *) 
(* C_PROBE725_MU_CNT = "1" *) (* C_PROBE726_MU_CNT = "1" *) (* C_PROBE727_MU_CNT = "1" *) 
(* C_PROBE728_MU_CNT = "1" *) (* C_PROBE729_MU_CNT = "1" *) (* C_PROBE730_MU_CNT = "1" *) 
(* C_PROBE731_MU_CNT = "1" *) (* C_PROBE732_MU_CNT = "1" *) (* C_PROBE733_MU_CNT = "1" *) 
(* C_PROBE734_MU_CNT = "1" *) (* C_PROBE735_MU_CNT = "1" *) (* C_PROBE736_MU_CNT = "1" *) 
(* C_PROBE737_MU_CNT = "1" *) (* C_PROBE738_MU_CNT = "1" *) (* C_PROBE739_MU_CNT = "1" *) 
(* C_PROBE740_MU_CNT = "1" *) (* C_PROBE741_MU_CNT = "1" *) (* C_PROBE742_MU_CNT = "1" *) 
(* C_PROBE743_MU_CNT = "1" *) (* C_PROBE744_MU_CNT = "1" *) (* C_PROBE745_MU_CNT = "1" *) 
(* C_PROBE746_MU_CNT = "1" *) (* C_PROBE747_MU_CNT = "1" *) (* C_PROBE748_MU_CNT = "1" *) 
(* C_PROBE749_MU_CNT = "1" *) (* C_PROBE750_MU_CNT = "1" *) (* C_PROBE751_MU_CNT = "1" *) 
(* C_PROBE752_MU_CNT = "1" *) (* C_PROBE753_MU_CNT = "1" *) (* C_PROBE754_MU_CNT = "1" *) 
(* C_PROBE755_MU_CNT = "1" *) (* C_PROBE756_MU_CNT = "1" *) (* C_PROBE757_MU_CNT = "1" *) 
(* C_PROBE758_MU_CNT = "1" *) (* C_PROBE759_MU_CNT = "1" *) (* C_PROBE760_MU_CNT = "1" *) 
(* C_PROBE761_MU_CNT = "1" *) (* C_PROBE762_MU_CNT = "1" *) (* C_PROBE763_MU_CNT = "1" *) 
(* C_PROBE764_MU_CNT = "1" *) (* C_PROBE765_MU_CNT = "1" *) (* C_PROBE766_MU_CNT = "1" *) 
(* C_PROBE767_MU_CNT = "1" *) (* C_PROBE768_MU_CNT = "1" *) (* C_PROBE769_MU_CNT = "1" *) 
(* C_PROBE770_MU_CNT = "1" *) (* C_PROBE771_MU_CNT = "1" *) (* C_PROBE772_MU_CNT = "1" *) 
(* C_PROBE773_MU_CNT = "1" *) (* C_PROBE774_MU_CNT = "1" *) (* C_PROBE775_MU_CNT = "1" *) 
(* C_PROBE776_MU_CNT = "1" *) (* C_PROBE777_MU_CNT = "1" *) (* C_PROBE778_MU_CNT = "1" *) 
(* C_PROBE779_MU_CNT = "1" *) (* C_PROBE780_MU_CNT = "1" *) (* C_PROBE781_MU_CNT = "1" *) 
(* C_PROBE782_MU_CNT = "1" *) (* C_PROBE783_MU_CNT = "1" *) (* C_PROBE784_MU_CNT = "1" *) 
(* C_PROBE785_MU_CNT = "1" *) (* C_PROBE786_MU_CNT = "1" *) (* C_PROBE787_MU_CNT = "1" *) 
(* C_PROBE788_MU_CNT = "1" *) (* C_PROBE789_MU_CNT = "1" *) (* C_PROBE790_MU_CNT = "1" *) 
(* C_PROBE791_MU_CNT = "1" *) (* C_PROBE792_MU_CNT = "1" *) (* C_PROBE793_MU_CNT = "1" *) 
(* C_PROBE794_MU_CNT = "1" *) (* C_PROBE795_MU_CNT = "1" *) (* C_PROBE796_MU_CNT = "1" *) 
(* C_PROBE797_MU_CNT = "1" *) (* C_PROBE798_MU_CNT = "1" *) (* C_PROBE799_MU_CNT = "1" *) 
(* C_PROBE800_MU_CNT = "1" *) (* C_PROBE801_MU_CNT = "1" *) (* C_PROBE802_MU_CNT = "1" *) 
(* C_PROBE803_MU_CNT = "1" *) (* C_PROBE804_MU_CNT = "1" *) (* C_PROBE805_MU_CNT = "1" *) 
(* C_PROBE806_MU_CNT = "1" *) (* C_PROBE807_MU_CNT = "1" *) (* C_PROBE808_MU_CNT = "1" *) 
(* C_PROBE809_MU_CNT = "1" *) (* C_PROBE810_MU_CNT = "1" *) (* C_PROBE811_MU_CNT = "1" *) 
(* C_PROBE812_MU_CNT = "1" *) (* C_PROBE813_MU_CNT = "1" *) (* C_PROBE814_MU_CNT = "1" *) 
(* C_PROBE815_MU_CNT = "1" *) (* C_PROBE816_MU_CNT = "1" *) (* C_PROBE817_MU_CNT = "1" *) 
(* C_PROBE818_MU_CNT = "1" *) (* C_PROBE819_MU_CNT = "1" *) (* C_PROBE820_MU_CNT = "1" *) 
(* C_PROBE821_MU_CNT = "1" *) (* C_PROBE822_MU_CNT = "1" *) (* C_PROBE823_MU_CNT = "1" *) 
(* C_PROBE824_MU_CNT = "1" *) (* C_PROBE825_MU_CNT = "1" *) (* C_PROBE826_MU_CNT = "1" *) 
(* C_PROBE827_MU_CNT = "1" *) (* C_PROBE828_MU_CNT = "1" *) (* C_PROBE829_MU_CNT = "1" *) 
(* C_PROBE830_MU_CNT = "1" *) (* C_PROBE831_MU_CNT = "1" *) (* C_PROBE832_MU_CNT = "1" *) 
(* C_PROBE833_MU_CNT = "1" *) (* C_PROBE834_MU_CNT = "1" *) (* C_PROBE835_MU_CNT = "1" *) 
(* C_PROBE836_MU_CNT = "1" *) (* C_PROBE837_MU_CNT = "1" *) (* C_PROBE838_MU_CNT = "1" *) 
(* C_PROBE839_MU_CNT = "1" *) (* C_PROBE840_MU_CNT = "1" *) (* C_PROBE841_MU_CNT = "1" *) 
(* C_PROBE842_MU_CNT = "1" *) (* C_PROBE843_MU_CNT = "1" *) (* C_PROBE844_MU_CNT = "1" *) 
(* C_PROBE845_MU_CNT = "1" *) (* C_PROBE846_MU_CNT = "1" *) (* C_PROBE847_MU_CNT = "1" *) 
(* C_PROBE848_MU_CNT = "1" *) (* C_PROBE849_MU_CNT = "1" *) (* C_PROBE850_MU_CNT = "1" *) 
(* C_PROBE851_MU_CNT = "1" *) (* C_PROBE852_MU_CNT = "1" *) (* C_PROBE853_MU_CNT = "1" *) 
(* C_PROBE854_MU_CNT = "1" *) (* C_PROBE855_MU_CNT = "1" *) (* C_PROBE856_MU_CNT = "1" *) 
(* C_PROBE857_MU_CNT = "1" *) (* C_PROBE858_MU_CNT = "1" *) (* C_PROBE859_MU_CNT = "1" *) 
(* C_PROBE860_MU_CNT = "1" *) (* C_PROBE861_MU_CNT = "1" *) (* C_PROBE862_MU_CNT = "1" *) 
(* C_PROBE863_MU_CNT = "1" *) (* C_PROBE864_MU_CNT = "1" *) (* C_PROBE865_MU_CNT = "1" *) 
(* C_PROBE866_MU_CNT = "1" *) (* C_PROBE867_MU_CNT = "1" *) (* C_PROBE868_MU_CNT = "1" *) 
(* C_PROBE869_MU_CNT = "1" *) (* C_PROBE870_MU_CNT = "1" *) (* C_PROBE871_MU_CNT = "1" *) 
(* C_PROBE872_MU_CNT = "1" *) (* C_PROBE873_MU_CNT = "1" *) (* C_PROBE874_MU_CNT = "1" *) 
(* C_PROBE875_MU_CNT = "1" *) (* C_PROBE876_MU_CNT = "1" *) (* C_PROBE877_MU_CNT = "1" *) 
(* C_PROBE878_MU_CNT = "1" *) (* C_PROBE879_MU_CNT = "1" *) (* C_PROBE880_MU_CNT = "1" *) 
(* C_PROBE881_MU_CNT = "1" *) (* C_PROBE882_MU_CNT = "1" *) (* C_PROBE883_MU_CNT = "1" *) 
(* C_PROBE884_MU_CNT = "1" *) (* C_PROBE885_MU_CNT = "1" *) (* C_PROBE886_MU_CNT = "1" *) 
(* C_PROBE887_MU_CNT = "1" *) (* C_PROBE888_MU_CNT = "1" *) (* C_PROBE889_MU_CNT = "1" *) 
(* C_PROBE890_MU_CNT = "1" *) (* C_PROBE891_MU_CNT = "1" *) (* C_PROBE892_MU_CNT = "1" *) 
(* C_PROBE893_MU_CNT = "1" *) (* C_PROBE894_MU_CNT = "1" *) (* C_PROBE895_MU_CNT = "1" *) 
(* C_PROBE896_MU_CNT = "1" *) (* C_PROBE897_MU_CNT = "1" *) (* C_PROBE898_MU_CNT = "1" *) 
(* C_PROBE899_MU_CNT = "1" *) (* C_PROBE900_MU_CNT = "1" *) (* C_PROBE901_MU_CNT = "1" *) 
(* C_PROBE902_MU_CNT = "1" *) (* C_PROBE903_MU_CNT = "1" *) (* C_PROBE904_MU_CNT = "1" *) 
(* C_PROBE905_MU_CNT = "1" *) (* C_PROBE906_MU_CNT = "1" *) (* C_PROBE907_MU_CNT = "1" *) 
(* C_PROBE908_MU_CNT = "1" *) (* C_PROBE909_MU_CNT = "1" *) (* C_PROBE910_MU_CNT = "1" *) 
(* C_PROBE911_MU_CNT = "1" *) (* C_PROBE912_MU_CNT = "1" *) (* C_PROBE913_MU_CNT = "1" *) 
(* C_PROBE914_MU_CNT = "1" *) (* C_PROBE915_MU_CNT = "1" *) (* C_PROBE916_MU_CNT = "1" *) 
(* C_PROBE917_MU_CNT = "1" *) (* C_PROBE918_MU_CNT = "1" *) (* C_PROBE919_MU_CNT = "1" *) 
(* C_PROBE920_MU_CNT = "1" *) (* C_PROBE921_MU_CNT = "1" *) (* C_PROBE922_MU_CNT = "1" *) 
(* C_PROBE923_MU_CNT = "1" *) (* C_PROBE924_MU_CNT = "1" *) (* C_PROBE925_MU_CNT = "1" *) 
(* C_PROBE926_MU_CNT = "1" *) (* C_PROBE927_MU_CNT = "1" *) (* C_PROBE928_MU_CNT = "1" *) 
(* C_PROBE929_MU_CNT = "1" *) (* C_PROBE930_MU_CNT = "1" *) (* C_PROBE931_MU_CNT = "1" *) 
(* C_PROBE932_MU_CNT = "1" *) (* C_PROBE933_MU_CNT = "1" *) (* C_PROBE934_MU_CNT = "1" *) 
(* C_PROBE935_MU_CNT = "1" *) (* C_PROBE936_MU_CNT = "1" *) (* C_PROBE937_MU_CNT = "1" *) 
(* C_PROBE938_MU_CNT = "1" *) (* C_PROBE939_MU_CNT = "1" *) (* C_PROBE940_MU_CNT = "1" *) 
(* C_PROBE941_MU_CNT = "1" *) (* C_PROBE942_MU_CNT = "1" *) (* C_PROBE943_MU_CNT = "1" *) 
(* C_PROBE944_MU_CNT = "1" *) (* C_PROBE945_MU_CNT = "1" *) (* C_PROBE946_MU_CNT = "1" *) 
(* C_PROBE947_MU_CNT = "1" *) (* C_PROBE948_MU_CNT = "1" *) (* C_PROBE949_MU_CNT = "1" *) 
(* C_PROBE950_MU_CNT = "1" *) (* C_PROBE951_MU_CNT = "1" *) (* C_PROBE952_MU_CNT = "1" *) 
(* C_PROBE953_MU_CNT = "1" *) (* C_PROBE954_MU_CNT = "1" *) (* C_PROBE955_MU_CNT = "1" *) 
(* C_PROBE956_MU_CNT = "1" *) (* C_PROBE957_MU_CNT = "1" *) (* C_PROBE958_MU_CNT = "1" *) 
(* C_PROBE959_MU_CNT = "1" *) (* C_PROBE960_MU_CNT = "1" *) (* C_PROBE961_MU_CNT = "1" *) 
(* C_PROBE962_MU_CNT = "1" *) (* C_PROBE963_MU_CNT = "1" *) (* C_PROBE964_MU_CNT = "1" *) 
(* C_PROBE965_MU_CNT = "1" *) (* C_PROBE966_MU_CNT = "1" *) (* C_PROBE967_MU_CNT = "1" *) 
(* C_PROBE968_MU_CNT = "1" *) (* C_PROBE969_MU_CNT = "1" *) (* C_PROBE970_MU_CNT = "1" *) 
(* C_PROBE971_MU_CNT = "1" *) (* C_PROBE972_MU_CNT = "1" *) (* C_PROBE973_MU_CNT = "1" *) 
(* C_PROBE974_MU_CNT = "1" *) (* C_PROBE975_MU_CNT = "1" *) (* C_PROBE976_MU_CNT = "1" *) 
(* C_PROBE977_MU_CNT = "1" *) (* C_PROBE978_MU_CNT = "1" *) (* C_PROBE979_MU_CNT = "1" *) 
(* C_PROBE980_MU_CNT = "1" *) (* C_PROBE981_MU_CNT = "1" *) (* C_PROBE982_MU_CNT = "1" *) 
(* C_PROBE983_MU_CNT = "1" *) (* C_PROBE984_MU_CNT = "1" *) (* C_PROBE985_MU_CNT = "1" *) 
(* C_PROBE986_MU_CNT = "1" *) (* C_PROBE987_MU_CNT = "1" *) (* C_PROBE988_MU_CNT = "1" *) 
(* C_PROBE989_MU_CNT = "1" *) (* C_PROBE990_MU_CNT = "1" *) (* C_PROBE991_MU_CNT = "1" *) 
(* C_PROBE992_MU_CNT = "1" *) (* C_PROBE993_MU_CNT = "1" *) (* C_PROBE994_MU_CNT = "1" *) 
(* C_PROBE995_MU_CNT = "1" *) (* C_PROBE996_MU_CNT = "1" *) (* C_PROBE997_MU_CNT = "1" *) 
(* C_PROBE998_MU_CNT = "1" *) (* C_PROBE999_MU_CNT = "1" *) (* C_PROBE1000_MU_CNT = "1" *) 
(* C_PROBE1001_MU_CNT = "1" *) (* C_PROBE1002_MU_CNT = "1" *) (* C_PROBE1003_MU_CNT = "1" *) 
(* C_PROBE1004_MU_CNT = "1" *) (* C_PROBE1005_MU_CNT = "1" *) (* C_PROBE1006_MU_CNT = "1" *) 
(* C_PROBE1007_MU_CNT = "1" *) (* C_PROBE1008_MU_CNT = "1" *) (* C_PROBE1009_MU_CNT = "1" *) 
(* C_PROBE1010_MU_CNT = "1" *) (* C_PROBE1011_MU_CNT = "1" *) (* C_PROBE1012_MU_CNT = "1" *) 
(* C_PROBE1013_MU_CNT = "1" *) (* C_PROBE1014_MU_CNT = "1" *) (* C_PROBE1015_MU_CNT = "1" *) 
(* C_PROBE1016_MU_CNT = "1" *) (* C_PROBE1017_MU_CNT = "1" *) (* C_PROBE1018_MU_CNT = "1" *) 
(* C_PROBE1019_MU_CNT = "1" *) (* C_PROBE1020_MU_CNT = "1" *) (* C_PROBE1021_MU_CNT = "1" *) 
(* C_PROBE1022_MU_CNT = "1" *) (* C_PROBE1023_MU_CNT = "1" *) (* LC_PROBE0_PID = "16'b0000000000000000" *) 
(* LC_PROBE1_PID = "16'b0000000000000001" *) (* LC_PROBE2_PID = "16'b0000000000000010" *) (* LC_PROBE3_PID = "16'b0000000000000011" *) 
(* LC_PROBE4_PID = "16'b0000000000000100" *) (* LC_PROBE5_PID = "16'b0000000000000101" *) (* LC_PROBE6_PID = "16'b0000000000000110" *) 
(* LC_PROBE7_PID = "16'b0000000000000111" *) (* LC_PROBE8_PID = "16'b0000000000001000" *) (* LC_PROBE9_PID = "16'b0000000000001001" *) 
(* LC_PROBE10_PID = "16'b0000000000001010" *) (* LC_PROBE11_PID = "16'b0000000000001011" *) (* LC_PROBE12_PID = "16'b0000000000001100" *) 
(* LC_PROBE13_PID = "16'b0000000000001101" *) (* LC_PROBE14_PID = "16'b0000000000001110" *) (* LC_PROBE15_PID = "16'b0000000000001111" *) 
(* LC_PROBE16_PID = "16'b0000000000010000" *) (* LC_PROBE17_PID = "16'b0000000000010001" *) (* LC_PROBE18_PID = "16'b0000000000010010" *) 
(* LC_PROBE19_PID = "16'b0000000000010011" *) (* LC_PROBE20_PID = "16'b0000000000010100" *) (* LC_PROBE21_PID = "16'b0000000000010101" *) 
(* LC_PROBE22_PID = "16'b0000000000010110" *) (* LC_PROBE23_PID = "16'b0000000000010111" *) (* LC_PROBE24_PID = "16'b0000000000011000" *) 
(* LC_PROBE25_PID = "16'b0000000000011001" *) (* LC_PROBE26_PID = "16'b0000000000011010" *) (* LC_PROBE27_PID = "16'b0000000000011011" *) 
(* LC_PROBE28_PID = "16'b0000000000011100" *) (* LC_PROBE29_PID = "16'b0000000000011101" *) (* LC_PROBE30_PID = "16'b0000000000011110" *) 
(* LC_PROBE31_PID = "16'b0000000000011111" *) (* LC_PROBE32_PID = "16'b0000000000100000" *) (* LC_PROBE33_PID = "16'b0000000000100001" *) 
(* LC_PROBE34_PID = "16'b0000000000100010" *) (* LC_PROBE35_PID = "16'b0000000000100011" *) (* LC_PROBE36_PID = "16'b0000000000100100" *) 
(* LC_PROBE37_PID = "16'b0000000000100101" *) (* LC_PROBE38_PID = "16'b0000000000100110" *) (* LC_PROBE39_PID = "16'b0000000000100111" *) 
(* LC_PROBE40_PID = "16'b0000000000101000" *) (* LC_PROBE41_PID = "16'b0000000000101001" *) (* LC_PROBE42_PID = "16'b0000000000101010" *) 
(* LC_PROBE43_PID = "16'b0000000000101011" *) (* LC_PROBE44_PID = "16'b0000000000101100" *) (* LC_PROBE45_PID = "16'b0000000000101101" *) 
(* LC_PROBE46_PID = "16'b0000000000101110" *) (* LC_PROBE47_PID = "16'b0000000000101111" *) (* LC_PROBE48_PID = "16'b0000000000110000" *) 
(* LC_PROBE49_PID = "16'b0000000000110001" *) (* LC_PROBE50_PID = "16'b0000000000110010" *) (* LC_PROBE51_PID = "16'b0000000000110011" *) 
(* LC_PROBE52_PID = "16'b0000000000110100" *) (* LC_PROBE53_PID = "16'b0000000000110101" *) (* LC_PROBE54_PID = "16'b0000000000110110" *) 
(* LC_PROBE55_PID = "16'b0000000000110111" *) (* LC_PROBE56_PID = "16'b0000000000111000" *) (* LC_PROBE57_PID = "16'b0000000000111001" *) 
(* LC_PROBE58_PID = "16'b0000000000111010" *) (* LC_PROBE59_PID = "16'b0000000000111011" *) (* LC_PROBE60_PID = "16'b0000000000111100" *) 
(* LC_PROBE61_PID = "16'b0000000000111101" *) (* LC_PROBE62_PID = "16'b0000000000111110" *) (* LC_PROBE63_PID = "16'b0000000000111111" *) 
(* LC_PROBE64_PID = "16'b0000000001000000" *) (* LC_PROBE65_PID = "16'b0000000001000001" *) (* LC_PROBE66_PID = "16'b0000000001000010" *) 
(* LC_PROBE67_PID = "16'b0000000001000011" *) (* LC_PROBE68_PID = "16'b0000000001000100" *) (* LC_PROBE69_PID = "16'b0000000001000101" *) 
(* LC_PROBE70_PID = "16'b0000000001000110" *) (* LC_PROBE71_PID = "16'b0000000001000111" *) (* LC_PROBE72_PID = "16'b0000000001001000" *) 
(* LC_PROBE73_PID = "16'b0000000001001001" *) (* LC_PROBE74_PID = "16'b0000000001001010" *) (* LC_PROBE75_PID = "16'b0000000001001011" *) 
(* LC_PROBE76_PID = "16'b0000000001001100" *) (* LC_PROBE77_PID = "16'b0000000001001101" *) (* LC_PROBE78_PID = "16'b0000000001001110" *) 
(* LC_PROBE79_PID = "16'b0000000001001111" *) (* LC_PROBE80_PID = "16'b0000000001010000" *) (* LC_PROBE81_PID = "16'b0000000001010001" *) 
(* LC_PROBE82_PID = "16'b0000000001010010" *) (* LC_PROBE83_PID = "16'b0000000001010011" *) (* LC_PROBE84_PID = "16'b0000000001010100" *) 
(* LC_PROBE85_PID = "16'b0000000001010101" *) (* LC_PROBE86_PID = "16'b0000000001010110" *) (* LC_PROBE87_PID = "16'b0000000001010111" *) 
(* LC_PROBE88_PID = "16'b0000000001011000" *) (* LC_PROBE89_PID = "16'b0000000001011001" *) (* LC_PROBE90_PID = "16'b0000000001011010" *) 
(* LC_PROBE91_PID = "16'b0000000001011011" *) (* LC_PROBE92_PID = "16'b0000000001011100" *) (* LC_PROBE93_PID = "16'b0000000001011101" *) 
(* LC_PROBE94_PID = "16'b0000000001011110" *) (* LC_PROBE95_PID = "16'b0000000001011111" *) (* LC_PROBE96_PID = "16'b0000000001100000" *) 
(* LC_PROBE97_PID = "16'b0000000001100001" *) (* LC_PROBE98_PID = "16'b0000000001100010" *) (* LC_PROBE99_PID = "16'b0000000001100011" *) 
(* LC_PROBE100_PID = "16'b0000000001100100" *) (* LC_PROBE101_PID = "16'b0000000001100101" *) (* LC_PROBE102_PID = "16'b0000000001100110" *) 
(* LC_PROBE103_PID = "16'b0000000001100111" *) (* LC_PROBE104_PID = "16'b0000000001101000" *) (* LC_PROBE105_PID = "16'b0000000001101001" *) 
(* LC_PROBE106_PID = "16'b0000000001101010" *) (* LC_PROBE107_PID = "16'b0000000001101011" *) (* LC_PROBE108_PID = "16'b0000000001101100" *) 
(* LC_PROBE109_PID = "16'b0000000001101101" *) (* LC_PROBE110_PID = "16'b0000000001101110" *) (* LC_PROBE111_PID = "16'b0000000001101111" *) 
(* LC_PROBE112_PID = "16'b0000000001110000" *) (* LC_PROBE113_PID = "16'b0000000001110001" *) (* LC_PROBE114_PID = "16'b0000000001110010" *) 
(* LC_PROBE115_PID = "16'b0000000001110011" *) (* LC_PROBE116_PID = "16'b0000000001110100" *) (* LC_PROBE117_PID = "16'b0000000001110101" *) 
(* LC_PROBE118_PID = "16'b0000000001110110" *) (* LC_PROBE119_PID = "16'b0000000001110111" *) (* LC_PROBE120_PID = "16'b0000000001111000" *) 
(* LC_PROBE121_PID = "16'b0000000001111001" *) (* LC_PROBE122_PID = "16'b0000000001111010" *) (* LC_PROBE123_PID = "16'b0000000001111011" *) 
(* LC_PROBE124_PID = "16'b0000000001111100" *) (* LC_PROBE125_PID = "16'b0000000001111101" *) (* LC_PROBE126_PID = "16'b0000000001111110" *) 
(* LC_PROBE127_PID = "16'b0000000001111111" *) (* LC_PROBE128_PID = "16'b0000000010000000" *) (* LC_PROBE129_PID = "16'b0000000010000001" *) 
(* LC_PROBE130_PID = "16'b0000000010000010" *) (* LC_PROBE131_PID = "16'b0000000010000011" *) (* LC_PROBE132_PID = "16'b0000000010000100" *) 
(* LC_PROBE133_PID = "16'b0000000010000101" *) (* LC_PROBE134_PID = "16'b0000000010000110" *) (* LC_PROBE135_PID = "16'b0000000010000111" *) 
(* LC_PROBE136_PID = "16'b0000000010001000" *) (* LC_PROBE137_PID = "16'b0000000010001001" *) (* LC_PROBE138_PID = "16'b0000000010001010" *) 
(* LC_PROBE139_PID = "16'b0000000010001011" *) (* LC_PROBE140_PID = "16'b0000000010001100" *) (* LC_PROBE141_PID = "16'b0000000010001101" *) 
(* LC_PROBE142_PID = "16'b0000000010001110" *) (* LC_PROBE143_PID = "16'b0000000010001111" *) (* LC_PROBE144_PID = "16'b0000000010010000" *) 
(* LC_PROBE145_PID = "16'b0000000010010001" *) (* LC_PROBE146_PID = "16'b0000000010010010" *) (* LC_PROBE147_PID = "16'b0000000010010011" *) 
(* LC_PROBE148_PID = "16'b0000000010010100" *) (* LC_PROBE149_PID = "16'b0000000010010101" *) (* LC_PROBE150_PID = "16'b0000000010010110" *) 
(* LC_PROBE151_PID = "16'b0000000010010111" *) (* LC_PROBE152_PID = "16'b0000000010011000" *) (* LC_PROBE153_PID = "16'b0000000010011001" *) 
(* LC_PROBE154_PID = "16'b0000000010011010" *) (* LC_PROBE155_PID = "16'b0000000010011011" *) (* LC_PROBE156_PID = "16'b0000000010011100" *) 
(* LC_PROBE157_PID = "16'b0000000010011101" *) (* LC_PROBE158_PID = "16'b0000000010011110" *) (* LC_PROBE159_PID = "16'b0000000010011111" *) 
(* LC_PROBE160_PID = "16'b0000000010100000" *) (* LC_PROBE161_PID = "16'b0000000010100001" *) (* LC_PROBE162_PID = "16'b0000000010100010" *) 
(* LC_PROBE163_PID = "16'b0000000010100011" *) (* LC_PROBE164_PID = "16'b0000000010100100" *) (* LC_PROBE165_PID = "16'b0000000010100101" *) 
(* LC_PROBE166_PID = "16'b0000000010100110" *) (* LC_PROBE167_PID = "16'b0000000010100111" *) (* LC_PROBE168_PID = "16'b0000000010101000" *) 
(* LC_PROBE169_PID = "16'b0000000010101001" *) (* LC_PROBE170_PID = "16'b0000000010101010" *) (* LC_PROBE171_PID = "16'b0000000010101011" *) 
(* LC_PROBE172_PID = "16'b0000000010101100" *) (* LC_PROBE173_PID = "16'b0000000010101101" *) (* LC_PROBE174_PID = "16'b0000000010101110" *) 
(* LC_PROBE175_PID = "16'b0000000010101111" *) (* LC_PROBE176_PID = "16'b0000000010110000" *) (* LC_PROBE177_PID = "16'b0000000010110001" *) 
(* LC_PROBE178_PID = "16'b0000000010110010" *) (* LC_PROBE179_PID = "16'b0000000010110011" *) (* LC_PROBE180_PID = "16'b0000000010110100" *) 
(* LC_PROBE181_PID = "16'b0000000010110101" *) (* LC_PROBE182_PID = "16'b0000000010110110" *) (* LC_PROBE183_PID = "16'b0000000010110111" *) 
(* LC_PROBE184_PID = "16'b0000000010111000" *) (* LC_PROBE185_PID = "16'b0000000010111001" *) (* LC_PROBE186_PID = "16'b0000000010111010" *) 
(* LC_PROBE187_PID = "16'b0000000010111011" *) (* LC_PROBE188_PID = "16'b0000000010111100" *) (* LC_PROBE189_PID = "16'b0000000010111101" *) 
(* LC_PROBE190_PID = "16'b0000000010111110" *) (* LC_PROBE191_PID = "16'b0000000010111111" *) (* LC_PROBE192_PID = "16'b0000000011000000" *) 
(* LC_PROBE193_PID = "16'b0000000011000001" *) (* LC_PROBE194_PID = "16'b0000000011000010" *) (* LC_PROBE195_PID = "16'b0000000011000011" *) 
(* LC_PROBE196_PID = "16'b0000000011000100" *) (* LC_PROBE197_PID = "16'b0000000011000101" *) (* LC_PROBE198_PID = "16'b0000000011000110" *) 
(* LC_PROBE199_PID = "16'b0000000011000111" *) (* LC_PROBE200_PID = "16'b0000000011001000" *) (* LC_PROBE201_PID = "16'b0000000011001001" *) 
(* LC_PROBE202_PID = "16'b0000000011001010" *) (* LC_PROBE203_PID = "16'b0000000011001011" *) (* LC_PROBE204_PID = "16'b0000000011001100" *) 
(* LC_PROBE205_PID = "16'b0000000011001101" *) (* LC_PROBE206_PID = "16'b0000000011001110" *) (* LC_PROBE207_PID = "16'b0000000011001111" *) 
(* LC_PROBE208_PID = "16'b0000000011010000" *) (* LC_PROBE209_PID = "16'b0000000011010001" *) (* LC_PROBE210_PID = "16'b0000000011010010" *) 
(* LC_PROBE211_PID = "16'b0000000011010011" *) (* LC_PROBE212_PID = "16'b0000000011010100" *) (* LC_PROBE213_PID = "16'b0000000011010101" *) 
(* LC_PROBE214_PID = "16'b0000000011010110" *) (* LC_PROBE215_PID = "16'b0000000011010111" *) (* LC_PROBE216_PID = "16'b0000000011011000" *) 
(* LC_PROBE217_PID = "16'b0000000011011001" *) (* LC_PROBE218_PID = "16'b0000000011011010" *) (* LC_PROBE219_PID = "16'b0000000011011011" *) 
(* LC_PROBE220_PID = "16'b0000000011011100" *) (* LC_PROBE221_PID = "16'b0000000011011101" *) (* LC_PROBE222_PID = "16'b0000000011011110" *) 
(* LC_PROBE223_PID = "16'b0000000011011111" *) (* LC_PROBE224_PID = "16'b0000000011100000" *) (* LC_PROBE225_PID = "16'b0000000011100001" *) 
(* LC_PROBE226_PID = "16'b0000000011100010" *) (* LC_PROBE227_PID = "16'b0000000011100011" *) (* LC_PROBE228_PID = "16'b0000000011100100" *) 
(* LC_PROBE229_PID = "16'b0000000011100101" *) (* LC_PROBE230_PID = "16'b0000000011100110" *) (* LC_PROBE231_PID = "16'b0000000011100111" *) 
(* LC_PROBE232_PID = "16'b0000000011101000" *) (* LC_PROBE233_PID = "16'b0000000011101001" *) (* LC_PROBE234_PID = "16'b0000000011101010" *) 
(* LC_PROBE235_PID = "16'b0000000011101011" *) (* LC_PROBE236_PID = "16'b0000000011101100" *) (* LC_PROBE237_PID = "16'b0000000011101101" *) 
(* LC_PROBE238_PID = "16'b0000000011101110" *) (* LC_PROBE239_PID = "16'b0000000011101111" *) (* LC_PROBE240_PID = "16'b0000000011110000" *) 
(* LC_PROBE241_PID = "16'b0000000011110001" *) (* LC_PROBE242_PID = "16'b0000000011110010" *) (* LC_PROBE243_PID = "16'b0000000011110011" *) 
(* LC_PROBE244_PID = "16'b0000000011110100" *) (* LC_PROBE245_PID = "16'b0000000011110101" *) (* LC_PROBE246_PID = "16'b0000000011110110" *) 
(* LC_PROBE247_PID = "16'b0000000011110111" *) (* LC_PROBE248_PID = "16'b0000000011111000" *) (* LC_PROBE249_PID = "16'b0000000011111001" *) 
(* LC_PROBE250_PID = "16'b0000000011111010" *) (* LC_PROBE251_PID = "16'b0000000011111011" *) (* LC_PROBE252_PID = "16'b0000000011111100" *) 
(* LC_PROBE253_PID = "16'b0000000011111101" *) (* LC_PROBE254_PID = "16'b0000000011111110" *) (* LC_PROBE255_PID = "16'b0000000011111111" *) 
(* LC_PROBE256_PID = "16'b0000000100000000" *) (* LC_PROBE257_PID = "16'b0000000100000001" *) (* LC_PROBE258_PID = "16'b0000000100000010" *) 
(* LC_PROBE259_PID = "16'b0000000100000011" *) (* LC_PROBE260_PID = "16'b0000000100000100" *) (* LC_PROBE261_PID = "16'b0000000100000101" *) 
(* LC_PROBE262_PID = "16'b0000000100000110" *) (* LC_PROBE263_PID = "16'b0000000100000111" *) (* LC_PROBE264_PID = "16'b0000000100001000" *) 
(* LC_PROBE265_PID = "16'b0000000100001001" *) (* LC_PROBE266_PID = "16'b0000000100001010" *) (* LC_PROBE267_PID = "16'b0000000100001011" *) 
(* LC_PROBE268_PID = "16'b0000000100001100" *) (* LC_PROBE269_PID = "16'b0000000100001101" *) (* LC_PROBE270_PID = "16'b0000000100001110" *) 
(* LC_PROBE271_PID = "16'b0000000100001111" *) (* LC_PROBE272_PID = "16'b0000000100010000" *) (* LC_PROBE273_PID = "16'b0000000100010001" *) 
(* LC_PROBE274_PID = "16'b0000000100010010" *) (* LC_PROBE275_PID = "16'b0000000100010011" *) (* LC_PROBE276_PID = "16'b0000000100010100" *) 
(* LC_PROBE277_PID = "16'b0000000100010101" *) (* LC_PROBE278_PID = "16'b0000000100010110" *) (* LC_PROBE279_PID = "16'b0000000100010111" *) 
(* LC_PROBE280_PID = "16'b0000000100011000" *) (* LC_PROBE281_PID = "16'b0000000100011001" *) (* LC_PROBE282_PID = "16'b0000000100011010" *) 
(* LC_PROBE283_PID = "16'b0000000100011011" *) (* LC_PROBE284_PID = "16'b0000000100011100" *) (* LC_PROBE285_PID = "16'b0000000100011101" *) 
(* LC_PROBE286_PID = "16'b0000000100011110" *) (* LC_PROBE287_PID = "16'b0000000100011111" *) (* LC_PROBE288_PID = "16'b0000000100100000" *) 
(* LC_PROBE289_PID = "16'b0000000100100001" *) (* LC_PROBE290_PID = "16'b0000000100100010" *) (* LC_PROBE291_PID = "16'b0000000100100011" *) 
(* LC_PROBE292_PID = "16'b0000000100100100" *) (* LC_PROBE293_PID = "16'b0000000100100101" *) (* LC_PROBE294_PID = "16'b0000000100100110" *) 
(* LC_PROBE295_PID = "16'b0000000100100111" *) (* LC_PROBE296_PID = "16'b0000000100101000" *) (* LC_PROBE297_PID = "16'b0000000100101001" *) 
(* LC_PROBE298_PID = "16'b0000000100101010" *) (* LC_PROBE299_PID = "16'b0000000100101011" *) (* LC_PROBE300_PID = "16'b0000000100101100" *) 
(* LC_PROBE301_PID = "16'b0000000100101101" *) (* LC_PROBE302_PID = "16'b0000000100101110" *) (* LC_PROBE303_PID = "16'b0000000100101111" *) 
(* LC_PROBE304_PID = "16'b0000000100110000" *) (* LC_PROBE305_PID = "16'b0000000100110001" *) (* LC_PROBE306_PID = "16'b0000000100110010" *) 
(* LC_PROBE307_PID = "16'b0000000100110011" *) (* LC_PROBE308_PID = "16'b0000000100110100" *) (* LC_PROBE309_PID = "16'b0000000100110101" *) 
(* LC_PROBE310_PID = "16'b0000000100110110" *) (* LC_PROBE311_PID = "16'b0000000100110111" *) (* LC_PROBE312_PID = "16'b0000000100111000" *) 
(* LC_PROBE313_PID = "16'b0000000100111001" *) (* LC_PROBE314_PID = "16'b0000000100111010" *) (* LC_PROBE315_PID = "16'b0000000100111011" *) 
(* LC_PROBE316_PID = "16'b0000000100111100" *) (* LC_PROBE317_PID = "16'b0000000100111101" *) (* LC_PROBE318_PID = "16'b0000000100111110" *) 
(* LC_PROBE319_PID = "16'b0000000100111111" *) (* LC_PROBE320_PID = "16'b0000000101000000" *) (* LC_PROBE321_PID = "16'b0000000101000001" *) 
(* LC_PROBE322_PID = "16'b0000000101000010" *) (* LC_PROBE323_PID = "16'b0000000101000011" *) (* LC_PROBE324_PID = "16'b0000000101000100" *) 
(* LC_PROBE325_PID = "16'b0000000101000101" *) (* LC_PROBE326_PID = "16'b0000000101000110" *) (* LC_PROBE327_PID = "16'b0000000101000111" *) 
(* LC_PROBE328_PID = "16'b0000000101001000" *) (* LC_PROBE329_PID = "16'b0000000101001001" *) (* LC_PROBE330_PID = "16'b0000000101001010" *) 
(* LC_PROBE331_PID = "16'b0000000101001011" *) (* LC_PROBE332_PID = "16'b0000000101001100" *) (* LC_PROBE333_PID = "16'b0000000101001101" *) 
(* LC_PROBE334_PID = "16'b0000000101001110" *) (* LC_PROBE335_PID = "16'b0000000101001111" *) (* LC_PROBE336_PID = "16'b0000000101010000" *) 
(* LC_PROBE337_PID = "16'b0000000101010001" *) (* LC_PROBE338_PID = "16'b0000000101010010" *) (* LC_PROBE339_PID = "16'b0000000101010011" *) 
(* LC_PROBE340_PID = "16'b0000000101010100" *) (* LC_PROBE341_PID = "16'b0000000101010101" *) (* LC_PROBE342_PID = "16'b0000000101010110" *) 
(* LC_PROBE343_PID = "16'b0000000101010111" *) (* LC_PROBE344_PID = "16'b0000000101011000" *) (* LC_PROBE345_PID = "16'b0000000101011001" *) 
(* LC_PROBE346_PID = "16'b0000000101011010" *) (* LC_PROBE347_PID = "16'b0000000101011011" *) (* LC_PROBE348_PID = "16'b0000000101011100" *) 
(* LC_PROBE349_PID = "16'b0000000101011101" *) (* LC_PROBE350_PID = "16'b0000000101011110" *) (* LC_PROBE351_PID = "16'b0000000101011111" *) 
(* LC_PROBE352_PID = "16'b0000000101100000" *) (* LC_PROBE353_PID = "16'b0000000101100001" *) (* LC_PROBE354_PID = "16'b0000000101100010" *) 
(* LC_PROBE355_PID = "16'b0000000101100011" *) (* LC_PROBE356_PID = "16'b0000000101100100" *) (* LC_PROBE357_PID = "16'b0000000101100101" *) 
(* LC_PROBE358_PID = "16'b0000000101100110" *) (* LC_PROBE359_PID = "16'b0000000101100111" *) (* LC_PROBE360_PID = "16'b0000000101101000" *) 
(* LC_PROBE361_PID = "16'b0000000101101001" *) (* LC_PROBE362_PID = "16'b0000000101101010" *) (* LC_PROBE363_PID = "16'b0000000101101011" *) 
(* LC_PROBE364_PID = "16'b0000000101101100" *) (* LC_PROBE365_PID = "16'b0000000101101101" *) (* LC_PROBE366_PID = "16'b0000000101101110" *) 
(* LC_PROBE367_PID = "16'b0000000101101111" *) (* LC_PROBE368_PID = "16'b0000000101110000" *) (* LC_PROBE369_PID = "16'b0000000101110001" *) 
(* LC_PROBE370_PID = "16'b0000000101110010" *) (* LC_PROBE371_PID = "16'b0000000101110011" *) (* LC_PROBE372_PID = "16'b0000000101110100" *) 
(* LC_PROBE373_PID = "16'b0000000101110101" *) (* LC_PROBE374_PID = "16'b0000000101110110" *) (* LC_PROBE375_PID = "16'b0000000101110111" *) 
(* LC_PROBE376_PID = "16'b0000000101111000" *) (* LC_PROBE377_PID = "16'b0000000101111001" *) (* LC_PROBE378_PID = "16'b0000000101111010" *) 
(* LC_PROBE379_PID = "16'b0000000101111011" *) (* LC_PROBE380_PID = "16'b0000000101111100" *) (* LC_PROBE381_PID = "16'b0000000101111101" *) 
(* LC_PROBE382_PID = "16'b0000000101111110" *) (* LC_PROBE383_PID = "16'b0000000101111111" *) (* LC_PROBE384_PID = "16'b0000000110000000" *) 
(* LC_PROBE385_PID = "16'b0000000110000001" *) (* LC_PROBE386_PID = "16'b0000000110000010" *) (* LC_PROBE387_PID = "16'b0000000110000011" *) 
(* LC_PROBE388_PID = "16'b0000000110000100" *) (* LC_PROBE389_PID = "16'b0000000110000101" *) (* LC_PROBE390_PID = "16'b0000000110000110" *) 
(* LC_PROBE391_PID = "16'b0000000110000111" *) (* LC_PROBE392_PID = "16'b0000000110001000" *) (* LC_PROBE393_PID = "16'b0000000110001001" *) 
(* LC_PROBE394_PID = "16'b0000000110001010" *) (* LC_PROBE395_PID = "16'b0000000110001011" *) (* LC_PROBE396_PID = "16'b0000000110001100" *) 
(* LC_PROBE397_PID = "16'b0000000110001101" *) (* LC_PROBE398_PID = "16'b0000000110001110" *) (* LC_PROBE399_PID = "16'b0000000110001111" *) 
(* LC_PROBE400_PID = "16'b0000000110010000" *) (* LC_PROBE401_PID = "16'b0000000110010001" *) (* LC_PROBE402_PID = "16'b0000000110010010" *) 
(* LC_PROBE403_PID = "16'b0000000110010011" *) (* LC_PROBE404_PID = "16'b0000000110010100" *) (* LC_PROBE405_PID = "16'b0000000110010101" *) 
(* LC_PROBE406_PID = "16'b0000000110010110" *) (* LC_PROBE407_PID = "16'b0000000110010111" *) (* LC_PROBE408_PID = "16'b0000000110011000" *) 
(* LC_PROBE409_PID = "16'b0000000110011001" *) (* LC_PROBE410_PID = "16'b0000000110011010" *) (* LC_PROBE411_PID = "16'b0000000110011011" *) 
(* LC_PROBE412_PID = "16'b0000000110011100" *) (* LC_PROBE413_PID = "16'b0000000110011101" *) (* LC_PROBE414_PID = "16'b0000000110011110" *) 
(* LC_PROBE415_PID = "16'b0000000110011111" *) (* LC_PROBE416_PID = "16'b0000000110100000" *) (* LC_PROBE417_PID = "16'b0000000110100001" *) 
(* LC_PROBE418_PID = "16'b0000000110100010" *) (* LC_PROBE419_PID = "16'b0000000110100011" *) (* LC_PROBE420_PID = "16'b0000000110100100" *) 
(* LC_PROBE421_PID = "16'b0000000110100101" *) (* LC_PROBE422_PID = "16'b0000000110100110" *) (* LC_PROBE423_PID = "16'b0000000110100111" *) 
(* LC_PROBE424_PID = "16'b0000000110101000" *) (* LC_PROBE425_PID = "16'b0000000110101001" *) (* LC_PROBE426_PID = "16'b0000000110101010" *) 
(* LC_PROBE427_PID = "16'b0000000110101011" *) (* LC_PROBE428_PID = "16'b0000000110101100" *) (* LC_PROBE429_PID = "16'b0000000110101101" *) 
(* LC_PROBE430_PID = "16'b0000000110101110" *) (* LC_PROBE431_PID = "16'b0000000110101111" *) (* LC_PROBE432_PID = "16'b0000000110110000" *) 
(* LC_PROBE433_PID = "16'b0000000110110001" *) (* LC_PROBE434_PID = "16'b0000000110110010" *) (* LC_PROBE435_PID = "16'b0000000110110011" *) 
(* LC_PROBE436_PID = "16'b0000000110110100" *) (* LC_PROBE437_PID = "16'b0000000110110101" *) (* LC_PROBE438_PID = "16'b0000000110110110" *) 
(* LC_PROBE439_PID = "16'b0000000110110111" *) (* LC_PROBE440_PID = "16'b0000000110111000" *) (* LC_PROBE441_PID = "16'b0000000110111001" *) 
(* LC_PROBE442_PID = "16'b0000000110111010" *) (* LC_PROBE443_PID = "16'b0000000110111011" *) (* LC_PROBE444_PID = "16'b0000000110111100" *) 
(* LC_PROBE445_PID = "16'b0000000110111101" *) (* LC_PROBE446_PID = "16'b0000000110111110" *) (* LC_PROBE447_PID = "16'b0000000110111111" *) 
(* LC_PROBE448_PID = "16'b0000000111000000" *) (* LC_PROBE449_PID = "16'b0000000111000001" *) (* LC_PROBE450_PID = "16'b0000000111000010" *) 
(* LC_PROBE451_PID = "16'b0000000111000011" *) (* LC_PROBE452_PID = "16'b0000000111000100" *) (* LC_PROBE453_PID = "16'b0000000111000101" *) 
(* LC_PROBE454_PID = "16'b0000000111000110" *) (* LC_PROBE455_PID = "16'b0000000111000111" *) (* LC_PROBE456_PID = "16'b0000000111001000" *) 
(* LC_PROBE457_PID = "16'b0000000111001001" *) (* LC_PROBE458_PID = "16'b0000000111001010" *) (* LC_PROBE459_PID = "16'b0000000111001011" *) 
(* LC_PROBE460_PID = "16'b0000000111001100" *) (* LC_PROBE461_PID = "16'b0000000111001101" *) (* LC_PROBE462_PID = "16'b0000000111001110" *) 
(* LC_PROBE463_PID = "16'b0000000111001111" *) (* LC_PROBE464_PID = "16'b0000000111010000" *) (* LC_PROBE465_PID = "16'b0000000111010001" *) 
(* LC_PROBE466_PID = "16'b0000000111010010" *) (* LC_PROBE467_PID = "16'b0000000111010011" *) (* LC_PROBE468_PID = "16'b0000000111010100" *) 
(* LC_PROBE469_PID = "16'b0000000111010101" *) (* LC_PROBE470_PID = "16'b0000000111010110" *) (* LC_PROBE471_PID = "16'b0000000111010111" *) 
(* LC_PROBE472_PID = "16'b0000000111011000" *) (* LC_PROBE473_PID = "16'b0000000111011001" *) (* LC_PROBE474_PID = "16'b0000000111011010" *) 
(* LC_PROBE475_PID = "16'b0000000111011011" *) (* LC_PROBE476_PID = "16'b0000000111011100" *) (* LC_PROBE477_PID = "16'b0000000111011101" *) 
(* LC_PROBE478_PID = "16'b0000000111011110" *) (* LC_PROBE479_PID = "16'b0000000111011111" *) (* LC_PROBE480_PID = "16'b0000000111100000" *) 
(* LC_PROBE481_PID = "16'b0000000111100001" *) (* LC_PROBE482_PID = "16'b0000000111100010" *) (* LC_PROBE483_PID = "16'b0000000111100011" *) 
(* LC_PROBE484_PID = "16'b0000000111100100" *) (* LC_PROBE485_PID = "16'b0000000111100101" *) (* LC_PROBE486_PID = "16'b0000000111100110" *) 
(* LC_PROBE487_PID = "16'b0000000111100111" *) (* LC_PROBE488_PID = "16'b0000000111101000" *) (* LC_PROBE489_PID = "16'b0000000111101001" *) 
(* LC_PROBE490_PID = "16'b0000000111101010" *) (* LC_PROBE491_PID = "16'b0000000111101011" *) (* LC_PROBE492_PID = "16'b0000000111101100" *) 
(* LC_PROBE493_PID = "16'b0000000111101101" *) (* LC_PROBE494_PID = "16'b0000000111101110" *) (* LC_PROBE495_PID = "16'b0000000111101111" *) 
(* LC_PROBE496_PID = "16'b0000000111110000" *) (* LC_PROBE497_PID = "16'b0000000111110001" *) (* LC_PROBE498_PID = "16'b0000000111110010" *) 
(* LC_PROBE499_PID = "16'b0000000111110011" *) (* LC_PROBE500_PID = "16'b0000000111110100" *) (* LC_PROBE501_PID = "16'b0000000111110101" *) 
(* LC_PROBE502_PID = "16'b0000000111110110" *) (* LC_PROBE503_PID = "16'b0000000111110111" *) (* LC_PROBE504_PID = "16'b0000000111111000" *) 
(* LC_PROBE505_PID = "16'b0000000111111001" *) (* LC_PROBE506_PID = "16'b0000000111111010" *) (* LC_PROBE507_PID = "16'b0000000111111011" *) 
(* LC_PROBE508_PID = "16'b0000000111111100" *) (* LC_PROBE509_PID = "16'b0000000111111101" *) (* LC_PROBE510_PID = "16'b0000000111111110" *) 
(* LC_PROBE511_PID = "16'b0000000111111111" *) (* LC_PROBE512_PID = "16'b0000001000000000" *) (* LC_PROBE513_PID = "16'b0000001000000001" *) 
(* LC_PROBE514_PID = "16'b0000001000000010" *) (* LC_PROBE515_PID = "16'b0000001000000011" *) (* LC_PROBE516_PID = "16'b0000001000000100" *) 
(* LC_PROBE517_PID = "16'b0000001000000101" *) (* LC_PROBE518_PID = "16'b0000001000000110" *) (* LC_PROBE519_PID = "16'b0000001000000111" *) 
(* LC_PROBE520_PID = "16'b0000001000001000" *) (* LC_PROBE521_PID = "16'b0000001000001001" *) (* LC_PROBE522_PID = "16'b0000001000001010" *) 
(* LC_PROBE523_PID = "16'b0000001000001011" *) (* LC_PROBE524_PID = "16'b0000001000001100" *) (* LC_PROBE525_PID = "16'b0000001000001101" *) 
(* LC_PROBE526_PID = "16'b0000001000001110" *) (* LC_PROBE527_PID = "16'b0000001000001111" *) (* LC_PROBE528_PID = "16'b0000001000010000" *) 
(* LC_PROBE529_PID = "16'b0000001000010001" *) (* LC_PROBE530_PID = "16'b0000001000010010" *) (* LC_PROBE531_PID = "16'b0000001000010011" *) 
(* LC_PROBE532_PID = "16'b0000001000010100" *) (* LC_PROBE533_PID = "16'b0000001000010101" *) (* LC_PROBE534_PID = "16'b0000001000010110" *) 
(* LC_PROBE535_PID = "16'b0000001000010111" *) (* LC_PROBE536_PID = "16'b0000001000011000" *) (* LC_PROBE537_PID = "16'b0000001000011001" *) 
(* LC_PROBE538_PID = "16'b0000001000011010" *) (* LC_PROBE539_PID = "16'b0000001000011011" *) (* LC_PROBE540_PID = "16'b0000001000011100" *) 
(* LC_PROBE541_PID = "16'b0000001000011101" *) (* LC_PROBE542_PID = "16'b0000001000011110" *) (* LC_PROBE543_PID = "16'b0000001000011111" *) 
(* LC_PROBE544_PID = "16'b0000001000100000" *) (* LC_PROBE545_PID = "16'b0000001000100001" *) (* LC_PROBE546_PID = "16'b0000001000100010" *) 
(* LC_PROBE547_PID = "16'b0000001000100011" *) (* LC_PROBE548_PID = "16'b0000001000100100" *) (* LC_PROBE549_PID = "16'b0000001000100101" *) 
(* LC_PROBE550_PID = "16'b0000001000100110" *) (* LC_PROBE551_PID = "16'b0000001000100111" *) (* LC_PROBE552_PID = "16'b0000001000101000" *) 
(* LC_PROBE553_PID = "16'b0000001000101001" *) (* LC_PROBE554_PID = "16'b0000001000101010" *) (* LC_PROBE555_PID = "16'b0000001000101011" *) 
(* LC_PROBE556_PID = "16'b0000001000101100" *) (* LC_PROBE557_PID = "16'b0000001000101101" *) (* LC_PROBE558_PID = "16'b0000001000101110" *) 
(* LC_PROBE559_PID = "16'b0000001000101111" *) (* LC_PROBE560_PID = "16'b0000001000110000" *) (* LC_PROBE561_PID = "16'b0000001000110001" *) 
(* LC_PROBE562_PID = "16'b0000001000110010" *) (* LC_PROBE563_PID = "16'b0000001000110011" *) (* LC_PROBE564_PID = "16'b0000001000110100" *) 
(* LC_PROBE565_PID = "16'b0000001000110101" *) (* LC_PROBE566_PID = "16'b0000001000110110" *) (* LC_PROBE567_PID = "16'b0000001000110111" *) 
(* LC_PROBE568_PID = "16'b0000001000111000" *) (* LC_PROBE569_PID = "16'b0000001000111001" *) (* LC_PROBE570_PID = "16'b0000001000111010" *) 
(* LC_PROBE571_PID = "16'b0000001000111011" *) (* LC_PROBE572_PID = "16'b0000001000111100" *) (* LC_PROBE573_PID = "16'b0000001000111101" *) 
(* LC_PROBE574_PID = "16'b0000001000111110" *) (* LC_PROBE575_PID = "16'b0000001000111111" *) (* LC_PROBE576_PID = "16'b0000001001000000" *) 
(* LC_PROBE577_PID = "16'b0000001001000001" *) (* LC_PROBE578_PID = "16'b0000001001000010" *) (* LC_PROBE579_PID = "16'b0000001001000011" *) 
(* LC_PROBE580_PID = "16'b0000001001000100" *) (* LC_PROBE581_PID = "16'b0000001001000101" *) (* LC_PROBE582_PID = "16'b0000001001000110" *) 
(* LC_PROBE583_PID = "16'b0000001001000111" *) (* LC_PROBE584_PID = "16'b0000001001001000" *) (* LC_PROBE585_PID = "16'b0000001001001001" *) 
(* LC_PROBE586_PID = "16'b0000001001001010" *) (* LC_PROBE587_PID = "16'b0000001001001011" *) (* LC_PROBE588_PID = "16'b0000001001001100" *) 
(* LC_PROBE589_PID = "16'b0000001001001101" *) (* LC_PROBE590_PID = "16'b0000001001001110" *) (* LC_PROBE591_PID = "16'b0000001001001111" *) 
(* LC_PROBE592_PID = "16'b0000001001010000" *) (* LC_PROBE593_PID = "16'b0000001001010001" *) (* LC_PROBE594_PID = "16'b0000001001010010" *) 
(* LC_PROBE595_PID = "16'b0000001001010011" *) (* LC_PROBE596_PID = "16'b0000001001010100" *) (* LC_PROBE597_PID = "16'b0000001001010101" *) 
(* LC_PROBE598_PID = "16'b0000001001010110" *) (* LC_PROBE599_PID = "16'b0000001001010111" *) (* LC_PROBE600_PID = "16'b0000001001011000" *) 
(* LC_PROBE601_PID = "16'b0000001001011001" *) (* LC_PROBE602_PID = "16'b0000001001011010" *) (* LC_PROBE603_PID = "16'b0000001001011011" *) 
(* LC_PROBE604_PID = "16'b0000001001011100" *) (* LC_PROBE605_PID = "16'b0000001001011101" *) (* LC_PROBE606_PID = "16'b0000001001011110" *) 
(* LC_PROBE607_PID = "16'b0000001001011111" *) (* LC_PROBE608_PID = "16'b0000001001100000" *) (* LC_PROBE609_PID = "16'b0000001001100001" *) 
(* LC_PROBE610_PID = "16'b0000001001100010" *) (* LC_PROBE611_PID = "16'b0000001001100011" *) (* LC_PROBE612_PID = "16'b0000001001100100" *) 
(* LC_PROBE613_PID = "16'b0000001001100101" *) (* LC_PROBE614_PID = "16'b0000001001100110" *) (* LC_PROBE615_PID = "16'b0000001001100111" *) 
(* LC_PROBE616_PID = "16'b0000001001101000" *) (* LC_PROBE617_PID = "16'b0000001001101001" *) (* LC_PROBE618_PID = "16'b0000001001101010" *) 
(* LC_PROBE619_PID = "16'b0000001001101011" *) (* LC_PROBE620_PID = "16'b0000001001101100" *) (* LC_PROBE621_PID = "16'b0000001001101101" *) 
(* LC_PROBE622_PID = "16'b0000001001101110" *) (* LC_PROBE623_PID = "16'b0000001001101111" *) (* LC_PROBE624_PID = "16'b0000001001110000" *) 
(* LC_PROBE625_PID = "16'b0000001001110001" *) (* LC_PROBE626_PID = "16'b0000001001110010" *) (* LC_PROBE627_PID = "16'b0000001001110011" *) 
(* LC_PROBE628_PID = "16'b0000001001110100" *) (* LC_PROBE629_PID = "16'b0000001001110101" *) (* LC_PROBE630_PID = "16'b0000001001110110" *) 
(* LC_PROBE631_PID = "16'b0000001001110111" *) (* LC_PROBE632_PID = "16'b0000001001111000" *) (* LC_PROBE633_PID = "16'b0000001001111001" *) 
(* LC_PROBE634_PID = "16'b0000001001111010" *) (* LC_PROBE635_PID = "16'b0000001001111011" *) (* LC_PROBE636_PID = "16'b0000001001111100" *) 
(* LC_PROBE637_PID = "16'b0000001001111101" *) (* LC_PROBE638_PID = "16'b0000001001111110" *) (* LC_PROBE639_PID = "16'b0000001001111111" *) 
(* LC_PROBE640_PID = "16'b0000001010000000" *) (* LC_PROBE641_PID = "16'b0000001010000001" *) (* LC_PROBE642_PID = "16'b0000001010000010" *) 
(* LC_PROBE643_PID = "16'b0000001010000011" *) (* LC_PROBE644_PID = "16'b0000001010000100" *) (* LC_PROBE645_PID = "16'b0000001010000101" *) 
(* LC_PROBE646_PID = "16'b0000001010000110" *) (* LC_PROBE647_PID = "16'b0000001010000111" *) (* LC_PROBE648_PID = "16'b0000001010001000" *) 
(* LC_PROBE649_PID = "16'b0000001010001001" *) (* LC_PROBE650_PID = "16'b0000001010001010" *) (* LC_PROBE651_PID = "16'b0000001010001011" *) 
(* LC_PROBE652_PID = "16'b0000001010001100" *) (* LC_PROBE653_PID = "16'b0000001010001101" *) (* LC_PROBE654_PID = "16'b0000001010001110" *) 
(* LC_PROBE655_PID = "16'b0000001010001111" *) (* LC_PROBE656_PID = "16'b0000001010010000" *) (* LC_PROBE657_PID = "16'b0000001010010001" *) 
(* LC_PROBE658_PID = "16'b0000001010010010" *) (* LC_PROBE659_PID = "16'b0000001010010011" *) (* LC_PROBE660_PID = "16'b0000001010010100" *) 
(* LC_PROBE661_PID = "16'b0000001010010101" *) (* LC_PROBE662_PID = "16'b0000001010010110" *) (* LC_PROBE663_PID = "16'b0000001010010111" *) 
(* LC_PROBE664_PID = "16'b0000001010011000" *) (* LC_PROBE665_PID = "16'b0000001010011001" *) (* LC_PROBE666_PID = "16'b0000001010011010" *) 
(* LC_PROBE667_PID = "16'b0000001010011011" *) (* LC_PROBE668_PID = "16'b0000001010011100" *) (* LC_PROBE669_PID = "16'b0000001010011101" *) 
(* LC_PROBE670_PID = "16'b0000001010011110" *) (* LC_PROBE671_PID = "16'b0000001010011111" *) (* LC_PROBE672_PID = "16'b0000001010100000" *) 
(* LC_PROBE673_PID = "16'b0000001010100001" *) (* LC_PROBE674_PID = "16'b0000001010100010" *) (* LC_PROBE675_PID = "16'b0000001010100011" *) 
(* LC_PROBE676_PID = "16'b0000001010100100" *) (* LC_PROBE677_PID = "16'b0000001010100101" *) (* LC_PROBE678_PID = "16'b0000001010100110" *) 
(* LC_PROBE679_PID = "16'b0000001010100111" *) (* LC_PROBE680_PID = "16'b0000001010101000" *) (* LC_PROBE681_PID = "16'b0000001010101001" *) 
(* LC_PROBE682_PID = "16'b0000001010101010" *) (* LC_PROBE683_PID = "16'b0000001010101011" *) (* LC_PROBE684_PID = "16'b0000001010101100" *) 
(* LC_PROBE685_PID = "16'b0000001010101101" *) (* LC_PROBE686_PID = "16'b0000001010101110" *) (* LC_PROBE687_PID = "16'b0000001010101111" *) 
(* LC_PROBE688_PID = "16'b0000001010110000" *) (* LC_PROBE689_PID = "16'b0000001010110001" *) (* LC_PROBE690_PID = "16'b0000001010110010" *) 
(* LC_PROBE691_PID = "16'b0000001010110011" *) (* LC_PROBE692_PID = "16'b0000001010110100" *) (* LC_PROBE693_PID = "16'b0000001010110101" *) 
(* LC_PROBE694_PID = "16'b0000001010110110" *) (* LC_PROBE695_PID = "16'b0000001010110111" *) (* LC_PROBE696_PID = "16'b0000001010111000" *) 
(* LC_PROBE697_PID = "16'b0000001010111001" *) (* LC_PROBE698_PID = "16'b0000001010111010" *) (* LC_PROBE699_PID = "16'b0000001010111011" *) 
(* LC_PROBE700_PID = "16'b0000001010111100" *) (* LC_PROBE701_PID = "16'b0000001010111101" *) (* LC_PROBE702_PID = "16'b0000001010111110" *) 
(* LC_PROBE703_PID = "16'b0000001010111111" *) (* LC_PROBE704_PID = "16'b0000001011000000" *) (* LC_PROBE705_PID = "16'b0000001011000001" *) 
(* LC_PROBE706_PID = "16'b0000001011000010" *) (* LC_PROBE707_PID = "16'b0000001011000011" *) (* LC_PROBE708_PID = "16'b0000001011000100" *) 
(* LC_PROBE709_PID = "16'b0000001011000101" *) (* LC_PROBE710_PID = "16'b0000001011000110" *) (* LC_PROBE711_PID = "16'b0000001011000111" *) 
(* LC_PROBE712_PID = "16'b0000001011001000" *) (* LC_PROBE713_PID = "16'b0000001011001001" *) (* LC_PROBE714_PID = "16'b0000001011001010" *) 
(* LC_PROBE715_PID = "16'b0000001011001011" *) (* LC_PROBE716_PID = "16'b0000001011001100" *) (* LC_PROBE717_PID = "16'b0000001011001101" *) 
(* LC_PROBE718_PID = "16'b0000001011001110" *) (* LC_PROBE719_PID = "16'b0000001011001111" *) (* LC_PROBE720_PID = "16'b0000001011010000" *) 
(* LC_PROBE721_PID = "16'b0000001011010001" *) (* LC_PROBE722_PID = "16'b0000001011010010" *) (* LC_PROBE723_PID = "16'b0000001011010011" *) 
(* LC_PROBE724_PID = "16'b0000001011010100" *) (* LC_PROBE725_PID = "16'b0000001011010101" *) (* LC_PROBE726_PID = "16'b0000001011010110" *) 
(* LC_PROBE727_PID = "16'b0000001011010111" *) (* LC_PROBE728_PID = "16'b0000001011011000" *) (* LC_PROBE729_PID = "16'b0000001011011001" *) 
(* LC_PROBE730_PID = "16'b0000001011011010" *) (* LC_PROBE731_PID = "16'b0000001011011011" *) (* LC_PROBE732_PID = "16'b0000001011011100" *) 
(* LC_PROBE733_PID = "16'b0000001011011101" *) (* LC_PROBE734_PID = "16'b0000001011011110" *) (* LC_PROBE735_PID = "16'b0000001011011111" *) 
(* LC_PROBE736_PID = "16'b0000001011100000" *) (* LC_PROBE737_PID = "16'b0000001011100001" *) (* LC_PROBE738_PID = "16'b0000001011100010" *) 
(* LC_PROBE739_PID = "16'b0000001011100011" *) (* LC_PROBE740_PID = "16'b0000001011100100" *) (* LC_PROBE741_PID = "16'b0000001011100101" *) 
(* LC_PROBE742_PID = "16'b0000001011100110" *) (* LC_PROBE743_PID = "16'b0000001011100111" *) (* LC_PROBE744_PID = "16'b0000001011101000" *) 
(* LC_PROBE745_PID = "16'b0000001011101001" *) (* LC_PROBE746_PID = "16'b0000001011101010" *) (* LC_PROBE747_PID = "16'b0000001011101011" *) 
(* LC_PROBE748_PID = "16'b0000001011101100" *) (* LC_PROBE749_PID = "16'b0000001011101101" *) (* LC_PROBE750_PID = "16'b0000001011101110" *) 
(* LC_PROBE751_PID = "16'b0000001011101111" *) (* LC_PROBE752_PID = "16'b0000001011110000" *) (* LC_PROBE753_PID = "16'b0000001011110001" *) 
(* LC_PROBE754_PID = "16'b0000001011110010" *) (* LC_PROBE755_PID = "16'b0000001011110011" *) (* LC_PROBE756_PID = "16'b0000001011110100" *) 
(* LC_PROBE757_PID = "16'b0000001011110101" *) (* LC_PROBE758_PID = "16'b0000001011110110" *) (* LC_PROBE759_PID = "16'b0000001011110111" *) 
(* LC_PROBE760_PID = "16'b0000001011111000" *) (* LC_PROBE761_PID = "16'b0000001011111001" *) (* LC_PROBE762_PID = "16'b0000001011111010" *) 
(* LC_PROBE763_PID = "16'b0000001011111011" *) (* LC_PROBE764_PID = "16'b0000001011111100" *) (* LC_PROBE765_PID = "16'b0000001011111101" *) 
(* LC_PROBE766_PID = "16'b0000001011111110" *) (* LC_PROBE767_PID = "16'b0000001011111111" *) (* LC_PROBE768_PID = "16'b0000001100000000" *) 
(* LC_PROBE769_PID = "16'b0000001100000001" *) (* LC_PROBE770_PID = "16'b0000001100000010" *) (* LC_PROBE771_PID = "16'b0000001100000011" *) 
(* LC_PROBE772_PID = "16'b0000001100000100" *) (* LC_PROBE773_PID = "16'b0000001100000101" *) (* LC_PROBE774_PID = "16'b0000001100000110" *) 
(* LC_PROBE775_PID = "16'b0000001100000111" *) (* LC_PROBE776_PID = "16'b0000001100001000" *) (* LC_PROBE777_PID = "16'b0000001100001001" *) 
(* LC_PROBE778_PID = "16'b0000001100001010" *) (* LC_PROBE779_PID = "16'b0000001100001011" *) (* LC_PROBE780_PID = "16'b0000001100001100" *) 
(* LC_PROBE781_PID = "16'b0000001100001101" *) (* LC_PROBE782_PID = "16'b0000001100001110" *) (* LC_PROBE783_PID = "16'b0000001100001111" *) 
(* LC_PROBE784_PID = "16'b0000001100010000" *) (* LC_PROBE785_PID = "16'b0000001100010001" *) (* LC_PROBE786_PID = "16'b0000001100010010" *) 
(* LC_PROBE787_PID = "16'b0000001100010011" *) (* LC_PROBE788_PID = "16'b0000001100010100" *) (* LC_PROBE789_PID = "16'b0000001100010101" *) 
(* LC_PROBE790_PID = "16'b0000001100010110" *) (* LC_PROBE791_PID = "16'b0000001100010111" *) (* LC_PROBE792_PID = "16'b0000001100011000" *) 
(* LC_PROBE793_PID = "16'b0000001100011001" *) (* LC_PROBE794_PID = "16'b0000001100011010" *) (* LC_PROBE795_PID = "16'b0000001100011011" *) 
(* LC_PROBE796_PID = "16'b0000001100011100" *) (* LC_PROBE797_PID = "16'b0000001100011101" *) (* LC_PROBE798_PID = "16'b0000001100011110" *) 
(* LC_PROBE799_PID = "16'b0000001100011111" *) (* LC_PROBE800_PID = "16'b0000001100100000" *) (* LC_PROBE801_PID = "16'b0000001100100001" *) 
(* LC_PROBE802_PID = "16'b0000001100100010" *) (* LC_PROBE803_PID = "16'b0000001100100011" *) (* LC_PROBE804_PID = "16'b0000001100100100" *) 
(* LC_PROBE805_PID = "16'b0000001100100101" *) (* LC_PROBE806_PID = "16'b0000001100100110" *) (* LC_PROBE807_PID = "16'b0000001100100111" *) 
(* LC_PROBE808_PID = "16'b0000001100101000" *) (* LC_PROBE809_PID = "16'b0000001100101001" *) (* LC_PROBE810_PID = "16'b0000001100101010" *) 
(* LC_PROBE811_PID = "16'b0000001100101011" *) (* LC_PROBE812_PID = "16'b0000001100101100" *) (* LC_PROBE813_PID = "16'b0000001100101101" *) 
(* LC_PROBE814_PID = "16'b0000001100101110" *) (* LC_PROBE815_PID = "16'b0000001100101111" *) (* LC_PROBE816_PID = "16'b0000001100110000" *) 
(* LC_PROBE817_PID = "16'b0000001100110001" *) (* LC_PROBE818_PID = "16'b0000001100110010" *) (* LC_PROBE819_PID = "16'b0000001100110011" *) 
(* LC_PROBE820_PID = "16'b0000001100110100" *) (* LC_PROBE821_PID = "16'b0000001100110101" *) (* LC_PROBE822_PID = "16'b0000001100110110" *) 
(* LC_PROBE823_PID = "16'b0000001100110111" *) (* LC_PROBE824_PID = "16'b0000001100111000" *) (* LC_PROBE825_PID = "16'b0000001100111001" *) 
(* LC_PROBE826_PID = "16'b0000001100111010" *) (* LC_PROBE827_PID = "16'b0000001100111011" *) (* LC_PROBE828_PID = "16'b0000001100111100" *) 
(* LC_PROBE829_PID = "16'b0000001100111101" *) (* LC_PROBE830_PID = "16'b0000001100111110" *) (* LC_PROBE831_PID = "16'b0000001100111111" *) 
(* LC_PROBE832_PID = "16'b0000001101000000" *) (* LC_PROBE833_PID = "16'b0000001101000001" *) (* LC_PROBE834_PID = "16'b0000001101000010" *) 
(* LC_PROBE835_PID = "16'b0000001101000011" *) (* LC_PROBE836_PID = "16'b0000001101000100" *) (* LC_PROBE837_PID = "16'b0000001101000101" *) 
(* LC_PROBE838_PID = "16'b0000001101000110" *) (* LC_PROBE839_PID = "16'b0000001101000111" *) (* LC_PROBE840_PID = "16'b0000001101001000" *) 
(* LC_PROBE841_PID = "16'b0000001101001001" *) (* LC_PROBE842_PID = "16'b0000001101001010" *) (* LC_PROBE843_PID = "16'b0000001101001011" *) 
(* LC_PROBE844_PID = "16'b0000001101001100" *) (* LC_PROBE845_PID = "16'b0000001101001101" *) (* LC_PROBE846_PID = "16'b0000001101001110" *) 
(* LC_PROBE847_PID = "16'b0000001101001111" *) (* LC_PROBE848_PID = "16'b0000001101010000" *) (* LC_PROBE849_PID = "16'b0000001101010001" *) 
(* LC_PROBE850_PID = "16'b0000001101010010" *) (* LC_PROBE851_PID = "16'b0000001101010011" *) (* LC_PROBE852_PID = "16'b0000001101010100" *) 
(* LC_PROBE853_PID = "16'b0000001101010101" *) (* LC_PROBE854_PID = "16'b0000001101010110" *) (* LC_PROBE855_PID = "16'b0000001101010111" *) 
(* LC_PROBE856_PID = "16'b0000001101011000" *) (* LC_PROBE857_PID = "16'b0000001101011001" *) (* LC_PROBE858_PID = "16'b0000001101011010" *) 
(* LC_PROBE859_PID = "16'b0000001101011011" *) (* LC_PROBE860_PID = "16'b0000001101011100" *) (* LC_PROBE861_PID = "16'b0000001101011101" *) 
(* LC_PROBE862_PID = "16'b0000001101011110" *) (* LC_PROBE863_PID = "16'b0000001101011111" *) (* LC_PROBE864_PID = "16'b0000001101100000" *) 
(* LC_PROBE865_PID = "16'b0000001101100001" *) (* LC_PROBE866_PID = "16'b0000001101100010" *) (* LC_PROBE867_PID = "16'b0000001101100011" *) 
(* LC_PROBE868_PID = "16'b0000001101100100" *) (* LC_PROBE869_PID = "16'b0000001101100101" *) (* LC_PROBE870_PID = "16'b0000001101100110" *) 
(* LC_PROBE871_PID = "16'b0000001101100111" *) (* LC_PROBE872_PID = "16'b0000001101101000" *) (* LC_PROBE873_PID = "16'b0000001101101001" *) 
(* LC_PROBE874_PID = "16'b0000001101101010" *) (* LC_PROBE875_PID = "16'b0000001101101011" *) (* LC_PROBE876_PID = "16'b0000001101101100" *) 
(* LC_PROBE877_PID = "16'b0000001101101101" *) (* LC_PROBE878_PID = "16'b0000001101101110" *) (* LC_PROBE879_PID = "16'b0000001101101111" *) 
(* LC_PROBE880_PID = "16'b0000001101110000" *) (* LC_PROBE881_PID = "16'b0000001101110001" *) (* LC_PROBE882_PID = "16'b0000001101110010" *) 
(* LC_PROBE883_PID = "16'b0000001101110011" *) (* LC_PROBE884_PID = "16'b0000001101110100" *) (* LC_PROBE885_PID = "16'b0000001101110101" *) 
(* LC_PROBE886_PID = "16'b0000001101110110" *) (* LC_PROBE887_PID = "16'b0000001101110111" *) (* LC_PROBE888_PID = "16'b0000001101111000" *) 
(* LC_PROBE889_PID = "16'b0000001101111001" *) (* LC_PROBE890_PID = "16'b0000001101111010" *) (* LC_PROBE891_PID = "16'b0000001101111011" *) 
(* LC_PROBE892_PID = "16'b0000001101111100" *) (* LC_PROBE893_PID = "16'b0000001101111101" *) (* LC_PROBE894_PID = "16'b0000001101111110" *) 
(* LC_PROBE895_PID = "16'b0000001101111111" *) (* LC_PROBE896_PID = "16'b0000001110000000" *) (* LC_PROBE897_PID = "16'b0000001110000001" *) 
(* LC_PROBE898_PID = "16'b0000001110000010" *) (* LC_PROBE899_PID = "16'b0000001110000011" *) (* LC_PROBE900_PID = "16'b0000001110000100" *) 
(* LC_PROBE901_PID = "16'b0000001110000101" *) (* LC_PROBE902_PID = "16'b0000001110000110" *) (* LC_PROBE903_PID = "16'b0000001110000111" *) 
(* LC_PROBE904_PID = "16'b0000001110001000" *) (* LC_PROBE905_PID = "16'b0000001110001001" *) (* LC_PROBE906_PID = "16'b0000001110001010" *) 
(* LC_PROBE907_PID = "16'b0000001110001011" *) (* LC_PROBE908_PID = "16'b0000001110001100" *) (* LC_PROBE909_PID = "16'b0000001110001101" *) 
(* LC_PROBE910_PID = "16'b0000001110001110" *) (* LC_PROBE911_PID = "16'b0000001110001111" *) (* LC_PROBE912_PID = "16'b0000001110010000" *) 
(* LC_PROBE913_PID = "16'b0000001110010001" *) (* LC_PROBE914_PID = "16'b0000001110010010" *) (* LC_PROBE915_PID = "16'b0000001110010011" *) 
(* LC_PROBE916_PID = "16'b0000001110010100" *) (* LC_PROBE917_PID = "16'b0000001110010101" *) (* LC_PROBE918_PID = "16'b0000001110010110" *) 
(* LC_PROBE919_PID = "16'b0000001110010111" *) (* LC_PROBE920_PID = "16'b0000001110011000" *) (* LC_PROBE921_PID = "16'b0000001110011001" *) 
(* LC_PROBE922_PID = "16'b0000001110011010" *) (* LC_PROBE923_PID = "16'b0000001110011011" *) (* LC_PROBE924_PID = "16'b0000001110011100" *) 
(* LC_PROBE925_PID = "16'b0000001110011101" *) (* LC_PROBE926_PID = "16'b0000001110011110" *) (* LC_PROBE927_PID = "16'b0000001110011111" *) 
(* LC_PROBE928_PID = "16'b0000001110100000" *) (* LC_PROBE929_PID = "16'b0000001110100001" *) (* LC_PROBE930_PID = "16'b0000001110100010" *) 
(* LC_PROBE931_PID = "16'b0000001110100011" *) (* LC_PROBE932_PID = "16'b0000001110100100" *) (* LC_PROBE933_PID = "16'b0000001110100101" *) 
(* LC_PROBE934_PID = "16'b0000001110100110" *) (* LC_PROBE935_PID = "16'b0000001110100111" *) (* LC_PROBE936_PID = "16'b0000001110101000" *) 
(* LC_PROBE937_PID = "16'b0000001110101001" *) (* LC_PROBE938_PID = "16'b0000001110101010" *) (* LC_PROBE939_PID = "16'b0000001110101011" *) 
(* LC_PROBE940_PID = "16'b0000001110101100" *) (* LC_PROBE941_PID = "16'b0000001110101101" *) (* LC_PROBE942_PID = "16'b0000001110101110" *) 
(* LC_PROBE943_PID = "16'b0000001110101111" *) (* LC_PROBE944_PID = "16'b0000001110110000" *) (* LC_PROBE945_PID = "16'b0000001110110001" *) 
(* LC_PROBE946_PID = "16'b0000001110110010" *) (* LC_PROBE947_PID = "16'b0000001110110011" *) (* LC_PROBE948_PID = "16'b0000001110110100" *) 
(* LC_PROBE949_PID = "16'b0000001110110101" *) (* LC_PROBE950_PID = "16'b0000001110110110" *) (* LC_PROBE951_PID = "16'b0000001110110111" *) 
(* LC_PROBE952_PID = "16'b0000001110111000" *) (* LC_PROBE953_PID = "16'b0000001110111001" *) (* LC_PROBE954_PID = "16'b0000001110111010" *) 
(* LC_PROBE955_PID = "16'b0000001110111011" *) (* LC_PROBE956_PID = "16'b0000001110111100" *) (* LC_PROBE957_PID = "16'b0000001110111101" *) 
(* LC_PROBE958_PID = "16'b0000001110111110" *) (* LC_PROBE959_PID = "16'b0000001110111111" *) (* LC_PROBE960_PID = "16'b0000001111000000" *) 
(* LC_PROBE961_PID = "16'b0000001111000001" *) (* LC_PROBE962_PID = "16'b0000001111000010" *) (* LC_PROBE963_PID = "16'b0000001111000011" *) 
(* LC_PROBE964_PID = "16'b0000001111000100" *) (* LC_PROBE965_PID = "16'b0000001111000101" *) (* LC_PROBE966_PID = "16'b0000001111000110" *) 
(* LC_PROBE967_PID = "16'b0000001111000111" *) (* LC_PROBE968_PID = "16'b0000001111001000" *) (* LC_PROBE969_PID = "16'b0000001111001001" *) 
(* LC_PROBE970_PID = "16'b0000001111001010" *) (* LC_PROBE971_PID = "16'b0000001111001011" *) (* LC_PROBE972_PID = "16'b0000001111001100" *) 
(* LC_PROBE973_PID = "16'b0000001111001101" *) (* LC_PROBE974_PID = "16'b0000001111001110" *) (* LC_PROBE975_PID = "16'b0000001111001111" *) 
(* LC_PROBE976_PID = "16'b0000001111010000" *) (* LC_PROBE977_PID = "16'b0000001111010001" *) (* LC_PROBE978_PID = "16'b0000001111010010" *) 
(* LC_PROBE979_PID = "16'b0000001111010011" *) (* LC_PROBE980_PID = "16'b0000001111010100" *) (* LC_PROBE981_PID = "16'b0000001111010101" *) 
(* LC_PROBE982_PID = "16'b0000001111010110" *) (* LC_PROBE983_PID = "16'b0000001111010111" *) (* LC_PROBE984_PID = "16'b0000001111011000" *) 
(* LC_PROBE985_PID = "16'b0000001111011001" *) (* LC_PROBE986_PID = "16'b0000001111011010" *) (* LC_PROBE987_PID = "16'b0000001111011011" *) 
(* LC_PROBE988_PID = "16'b0000001111011100" *) (* LC_PROBE989_PID = "16'b0000001111011101" *) (* LC_PROBE990_PID = "16'b0000001111011110" *) 
(* LC_PROBE991_PID = "16'b0000001111011111" *) (* LC_PROBE992_PID = "16'b0000001111100000" *) (* LC_PROBE993_PID = "16'b0000001111100001" *) 
(* LC_PROBE994_PID = "16'b0000001111100010" *) (* LC_PROBE995_PID = "16'b0000001111100011" *) (* LC_PROBE996_PID = "16'b0000001111100100" *) 
(* LC_PROBE997_PID = "16'b0000001111100101" *) (* LC_PROBE998_PID = "16'b0000001111100110" *) (* LC_PROBE999_PID = "16'b0000001111100111" *) 
(* LC_PROBE1000_PID = "16'b0000001111101000" *) (* LC_PROBE1001_PID = "16'b0000001111101001" *) (* LC_PROBE1002_PID = "16'b0000001111101010" *) 
(* LC_PROBE1003_PID = "16'b0000001111101011" *) (* LC_PROBE1004_PID = "16'b0000001111101100" *) (* LC_PROBE1005_PID = "16'b0000001111101101" *) 
(* LC_PROBE1006_PID = "16'b0000001111101110" *) (* LC_PROBE1007_PID = "16'b0000001111101111" *) (* LC_PROBE1008_PID = "16'b0000001111110000" *) 
(* LC_PROBE1009_PID = "16'b0000001111110001" *) (* LC_PROBE1010_PID = "16'b0000001111110010" *) (* LC_PROBE1011_PID = "16'b0000001111110011" *) 
(* LC_PROBE1012_PID = "16'b0000001111110100" *) (* LC_PROBE1013_PID = "16'b0000001111110101" *) (* LC_PROBE1014_PID = "16'b0000001111110110" *) 
(* LC_PROBE1015_PID = "16'b0000001111110111" *) (* LC_PROBE1016_PID = "16'b0000001111111000" *) (* LC_PROBE1017_PID = "16'b0000001111111001" *) 
(* LC_PROBE1018_PID = "16'b0000001111111010" *) (* LC_PROBE1019_PID = "16'b0000001111111011" *) (* LC_PROBE1020_PID = "16'b0000001111111100" *) 
(* LC_PROBE1021_PID = "16'b0000001111111101" *) (* LC_PROBE1022_PID = "16'b0000001111111110" *) (* LC_PROBE1023_PID = "16'b0000001111111111" *) 
(* LC_MU_CNT_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_WIDTH_STRING = "16384'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000011111" *) (* LC_MU_COUNT = "13" *) 
(* LC_MATCH_TPID_VEC = "208'b0000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBES_WIDTH = "140" *) (* LC_NUM_TRIG_EQS = "32" *) 
module ila_0_ila_v5_0_ila__parameterized0
   (clk,
    sl_iport0,
    sl_oport0,
    trig_in,
    trig_in_ack,
    trig_out,
    trig_out_ack,
    probe0,
    probe1,
    probe2,
    probe3,
    probe4,
    probe5,
    probe6,
    probe7,
    probe8,
    probe9,
    probe10,
    probe11,
    probe12,
    probe13,
    probe14,
    probe15,
    probe16,
    probe17,
    probe18,
    probe19,
    probe20,
    probe21,
    probe22,
    probe23,
    probe24,
    probe25,
    probe26,
    probe27,
    probe28,
    probe29,
    probe30,
    probe31,
    probe32,
    probe33,
    probe34,
    probe35,
    probe36,
    probe37,
    probe38,
    probe39,
    probe40,
    probe41,
    probe42,
    probe43,
    probe44,
    probe45,
    probe46,
    probe47,
    probe48,
    probe49,
    probe50,
    probe51,
    probe52,
    probe53,
    probe54,
    probe55,
    probe56,
    probe57,
    probe58,
    probe59,
    probe60,
    probe61,
    probe62,
    probe63,
    probe64,
    probe65,
    probe66,
    probe67,
    probe68,
    probe69,
    probe70,
    probe71,
    probe72,
    probe73,
    probe74,
    probe75,
    probe76,
    probe77,
    probe78,
    probe79,
    probe80,
    probe81,
    probe82,
    probe83,
    probe84,
    probe85,
    probe86,
    probe87,
    probe88,
    probe89,
    probe90,
    probe91,
    probe92,
    probe93,
    probe94,
    probe95,
    probe96,
    probe97,
    probe98,
    probe99,
    probe100,
    probe101,
    probe102,
    probe103,
    probe104,
    probe105,
    probe106,
    probe107,
    probe108,
    probe109,
    probe110,
    probe111,
    probe112,
    probe113,
    probe114,
    probe115,
    probe116,
    probe117,
    probe118,
    probe119,
    probe120,
    probe121,
    probe122,
    probe123,
    probe124,
    probe125,
    probe126,
    probe127,
    probe128,
    probe129,
    probe130,
    probe131,
    probe132,
    probe133,
    probe134,
    probe135,
    probe136,
    probe137,
    probe138,
    probe139,
    probe140,
    probe141,
    probe142,
    probe143,
    probe144,
    probe145,
    probe146,
    probe147,
    probe148,
    probe149,
    probe150,
    probe151,
    probe152,
    probe153,
    probe154,
    probe155,
    probe156,
    probe157,
    probe158,
    probe159,
    probe160,
    probe161,
    probe162,
    probe163,
    probe164,
    probe165,
    probe166,
    probe167,
    probe168,
    probe169,
    probe170,
    probe171,
    probe172,
    probe173,
    probe174,
    probe175,
    probe176,
    probe177,
    probe178,
    probe179,
    probe180,
    probe181,
    probe182,
    probe183,
    probe184,
    probe185,
    probe186,
    probe187,
    probe188,
    probe189,
    probe190,
    probe191,
    probe192,
    probe193,
    probe194,
    probe195,
    probe196,
    probe197,
    probe198,
    probe199,
    probe200,
    probe201,
    probe202,
    probe203,
    probe204,
    probe205,
    probe206,
    probe207,
    probe208,
    probe209,
    probe210,
    probe211,
    probe212,
    probe213,
    probe214,
    probe215,
    probe216,
    probe217,
    probe218,
    probe219,
    probe220,
    probe221,
    probe222,
    probe223,
    probe224,
    probe225,
    probe226,
    probe227,
    probe228,
    probe229,
    probe230,
    probe231,
    probe232,
    probe233,
    probe234,
    probe235,
    probe236,
    probe237,
    probe238,
    probe239,
    probe240,
    probe241,
    probe242,
    probe243,
    probe244,
    probe245,
    probe246,
    probe247,
    probe248,
    probe249,
    probe250,
    probe251,
    probe252,
    probe253,
    probe254,
    probe255,
    probe256,
    probe257,
    probe258,
    probe259,
    probe260,
    probe261,
    probe262,
    probe263,
    probe264,
    probe265,
    probe266,
    probe267,
    probe268,
    probe269,
    probe270,
    probe271,
    probe272,
    probe273,
    probe274,
    probe275,
    probe276,
    probe277,
    probe278,
    probe279,
    probe280,
    probe281,
    probe282,
    probe283,
    probe284,
    probe285,
    probe286,
    probe287,
    probe288,
    probe289,
    probe290,
    probe291,
    probe292,
    probe293,
    probe294,
    probe295,
    probe296,
    probe297,
    probe298,
    probe299,
    probe300,
    probe301,
    probe302,
    probe303,
    probe304,
    probe305,
    probe306,
    probe307,
    probe308,
    probe309,
    probe310,
    probe311,
    probe312,
    probe313,
    probe314,
    probe315,
    probe316,
    probe317,
    probe318,
    probe319,
    probe320,
    probe321,
    probe322,
    probe323,
    probe324,
    probe325,
    probe326,
    probe327,
    probe328,
    probe329,
    probe330,
    probe331,
    probe332,
    probe333,
    probe334,
    probe335,
    probe336,
    probe337,
    probe338,
    probe339,
    probe340,
    probe341,
    probe342,
    probe343,
    probe344,
    probe345,
    probe346,
    probe347,
    probe348,
    probe349,
    probe350,
    probe351,
    probe352,
    probe353,
    probe354,
    probe355,
    probe356,
    probe357,
    probe358,
    probe359,
    probe360,
    probe361,
    probe362,
    probe363,
    probe364,
    probe365,
    probe366,
    probe367,
    probe368,
    probe369,
    probe370,
    probe371,
    probe372,
    probe373,
    probe374,
    probe375,
    probe376,
    probe377,
    probe378,
    probe379,
    probe380,
    probe381,
    probe382,
    probe383,
    probe384,
    probe385,
    probe386,
    probe387,
    probe388,
    probe389,
    probe390,
    probe391,
    probe392,
    probe393,
    probe394,
    probe395,
    probe396,
    probe397,
    probe398,
    probe399,
    probe400,
    probe401,
    probe402,
    probe403,
    probe404,
    probe405,
    probe406,
    probe407,
    probe408,
    probe409,
    probe410,
    probe411,
    probe412,
    probe413,
    probe414,
    probe415,
    probe416,
    probe417,
    probe418,
    probe419,
    probe420,
    probe421,
    probe422,
    probe423,
    probe424,
    probe425,
    probe426,
    probe427,
    probe428,
    probe429,
    probe430,
    probe431,
    probe432,
    probe433,
    probe434,
    probe435,
    probe436,
    probe437,
    probe438,
    probe439,
    probe440,
    probe441,
    probe442,
    probe443,
    probe444,
    probe445,
    probe446,
    probe447,
    probe448,
    probe449,
    probe450,
    probe451,
    probe452,
    probe453,
    probe454,
    probe455,
    probe456,
    probe457,
    probe458,
    probe459,
    probe460,
    probe461,
    probe462,
    probe463,
    probe464,
    probe465,
    probe466,
    probe467,
    probe468,
    probe469,
    probe470,
    probe471,
    probe472,
    probe473,
    probe474,
    probe475,
    probe476,
    probe477,
    probe478,
    probe479,
    probe480,
    probe481,
    probe482,
    probe483,
    probe484,
    probe485,
    probe486,
    probe487,
    probe488,
    probe489,
    probe490,
    probe491,
    probe492,
    probe493,
    probe494,
    probe495,
    probe496,
    probe497,
    probe498,
    probe499,
    probe500,
    probe501,
    probe502,
    probe503,
    probe504,
    probe505,
    probe506,
    probe507,
    probe508,
    probe509,
    probe510,
    probe511,
    probe512,
    probe513,
    probe514,
    probe515,
    probe516,
    probe517,
    probe518,
    probe519,
    probe520,
    probe521,
    probe522,
    probe523,
    probe524,
    probe525,
    probe526,
    probe527,
    probe528,
    probe529,
    probe530,
    probe531,
    probe532,
    probe533,
    probe534,
    probe535,
    probe536,
    probe537,
    probe538,
    probe539,
    probe540,
    probe541,
    probe542,
    probe543,
    probe544,
    probe545,
    probe546,
    probe547,
    probe548,
    probe549,
    probe550,
    probe551,
    probe552,
    probe553,
    probe554,
    probe555,
    probe556,
    probe557,
    probe558,
    probe559,
    probe560,
    probe561,
    probe562,
    probe563,
    probe564,
    probe565,
    probe566,
    probe567,
    probe568,
    probe569,
    probe570,
    probe571,
    probe572,
    probe573,
    probe574,
    probe575,
    probe576,
    probe577,
    probe578,
    probe579,
    probe580,
    probe581,
    probe582,
    probe583,
    probe584,
    probe585,
    probe586,
    probe587,
    probe588,
    probe589,
    probe590,
    probe591,
    probe592,
    probe593,
    probe594,
    probe595,
    probe596,
    probe597,
    probe598,
    probe599,
    probe600,
    probe601,
    probe602,
    probe603,
    probe604,
    probe605,
    probe606,
    probe607,
    probe608,
    probe609,
    probe610,
    probe611,
    probe612,
    probe613,
    probe614,
    probe615,
    probe616,
    probe617,
    probe618,
    probe619,
    probe620,
    probe621,
    probe622,
    probe623,
    probe624,
    probe625,
    probe626,
    probe627,
    probe628,
    probe629,
    probe630,
    probe631,
    probe632,
    probe633,
    probe634,
    probe635,
    probe636,
    probe637,
    probe638,
    probe639,
    probe640,
    probe641,
    probe642,
    probe643,
    probe644,
    probe645,
    probe646,
    probe647,
    probe648,
    probe649,
    probe650,
    probe651,
    probe652,
    probe653,
    probe654,
    probe655,
    probe656,
    probe657,
    probe658,
    probe659,
    probe660,
    probe661,
    probe662,
    probe663,
    probe664,
    probe665,
    probe666,
    probe667,
    probe668,
    probe669,
    probe670,
    probe671,
    probe672,
    probe673,
    probe674,
    probe675,
    probe676,
    probe677,
    probe678,
    probe679,
    probe680,
    probe681,
    probe682,
    probe683,
    probe684,
    probe685,
    probe686,
    probe687,
    probe688,
    probe689,
    probe690,
    probe691,
    probe692,
    probe693,
    probe694,
    probe695,
    probe696,
    probe697,
    probe698,
    probe699,
    probe700,
    probe701,
    probe702,
    probe703,
    probe704,
    probe705,
    probe706,
    probe707,
    probe708,
    probe709,
    probe710,
    probe711,
    probe712,
    probe713,
    probe714,
    probe715,
    probe716,
    probe717,
    probe718,
    probe719,
    probe720,
    probe721,
    probe722,
    probe723,
    probe724,
    probe725,
    probe726,
    probe727,
    probe728,
    probe729,
    probe730,
    probe731,
    probe732,
    probe733,
    probe734,
    probe735,
    probe736,
    probe737,
    probe738,
    probe739,
    probe740,
    probe741,
    probe742,
    probe743,
    probe744,
    probe745,
    probe746,
    probe747,
    probe748,
    probe749,
    probe750,
    probe751,
    probe752,
    probe753,
    probe754,
    probe755,
    probe756,
    probe757,
    probe758,
    probe759,
    probe760,
    probe761,
    probe762,
    probe763,
    probe764,
    probe765,
    probe766,
    probe767,
    probe768,
    probe769,
    probe770,
    probe771,
    probe772,
    probe773,
    probe774,
    probe775,
    probe776,
    probe777,
    probe778,
    probe779,
    probe780,
    probe781,
    probe782,
    probe783,
    probe784,
    probe785,
    probe786,
    probe787,
    probe788,
    probe789,
    probe790,
    probe791,
    probe792,
    probe793,
    probe794,
    probe795,
    probe796,
    probe797,
    probe798,
    probe799,
    probe800,
    probe801,
    probe802,
    probe803,
    probe804,
    probe805,
    probe806,
    probe807,
    probe808,
    probe809,
    probe810,
    probe811,
    probe812,
    probe813,
    probe814,
    probe815,
    probe816,
    probe817,
    probe818,
    probe819,
    probe820,
    probe821,
    probe822,
    probe823,
    probe824,
    probe825,
    probe826,
    probe827,
    probe828,
    probe829,
    probe830,
    probe831,
    probe832,
    probe833,
    probe834,
    probe835,
    probe836,
    probe837,
    probe838,
    probe839,
    probe840,
    probe841,
    probe842,
    probe843,
    probe844,
    probe845,
    probe846,
    probe847,
    probe848,
    probe849,
    probe850,
    probe851,
    probe852,
    probe853,
    probe854,
    probe855,
    probe856,
    probe857,
    probe858,
    probe859,
    probe860,
    probe861,
    probe862,
    probe863,
    probe864,
    probe865,
    probe866,
    probe867,
    probe868,
    probe869,
    probe870,
    probe871,
    probe872,
    probe873,
    probe874,
    probe875,
    probe876,
    probe877,
    probe878,
    probe879,
    probe880,
    probe881,
    probe882,
    probe883,
    probe884,
    probe885,
    probe886,
    probe887,
    probe888,
    probe889,
    probe890,
    probe891,
    probe892,
    probe893,
    probe894,
    probe895,
    probe896,
    probe897,
    probe898,
    probe899,
    probe900,
    probe901,
    probe902,
    probe903,
    probe904,
    probe905,
    probe906,
    probe907,
    probe908,
    probe909,
    probe910,
    probe911,
    probe912,
    probe913,
    probe914,
    probe915,
    probe916,
    probe917,
    probe918,
    probe919,
    probe920,
    probe921,
    probe922,
    probe923,
    probe924,
    probe925,
    probe926,
    probe927,
    probe928,
    probe929,
    probe930,
    probe931,
    probe932,
    probe933,
    probe934,
    probe935,
    probe936,
    probe937,
    probe938,
    probe939,
    probe940,
    probe941,
    probe942,
    probe943,
    probe944,
    probe945,
    probe946,
    probe947,
    probe948,
    probe949,
    probe950,
    probe951,
    probe952,
    probe953,
    probe954,
    probe955,
    probe956,
    probe957,
    probe958,
    probe959,
    probe960,
    probe961,
    probe962,
    probe963,
    probe964,
    probe965,
    probe966,
    probe967,
    probe968,
    probe969,
    probe970,
    probe971,
    probe972,
    probe973,
    probe974,
    probe975,
    probe976,
    probe977,
    probe978,
    probe979,
    probe980,
    probe981,
    probe982,
    probe983,
    probe984,
    probe985,
    probe986,
    probe987,
    probe988,
    probe989,
    probe990,
    probe991,
    probe992,
    probe993,
    probe994,
    probe995,
    probe996,
    probe997,
    probe998,
    probe999,
    probe1000,
    probe1001,
    probe1002,
    probe1003,
    probe1004,
    probe1005,
    probe1006,
    probe1007,
    probe1008,
    probe1009,
    probe1010,
    probe1011,
    probe1012,
    probe1013,
    probe1014,
    probe1015,
    probe1016,
    probe1017,
    probe1018,
    probe1019,
    probe1020,
    probe1021,
    probe1022,
    probe1023);
  input clk;
  input [36:0]sl_iport0;
  output [16:0]sl_oport0;
  input trig_in;
  output trig_in_ack;
  output trig_out;
  input trig_out_ack;
  input [31:0]probe0;
  input [0:0]probe1;
  input [0:0]probe2;
  input [31:0]probe3;
  input [0:0]probe4;
  input [0:0]probe5;
  input [31:0]probe6;
  input [0:0]probe7;
  input [0:0]probe8;
  input [31:0]probe9;
  input [0:0]probe10;
  input [0:0]probe11;
  input [3:0]probe12;
  input [0:0]probe13;
  input [0:0]probe14;
  input [0:0]probe15;
  input [0:0]probe16;
  input [0:0]probe17;
  input [0:0]probe18;
  input [0:0]probe19;
  input [0:0]probe20;
  input [0:0]probe21;
  input [0:0]probe22;
  input [0:0]probe23;
  input [0:0]probe24;
  input [0:0]probe25;
  input [0:0]probe26;
  input [0:0]probe27;
  input [0:0]probe28;
  input [0:0]probe29;
  input [0:0]probe30;
  input [0:0]probe31;
  input [0:0]probe32;
  input [0:0]probe33;
  input [0:0]probe34;
  input [0:0]probe35;
  input [0:0]probe36;
  input [0:0]probe37;
  input [0:0]probe38;
  input [0:0]probe39;
  input [0:0]probe40;
  input [0:0]probe41;
  input [0:0]probe42;
  input [0:0]probe43;
  input [0:0]probe44;
  input [0:0]probe45;
  input [0:0]probe46;
  input [0:0]probe47;
  input [0:0]probe48;
  input [0:0]probe49;
  input [0:0]probe50;
  input [0:0]probe51;
  input [0:0]probe52;
  input [0:0]probe53;
  input [0:0]probe54;
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  input [0:0]probe733;
  input [0:0]probe734;
  input [0:0]probe735;
  input [0:0]probe736;
  input [0:0]probe737;
  input [0:0]probe738;
  input [0:0]probe739;
  input [0:0]probe740;
  input [0:0]probe741;
  input [0:0]probe742;
  input [0:0]probe743;
  input [0:0]probe744;
  input [0:0]probe745;
  input [0:0]probe746;
  input [0:0]probe747;
  input [0:0]probe748;
  input [0:0]probe749;
  input [0:0]probe750;
  input [0:0]probe751;
  input [0:0]probe752;
  input [0:0]probe753;
  input [0:0]probe754;
  input [0:0]probe755;
  input [0:0]probe756;
  input [0:0]probe757;
  input [0:0]probe758;
  input [0:0]probe759;
  input [0:0]probe760;
  input [0:0]probe761;
  input [0:0]probe762;
  input [0:0]probe763;
  input [0:0]probe764;
  input [0:0]probe765;
  input [0:0]probe766;
  input [0:0]probe767;
  input [0:0]probe768;
  input [0:0]probe769;
  input [0:0]probe770;
  input [0:0]probe771;
  input [0:0]probe772;
  input [0:0]probe773;
  input [0:0]probe774;
  input [0:0]probe775;
  input [0:0]probe776;
  input [0:0]probe777;
  input [0:0]probe778;
  input [0:0]probe779;
  input [0:0]probe780;
  input [0:0]probe781;
  input [0:0]probe782;
  input [0:0]probe783;
  input [0:0]probe784;
  input [0:0]probe785;
  input [0:0]probe786;
  input [0:0]probe787;
  input [0:0]probe788;
  input [0:0]probe789;
  input [0:0]probe790;
  input [0:0]probe791;
  input [0:0]probe792;
  input [0:0]probe793;
  input [0:0]probe794;
  input [0:0]probe795;
  input [0:0]probe796;
  input [0:0]probe797;
  input [0:0]probe798;
  input [0:0]probe799;
  input [0:0]probe800;
  input [0:0]probe801;
  input [0:0]probe802;
  input [0:0]probe803;
  input [0:0]probe804;
  input [0:0]probe805;
  input [0:0]probe806;
  input [0:0]probe807;
  input [0:0]probe808;
  input [0:0]probe809;
  input [0:0]probe810;
  input [0:0]probe811;
  input [0:0]probe812;
  input [0:0]probe813;
  input [0:0]probe814;
  input [0:0]probe815;
  input [0:0]probe816;
  input [0:0]probe817;
  input [0:0]probe818;
  input [0:0]probe819;
  input [0:0]probe820;
  input [0:0]probe821;
  input [0:0]probe822;
  input [0:0]probe823;
  input [0:0]probe824;
  input [0:0]probe825;
  input [0:0]probe826;
  input [0:0]probe827;
  input [0:0]probe828;
  input [0:0]probe829;
  input [0:0]probe830;
  input [0:0]probe831;
  input [0:0]probe832;
  input [0:0]probe833;
  input [0:0]probe834;
  input [0:0]probe835;
  input [0:0]probe836;
  input [0:0]probe837;
  input [0:0]probe838;
  input [0:0]probe839;
  input [0:0]probe840;
  input [0:0]probe841;
  input [0:0]probe842;
  input [0:0]probe843;
  input [0:0]probe844;
  input [0:0]probe845;
  input [0:0]probe846;
  input [0:0]probe847;
  input [0:0]probe848;
  input [0:0]probe849;
  input [0:0]probe850;
  input [0:0]probe851;
  input [0:0]probe852;
  input [0:0]probe853;
  input [0:0]probe854;
  input [0:0]probe855;
  input [0:0]probe856;
  input [0:0]probe857;
  input [0:0]probe858;
  input [0:0]probe859;
  input [0:0]probe860;
  input [0:0]probe861;
  input [0:0]probe862;
  input [0:0]probe863;
  input [0:0]probe864;
  input [0:0]probe865;
  input [0:0]probe866;
  input [0:0]probe867;
  input [0:0]probe868;
  input [0:0]probe869;
  input [0:0]probe870;
  input [0:0]probe871;
  input [0:0]probe872;
  input [0:0]probe873;
  input [0:0]probe874;
  input [0:0]probe875;
  input [0:0]probe876;
  input [0:0]probe877;
  input [0:0]probe878;
  input [0:0]probe879;
  input [0:0]probe880;
  input [0:0]probe881;
  input [0:0]probe882;
  input [0:0]probe883;
  input [0:0]probe884;
  input [0:0]probe885;
  input [0:0]probe886;
  input [0:0]probe887;
  input [0:0]probe888;
  input [0:0]probe889;
  input [0:0]probe890;
  input [0:0]probe891;
  input [0:0]probe892;
  input [0:0]probe893;
  input [0:0]probe894;
  input [0:0]probe895;
  input [0:0]probe896;
  input [0:0]probe897;
  input [0:0]probe898;
  input [0:0]probe899;
  input [0:0]probe900;
  input [0:0]probe901;
  input [0:0]probe902;
  input [0:0]probe903;
  input [0:0]probe904;
  input [0:0]probe905;
  input [0:0]probe906;
  input [0:0]probe907;
  input [0:0]probe908;
  input [0:0]probe909;
  input [0:0]probe910;
  input [0:0]probe911;
  input [0:0]probe912;
  input [0:0]probe913;
  input [0:0]probe914;
  input [0:0]probe915;
  input [0:0]probe916;
  input [0:0]probe917;
  input [0:0]probe918;
  input [0:0]probe919;
  input [0:0]probe920;
  input [0:0]probe921;
  input [0:0]probe922;
  input [0:0]probe923;
  input [0:0]probe924;
  input [0:0]probe925;
  input [0:0]probe926;
  input [0:0]probe927;
  input [0:0]probe928;
  input [0:0]probe929;
  input [0:0]probe930;
  input [0:0]probe931;
  input [0:0]probe932;
  input [0:0]probe933;
  input [0:0]probe934;
  input [0:0]probe935;
  input [0:0]probe936;
  input [0:0]probe937;
  input [0:0]probe938;
  input [0:0]probe939;
  input [0:0]probe940;
  input [0:0]probe941;
  input [0:0]probe942;
  input [0:0]probe943;
  input [0:0]probe944;
  input [0:0]probe945;
  input [0:0]probe946;
  input [0:0]probe947;
  input [0:0]probe948;
  input [0:0]probe949;
  input [0:0]probe950;
  input [0:0]probe951;
  input [0:0]probe952;
  input [0:0]probe953;
  input [0:0]probe954;
  input [0:0]probe955;
  input [0:0]probe956;
  input [0:0]probe957;
  input [0:0]probe958;
  input [0:0]probe959;
  input [0:0]probe960;
  input [0:0]probe961;
  input [0:0]probe962;
  input [0:0]probe963;
  input [0:0]probe964;
  input [0:0]probe965;
  input [0:0]probe966;
  input [0:0]probe967;
  input [0:0]probe968;
  input [0:0]probe969;
  input [0:0]probe970;
  input [0:0]probe971;
  input [0:0]probe972;
  input [0:0]probe973;
  input [0:0]probe974;
  input [0:0]probe975;
  input [0:0]probe976;
  input [0:0]probe977;
  input [0:0]probe978;
  input [0:0]probe979;
  input [0:0]probe980;
  input [0:0]probe981;
  input [0:0]probe982;
  input [0:0]probe983;
  input [0:0]probe984;
  input [0:0]probe985;
  input [0:0]probe986;
  input [0:0]probe987;
  input [0:0]probe988;
  input [0:0]probe989;
  input [0:0]probe990;
  input [0:0]probe991;
  input [0:0]probe992;
  input [0:0]probe993;
  input [0:0]probe994;
  input [0:0]probe995;
  input [0:0]probe996;
  input [0:0]probe997;
  input [0:0]probe998;
  input [0:0]probe999;
  input [0:0]probe1000;
  input [0:0]probe1001;
  input [0:0]probe1002;
  input [0:0]probe1003;
  input [0:0]probe1004;
  input [0:0]probe1005;
  input [0:0]probe1006;
  input [0:0]probe1007;
  input [0:0]probe1008;
  input [0:0]probe1009;
  input [0:0]probe1010;
  input [0:0]probe1011;
  input [0:0]probe1012;
  input [0:0]probe1013;
  input [0:0]probe1014;
  input [0:0]probe1015;
  input [0:0]probe1016;
  input [0:0]probe1017;
  input [0:0]probe1018;
  input [0:0]probe1019;
  input [0:0]probe1020;
  input [0:0]probe1021;
  input [0:0]probe1022;
  input [0:0]probe1023;

  wire \<const0> ;
  wire clk;
  wire [31:0]probe0;
  wire [0:0]probe1;
  wire [0:0]probe10;
  wire [0:0]probe11;
  wire [3:0]probe12;
  wire [0:0]probe2;
  wire [31:0]probe3;
  wire [0:0]probe4;
  wire [0:0]probe5;
  wire [31:0]probe6;
  wire [0:0]probe7;
  wire [0:0]probe8;
  wire [31:0]probe9;
(* DONT_TOUCH *)   wire [36:0]sl_iport0;
(* DONT_TOUCH *)   wire [16:0]sl_oport0;
  wire trig_in;
  wire trig_out_ack;

  assign trig_in_ack = \<const0> ;
  assign trig_out = \<const0> ;
GND GND
       (.G(\<const0> ));
ila_0_ila_v5_0_ila_core ila_core_inst
       (.SL_IPORT_I(sl_iport0),
        .SL_OPORT_O(sl_oport0),
        .clk(clk),
        .probe0(probe0),
        .probe1(probe1),
        .probe10(probe10),
        .probe11(probe11),
        .probe12(probe12),
        .probe2(probe2),
        .probe3(probe3),
        .probe4(probe4),
        .probe5(probe5),
        .probe6(probe6),
        .probe7(probe7),
        .probe8(probe8),
        .probe9(probe9));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_adv_trigger_sequencer" *) 
module ila_0_ila_v5_0_ila_adv_trigger_sequencer
   (capture_fsm_temp,
    trig_out_fsm_temp,
    CNT_CTRL,
    addra,
    O1,
    O2,
    O3,
    cntcmpsel,
    SEQUENCER_STATE_I,
    FLAG0_I,
    FLAG1_I,
    FLAG2_I,
    FLAG3_I,
    toggle_rd,
    S_DCLK_O,
    bram_rd_en,
    E,
    bram_en,
    I1,
    clk,
    I2,
    I3,
    arm_status,
    Q,
    I4,
    p_2_out,
    CFG_BRAM_DATA,
    ADDRA);
  output capture_fsm_temp;
  output trig_out_fsm_temp;
  output [7:0]CNT_CTRL;
  output [3:0]addra;
  output O1;
  output O2;
  output [23:0]O3;
  output [1:0]cntcmpsel;
  output [15:0]SEQUENCER_STATE_I;
  output FLAG0_I;
  output FLAG1_I;
  output FLAG2_I;
  output FLAG3_I;
  input toggle_rd;
  input S_DCLK_O;
  input bram_rd_en;
  input [0:0]E;
  input bram_en;
  input I1;
  input clk;
  input I2;
  input I3;
  input arm_status;
  input [1:0]Q;
  input I4;
  input [0:0]p_2_out;
  input [23:0]CFG_BRAM_DATA;
  input [2:0]ADDRA;

  wire [2:0]ADDRA;
  wire [23:0]CFG_BRAM_DATA;
  wire CFG_BRAM_RD_DATA0;
  wire [7:0]CNT_CTRL;
  wire [0:0]E;
  wire FLAG0_I;
  wire FLAG1_I;
  wire FLAG2_I;
  wire FLAG3_I;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire O1;
  wire O2;
  wire [23:0]O3;
  wire [1:0]Q;
  wire [15:0]SEQUENCER_STATE_I;
  wire S_DCLK_O;
  wire [3:0]addra;
  wire arm_status;
  wire [6:0]bram_addr_reg;
  wire bram_en;
  wire bram_en_1;
  wire [6:0]bram_rd_addr_reg;
  wire bram_rd_en;
  wire bram_rd_en_0;
  wire bram_rd_we;
  wire bram_we;
  wire capture_fsm_temp;
  wire clk;
  wire [1:0]cntcmpsel;
  wire [13:0]douta0;
  wire \n_0_CFG_BRAM_RD_DATA[0]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[10]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[11]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[12]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[13]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[14]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[15]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[16]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[17]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[18]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[19]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[1]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[20]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[21]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[22]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[23]_i_2 ;
  wire \n_0_CFG_BRAM_RD_DATA[2]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[3]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[4]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[5]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[6]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[7]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[8]_i_1 ;
  wire \n_0_CFG_BRAM_RD_DATA[9]_i_1 ;
  wire n_0_FLAG0_O_i_1;
  wire n_0_FLAG0_O_i_2;
  wire n_0_FLAG1_O_i_1;
  wire n_0_FLAG1_O_i_2;
  wire n_0_FLAG2_O_i_1;
  wire n_0_FLAG2_O_i_2;
  wire n_0_FLAG3_O_i_1;
  wire n_0_FLAG3_O_i_2;
  wire \n_0_SEQUENCER_STATE_O[0]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[10]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[11]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[12]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[13]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[14]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[15]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[1]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[2]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[3]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[4]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[5]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[6]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[7]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[8]_i_1 ;
  wire \n_0_SEQUENCER_STATE_O[9]_i_1 ;
  wire \n_0_bram_addr[6]_i_3 ;
  wire \n_0_bram_rd_addr[6]_i_2 ;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1;
  wire n_0_fsm_mem_data_reg_r1_0_63_12_14;
  wire n_0_fsm_mem_data_reg_r1_0_63_15_17;
  wire n_0_fsm_mem_data_reg_r1_0_63_18_20;
  wire n_0_fsm_mem_data_reg_r1_0_63_21_23;
  wire n_0_fsm_mem_data_reg_r1_0_63_3_5;
  wire n_0_fsm_mem_data_reg_r1_0_63_6_8;
  wire n_0_fsm_mem_data_reg_r1_0_63_9_11;
  wire n_0_fsm_mem_data_reg_r1_64_127_0_2;
  wire n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1;
  wire n_0_fsm_mem_data_reg_r1_64_127_12_14;
  wire n_0_fsm_mem_data_reg_r1_64_127_15_17;
  wire n_0_fsm_mem_data_reg_r1_64_127_18_20;
  wire n_0_fsm_mem_data_reg_r1_64_127_21_23;
  wire n_0_fsm_mem_data_reg_r1_64_127_3_5;
  wire n_0_fsm_mem_data_reg_r1_64_127_6_8;
  wire n_0_fsm_mem_data_reg_r1_64_127_9_11;
  wire n_0_fsm_mem_data_reg_r2_0_63_0_2;
  wire n_0_fsm_mem_data_reg_r2_0_63_12_14;
  wire n_0_fsm_mem_data_reg_r2_0_63_15_17;
  wire n_0_fsm_mem_data_reg_r2_0_63_18_20;
  wire n_0_fsm_mem_data_reg_r2_0_63_21_23;
  wire n_0_fsm_mem_data_reg_r2_0_63_3_5;
  wire n_0_fsm_mem_data_reg_r2_0_63_6_8;
  wire n_0_fsm_mem_data_reg_r2_0_63_9_11;
  wire n_0_fsm_mem_data_reg_r2_64_127_0_2;
  wire n_0_fsm_mem_data_reg_r2_64_127_12_14;
  wire n_0_fsm_mem_data_reg_r2_64_127_15_17;
  wire n_0_fsm_mem_data_reg_r2_64_127_18_20;
  wire n_0_fsm_mem_data_reg_r2_64_127_21_23;
  wire n_0_fsm_mem_data_reg_r2_64_127_3_5;
  wire n_0_fsm_mem_data_reg_r2_64_127_6_8;
  wire n_0_fsm_mem_data_reg_r2_64_127_9_11;
  wire n_1_fsm_mem_data_reg_r1_0_63_0_2;
  wire n_1_fsm_mem_data_reg_r1_0_63_12_14;
  wire n_1_fsm_mem_data_reg_r1_0_63_15_17;
  wire n_1_fsm_mem_data_reg_r1_0_63_18_20;
  wire n_1_fsm_mem_data_reg_r1_0_63_21_23;
  wire n_1_fsm_mem_data_reg_r1_0_63_3_5;
  wire n_1_fsm_mem_data_reg_r1_0_63_6_8;
  wire n_1_fsm_mem_data_reg_r1_0_63_9_11;
  wire n_1_fsm_mem_data_reg_r1_64_127_0_2;
  wire n_1_fsm_mem_data_reg_r1_64_127_12_14;
  wire n_1_fsm_mem_data_reg_r1_64_127_15_17;
  wire n_1_fsm_mem_data_reg_r1_64_127_18_20;
  wire n_1_fsm_mem_data_reg_r1_64_127_21_23;
  wire n_1_fsm_mem_data_reg_r1_64_127_3_5;
  wire n_1_fsm_mem_data_reg_r1_64_127_6_8;
  wire n_1_fsm_mem_data_reg_r1_64_127_9_11;
  wire n_1_fsm_mem_data_reg_r2_0_63_0_2;
  wire n_1_fsm_mem_data_reg_r2_0_63_12_14;
  wire n_1_fsm_mem_data_reg_r2_0_63_15_17;
  wire n_1_fsm_mem_data_reg_r2_0_63_18_20;
  wire n_1_fsm_mem_data_reg_r2_0_63_21_23;
  wire n_1_fsm_mem_data_reg_r2_0_63_3_5;
  wire n_1_fsm_mem_data_reg_r2_0_63_6_8;
  wire n_1_fsm_mem_data_reg_r2_0_63_9_11;
  wire n_1_fsm_mem_data_reg_r2_64_127_0_2;
  wire n_1_fsm_mem_data_reg_r2_64_127_12_14;
  wire n_1_fsm_mem_data_reg_r2_64_127_15_17;
  wire n_1_fsm_mem_data_reg_r2_64_127_18_20;
  wire n_1_fsm_mem_data_reg_r2_64_127_21_23;
  wire n_1_fsm_mem_data_reg_r2_64_127_3_5;
  wire n_1_fsm_mem_data_reg_r2_64_127_6_8;
  wire n_1_fsm_mem_data_reg_r2_64_127_9_11;
  wire n_2_fsm_mem_data_reg_r1_0_63_0_2;
  wire n_2_fsm_mem_data_reg_r1_0_63_12_14;
  wire n_2_fsm_mem_data_reg_r1_0_63_15_17;
  wire n_2_fsm_mem_data_reg_r1_0_63_18_20;
  wire n_2_fsm_mem_data_reg_r1_0_63_21_23;
  wire n_2_fsm_mem_data_reg_r1_0_63_3_5;
  wire n_2_fsm_mem_data_reg_r1_0_63_6_8;
  wire n_2_fsm_mem_data_reg_r1_0_63_9_11;
  wire n_2_fsm_mem_data_reg_r1_64_127_0_2;
  wire n_2_fsm_mem_data_reg_r1_64_127_12_14;
  wire n_2_fsm_mem_data_reg_r1_64_127_15_17;
  wire n_2_fsm_mem_data_reg_r1_64_127_18_20;
  wire n_2_fsm_mem_data_reg_r1_64_127_21_23;
  wire n_2_fsm_mem_data_reg_r1_64_127_3_5;
  wire n_2_fsm_mem_data_reg_r1_64_127_6_8;
  wire n_2_fsm_mem_data_reg_r1_64_127_9_11;
  wire n_2_fsm_mem_data_reg_r2_0_63_0_2;
  wire n_2_fsm_mem_data_reg_r2_0_63_12_14;
  wire n_2_fsm_mem_data_reg_r2_0_63_15_17;
  wire n_2_fsm_mem_data_reg_r2_0_63_18_20;
  wire n_2_fsm_mem_data_reg_r2_0_63_21_23;
  wire n_2_fsm_mem_data_reg_r2_0_63_3_5;
  wire n_2_fsm_mem_data_reg_r2_0_63_6_8;
  wire n_2_fsm_mem_data_reg_r2_0_63_9_11;
  wire n_2_fsm_mem_data_reg_r2_64_127_0_2;
  wire n_2_fsm_mem_data_reg_r2_64_127_12_14;
  wire n_2_fsm_mem_data_reg_r2_64_127_15_17;
  wire n_2_fsm_mem_data_reg_r2_64_127_18_20;
  wire n_2_fsm_mem_data_reg_r2_64_127_21_23;
  wire n_2_fsm_mem_data_reg_r2_64_127_3_5;
  wire n_2_fsm_mem_data_reg_r2_64_127_6_8;
  wire n_2_fsm_mem_data_reg_r2_64_127_9_11;
  wire p_0_in13_out;
  wire [6:0]p_0_in__1;
  wire [6:0]p_0_in__2;
  wire [0:0]p_2_out;
  wire toggle_rd;
  wire trig_out_fsm_temp;
  wire NLW_fsm_mem_data_reg_r1_0_63_0_2_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_12_14_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_15_17_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_18_20_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_21_23_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_3_5_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_6_8_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_0_63_9_11_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_0_2_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_12_14_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_15_17_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_18_20_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_21_23_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_3_5_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_6_8_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r1_64_127_9_11_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_0_2_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_12_14_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_15_17_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_18_20_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_21_23_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_3_5_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_6_8_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_0_63_9_11_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_0_2_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_12_14_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_15_17_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_18_20_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_21_23_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_3_5_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_6_8_DOD_UNCONNECTED;
  wire NLW_fsm_mem_data_reg_r2_64_127_9_11_DOD_UNCONNECTED;

LUT4 #(
    .INIT(16'hE200)) 
     CAPTURE_O_i_3
       (.I0(n_0_fsm_mem_data_reg_r1_0_63_18_20),
        .I1(addra[3]),
        .I2(n_0_fsm_mem_data_reg_r1_64_127_18_20),
        .I3(arm_status),
        .O(O1));
FDRE CAPTURE_O_reg
       (.C(clk),
        .CE(1'b1),
        .D(I1),
        .Q(capture_fsm_temp),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[0]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r2_64_127_0_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_0_fsm_mem_data_reg_r2_0_63_0_2),
        .O(\n_0_CFG_BRAM_RD_DATA[0]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair13" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[10]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r2_64_127_9_11),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_1_fsm_mem_data_reg_r2_0_63_9_11),
        .O(\n_0_CFG_BRAM_RD_DATA[10]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair12" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[11]_i_1 
       (.I0(n_2_fsm_mem_data_reg_r2_64_127_9_11),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_2_fsm_mem_data_reg_r2_0_63_9_11),
        .O(\n_0_CFG_BRAM_RD_DATA[11]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair11" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[12]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r2_64_127_12_14),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_0_fsm_mem_data_reg_r2_0_63_12_14),
        .O(\n_0_CFG_BRAM_RD_DATA[12]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[13]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r2_64_127_12_14),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_1_fsm_mem_data_reg_r2_0_63_12_14),
        .O(\n_0_CFG_BRAM_RD_DATA[13]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair9" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[14]_i_1 
       (.I0(n_2_fsm_mem_data_reg_r2_64_127_12_14),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_2_fsm_mem_data_reg_r2_0_63_12_14),
        .O(\n_0_CFG_BRAM_RD_DATA[14]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair10" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[15]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r2_64_127_15_17),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_0_fsm_mem_data_reg_r2_0_63_15_17),
        .O(\n_0_CFG_BRAM_RD_DATA[15]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair7" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[16]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r2_64_127_15_17),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_1_fsm_mem_data_reg_r2_0_63_15_17),
        .O(\n_0_CFG_BRAM_RD_DATA[16]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair14" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[17]_i_1 
       (.I0(n_2_fsm_mem_data_reg_r2_64_127_15_17),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_2_fsm_mem_data_reg_r2_0_63_15_17),
        .O(\n_0_CFG_BRAM_RD_DATA[17]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair8" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[18]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r2_64_127_18_20),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_0_fsm_mem_data_reg_r2_0_63_18_20),
        .O(\n_0_CFG_BRAM_RD_DATA[18]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair18" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[19]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r2_64_127_18_20),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_1_fsm_mem_data_reg_r2_0_63_18_20),
        .O(\n_0_CFG_BRAM_RD_DATA[19]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair5" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[1]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r2_64_127_0_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_1_fsm_mem_data_reg_r2_0_63_0_2),
        .O(\n_0_CFG_BRAM_RD_DATA[1]_i_1 ));
LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[20]_i_1 
       (.I0(n_2_fsm_mem_data_reg_r2_64_127_18_20),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_2_fsm_mem_data_reg_r2_0_63_18_20),
        .O(\n_0_CFG_BRAM_RD_DATA[20]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair4" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[21]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r2_64_127_21_23),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_0_fsm_mem_data_reg_r2_0_63_21_23),
        .O(\n_0_CFG_BRAM_RD_DATA[21]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair5" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[22]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r2_64_127_21_23),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_1_fsm_mem_data_reg_r2_0_63_21_23),
        .O(\n_0_CFG_BRAM_RD_DATA[22]_i_1 ));
LUT2 #(
    .INIT(4'h2)) 
     \CFG_BRAM_RD_DATA[23]_i_1 
       (.I0(bram_rd_en_0),
        .I1(bram_rd_we),
        .O(CFG_BRAM_RD_DATA0));
(* SOFT_HLUTNM = "soft_lutpair6" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[23]_i_2 
       (.I0(n_2_fsm_mem_data_reg_r2_64_127_21_23),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_2_fsm_mem_data_reg_r2_0_63_21_23),
        .O(\n_0_CFG_BRAM_RD_DATA[23]_i_2 ));
(* SOFT_HLUTNM = "soft_lutpair6" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[2]_i_1 
       (.I0(n_2_fsm_mem_data_reg_r2_64_127_0_2),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_2_fsm_mem_data_reg_r2_0_63_0_2),
        .O(\n_0_CFG_BRAM_RD_DATA[2]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair7" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[3]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r2_64_127_3_5),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_0_fsm_mem_data_reg_r2_0_63_3_5),
        .O(\n_0_CFG_BRAM_RD_DATA[3]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair8" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[4]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r2_64_127_3_5),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_1_fsm_mem_data_reg_r2_0_63_3_5),
        .O(\n_0_CFG_BRAM_RD_DATA[4]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair9" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[5]_i_1 
       (.I0(n_2_fsm_mem_data_reg_r2_64_127_3_5),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_2_fsm_mem_data_reg_r2_0_63_3_5),
        .O(\n_0_CFG_BRAM_RD_DATA[5]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair10" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[6]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r2_64_127_6_8),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_0_fsm_mem_data_reg_r2_0_63_6_8),
        .O(\n_0_CFG_BRAM_RD_DATA[6]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair11" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[7]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r2_64_127_6_8),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_1_fsm_mem_data_reg_r2_0_63_6_8),
        .O(\n_0_CFG_BRAM_RD_DATA[7]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair12" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[8]_i_1 
       (.I0(n_2_fsm_mem_data_reg_r2_64_127_6_8),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_2_fsm_mem_data_reg_r2_0_63_6_8),
        .O(\n_0_CFG_BRAM_RD_DATA[8]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair13" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \CFG_BRAM_RD_DATA[9]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r2_64_127_9_11),
        .I1(bram_rd_addr_reg[6]),
        .I2(n_0_fsm_mem_data_reg_r2_0_63_9_11),
        .O(\n_0_CFG_BRAM_RD_DATA[9]_i_1 ));
FDRE \CFG_BRAM_RD_DATA_reg[0] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[0]_i_1 ),
        .Q(O3[0]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[10] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[10]_i_1 ),
        .Q(O3[10]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[11] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[11]_i_1 ),
        .Q(O3[11]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[12] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[12]_i_1 ),
        .Q(O3[12]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[13] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[13]_i_1 ),
        .Q(O3[13]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[14] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[14]_i_1 ),
        .Q(O3[14]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[15] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[15]_i_1 ),
        .Q(O3[15]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[16] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[16]_i_1 ),
        .Q(O3[16]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[17] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[17]_i_1 ),
        .Q(O3[17]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[18] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[18]_i_1 ),
        .Q(O3[18]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[19] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[19]_i_1 ),
        .Q(O3[19]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[1] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[1]_i_1 ),
        .Q(O3[1]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[20] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[20]_i_1 ),
        .Q(O3[20]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[21] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[21]_i_1 ),
        .Q(O3[21]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[22] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[22]_i_1 ),
        .Q(O3[22]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[23] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[23]_i_2 ),
        .Q(O3[23]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[2] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[2]_i_1 ),
        .Q(O3[2]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[3] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[3]_i_1 ),
        .Q(O3[3]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[4] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[4]_i_1 ),
        .Q(O3[4]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[5] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[5]_i_1 ),
        .Q(O3[5]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[6] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[6]_i_1 ),
        .Q(O3[6]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[7] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[7]_i_1 ),
        .Q(O3[7]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[8] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[8]_i_1 ),
        .Q(O3[8]),
        .R(1'b0));
FDRE \CFG_BRAM_RD_DATA_reg[9] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(\n_0_CFG_BRAM_RD_DATA[9]_i_1 ),
        .Q(O3[9]),
        .R(1'b0));
LUT6 #(
    .INIT(64'hF4FFF44444444444)) 
     FLAG0_O_i_1
       (.I0(n_0_FLAG0_O_i_2),
        .I1(FLAG0_I),
        .I2(n_2_fsm_mem_data_reg_r1_64_127_12_14),
        .I3(addra[3]),
        .I4(n_2_fsm_mem_data_reg_r1_0_63_12_14),
        .I5(I3),
        .O(n_0_FLAG0_O_i_1));
LUT6 #(
    .INIT(64'hB800FFFFB800B800)) 
     FLAG0_O_i_2
       (.I0(n_2_fsm_mem_data_reg_r1_64_127_18_20),
        .I1(addra[3]),
        .I2(n_2_fsm_mem_data_reg_r1_0_63_18_20),
        .I3(I3),
        .I4(Q[0]),
        .I5(Q[1]),
        .O(n_0_FLAG0_O_i_2));
FDRE FLAG0_O_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_FLAG0_O_i_1),
        .Q(FLAG0_I),
        .R(1'b0));
LUT6 #(
    .INIT(64'hF4FFF44444444444)) 
     FLAG1_O_i_1
       (.I0(n_0_FLAG1_O_i_2),
        .I1(FLAG1_I),
        .I2(n_0_fsm_mem_data_reg_r1_64_127_15_17),
        .I3(addra[3]),
        .I4(n_0_fsm_mem_data_reg_r1_0_63_15_17),
        .I5(I3),
        .O(n_0_FLAG1_O_i_1));
LUT6 #(
    .INIT(64'hB800FFFFB800B800)) 
     FLAG1_O_i_2
       (.I0(n_0_fsm_mem_data_reg_r1_64_127_21_23),
        .I1(addra[3]),
        .I2(n_0_fsm_mem_data_reg_r1_0_63_21_23),
        .I3(I3),
        .I4(Q[0]),
        .I5(Q[1]),
        .O(n_0_FLAG1_O_i_2));
FDRE FLAG1_O_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_FLAG1_O_i_1),
        .Q(FLAG1_I),
        .R(1'b0));
LUT6 #(
    .INIT(64'hF4FFF44444444444)) 
     FLAG2_O_i_1
       (.I0(n_0_FLAG2_O_i_2),
        .I1(FLAG2_I),
        .I2(n_1_fsm_mem_data_reg_r1_64_127_15_17),
        .I3(addra[3]),
        .I4(n_1_fsm_mem_data_reg_r1_0_63_15_17),
        .I5(I3),
        .O(n_0_FLAG2_O_i_1));
LUT6 #(
    .INIT(64'hB800FFFFB800B800)) 
     FLAG2_O_i_2
       (.I0(n_1_fsm_mem_data_reg_r1_64_127_21_23),
        .I1(addra[3]),
        .I2(n_1_fsm_mem_data_reg_r1_0_63_21_23),
        .I3(I3),
        .I4(Q[0]),
        .I5(Q[1]),
        .O(n_0_FLAG2_O_i_2));
FDRE FLAG2_O_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_FLAG2_O_i_1),
        .Q(FLAG2_I),
        .R(1'b0));
LUT6 #(
    .INIT(64'hF4FFF44444444444)) 
     FLAG3_O_i_1
       (.I0(n_0_FLAG3_O_i_2),
        .I1(FLAG3_I),
        .I2(n_2_fsm_mem_data_reg_r1_64_127_15_17),
        .I3(addra[3]),
        .I4(n_2_fsm_mem_data_reg_r1_0_63_15_17),
        .I5(I3),
        .O(n_0_FLAG3_O_i_1));
LUT6 #(
    .INIT(64'hB800FFFFB800B800)) 
     FLAG3_O_i_2
       (.I0(n_2_fsm_mem_data_reg_r1_64_127_21_23),
        .I1(addra[3]),
        .I2(n_2_fsm_mem_data_reg_r1_0_63_21_23),
        .I3(I3),
        .I4(Q[0]),
        .I5(Q[1]),
        .O(n_0_FLAG3_O_i_2));
FDRE FLAG3_O_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_FLAG3_O_i_1),
        .Q(FLAG3_I),
        .R(1'b0));
LUT4 #(
    .INIT(16'hA808)) 
     \G_COUNTER[0].U_COUNTER_i_2 
       (.I0(I3),
        .I1(n_2_fsm_mem_data_reg_r1_0_63_3_5),
        .I2(addra[3]),
        .I3(n_2_fsm_mem_data_reg_r1_64_127_3_5),
        .O(CNT_CTRL[1]));
LUT4 #(
    .INIT(16'hA808)) 
     \G_COUNTER[0].U_COUNTER_i_3 
       (.I0(I3),
        .I1(n_1_fsm_mem_data_reg_r1_0_63_3_5),
        .I2(addra[3]),
        .I3(n_1_fsm_mem_data_reg_r1_64_127_3_5),
        .O(CNT_CTRL[0]));
LUT4 #(
    .INIT(16'hA808)) 
     \G_COUNTER[1].U_COUNTER_i_1 
       (.I0(I3),
        .I1(n_1_fsm_mem_data_reg_r1_0_63_6_8),
        .I2(addra[3]),
        .I3(n_1_fsm_mem_data_reg_r1_64_127_6_8),
        .O(CNT_CTRL[3]));
LUT4 #(
    .INIT(16'hA808)) 
     \G_COUNTER[1].U_COUNTER_i_2 
       (.I0(I3),
        .I1(n_0_fsm_mem_data_reg_r1_0_63_6_8),
        .I2(addra[3]),
        .I3(n_0_fsm_mem_data_reg_r1_64_127_6_8),
        .O(CNT_CTRL[2]));
LUT4 #(
    .INIT(16'hA808)) 
     \G_COUNTER[2].U_COUNTER_i_1 
       (.I0(I3),
        .I1(n_0_fsm_mem_data_reg_r1_0_63_9_11),
        .I2(addra[3]),
        .I3(n_0_fsm_mem_data_reg_r1_64_127_9_11),
        .O(CNT_CTRL[5]));
LUT4 #(
    .INIT(16'hA808)) 
     \G_COUNTER[2].U_COUNTER_i_2 
       (.I0(I3),
        .I1(n_2_fsm_mem_data_reg_r1_0_63_6_8),
        .I2(addra[3]),
        .I3(n_2_fsm_mem_data_reg_r1_64_127_6_8),
        .O(CNT_CTRL[4]));
LUT4 #(
    .INIT(16'hA808)) 
     \G_COUNTER[3].U_COUNTER_i_1 
       (.I0(I3),
        .I1(n_2_fsm_mem_data_reg_r1_0_63_9_11),
        .I2(addra[3]),
        .I3(n_2_fsm_mem_data_reg_r1_64_127_9_11),
        .O(CNT_CTRL[7]));
LUT4 #(
    .INIT(16'hA808)) 
     \G_COUNTER[3].U_COUNTER_i_2 
       (.I0(I3),
        .I1(n_1_fsm_mem_data_reg_r1_0_63_9_11),
        .I2(addra[3]),
        .I3(n_1_fsm_mem_data_reg_r1_64_127_9_11),
        .O(CNT_CTRL[6]));
LUT6 #(
    .INIT(64'h0001FFFF00010000)) 
     \SEQUENCER_STATE_O[0]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[0]),
        .O(\n_0_SEQUENCER_STATE_O[0]_i_1 ));
LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
     \SEQUENCER_STATE_O[10]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[3]),
        .I3(addra[2]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[10]),
        .O(\n_0_SEQUENCER_STATE_O[10]_i_1 ));
LUT6 #(
    .INIT(64'h0080FFFF00800000)) 
     \SEQUENCER_STATE_O[11]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[3]),
        .I3(addra[2]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[11]),
        .O(\n_0_SEQUENCER_STATE_O[11]_i_1 ));
LUT6 #(
    .INIT(64'h1000FFFF10000000)) 
     \SEQUENCER_STATE_O[12]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[12]),
        .O(\n_0_SEQUENCER_STATE_O[12]_i_1 ));
LUT6 #(
    .INIT(64'h4000FFFF40000000)) 
     \SEQUENCER_STATE_O[13]_i_1 
       (.I0(addra[1]),
        .I1(addra[0]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[13]),
        .O(\n_0_SEQUENCER_STATE_O[13]_i_1 ));
LUT6 #(
    .INIT(64'h4000FFFF40000000)) 
     \SEQUENCER_STATE_O[14]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[14]),
        .O(\n_0_SEQUENCER_STATE_O[14]_i_1 ));
LUT6 #(
    .INIT(64'h8000FFFF80000000)) 
     \SEQUENCER_STATE_O[15]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[15]),
        .O(\n_0_SEQUENCER_STATE_O[15]_i_1 ));
LUT6 #(
    .INIT(64'h0004FFFF00040000)) 
     \SEQUENCER_STATE_O[1]_i_1 
       (.I0(addra[1]),
        .I1(addra[0]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[1]),
        .O(\n_0_SEQUENCER_STATE_O[1]_i_1 ));
LUT6 #(
    .INIT(64'h0004FFFF00040000)) 
     \SEQUENCER_STATE_O[2]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[2]),
        .O(\n_0_SEQUENCER_STATE_O[2]_i_1 ));
LUT6 #(
    .INIT(64'h0008FFFF00080000)) 
     \SEQUENCER_STATE_O[3]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[3]),
        .O(\n_0_SEQUENCER_STATE_O[3]_i_1 ));
LUT6 #(
    .INIT(64'h0010FFFF00100000)) 
     \SEQUENCER_STATE_O[4]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[4]),
        .O(\n_0_SEQUENCER_STATE_O[4]_i_1 ));
LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
     \SEQUENCER_STATE_O[5]_i_1 
       (.I0(addra[1]),
        .I1(addra[0]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[5]),
        .O(\n_0_SEQUENCER_STATE_O[5]_i_1 ));
LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
     \SEQUENCER_STATE_O[6]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[6]),
        .O(\n_0_SEQUENCER_STATE_O[6]_i_1 ));
LUT6 #(
    .INIT(64'h0080FFFF00800000)) 
     \SEQUENCER_STATE_O[7]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[2]),
        .I3(addra[3]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[7]),
        .O(\n_0_SEQUENCER_STATE_O[7]_i_1 ));
LUT6 #(
    .INIT(64'h0010FFFF00100000)) 
     \SEQUENCER_STATE_O[8]_i_1 
       (.I0(addra[0]),
        .I1(addra[1]),
        .I2(addra[3]),
        .I3(addra[2]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[8]),
        .O(\n_0_SEQUENCER_STATE_O[8]_i_1 ));
LUT6 #(
    .INIT(64'h0040FFFF00400000)) 
     \SEQUENCER_STATE_O[9]_i_1 
       (.I0(addra[1]),
        .I1(addra[0]),
        .I2(addra[3]),
        .I3(addra[2]),
        .I4(p_2_out),
        .I5(SEQUENCER_STATE_I[9]),
        .O(\n_0_SEQUENCER_STATE_O[9]_i_1 ));
FDRE \SEQUENCER_STATE_O_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[0]_i_1 ),
        .Q(SEQUENCER_STATE_I[0]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[10]_i_1 ),
        .Q(SEQUENCER_STATE_I[10]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[11]_i_1 ),
        .Q(SEQUENCER_STATE_I[11]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[12]_i_1 ),
        .Q(SEQUENCER_STATE_I[12]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[13]_i_1 ),
        .Q(SEQUENCER_STATE_I[13]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[14]_i_1 ),
        .Q(SEQUENCER_STATE_I[14]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[15]_i_1 ),
        .Q(SEQUENCER_STATE_I[15]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[1]_i_1 ),
        .Q(SEQUENCER_STATE_I[1]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[2]_i_1 ),
        .Q(SEQUENCER_STATE_I[2]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[3]_i_1 ),
        .Q(SEQUENCER_STATE_I[3]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[4]_i_1 ),
        .Q(SEQUENCER_STATE_I[4]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[5]_i_1 ),
        .Q(SEQUENCER_STATE_I[5]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[6]_i_1 ),
        .Q(SEQUENCER_STATE_I[6]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[7]_i_1 ),
        .Q(SEQUENCER_STATE_I[7]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[8]_i_1 ),
        .Q(SEQUENCER_STATE_I[8]),
        .R(1'b0));
FDRE \SEQUENCER_STATE_O_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_SEQUENCER_STATE_O[9]_i_1 ),
        .Q(SEQUENCER_STATE_I[9]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair20" *) 
   LUT1 #(
    .INIT(2'h1)) 
     \bram_addr[0]_i_1 
       (.I0(bram_addr_reg[0]),
        .O(p_0_in__2[0]));
(* SOFT_HLUTNM = "soft_lutpair20" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \bram_addr[1]_i_1 
       (.I0(bram_addr_reg[0]),
        .I1(bram_addr_reg[1]),
        .O(p_0_in__2[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \bram_addr[2]_i_1 
       (.I0(bram_addr_reg[0]),
        .I1(bram_addr_reg[1]),
        .I2(bram_addr_reg[2]),
        .O(p_0_in__2[2]));
(* SOFT_HLUTNM = "soft_lutpair3" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \bram_addr[3]_i_1 
       (.I0(bram_addr_reg[1]),
        .I1(bram_addr_reg[0]),
        .I2(bram_addr_reg[2]),
        .I3(bram_addr_reg[3]),
        .O(p_0_in__2[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *) 
   LUT5 #(
    .INIT(32'h7FFF8000)) 
     \bram_addr[4]_i_1 
       (.I0(bram_addr_reg[2]),
        .I1(bram_addr_reg[0]),
        .I2(bram_addr_reg[1]),
        .I3(bram_addr_reg[3]),
        .I4(bram_addr_reg[4]),
        .O(p_0_in__2[4]));
LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
     \bram_addr[5]_i_1 
       (.I0(bram_addr_reg[3]),
        .I1(bram_addr_reg[1]),
        .I2(bram_addr_reg[0]),
        .I3(bram_addr_reg[2]),
        .I4(bram_addr_reg[4]),
        .I5(bram_addr_reg[5]),
        .O(p_0_in__2[5]));
LUT2 #(
    .INIT(4'h8)) 
     \bram_addr[6]_i_1 
       (.I0(bram_en_1),
        .I1(bram_we),
        .O(p_0_in13_out));
LUT3 #(
    .INIT(8'h78)) 
     \bram_addr[6]_i_2 
       (.I0(\n_0_bram_addr[6]_i_3 ),
        .I1(bram_addr_reg[5]),
        .I2(bram_addr_reg[6]),
        .O(p_0_in__2[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *) 
   LUT5 #(
    .INIT(32'h80000000)) 
     \bram_addr[6]_i_3 
       (.I0(bram_addr_reg[4]),
        .I1(bram_addr_reg[2]),
        .I2(bram_addr_reg[0]),
        .I3(bram_addr_reg[1]),
        .I4(bram_addr_reg[3]),
        .O(\n_0_bram_addr[6]_i_3 ));
FDRE #(
    .INIT(1'b0)) 
     \bram_addr_reg[0] 
       (.C(S_DCLK_O),
        .CE(p_0_in13_out),
        .D(p_0_in__2[0]),
        .Q(bram_addr_reg[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_addr_reg[1] 
       (.C(S_DCLK_O),
        .CE(p_0_in13_out),
        .D(p_0_in__2[1]),
        .Q(bram_addr_reg[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_addr_reg[2] 
       (.C(S_DCLK_O),
        .CE(p_0_in13_out),
        .D(p_0_in__2[2]),
        .Q(bram_addr_reg[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_addr_reg[3] 
       (.C(S_DCLK_O),
        .CE(p_0_in13_out),
        .D(p_0_in__2[3]),
        .Q(bram_addr_reg[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_addr_reg[4] 
       (.C(S_DCLK_O),
        .CE(p_0_in13_out),
        .D(p_0_in__2[4]),
        .Q(bram_addr_reg[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_addr_reg[5] 
       (.C(S_DCLK_O),
        .CE(p_0_in13_out),
        .D(p_0_in__2[5]),
        .Q(bram_addr_reg[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_addr_reg[6] 
       (.C(S_DCLK_O),
        .CE(p_0_in13_out),
        .D(p_0_in__2[6]),
        .Q(bram_addr_reg[6]),
        .R(1'b0));
FDRE bram_en_reg
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(bram_en),
        .Q(bram_en_1),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair19" *) 
   LUT1 #(
    .INIT(2'h1)) 
     \bram_rd_addr[0]_i_1 
       (.I0(bram_rd_addr_reg[0]),
        .O(p_0_in__1[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \bram_rd_addr[1]_i_1 
       (.I0(bram_rd_addr_reg[0]),
        .I1(bram_rd_addr_reg[1]),
        .O(p_0_in__1[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \bram_rd_addr[2]_i_1 
       (.I0(bram_rd_addr_reg[0]),
        .I1(bram_rd_addr_reg[1]),
        .I2(bram_rd_addr_reg[2]),
        .O(p_0_in__1[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \bram_rd_addr[3]_i_1 
       (.I0(bram_rd_addr_reg[1]),
        .I1(bram_rd_addr_reg[0]),
        .I2(bram_rd_addr_reg[2]),
        .I3(bram_rd_addr_reg[3]),
        .O(p_0_in__1[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *) 
   LUT5 #(
    .INIT(32'h7FFF8000)) 
     \bram_rd_addr[4]_i_1 
       (.I0(bram_rd_addr_reg[2]),
        .I1(bram_rd_addr_reg[0]),
        .I2(bram_rd_addr_reg[1]),
        .I3(bram_rd_addr_reg[3]),
        .I4(bram_rd_addr_reg[4]),
        .O(p_0_in__1[4]));
LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
     \bram_rd_addr[5]_i_1 
       (.I0(bram_rd_addr_reg[3]),
        .I1(bram_rd_addr_reg[1]),
        .I2(bram_rd_addr_reg[0]),
        .I3(bram_rd_addr_reg[2]),
        .I4(bram_rd_addr_reg[4]),
        .I5(bram_rd_addr_reg[5]),
        .O(p_0_in__1[5]));
(* SOFT_HLUTNM = "soft_lutpair18" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \bram_rd_addr[6]_i_1 
       (.I0(\n_0_bram_rd_addr[6]_i_2 ),
        .I1(bram_rd_addr_reg[5]),
        .I2(bram_rd_addr_reg[6]),
        .O(p_0_in__1[6]));
(* SOFT_HLUTNM = "soft_lutpair0" *) 
   LUT5 #(
    .INIT(32'h80000000)) 
     \bram_rd_addr[6]_i_2 
       (.I0(bram_rd_addr_reg[4]),
        .I1(bram_rd_addr_reg[2]),
        .I2(bram_rd_addr_reg[0]),
        .I3(bram_rd_addr_reg[1]),
        .I4(bram_rd_addr_reg[3]),
        .O(\n_0_bram_rd_addr[6]_i_2 ));
FDRE #(
    .INIT(1'b0)) 
     \bram_rd_addr_reg[0] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(p_0_in__1[0]),
        .Q(bram_rd_addr_reg[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_rd_addr_reg[1] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(p_0_in__1[1]),
        .Q(bram_rd_addr_reg[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_rd_addr_reg[2] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(p_0_in__1[2]),
        .Q(bram_rd_addr_reg[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_rd_addr_reg[3] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(p_0_in__1[3]),
        .Q(bram_rd_addr_reg[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_rd_addr_reg[4] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(p_0_in__1[4]),
        .Q(bram_rd_addr_reg[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_rd_addr_reg[5] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(p_0_in__1[5]),
        .Q(bram_rd_addr_reg[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \bram_rd_addr_reg[6] 
       (.C(S_DCLK_O),
        .CE(CFG_BRAM_RD_DATA0),
        .D(p_0_in__1[6]),
        .Q(bram_rd_addr_reg[6]),
        .R(1'b0));
FDRE bram_rd_en_reg
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(bram_rd_en),
        .Q(bram_rd_en_0),
        .R(1'b0));
FDRE bram_rd_we_reg
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(toggle_rd),
        .Q(bram_rd_we),
        .R(1'b0));
FDRE bram_we_reg
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(E),
        .Q(bram_we),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \cntcmpsel[0]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r1_64_127_12_14),
        .I1(addra[3]),
        .I2(n_0_fsm_mem_data_reg_r1_0_63_12_14),
        .O(douta0[12]));
(* SOFT_HLUTNM = "soft_lutpair15" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \cntcmpsel[1]_i_3 
       (.I0(n_1_fsm_mem_data_reg_r1_64_127_12_14),
        .I1(addra[3]),
        .I2(n_1_fsm_mem_data_reg_r1_0_63_12_14),
        .O(douta0[13]));
FDRE \cntcmpsel_reg[0] 
       (.C(clk),
        .CE(p_2_out),
        .D(douta0[12]),
        .Q(cntcmpsel[0]),
        .R(I4));
FDRE \cntcmpsel_reg[1] 
       (.C(clk),
        .CE(p_2_out),
        .D(douta0[13]),
        .Q(cntcmpsel[1]),
        .R(I4));
(* SOFT_HLUTNM = "soft_lutpair15" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \current_state[0]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r1_64_127_0_2),
        .I1(addra[3]),
        .I2(n_0_fsm_mem_data_reg_r1_0_63_0_2),
        .O(douta0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \current_state[1]_i_1 
       (.I0(n_1_fsm_mem_data_reg_r1_64_127_0_2),
        .I1(addra[3]),
        .I2(n_1_fsm_mem_data_reg_r1_0_63_0_2),
        .O(douta0[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \current_state[2]_i_1 
       (.I0(n_2_fsm_mem_data_reg_r1_64_127_0_2),
        .I1(addra[3]),
        .I2(n_2_fsm_mem_data_reg_r1_0_63_0_2),
        .O(douta0[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \current_state[3]_i_1 
       (.I0(n_0_fsm_mem_data_reg_r1_64_127_3_5),
        .I1(addra[3]),
        .I2(n_0_fsm_mem_data_reg_r1_0_63_3_5),
        .O(douta0[3]));
FDRE \current_state_reg[0] 
       (.C(clk),
        .CE(p_2_out),
        .D(douta0[0]),
        .Q(addra[0]),
        .R(I4));
FDRE \current_state_reg[1] 
       (.C(clk),
        .CE(p_2_out),
        .D(douta0[1]),
        .Q(addra[1]),
        .R(I4));
FDRE \current_state_reg[2] 
       (.C(clk),
        .CE(p_2_out),
        .D(douta0[2]),
        .Q(addra[2]),
        .R(I4));
FDRE \current_state_reg[3] 
       (.C(clk),
        .CE(p_2_out),
        .D(douta0[3]),
        .Q(addra[3]),
        .R(I4));
RAM64M fsm_mem_data_reg_r1_0_63_0_2
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[0]),
        .DIB(CFG_BRAM_DATA[1]),
        .DIC(CFG_BRAM_DATA[2]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_0_63_0_2),
        .DOB(n_1_fsm_mem_data_reg_r1_0_63_0_2),
        .DOC(n_2_fsm_mem_data_reg_r1_0_63_0_2),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_0_2_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
LUT3 #(
    .INIT(8'h08)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_1
       (.I0(bram_we),
        .I1(bram_en_1),
        .I2(bram_addr_reg[6]),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_0_63_12_14
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[12]),
        .DIB(CFG_BRAM_DATA[13]),
        .DIC(CFG_BRAM_DATA[14]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_0_63_12_14),
        .DOB(n_1_fsm_mem_data_reg_r1_0_63_12_14),
        .DOC(n_2_fsm_mem_data_reg_r1_0_63_12_14),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_12_14_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_0_63_15_17
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[15]),
        .DIB(CFG_BRAM_DATA[16]),
        .DIC(CFG_BRAM_DATA[17]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_0_63_15_17),
        .DOB(n_1_fsm_mem_data_reg_r1_0_63_15_17),
        .DOC(n_2_fsm_mem_data_reg_r1_0_63_15_17),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_15_17_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_0_63_18_20
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[18]),
        .DIB(CFG_BRAM_DATA[19]),
        .DIC(CFG_BRAM_DATA[20]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_0_63_18_20),
        .DOB(n_1_fsm_mem_data_reg_r1_0_63_18_20),
        .DOC(n_2_fsm_mem_data_reg_r1_0_63_18_20),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_18_20_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_0_63_21_23
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[21]),
        .DIB(CFG_BRAM_DATA[22]),
        .DIC(CFG_BRAM_DATA[23]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_0_63_21_23),
        .DOB(n_1_fsm_mem_data_reg_r1_0_63_21_23),
        .DOC(n_2_fsm_mem_data_reg_r1_0_63_21_23),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_21_23_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_0_63_3_5
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[3]),
        .DIB(CFG_BRAM_DATA[4]),
        .DIC(CFG_BRAM_DATA[5]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_0_63_3_5),
        .DOB(n_1_fsm_mem_data_reg_r1_0_63_3_5),
        .DOC(n_2_fsm_mem_data_reg_r1_0_63_3_5),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_3_5_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_0_63_6_8
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[6]),
        .DIB(CFG_BRAM_DATA[7]),
        .DIC(CFG_BRAM_DATA[8]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_0_63_6_8),
        .DOB(n_1_fsm_mem_data_reg_r1_0_63_6_8),
        .DOC(n_2_fsm_mem_data_reg_r1_0_63_6_8),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_6_8_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_0_63_9_11
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[9]),
        .DIB(CFG_BRAM_DATA[10]),
        .DIC(CFG_BRAM_DATA[11]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_0_63_9_11),
        .DOB(n_1_fsm_mem_data_reg_r1_0_63_9_11),
        .DOC(n_2_fsm_mem_data_reg_r1_0_63_9_11),
        .DOD(NLW_fsm_mem_data_reg_r1_0_63_9_11_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_64_127_0_2
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[0]),
        .DIB(CFG_BRAM_DATA[1]),
        .DIC(CFG_BRAM_DATA[2]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_64_127_0_2),
        .DOB(n_1_fsm_mem_data_reg_r1_64_127_0_2),
        .DOC(n_2_fsm_mem_data_reg_r1_64_127_0_2),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_0_2_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
LUT3 #(
    .INIT(8'h80)) 
     fsm_mem_data_reg_r1_64_127_0_2_i_1
       (.I0(bram_we),
        .I1(bram_en_1),
        .I2(bram_addr_reg[6]),
        .O(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_64_127_12_14
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[12]),
        .DIB(CFG_BRAM_DATA[13]),
        .DIC(CFG_BRAM_DATA[14]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_64_127_12_14),
        .DOB(n_1_fsm_mem_data_reg_r1_64_127_12_14),
        .DOC(n_2_fsm_mem_data_reg_r1_64_127_12_14),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_12_14_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_64_127_15_17
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[15]),
        .DIB(CFG_BRAM_DATA[16]),
        .DIC(CFG_BRAM_DATA[17]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_64_127_15_17),
        .DOB(n_1_fsm_mem_data_reg_r1_64_127_15_17),
        .DOC(n_2_fsm_mem_data_reg_r1_64_127_15_17),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_15_17_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_64_127_18_20
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[18]),
        .DIB(CFG_BRAM_DATA[19]),
        .DIC(CFG_BRAM_DATA[20]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_64_127_18_20),
        .DOB(n_1_fsm_mem_data_reg_r1_64_127_18_20),
        .DOC(n_2_fsm_mem_data_reg_r1_64_127_18_20),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_18_20_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_64_127_21_23
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[21]),
        .DIB(CFG_BRAM_DATA[22]),
        .DIC(CFG_BRAM_DATA[23]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_64_127_21_23),
        .DOB(n_1_fsm_mem_data_reg_r1_64_127_21_23),
        .DOC(n_2_fsm_mem_data_reg_r1_64_127_21_23),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_21_23_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_64_127_3_5
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[3]),
        .DIB(CFG_BRAM_DATA[4]),
        .DIC(CFG_BRAM_DATA[5]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_64_127_3_5),
        .DOB(n_1_fsm_mem_data_reg_r1_64_127_3_5),
        .DOC(n_2_fsm_mem_data_reg_r1_64_127_3_5),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_3_5_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_64_127_6_8
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[6]),
        .DIB(CFG_BRAM_DATA[7]),
        .DIC(CFG_BRAM_DATA[8]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_64_127_6_8),
        .DOB(n_1_fsm_mem_data_reg_r1_64_127_6_8),
        .DOC(n_2_fsm_mem_data_reg_r1_64_127_6_8),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_6_8_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r1_64_127_9_11
       (.ADDRA({addra[2:0],ADDRA}),
        .ADDRB({addra[2:0],ADDRA}),
        .ADDRC({addra[2:0],ADDRA}),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[9]),
        .DIB(CFG_BRAM_DATA[10]),
        .DIC(CFG_BRAM_DATA[11]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r1_64_127_9_11),
        .DOB(n_1_fsm_mem_data_reg_r1_64_127_9_11),
        .DOC(n_2_fsm_mem_data_reg_r1_64_127_9_11),
        .DOD(NLW_fsm_mem_data_reg_r1_64_127_9_11_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_0_63_0_2
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[0]),
        .DIB(CFG_BRAM_DATA[1]),
        .DIC(CFG_BRAM_DATA[2]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_0_63_0_2),
        .DOB(n_1_fsm_mem_data_reg_r2_0_63_0_2),
        .DOC(n_2_fsm_mem_data_reg_r2_0_63_0_2),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_0_2_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_0_63_12_14
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[12]),
        .DIB(CFG_BRAM_DATA[13]),
        .DIC(CFG_BRAM_DATA[14]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_0_63_12_14),
        .DOB(n_1_fsm_mem_data_reg_r2_0_63_12_14),
        .DOC(n_2_fsm_mem_data_reg_r2_0_63_12_14),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_12_14_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_0_63_15_17
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[15]),
        .DIB(CFG_BRAM_DATA[16]),
        .DIC(CFG_BRAM_DATA[17]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_0_63_15_17),
        .DOB(n_1_fsm_mem_data_reg_r2_0_63_15_17),
        .DOC(n_2_fsm_mem_data_reg_r2_0_63_15_17),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_15_17_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_0_63_18_20
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[18]),
        .DIB(CFG_BRAM_DATA[19]),
        .DIC(CFG_BRAM_DATA[20]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_0_63_18_20),
        .DOB(n_1_fsm_mem_data_reg_r2_0_63_18_20),
        .DOC(n_2_fsm_mem_data_reg_r2_0_63_18_20),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_18_20_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_0_63_21_23
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[21]),
        .DIB(CFG_BRAM_DATA[22]),
        .DIC(CFG_BRAM_DATA[23]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_0_63_21_23),
        .DOB(n_1_fsm_mem_data_reg_r2_0_63_21_23),
        .DOC(n_2_fsm_mem_data_reg_r2_0_63_21_23),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_21_23_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_0_63_3_5
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[3]),
        .DIB(CFG_BRAM_DATA[4]),
        .DIC(CFG_BRAM_DATA[5]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_0_63_3_5),
        .DOB(n_1_fsm_mem_data_reg_r2_0_63_3_5),
        .DOC(n_2_fsm_mem_data_reg_r2_0_63_3_5),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_3_5_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_0_63_6_8
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[6]),
        .DIB(CFG_BRAM_DATA[7]),
        .DIC(CFG_BRAM_DATA[8]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_0_63_6_8),
        .DOB(n_1_fsm_mem_data_reg_r2_0_63_6_8),
        .DOC(n_2_fsm_mem_data_reg_r2_0_63_6_8),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_6_8_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_0_63_9_11
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[9]),
        .DIB(CFG_BRAM_DATA[10]),
        .DIC(CFG_BRAM_DATA[11]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_0_63_9_11),
        .DOB(n_1_fsm_mem_data_reg_r2_0_63_9_11),
        .DOC(n_2_fsm_mem_data_reg_r2_0_63_9_11),
        .DOD(NLW_fsm_mem_data_reg_r2_0_63_9_11_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_64_127_0_2
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[0]),
        .DIB(CFG_BRAM_DATA[1]),
        .DIC(CFG_BRAM_DATA[2]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_64_127_0_2),
        .DOB(n_1_fsm_mem_data_reg_r2_64_127_0_2),
        .DOC(n_2_fsm_mem_data_reg_r2_64_127_0_2),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_0_2_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_64_127_12_14
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[12]),
        .DIB(CFG_BRAM_DATA[13]),
        .DIC(CFG_BRAM_DATA[14]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_64_127_12_14),
        .DOB(n_1_fsm_mem_data_reg_r2_64_127_12_14),
        .DOC(n_2_fsm_mem_data_reg_r2_64_127_12_14),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_12_14_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_64_127_15_17
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[15]),
        .DIB(CFG_BRAM_DATA[16]),
        .DIC(CFG_BRAM_DATA[17]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_64_127_15_17),
        .DOB(n_1_fsm_mem_data_reg_r2_64_127_15_17),
        .DOC(n_2_fsm_mem_data_reg_r2_64_127_15_17),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_15_17_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_64_127_18_20
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[18]),
        .DIB(CFG_BRAM_DATA[19]),
        .DIC(CFG_BRAM_DATA[20]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_64_127_18_20),
        .DOB(n_1_fsm_mem_data_reg_r2_64_127_18_20),
        .DOC(n_2_fsm_mem_data_reg_r2_64_127_18_20),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_18_20_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_64_127_21_23
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[21]),
        .DIB(CFG_BRAM_DATA[22]),
        .DIC(CFG_BRAM_DATA[23]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_64_127_21_23),
        .DOB(n_1_fsm_mem_data_reg_r2_64_127_21_23),
        .DOC(n_2_fsm_mem_data_reg_r2_64_127_21_23),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_21_23_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_64_127_3_5
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[3]),
        .DIB(CFG_BRAM_DATA[4]),
        .DIC(CFG_BRAM_DATA[5]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_64_127_3_5),
        .DOB(n_1_fsm_mem_data_reg_r2_64_127_3_5),
        .DOC(n_2_fsm_mem_data_reg_r2_64_127_3_5),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_3_5_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_64_127_6_8
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[6]),
        .DIB(CFG_BRAM_DATA[7]),
        .DIC(CFG_BRAM_DATA[8]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_64_127_6_8),
        .DOB(n_1_fsm_mem_data_reg_r2_64_127_6_8),
        .DOC(n_2_fsm_mem_data_reg_r2_64_127_6_8),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_6_8_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
RAM64M fsm_mem_data_reg_r2_64_127_9_11
       (.ADDRA(bram_rd_addr_reg[5:0]),
        .ADDRB(bram_rd_addr_reg[5:0]),
        .ADDRC(bram_rd_addr_reg[5:0]),
        .ADDRD(bram_addr_reg[5:0]),
        .DIA(CFG_BRAM_DATA[9]),
        .DIB(CFG_BRAM_DATA[10]),
        .DIC(CFG_BRAM_DATA[11]),
        .DID(1'b0),
        .DOA(n_0_fsm_mem_data_reg_r2_64_127_9_11),
        .DOB(n_1_fsm_mem_data_reg_r2_64_127_9_11),
        .DOC(n_2_fsm_mem_data_reg_r2_64_127_9_11),
        .DOD(NLW_fsm_mem_data_reg_r2_64_127_9_11_DOD_UNCONNECTED),
        .WCLK(S_DCLK_O),
        .WE(n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1));
LUT4 #(
    .INIT(16'hE200)) 
     trigger_i_2
       (.I0(n_1_fsm_mem_data_reg_r1_0_63_18_20),
        .I1(addra[3]),
        .I2(n_1_fsm_mem_data_reg_r1_64_127_18_20),
        .I3(arm_status),
        .O(O2));
FDRE trigger_reg
       (.C(clk),
        .CE(1'b1),
        .D(I2),
        .Q(trig_out_fsm_temp),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_cap_addrgen" *) 
module ila_0_ila_v5_0_ila_cap_addrgen
   (I1,
    O1,
    wcnt_hcmp,
    cap_wr_en,
    SR,
    O5,
    O6,
    SRL_Q_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    A,
    clk,
    Q,
    D,
    E);
  output [0:0]I1;
  output [0:0]O1;
  output wcnt_hcmp;
  output cap_wr_en;
  output [0:0]SR;
  output [9:0]O5;
  output [9:0]O6;
  output SRL_Q_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [3:0]A;
  input clk;
  input [1:0]Q;
  input [0:0]D;
  input [0:0]E;

  wire [3:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire [0:0]D;
  wire [0:0]E;
  wire [0:0]I1;
  wire [0:0]O1;
  wire [9:0]O5;
  wire [9:0]O6;
  wire [1:0]Q;
  wire [0:0]SR;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire [9:0]cap_addr_next;
  wire cap_wr_en;
  wire clk;
  wire cmp_reset;
(* DONT_TOUCH *)   wire [9:0]icap_addr;
(* DONT_TOUCH *)   wire icap_wr_en;
  wire n_0_U_CMPRESET;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[10] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[15]_srl5 ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[16] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[1] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[2] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[3] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[4] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[5] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[6] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[7] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[8] ;
  wire \n_0_i_o_to_64k.cfg_data_vec_reg[9] ;
  wire \n_0_i_o_to_64k.u_selx ;
  wire n_11_u_cap_window_counter;
  wire n_13_u_cap_sample_counter;
  wire n_2_u_cap_window_counter;
  wire p_10_in;
  wire p_13_in;
  wire p_16_in;
  wire p_19_in;
  wire p_22_in;
  wire p_25_in;
  wire p_4_in;
  wire p_7_in;
  wire scnt_ce;
  wire wcnt_hcmp;

FDRE CAP_WR_EN_O_reg
       (.C(clk),
        .CE(1'b1),
        .D(icap_wr_en),
        .Q(cap_wr_en),
        .R(Q[1]));
ila_0_ltlib_v1_0_cfglut6 U_CMPRESET
       (.A({I1,A}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .I1(\n_0_i_o_to_64k.u_selx ),
        .I2(O1),
        .O1(n_0_U_CMPRESET),
        .S_DCLK_O(S_DCLK_O),
        .cmp_reset(cmp_reset));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[0] 
       (.C(clk),
        .CE(E),
        .D(n_11_u_cap_window_counter),
        .Q(O6[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[1] 
       (.C(clk),
        .CE(E),
        .D(p_4_in),
        .Q(O6[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[2] 
       (.C(clk),
        .CE(E),
        .D(p_7_in),
        .Q(O6[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[3] 
       (.C(clk),
        .CE(E),
        .D(p_10_in),
        .Q(O6[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[4] 
       (.C(clk),
        .CE(E),
        .D(p_13_in),
        .Q(O6[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[5] 
       (.C(clk),
        .CE(E),
        .D(p_16_in),
        .Q(O6[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[6] 
       (.C(clk),
        .CE(E),
        .D(p_19_in),
        .Q(O6[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[7] 
       (.C(clk),
        .CE(E),
        .D(p_22_in),
        .Q(O6[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[8] 
       (.C(clk),
        .CE(E),
        .D(p_25_in),
        .Q(O6[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \captured_samples_reg[9] 
       (.C(clk),
        .CE(E),
        .D(n_2_u_cap_window_counter),
        .Q(O6[9]),
        .R(1'b0));
FDRE \i_intcap.CAP_ADDR_O_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[0]),
        .Q(O5[0]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[1]),
        .Q(O5[1]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[2]),
        .Q(O5[2]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[3]),
        .Q(O5[3]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[4]),
        .Q(O5[4]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[5]),
        .Q(O5[5]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[6]),
        .Q(O5[6]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[7]),
        .Q(O5[7]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[8]),
        .Q(O5[8]),
        .R(Q[0]));
FDRE \i_intcap.CAP_ADDR_O_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(icap_addr[9]),
        .Q(O5[9]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[0]),
        .Q(icap_addr[0]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[1]),
        .Q(icap_addr[1]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[2]),
        .Q(icap_addr[2]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[3]),
        .Q(icap_addr[3]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[4]),
        .Q(icap_addr[4]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[5]),
        .Q(icap_addr[5]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[6]),
        .Q(icap_addr[6]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[7]),
        .Q(icap_addr[7]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[8]),
        .Q(icap_addr[8]),
        .R(Q[0]));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE \i_intcap.icap_addr_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(cap_addr_next[9]),
        .Q(icap_addr[9]),
        .R(Q[0]));
FDRE \i_o_to_64k.cfg_data_vec_reg[10] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[9] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[10] ),
        .R(1'b0));
(* srl_bus_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/i_o_to_64k.cfg_data_vec_reg " *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/i_o_to_64k.cfg_data_vec_reg[15]_srl5 " *) 
   SRL16E \i_o_to_64k.cfg_data_vec_reg[15]_srl5 
       (.A0(1'b0),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[10] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[15]_srl5 ));
FDRE \i_o_to_64k.cfg_data_vec_reg[16] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[15]_srl5 ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[16] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[1] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(D),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[1] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[2] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[1] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[2] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[3] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[2] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[3] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[4] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[3] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[4] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[5] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[4] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[5] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[6] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[5] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[6] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[7] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[6] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[7] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[8] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[7] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[8] ),
        .R(1'b0));
FDRE \i_o_to_64k.cfg_data_vec_reg[9] 
       (.C(S_DCLK_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[8] ),
        .Q(\n_0_i_o_to_64k.cfg_data_vec_reg[9] ),
        .R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/i_o_to_64k.u_selx " *) 
   SRL16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
     \i_o_to_64k.u_selx 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(\n_0_i_o_to_64k.cfg_data_vec_reg[16] ),
        .Q(\n_0_i_o_to_64k.u_selx ));
(* DONT_TOUCH *) 
   (* KEEP = "yes" *) 
   FDRE icap_wr_en_reg
       (.C(clk),
        .CE(1'b1),
        .D(scnt_ce),
        .Q(icap_wr_en),
        .R(Q[0]));
ila_0_ila_v5_0_ila_cap_sample_counter u_cap_sample_counter
       (.A({I1,A}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(cap_addr_next),
        .E(scnt_ce),
        .I1(n_0_U_CMPRESET),
        .I2(O1),
        .I3({n_2_u_cap_window_counter,p_25_in,p_22_in,p_19_in,p_16_in,p_13_in,p_10_in,p_7_in,p_4_in,n_11_u_cap_window_counter}),
        .Q({\n_0_i_o_to_64k.cfg_data_vec_reg[10] ,\n_0_i_o_to_64k.cfg_data_vec_reg[9] ,\n_0_i_o_to_64k.cfg_data_vec_reg[8] ,\n_0_i_o_to_64k.cfg_data_vec_reg[7] ,\n_0_i_o_to_64k.cfg_data_vec_reg[6] ,\n_0_i_o_to_64k.cfg_data_vec_reg[5] ,\n_0_i_o_to_64k.cfg_data_vec_reg[4] ,\n_0_i_o_to_64k.cfg_data_vec_reg[3] ,\n_0_i_o_to_64k.cfg_data_vec_reg[2] ,\n_0_i_o_to_64k.cfg_data_vec_reg[1] }),
        .SR(SR),
        .SRL_Q_O(n_13_u_cap_sample_counter),
        .S_DCLK_O(S_DCLK_O),
        .clk(clk),
        .cmp_reset(cmp_reset));
ila_0_ila_v5_0_ila_cap_window_counter u_cap_window_counter
       (.A(A),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .I1(n_13_u_cap_sample_counter),
        .I2(Q[0]),
        .O1(I1),
        .Q({n_2_u_cap_window_counter,p_25_in,p_22_in,p_19_in,p_16_in,p_13_in,p_10_in,p_7_in,p_4_in,n_11_u_cap_window_counter}),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O),
        .clk(clk),
        .cmp_reset(cmp_reset),
        .wcnt_hcmp(wcnt_hcmp));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_cap_ctrl_legacy" *) 
module ila_0_ila_v5_0_ila_cap_ctrl_legacy
   (O_reg,
    cap_state,
    D,
    cap_wr_en,
    TRIGGERED_SL_I,
    O1,
    cap_done,
    O2,
    SR,
    O3,
    O4,
    O5,
    O6,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    capture_ctrl_config_serial_output,
    A,
    clk,
    Q,
    trig_out_fsm_temp,
    arm_status,
    en_adv_trigger,
    basic_trigger,
    I1,
    capture_fsm_temp,
    I2,
    E);
  output O_reg;
  output [0:0]cap_state;
  output [0:0]D;
  output cap_wr_en;
  output TRIGGERED_SL_I;
  output O1;
  output cap_done;
  output O2;
  output [0:0]SR;
  output O3;
  output O4;
  output [9:0]O5;
  output [9:0]O6;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input capture_ctrl_config_serial_output;
  input [1:0]A;
  input clk;
  input [1:0]Q;
  input trig_out_fsm_temp;
  input arm_status;
  input en_adv_trigger;
  input basic_trigger;
  input I1;
  input capture_fsm_temp;
  input I2;
  input [0:0]E;

  wire [1:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire [0:0]D;
  wire [0:0]E;
  wire I1;
  wire I2;
  wire O1;
  wire O2;
  wire O3;
  wire O4;
  wire [9:0]O5;
  wire [9:0]O6;
  wire O_reg;
  wire [1:0]Q;
  wire [0:0]SR;
  wire S_DCLK_O;
  wire TRIGGERED_SL_I;
  wire arm_status;
  wire basic_trigger;
  wire cap_done;
  wire cap_done_i;
  wire [0:0]cap_state;
  wire cap_wr_en;
  wire capture_ctrl_config_serial_output;
  wire capture_fsm_temp;
  wire clk;
  wire en_adv_trigger;
  wire itrigger_in;
  wire itrigger_out;
  wire n_0_CAP_DONE_O_i_1;
  wire n_1_U_NS0;
  wire n_1_U_NS1;
  wire n_25_u_cap_addrgen;
  wire scnt_cmp;
  wire trig_out_fsm_temp;
  wire wcnt_hcmp;
  wire wcnt_lcmp;

LUT4 #(
    .INIT(16'hA0AE)) 
     CAP_DONE_O_i_1
       (.I0(cap_done),
        .I1(cap_done_i),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(n_0_CAP_DONE_O_i_1));
FDRE #(
    .INIT(1'b0)) 
     CAP_DONE_O_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_CAP_DONE_O_i_1),
        .Q(cap_done),
        .R(1'b0));
FDRE CAP_TRIGGER_O_reg
       (.C(clk),
        .CE(1'b1),
        .D(itrigger_out),
        .Q(TRIGGERED_SL_I),
        .R(Q[1]));
ila_0_ltlib_v1_0_cfglut6__parameterized0 U_CDONE
       (.A({wcnt_lcmp,A,O_reg,cap_state}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(D),
        .SRL_Q_O(n_25_u_cap_addrgen),
        .S_DCLK_O(S_DCLK_O),
        .cap_done_i(cap_done_i),
        .clk(clk),
        .wcnt_hcmp(wcnt_hcmp));
ila_0_ltlib_v1_0_cfglut7 U_NS0
       (.A({scnt_cmp,A,O_reg}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(n_1_U_NS0),
        .I1(n_1_U_NS1),
        .I2(wcnt_lcmp),
        .O1(cap_state),
        .Q(Q[0]),
        .S_DCLK_O(S_DCLK_O),
        .clk(clk),
        .wcnt_hcmp(wcnt_hcmp));
ila_0_ltlib_v1_0_cfglut7_262 U_NS1
       (.A({scnt_cmp,A}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .I1({wcnt_lcmp,cap_state}),
        .I2(cap_done),
        .I3(I1),
        .I4(I2),
        .O1(O_reg),
        .O2(n_1_U_NS1),
        .O3(O1),
        .O4(O2),
        .O5(O3),
        .O6(O4),
        .Q(Q[0]),
        .S_DCLK_O(S_DCLK_O),
        .arm_status(arm_status),
        .basic_trigger(basic_trigger),
        .capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
        .capture_fsm_temp(capture_fsm_temp),
        .clk(clk),
        .en_adv_trigger(en_adv_trigger),
        .itrigger_in(itrigger_in),
        .trig_out_fsm_temp(trig_out_fsm_temp),
        .wcnt_hcmp(wcnt_hcmp));
FDRE #(
    .INIT(1'b0)) 
     itrigger_out_reg
       (.C(clk),
        .CE(1'b1),
        .D(itrigger_in),
        .Q(itrigger_out),
        .R(Q[0]));
ila_0_ila_v5_0_ila_cap_addrgen u_cap_addrgen
       (.A({A,O_reg,cap_state}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .D(n_1_U_NS0),
        .E(E),
        .I1(wcnt_lcmp),
        .O1(scnt_cmp),
        .O5(O5),
        .O6(O6),
        .Q(Q),
        .SR(SR),
        .SRL_Q_O(n_25_u_cap_addrgen),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk),
        .wcnt_hcmp(wcnt_hcmp));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_cap_sample_counter" *) 
module ila_0_ila_v5_0_ila_cap_sample_counter
   (E,
    I2,
    SR,
    D,
    SRL_Q_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O,
    cmp_reset,
    clk,
    Q,
    I3);
  output [0:0]E;
  output [0:0]I2;
  output [0:0]SR;
  output [9:0]D;
  output SRL_Q_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [4:0]A;
  input S_DCLK_O;
  input cmp_reset;
  input clk;
  input [9:0]Q;
  input [9:0]I3;

  wire [4:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire [9:0]D;
  wire [0:0]E;
  wire I1;
  wire [0:0]I2;
  wire [9:0]I3;
  wire [9:0]Q;
  wire [0:0]SR;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire clk;
  wire cmp_reset;
  wire n_0_U_SCRST;
  wire \n_0_iscnt[9]_i_2 ;
  wire \n_0_iscnt_reg[0] ;
  wire \n_0_iscnt_reg[9] ;
  wire n_1_U_SCE;
  wire n_1_U_SCMPCE;
  wire [9:0]p_0_in;
  wire p_11_in;
  wire p_14_in;
  wire p_17_in;
  wire p_20_in;
  wire p_23_in;
  wire p_26_in;
  wire p_5_in;
  wire p_8_in;
  wire scnt_cmp_ce;
  wire scnt_cmp_temp;

ila_0_ltlib_v1_0_cfglut4_269 U_SCE
       (.A(A[3:0]),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .E(E),
        .I1(I1),
        .O1(n_1_U_SCE),
        .S_DCLK_O(S_DCLK_O));
ila_0_ltlib_v1_0_cfglut5_270 U_SCMPCE
       (.A({I2,A[3:0]}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .I1(n_1_U_SCE),
        .O1(n_1_U_SCMPCE),
        .S_DCLK_O(S_DCLK_O),
        .scnt_cmp_ce(scnt_cmp_ce));
ila_0_ltlib_v1_0_cfglut6_271 U_SCRST
       (.A(A),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .I1(n_1_U_SCMPCE),
        .I2(I2),
        .SR(SR),
        .SRL_D_I(n_0_U_SCRST),
        .S_DCLK_O(S_DCLK_O));
(* SOFT_HLUTNM = "soft_lutpair30" *) 
   LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[0]_i_1 
       (.I0(\n_0_iscnt_reg[0] ),
        .I1(Q[0]),
        .I2(I3[0]),
        .O(D[0]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[1]_i_1 
       (.I0(p_5_in),
        .I1(Q[1]),
        .I2(I3[1]),
        .O(D[1]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[2]_i_1 
       (.I0(p_8_in),
        .I1(Q[2]),
        .I2(I3[2]),
        .O(D[2]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[3]_i_1 
       (.I0(p_11_in),
        .I1(Q[3]),
        .I2(I3[3]),
        .O(D[3]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[4]_i_1 
       (.I0(p_14_in),
        .I1(Q[4]),
        .I2(I3[4]),
        .O(D[4]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[5]_i_1 
       (.I0(p_17_in),
        .I1(Q[5]),
        .I2(I3[5]),
        .O(D[5]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[6]_i_1 
       (.I0(p_20_in),
        .I1(Q[6]),
        .I2(I3[6]),
        .O(D[6]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[7]_i_1 
       (.I0(p_23_in),
        .I1(Q[7]),
        .I2(I3[7]),
        .O(D[7]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[8]_i_1 
       (.I0(p_26_in),
        .I1(Q[8]),
        .I2(I3[8]),
        .O(D[8]));
LUT3 #(
    .INIT(8'hB8)) 
     \i_intcap.icap_addr[9]_i_1 
       (.I0(\n_0_iscnt_reg[9] ),
        .I1(Q[9]),
        .I2(I3[9]),
        .O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair30" *) 
   LUT1 #(
    .INIT(2'h1)) 
     \iscnt[0]_i_1 
       (.I0(\n_0_iscnt_reg[0] ),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair29" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \iscnt[1]_i_1 
       (.I0(\n_0_iscnt_reg[0] ),
        .I1(p_5_in),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair29" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \iscnt[2]_i_1 
       (.I0(p_5_in),
        .I1(\n_0_iscnt_reg[0] ),
        .I2(p_8_in),
        .O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair26" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \iscnt[3]_i_1 
       (.I0(p_8_in),
        .I1(\n_0_iscnt_reg[0] ),
        .I2(p_5_in),
        .I3(p_11_in),
        .O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair26" *) 
   LUT5 #(
    .INIT(32'h7FFF8000)) 
     \iscnt[4]_i_1 
       (.I0(p_11_in),
        .I1(p_5_in),
        .I2(\n_0_iscnt_reg[0] ),
        .I3(p_8_in),
        .I4(p_14_in),
        .O(p_0_in[4]));
LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
     \iscnt[5]_i_1 
       (.I0(p_14_in),
        .I1(p_8_in),
        .I2(\n_0_iscnt_reg[0] ),
        .I3(p_5_in),
        .I4(p_11_in),
        .I5(p_17_in),
        .O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair28" *) 
   LUT2 #(
    .INIT(4'h9)) 
     \iscnt[6]_i_1 
       (.I0(\n_0_iscnt[9]_i_2 ),
        .I1(p_20_in),
        .O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair28" *) 
   LUT3 #(
    .INIT(8'hD2)) 
     \iscnt[7]_i_1 
       (.I0(p_20_in),
        .I1(\n_0_iscnt[9]_i_2 ),
        .I2(p_23_in),
        .O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair27" *) 
   LUT4 #(
    .INIT(16'hDF20)) 
     \iscnt[8]_i_1 
       (.I0(p_23_in),
        .I1(\n_0_iscnt[9]_i_2 ),
        .I2(p_20_in),
        .I3(p_26_in),
        .O(p_0_in[8]));
(* SOFT_HLUTNM = "soft_lutpair27" *) 
   LUT5 #(
    .INIT(32'hF7FF0800)) 
     \iscnt[9]_i_1 
       (.I0(p_26_in),
        .I1(p_20_in),
        .I2(\n_0_iscnt[9]_i_2 ),
        .I3(p_23_in),
        .I4(\n_0_iscnt_reg[9] ),
        .O(p_0_in[9]));
LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
     \iscnt[9]_i_2 
       (.I0(p_14_in),
        .I1(p_8_in),
        .I2(\n_0_iscnt_reg[0] ),
        .I3(p_5_in),
        .I4(p_11_in),
        .I5(p_17_in),
        .O(\n_0_iscnt[9]_i_2 ));
FDRE \iscnt_reg[0] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[0]),
        .Q(\n_0_iscnt_reg[0] ),
        .R(SR));
FDRE \iscnt_reg[1] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[1]),
        .Q(p_5_in),
        .R(SR));
FDRE \iscnt_reg[2] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[2]),
        .Q(p_8_in),
        .R(SR));
FDRE \iscnt_reg[3] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[3]),
        .Q(p_11_in),
        .R(SR));
FDRE \iscnt_reg[4] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[4]),
        .Q(p_14_in),
        .R(SR));
FDRE \iscnt_reg[5] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[5]),
        .Q(p_17_in),
        .R(SR));
FDRE \iscnt_reg[6] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[6]),
        .Q(p_20_in),
        .R(SR));
FDRE \iscnt_reg[7] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[7]),
        .Q(p_23_in),
        .R(SR));
FDRE \iscnt_reg[8] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[8]),
        .Q(p_26_in),
        .R(SR));
FDRE \iscnt_reg[9] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[9]),
        .Q(\n_0_iscnt_reg[9] ),
        .R(SR));
ila_0_ltlib_v1_0_match_nodelay_272 u_scnt_cmp
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(scnt_cmp_temp),
        .Q({\n_0_iscnt_reg[9] ,p_26_in,p_23_in,p_20_in,p_17_in,p_14_in,p_11_in,p_8_in,p_5_in,\n_0_iscnt_reg[0] }),
        .SRL_D_I(n_0_U_SCRST),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O),
        .clk(clk));
(* BOX_TYPE = "PRIMITIVE" *) 
   FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
     u_scnt_cmp_q
       (.C(clk),
        .CE(scnt_cmp_ce),
        .D(scnt_cmp_temp),
        .Q(I2),
        .R(cmp_reset));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_cap_window_counter" *) 
module ila_0_ila_v5_0_ila_cap_window_counter
   (O1,
    wcnt_hcmp,
    Q,
    SRL_Q_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O,
    cmp_reset,
    clk,
    I2);
  output [0:0]O1;
  output wcnt_hcmp;
  output [9:0]Q;
  output SRL_Q_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [3:0]A;
  input S_DCLK_O;
  input cmp_reset;
  input clk;
  input [0:0]I2;

  wire [3:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire I1;
  wire [0:0]I2;
  wire [0:0]O1;
  wire [9:0]Q;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire [9:0]\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 ;
  wire clk;
  wire cmp_reset;
  wire \n_0_iwcnt[9]_i_2 ;
  wire n_10_u_wcnt_lcmp;
  wire n_1_U_WCE;
  wire n_1_U_WHCMPCE;
  wire n_1_U_WLCMPCE;
  wire [9:0]p_0_in__0;
  wire wcnt_ce;
  wire wcnt_hcmp;
  wire wcnt_hcmp_ce;
  wire wcnt_hcmp_temp;
  wire wcnt_lcmp_ce;
  wire wcnt_lcmp_temp;

ila_0_ltlib_v1_0_cfglut4 U_WCE
       (.A(A),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .E(wcnt_ce),
        .I1(I1),
        .O1(n_1_U_WCE),
        .S_DCLK_O(S_DCLK_O));
ila_0_ltlib_v1_0_cfglut5 U_WHCMPCE
       (.A({wcnt_hcmp,A}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .SRL_D_I(n_1_U_WHCMPCE),
        .SRL_Q_O(n_10_u_wcnt_lcmp),
        .S_DCLK_O(S_DCLK_O),
        .wcnt_hcmp_ce(wcnt_hcmp_ce));
ila_0_ltlib_v1_0_cfglut5_263 U_WLCMPCE
       (.A({O1,A}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .I1(n_1_U_WCE),
        .SRL_D_I(n_1_U_WLCMPCE),
        .S_DCLK_O(S_DCLK_O),
        .wcnt_lcmp_ce(wcnt_lcmp_ce));
LUT1 #(
    .INIT(2'h1)) 
     \iwcnt[0]_i_1 
       (.I0(Q[0]),
        .O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair33" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \iwcnt[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair33" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \iwcnt[2]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(Q[2]),
        .O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair31" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \iwcnt[3]_i_1 
       (.I0(Q[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[3]),
        .O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair31" *) 
   LUT5 #(
    .INIT(32'h7FFF8000)) 
     \iwcnt[4]_i_1 
       (.I0(Q[3]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[2]),
        .I4(Q[4]),
        .O(p_0_in__0[4]));
LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
     \iwcnt[5]_i_1 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .I5(Q[5]),
        .O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair34" *) 
   LUT2 #(
    .INIT(4'h9)) 
     \iwcnt[6]_i_1 
       (.I0(\n_0_iwcnt[9]_i_2 ),
        .I1(Q[6]),
        .O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair34" *) 
   LUT3 #(
    .INIT(8'hD2)) 
     \iwcnt[7]_i_1 
       (.I0(Q[6]),
        .I1(\n_0_iwcnt[9]_i_2 ),
        .I2(Q[7]),
        .O(p_0_in__0[7]));
(* SOFT_HLUTNM = "soft_lutpair32" *) 
   LUT4 #(
    .INIT(16'hDF20)) 
     \iwcnt[8]_i_1 
       (.I0(Q[7]),
        .I1(\n_0_iwcnt[9]_i_2 ),
        .I2(Q[6]),
        .I3(Q[8]),
        .O(p_0_in__0[8]));
(* SOFT_HLUTNM = "soft_lutpair32" *) 
   LUT5 #(
    .INIT(32'hF7FF0800)) 
     \iwcnt[9]_i_1 
       (.I0(Q[8]),
        .I1(Q[6]),
        .I2(\n_0_iwcnt[9]_i_2 ),
        .I3(Q[7]),
        .I4(Q[9]),
        .O(p_0_in__0[9]));
LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
     \iwcnt[9]_i_2 
       (.I0(Q[4]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[3]),
        .I5(Q[5]),
        .O(\n_0_iwcnt[9]_i_2 ));
FDRE \iwcnt_reg[0] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[0]),
        .Q(Q[0]),
        .R(I2));
FDRE \iwcnt_reg[1] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[1]),
        .Q(Q[1]),
        .R(I2));
FDRE \iwcnt_reg[2] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[2]),
        .Q(Q[2]),
        .R(I2));
FDRE \iwcnt_reg[3] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[3]),
        .Q(Q[3]),
        .R(I2));
FDRE \iwcnt_reg[4] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[4]),
        .Q(Q[4]),
        .R(I2));
FDRE \iwcnt_reg[5] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[5]),
        .Q(Q[5]),
        .R(I2));
FDRE \iwcnt_reg[6] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[6]),
        .Q(Q[6]),
        .R(I2));
FDRE \iwcnt_reg[7] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[7]),
        .Q(Q[7]),
        .R(I2));
FDRE \iwcnt_reg[8] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[8]),
        .Q(Q[8]),
        .R(I2));
FDRE \iwcnt_reg[9] 
       (.C(clk),
        .CE(wcnt_ce),
        .D(p_0_in__0[9]),
        .Q(Q[9]),
        .R(I2));
ila_0_ltlib_v1_0_match_nodelay u_wcnt_hcmp
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(wcnt_hcmp_temp),
        .PROBES_I({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [9],Q[9],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [8],Q[8],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [7],Q[7],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [6],Q[6],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [5],Q[5],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [4],Q[4],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [3],Q[3],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [2],Q[2],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [1],Q[1],\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 [0],Q[0]}),
        .SRL_D_I(n_1_U_WHCMPCE),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O));
(* BOX_TYPE = "PRIMITIVE" *) 
   FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
     u_wcnt_hcmp_q
       (.C(clk),
        .CE(wcnt_hcmp_ce),
        .D(wcnt_hcmp_temp),
        .Q(wcnt_hcmp),
        .R(cmp_reset));
ila_0_ltlib_v1_0_match_nodelay_264 u_wcnt_lcmp
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(wcnt_lcmp_temp),
        .I1(Q),
        .Q(\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 ),
        .SRL_D_I(n_1_U_WLCMPCE),
        .SRL_Q_O(n_10_u_wcnt_lcmp),
        .S_DCLK_O(S_DCLK_O),
        .clk(clk));
(* BOX_TYPE = "PRIMITIVE" *) 
   FDRE #(
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_R_INVERTED(1'b0)) 
     u_wcnt_lcmp_q
       (.C(clk),
        .CE(wcnt_lcmp_ce),
        .D(wcnt_lcmp_temp),
        .Q(O1),
        .R(cmp_reset));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_core" *) 
module ila_0_ila_v5_0_ila_core
   (SL_OPORT_O,
    probe12,
    clk,
    probe11,
    probe10,
    probe9,
    probe8,
    probe7,
    probe6,
    probe5,
    probe4,
    probe3,
    probe2,
    probe1,
    probe0,
    SL_IPORT_I);
  output [16:0]SL_OPORT_O;
  input [3:0]probe12;
  input clk;
  input [0:0]probe11;
  input [0:0]probe10;
  input [31:0]probe9;
  input [0:0]probe8;
  input [0:0]probe7;
  input [31:0]probe6;
  input [0:0]probe5;
  input [0:0]probe4;
  input [31:0]probe3;
  input [0:0]probe2;
  input [0:0]probe1;
  input [31:0]probe0;
  input [36:0]SL_IPORT_I;

  wire [23:0]CFG_BRAM_DATA;
  wire O_reg;
  wire [36:0]SL_IPORT_I;
  wire [16:0]SL_OPORT_O;
  wire [6:0]addra;
  wire adv_drdy;
  wire arm_ctrl;
  wire arm_status;
  wire basic_trigger;
  wire bram_en;
  wire bram_rd_en;
  wire cap_done;
  wire [0:0]cap_state;
  wire cap_trigger_out;
  wire [9:0]cap_wr_addr;
  wire cap_wr_en;
  wire capture_ctrl_config_cs_serial_input;
  wire capture_ctrl_config_en;
  wire capture_ctrl_config_serial_output;
  wire capture_fsm_temp;
  wire capture_i;
  wire capture_strg_qual;
  wire clk;
  wire [3:0]cnt_config_cs_serial_input;
  wire [3:0]cnt_config_cs_serial_output;
  wire [3:0]cnt_config_cs_shift_en;
  wire [1:0]cntcmpsel;
  wire [15:0]config_fsm_data;
  wire [15:0]config_fsm_data_rd_temp;
  wire [7:0]counter_ctrl_temp;
  wire data_out_en_0;
  wire [15:0]data_word_out;
  wire [15:0]debug_data_in;
  wire den;
  wire en_adv_trigger;
  wire flag0_temp;
  wire flag1_temp;
  wire flag2_temp;
  wire flag3_temp;
  wire [23:0]fsm_bram_data_rd;
  wire halt_ctrl;
  wire halt_status;
  wire [140:0]mem_data_out;
  wire [12:0]mu_config_cs_serial_input;
  wire [12:0]mu_config_cs_serial_output;
  wire [12:0]mu_config_cs_shift_en;
  wire n_0_adv_drdy_i_1;
  wire \n_0_shifted_data_in_reg[7][0]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][100]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][101]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][102]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][103]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][104]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][105]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][106]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][107]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][108]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][109]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][10]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][110]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][111]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][112]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][113]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][114]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][115]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][116]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][117]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][118]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][119]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][11]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][120]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][121]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][122]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][123]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][124]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][125]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][126]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][127]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][128]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][129]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][12]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][130]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][131]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][132]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][133]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][134]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][135]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][136]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][137]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][138]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][139]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][13]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][14]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][15]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][16]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][17]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][18]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][19]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][1]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][20]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][21]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][22]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][23]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][24]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][25]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][26]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][27]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][28]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][29]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][2]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][30]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][31]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][32]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][33]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][34]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][35]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][36]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][37]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][38]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][39]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][3]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][40]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][41]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][42]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][43]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][44]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][45]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][46]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][47]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][48]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][49]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][4]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][50]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][51]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][52]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][53]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][54]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][55]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][56]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][57]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][58]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][59]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][5]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][60]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][61]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][62]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][63]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][64]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][65]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][66]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][67]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][68]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][69]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][6]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][70]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][71]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][72]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][73]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][74]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][75]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][76]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][77]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][78]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][79]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][7]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][80]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][81]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][82]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][83]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][84]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][85]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][86]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][87]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][88]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][89]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][8]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][90]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][91]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][92]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][93]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][94]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][95]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][96]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][97]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][98]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][99]_srl8 ;
  wire \n_0_shifted_data_in_reg[7][9]_srl8 ;
  wire \n_0_shifted_data_in_reg[8][0] ;
  wire \n_0_shifted_data_in_reg[8][100] ;
  wire \n_0_shifted_data_in_reg[8][101] ;
  wire \n_0_shifted_data_in_reg[8][102] ;
  wire \n_0_shifted_data_in_reg[8][103] ;
  wire \n_0_shifted_data_in_reg[8][104] ;
  wire \n_0_shifted_data_in_reg[8][105] ;
  wire \n_0_shifted_data_in_reg[8][106] ;
  wire \n_0_shifted_data_in_reg[8][107] ;
  wire \n_0_shifted_data_in_reg[8][108] ;
  wire \n_0_shifted_data_in_reg[8][109] ;
  wire \n_0_shifted_data_in_reg[8][10] ;
  wire \n_0_shifted_data_in_reg[8][110] ;
  wire \n_0_shifted_data_in_reg[8][111] ;
  wire \n_0_shifted_data_in_reg[8][112] ;
  wire \n_0_shifted_data_in_reg[8][113] ;
  wire \n_0_shifted_data_in_reg[8][114] ;
  wire \n_0_shifted_data_in_reg[8][115] ;
  wire \n_0_shifted_data_in_reg[8][116] ;
  wire \n_0_shifted_data_in_reg[8][117] ;
  wire \n_0_shifted_data_in_reg[8][118] ;
  wire \n_0_shifted_data_in_reg[8][119] ;
  wire \n_0_shifted_data_in_reg[8][11] ;
  wire \n_0_shifted_data_in_reg[8][120] ;
  wire \n_0_shifted_data_in_reg[8][121] ;
  wire \n_0_shifted_data_in_reg[8][122] ;
  wire \n_0_shifted_data_in_reg[8][123] ;
  wire \n_0_shifted_data_in_reg[8][124] ;
  wire \n_0_shifted_data_in_reg[8][125] ;
  wire \n_0_shifted_data_in_reg[8][126] ;
  wire \n_0_shifted_data_in_reg[8][127] ;
  wire \n_0_shifted_data_in_reg[8][128] ;
  wire \n_0_shifted_data_in_reg[8][129] ;
  wire \n_0_shifted_data_in_reg[8][12] ;
  wire \n_0_shifted_data_in_reg[8][130] ;
  wire \n_0_shifted_data_in_reg[8][131] ;
  wire \n_0_shifted_data_in_reg[8][132] ;
  wire \n_0_shifted_data_in_reg[8][133] ;
  wire \n_0_shifted_data_in_reg[8][134] ;
  wire \n_0_shifted_data_in_reg[8][135] ;
  wire \n_0_shifted_data_in_reg[8][136] ;
  wire \n_0_shifted_data_in_reg[8][137] ;
  wire \n_0_shifted_data_in_reg[8][138] ;
  wire \n_0_shifted_data_in_reg[8][139] ;
  wire \n_0_shifted_data_in_reg[8][13] ;
  wire \n_0_shifted_data_in_reg[8][14] ;
  wire \n_0_shifted_data_in_reg[8][15] ;
  wire \n_0_shifted_data_in_reg[8][16] ;
  wire \n_0_shifted_data_in_reg[8][17] ;
  wire \n_0_shifted_data_in_reg[8][18] ;
  wire \n_0_shifted_data_in_reg[8][19] ;
  wire \n_0_shifted_data_in_reg[8][1] ;
  wire \n_0_shifted_data_in_reg[8][20] ;
  wire \n_0_shifted_data_in_reg[8][21] ;
  wire \n_0_shifted_data_in_reg[8][22] ;
  wire \n_0_shifted_data_in_reg[8][23] ;
  wire \n_0_shifted_data_in_reg[8][24] ;
  wire \n_0_shifted_data_in_reg[8][25] ;
  wire \n_0_shifted_data_in_reg[8][26] ;
  wire \n_0_shifted_data_in_reg[8][27] ;
  wire \n_0_shifted_data_in_reg[8][28] ;
  wire \n_0_shifted_data_in_reg[8][29] ;
  wire \n_0_shifted_data_in_reg[8][2] ;
  wire \n_0_shifted_data_in_reg[8][30] ;
  wire \n_0_shifted_data_in_reg[8][31] ;
  wire \n_0_shifted_data_in_reg[8][32] ;
  wire \n_0_shifted_data_in_reg[8][33] ;
  wire \n_0_shifted_data_in_reg[8][34] ;
  wire \n_0_shifted_data_in_reg[8][35] ;
  wire \n_0_shifted_data_in_reg[8][36] ;
  wire \n_0_shifted_data_in_reg[8][37] ;
  wire \n_0_shifted_data_in_reg[8][38] ;
  wire \n_0_shifted_data_in_reg[8][39] ;
  wire \n_0_shifted_data_in_reg[8][3] ;
  wire \n_0_shifted_data_in_reg[8][40] ;
  wire \n_0_shifted_data_in_reg[8][41] ;
  wire \n_0_shifted_data_in_reg[8][42] ;
  wire \n_0_shifted_data_in_reg[8][43] ;
  wire \n_0_shifted_data_in_reg[8][44] ;
  wire \n_0_shifted_data_in_reg[8][45] ;
  wire \n_0_shifted_data_in_reg[8][46] ;
  wire \n_0_shifted_data_in_reg[8][47] ;
  wire \n_0_shifted_data_in_reg[8][48] ;
  wire \n_0_shifted_data_in_reg[8][49] ;
  wire \n_0_shifted_data_in_reg[8][4] ;
  wire \n_0_shifted_data_in_reg[8][50] ;
  wire \n_0_shifted_data_in_reg[8][51] ;
  wire \n_0_shifted_data_in_reg[8][52] ;
  wire \n_0_shifted_data_in_reg[8][53] ;
  wire \n_0_shifted_data_in_reg[8][54] ;
  wire \n_0_shifted_data_in_reg[8][55] ;
  wire \n_0_shifted_data_in_reg[8][56] ;
  wire \n_0_shifted_data_in_reg[8][57] ;
  wire \n_0_shifted_data_in_reg[8][58] ;
  wire \n_0_shifted_data_in_reg[8][59] ;
  wire \n_0_shifted_data_in_reg[8][5] ;
  wire \n_0_shifted_data_in_reg[8][60] ;
  wire \n_0_shifted_data_in_reg[8][61] ;
  wire \n_0_shifted_data_in_reg[8][62] ;
  wire \n_0_shifted_data_in_reg[8][63] ;
  wire \n_0_shifted_data_in_reg[8][64] ;
  wire \n_0_shifted_data_in_reg[8][65] ;
  wire \n_0_shifted_data_in_reg[8][66] ;
  wire \n_0_shifted_data_in_reg[8][67] ;
  wire \n_0_shifted_data_in_reg[8][68] ;
  wire \n_0_shifted_data_in_reg[8][69] ;
  wire \n_0_shifted_data_in_reg[8][6] ;
  wire \n_0_shifted_data_in_reg[8][70] ;
  wire \n_0_shifted_data_in_reg[8][71] ;
  wire \n_0_shifted_data_in_reg[8][72] ;
  wire \n_0_shifted_data_in_reg[8][73] ;
  wire \n_0_shifted_data_in_reg[8][74] ;
  wire \n_0_shifted_data_in_reg[8][75] ;
  wire \n_0_shifted_data_in_reg[8][76] ;
  wire \n_0_shifted_data_in_reg[8][77] ;
  wire \n_0_shifted_data_in_reg[8][78] ;
  wire \n_0_shifted_data_in_reg[8][79] ;
  wire \n_0_shifted_data_in_reg[8][7] ;
  wire \n_0_shifted_data_in_reg[8][80] ;
  wire \n_0_shifted_data_in_reg[8][81] ;
  wire \n_0_shifted_data_in_reg[8][82] ;
  wire \n_0_shifted_data_in_reg[8][83] ;
  wire \n_0_shifted_data_in_reg[8][84] ;
  wire \n_0_shifted_data_in_reg[8][85] ;
  wire \n_0_shifted_data_in_reg[8][86] ;
  wire \n_0_shifted_data_in_reg[8][87] ;
  wire \n_0_shifted_data_in_reg[8][88] ;
  wire \n_0_shifted_data_in_reg[8][89] ;
  wire \n_0_shifted_data_in_reg[8][8] ;
  wire \n_0_shifted_data_in_reg[8][90] ;
  wire \n_0_shifted_data_in_reg[8][91] ;
  wire \n_0_shifted_data_in_reg[8][92] ;
  wire \n_0_shifted_data_in_reg[8][93] ;
  wire \n_0_shifted_data_in_reg[8][94] ;
  wire \n_0_shifted_data_in_reg[8][95] ;
  wire \n_0_shifted_data_in_reg[8][96] ;
  wire \n_0_shifted_data_in_reg[8][97] ;
  wire \n_0_shifted_data_in_reg[8][98] ;
  wire \n_0_shifted_data_in_reg[8][99] ;
  wire \n_0_shifted_data_in_reg[8][9] ;
  wire \n_0_trace_data_ack_reg[0] ;
  wire n_10_u_ila_cap_ctrl;
  wire \n_14_ADV_TRIG.u_adv_trig ;
  wire \n_15_ADV_TRIG.u_adv_trig ;
  wire n_21_u_ila_cap_ctrl;
  wire n_22_u_ila_cap_ctrl;
  wire n_23_u_ila_cap_ctrl;
  wire n_23_u_ila_regs;
  wire n_24_u_ila_cap_ctrl;
  wire n_25_u_ila_cap_ctrl;
  wire n_25_u_ila_regs;
  wire n_26_u_ila_cap_ctrl;
  wire n_26_u_ila_regs;
  wire n_27_u_ila_cap_ctrl;
  wire n_28_u_ila_cap_ctrl;
  wire n_29_u_ila_cap_ctrl;
  wire n_2_u_ila_regs;
  wire n_2_u_ila_reset_ctrl;
  wire n_30_u_ila_cap_ctrl;
  wire n_30_u_ila_regs;
  wire n_33_u_ila_regs;
  wire n_34_u_ila_regs;
  wire n_38_u_ila_regs;
  wire n_39_u_ila_regs;
  wire n_3_u_ila_regs;
  wire n_40_u_ila_regs;
  wire n_41_u_ila_regs;
  wire n_42_u_ila_regs;
  wire n_43_u_ila_regs;
  wire n_44_u_ila_regs;
  wire n_45_u_ila_regs;
  wire n_46_u_ila_regs;
  wire n_48_u_trig;
  wire n_4_u_ila_regs;
  wire n_5_u_ila_cap_ctrl;
  wire n_79_u_ila_regs;
  wire n_7_u_ila_cap_ctrl;
  wire n_80_u_ila_regs;
  wire n_8_u_ila_reset_ctrl;
  wire n_9_u_ila_cap_ctrl;
  wire [5:4]p_0_out;
  wire [15:15]p_2_out;
  wire [31:0]probe0;
  wire [0:0]probe1;
  wire [0:0]probe10;
  wire [0:0]probe11;
  wire [3:0]probe12;
  wire [0:0]probe2;
  wire [31:0]probe3;
  wire [0:0]probe4;
  wire [0:0]probe5;
  wire [31:0]probe6;
  wire [0:0]probe7;
  wire [0:0]probe8;
  wire [31:0]probe9;
  wire [15:0]probe_data;
  wire read_addr_reset;
  wire read_data_en;
  wire [1:0]reset;
  wire s_dclk;
  wire scnt_reset;
  wire [15:0]sequencer_state_temp;
  wire [31:0]tc_config_cs_serial_input;
  wire [31:0]tc_config_cs_serial_output;
  wire [31:0]tc_config_cs_shift_en;
  wire toggle;
  wire toggle_rd;
  wire [1:1]trace_data_ack;
  wire [9:0]trace_read_addr;
  wire trace_read_en;
  wire trig_out_fsm_temp;
  wire use_probe_debug_circuit;

ila_0_ila_v5_0_ila_adv_trigger_sequencer \ADV_TRIG.u_adv_trig 
       (.ADDRA(addra[2:0]),
        .CFG_BRAM_DATA(CFG_BRAM_DATA),
        .CNT_CTRL(counter_ctrl_temp),
        .E(toggle),
        .FLAG0_I(flag0_temp),
        .FLAG1_I(flag1_temp),
        .FLAG2_I(flag2_temp),
        .FLAG3_I(flag3_temp),
        .I1(n_9_u_ila_cap_ctrl),
        .I2(n_10_u_ila_cap_ctrl),
        .I3(n_7_u_ila_cap_ctrl),
        .I4(n_5_u_ila_cap_ctrl),
        .O1(\n_14_ADV_TRIG.u_adv_trig ),
        .O2(\n_15_ADV_TRIG.u_adv_trig ),
        .O3(fsm_bram_data_rd),
        .Q(reset),
        .SEQUENCER_STATE_I(sequencer_state_temp),
        .S_DCLK_O(s_dclk),
        .addra(addra[6:3]),
        .arm_status(arm_status),
        .bram_en(bram_en),
        .bram_rd_en(bram_rd_en),
        .capture_fsm_temp(capture_fsm_temp),
        .clk(clk),
        .cntcmpsel(cntcmpsel),
        .p_2_out(p_2_out),
        .toggle_rd(toggle_rd),
        .trig_out_fsm_temp(trig_out_fsm_temp));
ila_0_ila_v5_0_ila_fsm_memory_read \ADV_TRIG_MEM_READ.u_fsm_memory_read_inst 
       (.CFG_BRAM_DATA(CFG_BRAM_DATA),
        .D(config_fsm_data),
        .E(toggle),
        .FSM_BRAM_CONFIG_DATA_I(config_fsm_data_rd_temp),
        .I1(n_34_u_ila_regs),
        .I2(n_33_u_ila_regs),
        .O3(fsm_bram_data_rd),
        .S_DCLK_O(s_dclk),
        .toggle_rd(toggle_rd));
ila_0_ila_v5_0_ila_counter \COUNTER.u_count 
       (.ADDRA(addra[0]),
        .CFG_CNT_DIN(cnt_config_cs_serial_output),
        .CFG_CNT_DOUT(cnt_config_cs_serial_input),
        .CNT_CONFIG_CS_SHIFT_EN_O(cnt_config_cs_shift_en),
        .CNT_CTRL(counter_ctrl_temp),
        .Q(reset),
        .SR(scnt_reset),
        .S_DCLK_O(s_dclk),
        .clk(clk),
        .cntcmpsel(cntcmpsel));
LUT6 #(
    .INIT(64'hFFFBFFFF00080000)) 
     adv_drdy_i_1
       (.I0(den),
        .I1(n_79_u_ila_regs),
        .I2(n_3_u_ila_regs),
        .I3(n_4_u_ila_regs),
        .I4(n_2_u_ila_regs),
        .I5(adv_drdy),
        .O(n_0_adv_drdy_i_1));
FDRE basic_trigger_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_48_u_trig),
        .Q(basic_trigger),
        .R(1'b0));
ila_0_ila_v5_0_ila_trace_memory ila_trace_memory_inst
       (.D(trace_read_en),
        .DINA({cap_trigger_out,\n_0_shifted_data_in_reg[8][139] ,\n_0_shifted_data_in_reg[8][138] ,\n_0_shifted_data_in_reg[8][137] ,\n_0_shifted_data_in_reg[8][136] ,\n_0_shifted_data_in_reg[8][135] ,\n_0_shifted_data_in_reg[8][134] ,\n_0_shifted_data_in_reg[8][133] ,\n_0_shifted_data_in_reg[8][132] ,\n_0_shifted_data_in_reg[8][131] ,\n_0_shifted_data_in_reg[8][130] ,\n_0_shifted_data_in_reg[8][129] ,\n_0_shifted_data_in_reg[8][128] ,\n_0_shifted_data_in_reg[8][127] ,\n_0_shifted_data_in_reg[8][126] ,\n_0_shifted_data_in_reg[8][125] ,\n_0_shifted_data_in_reg[8][124] ,\n_0_shifted_data_in_reg[8][123] ,\n_0_shifted_data_in_reg[8][122] ,\n_0_shifted_data_in_reg[8][121] ,\n_0_shifted_data_in_reg[8][120] ,\n_0_shifted_data_in_reg[8][119] ,\n_0_shifted_data_in_reg[8][118] ,\n_0_shifted_data_in_reg[8][117] ,\n_0_shifted_data_in_reg[8][116] ,\n_0_shifted_data_in_reg[8][115] ,\n_0_shifted_data_in_reg[8][114] ,\n_0_shifted_data_in_reg[8][113] ,\n_0_shifted_data_in_reg[8][112] ,\n_0_shifted_data_in_reg[8][111] ,\n_0_shifted_data_in_reg[8][110] ,\n_0_shifted_data_in_reg[8][109] ,\n_0_shifted_data_in_reg[8][108] ,\n_0_shifted_data_in_reg[8][107] ,\n_0_shifted_data_in_reg[8][106] ,\n_0_shifted_data_in_reg[8][105] ,\n_0_shifted_data_in_reg[8][104] ,\n_0_shifted_data_in_reg[8][103] ,\n_0_shifted_data_in_reg[8][102] ,\n_0_shifted_data_in_reg[8][101] ,\n_0_shifted_data_in_reg[8][100] ,\n_0_shifted_data_in_reg[8][99] ,\n_0_shifted_data_in_reg[8][98] ,\n_0_shifted_data_in_reg[8][97] ,\n_0_shifted_data_in_reg[8][96] ,\n_0_shifted_data_in_reg[8][95] ,\n_0_shifted_data_in_reg[8][94] ,\n_0_shifted_data_in_reg[8][93] ,\n_0_shifted_data_in_reg[8][92] ,\n_0_shifted_data_in_reg[8][91] ,\n_0_shifted_data_in_reg[8][90] ,\n_0_shifted_data_in_reg[8][89] ,\n_0_shifted_data_in_reg[8][88] ,\n_0_shifted_data_in_reg[8][87] ,\n_0_shifted_data_in_reg[8][86] ,\n_0_shifted_data_in_reg[8][85] ,\n_0_shifted_data_in_reg[8][84] ,\n_0_shifted_data_in_reg[8][83] ,\n_0_shifted_data_in_reg[8][82] ,\n_0_shifted_data_in_reg[8][81] ,\n_0_shifted_data_in_reg[8][80] ,\n_0_shifted_data_in_reg[8][79] ,\n_0_shifted_data_in_reg[8][78] ,\n_0_shifted_data_in_reg[8][77] ,\n_0_shifted_data_in_reg[8][76] ,\n_0_shifted_data_in_reg[8][75] ,\n_0_shifted_data_in_reg[8][74] ,\n_0_shifted_data_in_reg[8][73] ,\n_0_shifted_data_in_reg[8][72] ,\n_0_shifted_data_in_reg[8][71] ,\n_0_shifted_data_in_reg[8][70] ,\n_0_shifted_data_in_reg[8][69] ,\n_0_shifted_data_in_reg[8][68] ,\n_0_shifted_data_in_reg[8][67] ,\n_0_shifted_data_in_reg[8][66] ,\n_0_shifted_data_in_reg[8][65] ,\n_0_shifted_data_in_reg[8][64] ,\n_0_shifted_data_in_reg[8][63] ,\n_0_shifted_data_in_reg[8][62] ,\n_0_shifted_data_in_reg[8][61] ,\n_0_shifted_data_in_reg[8][60] ,\n_0_shifted_data_in_reg[8][59] ,\n_0_shifted_data_in_reg[8][58] ,\n_0_shifted_data_in_reg[8][57] ,\n_0_shifted_data_in_reg[8][56] ,\n_0_shifted_data_in_reg[8][55] ,\n_0_shifted_data_in_reg[8][54] ,\n_0_shifted_data_in_reg[8][53] ,\n_0_shifted_data_in_reg[8][52] ,\n_0_shifted_data_in_reg[8][51] ,\n_0_shifted_data_in_reg[8][50] ,\n_0_shifted_data_in_reg[8][49] ,\n_0_shifted_data_in_reg[8][48] ,\n_0_shifted_data_in_reg[8][47] ,\n_0_shifted_data_in_reg[8][46] ,\n_0_shifted_data_in_reg[8][45] ,\n_0_shifted_data_in_reg[8][44] ,\n_0_shifted_data_in_reg[8][43] ,\n_0_shifted_data_in_reg[8][42] ,\n_0_shifted_data_in_reg[8][41] ,\n_0_shifted_data_in_reg[8][40] ,\n_0_shifted_data_in_reg[8][39] ,\n_0_shifted_data_in_reg[8][38] ,\n_0_shifted_data_in_reg[8][37] ,\n_0_shifted_data_in_reg[8][36] ,\n_0_shifted_data_in_reg[8][35] ,\n_0_shifted_data_in_reg[8][34] ,\n_0_shifted_data_in_reg[8][33] ,\n_0_shifted_data_in_reg[8][32] ,\n_0_shifted_data_in_reg[8][31] ,\n_0_shifted_data_in_reg[8][30] ,\n_0_shifted_data_in_reg[8][29] ,\n_0_shifted_data_in_reg[8][28] ,\n_0_shifted_data_in_reg[8][27] ,\n_0_shifted_data_in_reg[8][26] ,\n_0_shifted_data_in_reg[8][25] ,\n_0_shifted_data_in_reg[8][24] ,\n_0_shifted_data_in_reg[8][23] ,\n_0_shifted_data_in_reg[8][22] ,\n_0_shifted_data_in_reg[8][21] ,\n_0_shifted_data_in_reg[8][20] ,\n_0_shifted_data_in_reg[8][19] ,\n_0_shifted_data_in_reg[8][18] ,\n_0_shifted_data_in_reg[8][17] ,\n_0_shifted_data_in_reg[8][16] ,\n_0_shifted_data_in_reg[8][15] ,\n_0_shifted_data_in_reg[8][14] ,\n_0_shifted_data_in_reg[8][13] ,\n_0_shifted_data_in_reg[8][12] ,\n_0_shifted_data_in_reg[8][11] ,\n_0_shifted_data_in_reg[8][10] ,\n_0_shifted_data_in_reg[8][9] ,\n_0_shifted_data_in_reg[8][8] ,\n_0_shifted_data_in_reg[8][7] ,\n_0_shifted_data_in_reg[8][6] ,\n_0_shifted_data_in_reg[8][5] ,\n_0_shifted_data_in_reg[8][4] ,\n_0_shifted_data_in_reg[8][3] ,\n_0_shifted_data_in_reg[8][2] ,\n_0_shifted_data_in_reg[8][1] ,\n_0_shifted_data_in_reg[8][0] }),
        .DOUTB(mem_data_out),
        .I1(trace_read_addr),
        .Q(cap_wr_addr),
        .S_DCLK_O(s_dclk),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
(* SOFT_HLUTNM = "soft_lutpair266" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[0]_i_1 
       (.I0(debug_data_in[0]),
        .I1(probe0[0]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[0]));
(* SOFT_HLUTNM = "soft_lutpair271" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[10]_i_1 
       (.I0(debug_data_in[10]),
        .I1(probe0[10]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[10]));
(* SOFT_HLUTNM = "soft_lutpair271" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[11]_i_1 
       (.I0(debug_data_in[11]),
        .I1(probe0[11]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[11]));
(* SOFT_HLUTNM = "soft_lutpair272" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[12]_i_1 
       (.I0(debug_data_in[12]),
        .I1(probe0[12]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[12]));
(* SOFT_HLUTNM = "soft_lutpair272" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[13]_i_1 
       (.I0(debug_data_in[13]),
        .I1(probe0[13]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[13]));
(* SOFT_HLUTNM = "soft_lutpair273" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[14]_i_1 
       (.I0(debug_data_in[14]),
        .I1(probe0[14]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[14]));
(* SOFT_HLUTNM = "soft_lutpair273" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[15]_i_1 
       (.I0(debug_data_in[15]),
        .I1(probe0[15]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[15]));
(* SOFT_HLUTNM = "soft_lutpair266" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[1]_i_1 
       (.I0(debug_data_in[1]),
        .I1(probe0[1]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[1]));
(* SOFT_HLUTNM = "soft_lutpair267" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[2]_i_1 
       (.I0(debug_data_in[2]),
        .I1(probe0[2]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[2]));
(* SOFT_HLUTNM = "soft_lutpair267" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[3]_i_1 
       (.I0(debug_data_in[3]),
        .I1(probe0[3]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[3]));
(* SOFT_HLUTNM = "soft_lutpair268" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[4]_i_1 
       (.I0(debug_data_in[4]),
        .I1(probe0[4]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[4]));
(* SOFT_HLUTNM = "soft_lutpair268" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[5]_i_1 
       (.I0(debug_data_in[5]),
        .I1(probe0[5]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[5]));
(* SOFT_HLUTNM = "soft_lutpair269" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[6]_i_1 
       (.I0(debug_data_in[6]),
        .I1(probe0[6]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[6]));
(* SOFT_HLUTNM = "soft_lutpair269" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[7]_i_1 
       (.I0(debug_data_in[7]),
        .I1(probe0[7]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[7]));
(* SOFT_HLUTNM = "soft_lutpair270" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[8]_i_1 
       (.I0(debug_data_in[8]),
        .I1(probe0[8]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[8]));
(* SOFT_HLUTNM = "soft_lutpair270" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \probeDelay1[9]_i_1 
       (.I0(debug_data_in[9]),
        .I1(probe0[9]),
        .I2(use_probe_debug_circuit),
        .O(probe_data[9]));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][0]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][0]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[0]),
        .Q(\n_0_shifted_data_in_reg[7][0]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][100]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][100]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe7),
        .Q(\n_0_shifted_data_in_reg[7][100]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][101]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][101]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe8),
        .Q(\n_0_shifted_data_in_reg[7][101]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][102]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][102]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[0]),
        .Q(\n_0_shifted_data_in_reg[7][102]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][103]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][103]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[1]),
        .Q(\n_0_shifted_data_in_reg[7][103]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][104]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][104]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[2]),
        .Q(\n_0_shifted_data_in_reg[7][104]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][105]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][105]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[3]),
        .Q(\n_0_shifted_data_in_reg[7][105]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][106]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][106]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[4]),
        .Q(\n_0_shifted_data_in_reg[7][106]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][107]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][107]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[5]),
        .Q(\n_0_shifted_data_in_reg[7][107]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][108]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][108]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[6]),
        .Q(\n_0_shifted_data_in_reg[7][108]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][109]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][109]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[7]),
        .Q(\n_0_shifted_data_in_reg[7][109]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][10]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][10]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[10]),
        .Q(\n_0_shifted_data_in_reg[7][10]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][110]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][110]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[8]),
        .Q(\n_0_shifted_data_in_reg[7][110]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][111]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][111]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[9]),
        .Q(\n_0_shifted_data_in_reg[7][111]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][112]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][112]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[10]),
        .Q(\n_0_shifted_data_in_reg[7][112]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][113]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][113]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[11]),
        .Q(\n_0_shifted_data_in_reg[7][113]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][114]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][114]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[12]),
        .Q(\n_0_shifted_data_in_reg[7][114]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][115]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][115]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[13]),
        .Q(\n_0_shifted_data_in_reg[7][115]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][116]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][116]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[14]),
        .Q(\n_0_shifted_data_in_reg[7][116]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][117]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][117]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[15]),
        .Q(\n_0_shifted_data_in_reg[7][117]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][118]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][118]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[16]),
        .Q(\n_0_shifted_data_in_reg[7][118]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][119]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][119]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[17]),
        .Q(\n_0_shifted_data_in_reg[7][119]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][11]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][11]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[11]),
        .Q(\n_0_shifted_data_in_reg[7][11]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][120]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][120]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[18]),
        .Q(\n_0_shifted_data_in_reg[7][120]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][121]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][121]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[19]),
        .Q(\n_0_shifted_data_in_reg[7][121]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][122]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][122]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[20]),
        .Q(\n_0_shifted_data_in_reg[7][122]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][123]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][123]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[21]),
        .Q(\n_0_shifted_data_in_reg[7][123]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][124]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][124]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[22]),
        .Q(\n_0_shifted_data_in_reg[7][124]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][125]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][125]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[23]),
        .Q(\n_0_shifted_data_in_reg[7][125]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][126]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][126]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[24]),
        .Q(\n_0_shifted_data_in_reg[7][126]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][127]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][127]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[25]),
        .Q(\n_0_shifted_data_in_reg[7][127]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][128]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][128]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[26]),
        .Q(\n_0_shifted_data_in_reg[7][128]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][129]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][129]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[27]),
        .Q(\n_0_shifted_data_in_reg[7][129]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][12]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][12]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[12]),
        .Q(\n_0_shifted_data_in_reg[7][12]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][130]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][130]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[28]),
        .Q(\n_0_shifted_data_in_reg[7][130]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][131]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][131]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[29]),
        .Q(\n_0_shifted_data_in_reg[7][131]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][132]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][132]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[30]),
        .Q(\n_0_shifted_data_in_reg[7][132]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][133]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][133]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe9[31]),
        .Q(\n_0_shifted_data_in_reg[7][133]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][134]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][134]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe10),
        .Q(\n_0_shifted_data_in_reg[7][134]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][135]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][135]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe11),
        .Q(\n_0_shifted_data_in_reg[7][135]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][136]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][136]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe12[0]),
        .Q(\n_0_shifted_data_in_reg[7][136]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][137]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][137]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe12[1]),
        .Q(\n_0_shifted_data_in_reg[7][137]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][138]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][138]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe12[2]),
        .Q(\n_0_shifted_data_in_reg[7][138]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][139]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][139]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe12[3]),
        .Q(\n_0_shifted_data_in_reg[7][139]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][13]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][13]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[13]),
        .Q(\n_0_shifted_data_in_reg[7][13]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][14]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][14]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[14]),
        .Q(\n_0_shifted_data_in_reg[7][14]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][15]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][15]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[15]),
        .Q(\n_0_shifted_data_in_reg[7][15]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][16]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][16]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[16]),
        .Q(\n_0_shifted_data_in_reg[7][16]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][17]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][17]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[17]),
        .Q(\n_0_shifted_data_in_reg[7][17]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][18]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][18]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[18]),
        .Q(\n_0_shifted_data_in_reg[7][18]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][19]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][19]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[19]),
        .Q(\n_0_shifted_data_in_reg[7][19]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][1]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][1]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[1]),
        .Q(\n_0_shifted_data_in_reg[7][1]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][20]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][20]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[20]),
        .Q(\n_0_shifted_data_in_reg[7][20]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][21]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][21]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[21]),
        .Q(\n_0_shifted_data_in_reg[7][21]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][22]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][22]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[22]),
        .Q(\n_0_shifted_data_in_reg[7][22]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][23]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][23]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[23]),
        .Q(\n_0_shifted_data_in_reg[7][23]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][24]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][24]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[24]),
        .Q(\n_0_shifted_data_in_reg[7][24]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][25]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][25]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[25]),
        .Q(\n_0_shifted_data_in_reg[7][25]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][26]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][26]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[26]),
        .Q(\n_0_shifted_data_in_reg[7][26]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][27]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][27]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[27]),
        .Q(\n_0_shifted_data_in_reg[7][27]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][28]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][28]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[28]),
        .Q(\n_0_shifted_data_in_reg[7][28]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][29]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][29]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[29]),
        .Q(\n_0_shifted_data_in_reg[7][29]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][2]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][2]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[2]),
        .Q(\n_0_shifted_data_in_reg[7][2]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][30]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][30]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[30]),
        .Q(\n_0_shifted_data_in_reg[7][30]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][31]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][31]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[31]),
        .Q(\n_0_shifted_data_in_reg[7][31]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][32]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][32]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe1),
        .Q(\n_0_shifted_data_in_reg[7][32]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][33]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][33]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe2),
        .Q(\n_0_shifted_data_in_reg[7][33]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][34]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][34]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[0]),
        .Q(\n_0_shifted_data_in_reg[7][34]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][35]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][35]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[1]),
        .Q(\n_0_shifted_data_in_reg[7][35]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][36]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][36]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[2]),
        .Q(\n_0_shifted_data_in_reg[7][36]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][37]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][37]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[3]),
        .Q(\n_0_shifted_data_in_reg[7][37]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][38]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][38]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[4]),
        .Q(\n_0_shifted_data_in_reg[7][38]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][39]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][39]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[5]),
        .Q(\n_0_shifted_data_in_reg[7][39]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][3]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][3]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[3]),
        .Q(\n_0_shifted_data_in_reg[7][3]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][40]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][40]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[6]),
        .Q(\n_0_shifted_data_in_reg[7][40]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][41]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][41]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[7]),
        .Q(\n_0_shifted_data_in_reg[7][41]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][42]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][42]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[8]),
        .Q(\n_0_shifted_data_in_reg[7][42]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][43]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][43]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[9]),
        .Q(\n_0_shifted_data_in_reg[7][43]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][44]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][44]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[10]),
        .Q(\n_0_shifted_data_in_reg[7][44]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][45]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][45]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[11]),
        .Q(\n_0_shifted_data_in_reg[7][45]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][46]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][46]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[12]),
        .Q(\n_0_shifted_data_in_reg[7][46]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][47]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][47]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[13]),
        .Q(\n_0_shifted_data_in_reg[7][47]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][48]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][48]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[14]),
        .Q(\n_0_shifted_data_in_reg[7][48]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][49]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][49]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[15]),
        .Q(\n_0_shifted_data_in_reg[7][49]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][4]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][4]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[4]),
        .Q(\n_0_shifted_data_in_reg[7][4]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][50]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][50]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[16]),
        .Q(\n_0_shifted_data_in_reg[7][50]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][51]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][51]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[17]),
        .Q(\n_0_shifted_data_in_reg[7][51]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][52]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][52]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[18]),
        .Q(\n_0_shifted_data_in_reg[7][52]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][53]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][53]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[19]),
        .Q(\n_0_shifted_data_in_reg[7][53]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][54]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][54]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[20]),
        .Q(\n_0_shifted_data_in_reg[7][54]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][55]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][55]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[21]),
        .Q(\n_0_shifted_data_in_reg[7][55]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][56]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][56]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[22]),
        .Q(\n_0_shifted_data_in_reg[7][56]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][57]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][57]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[23]),
        .Q(\n_0_shifted_data_in_reg[7][57]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][58]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][58]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[24]),
        .Q(\n_0_shifted_data_in_reg[7][58]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][59]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][59]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[25]),
        .Q(\n_0_shifted_data_in_reg[7][59]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][5]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][5]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[5]),
        .Q(\n_0_shifted_data_in_reg[7][5]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][60]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][60]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[26]),
        .Q(\n_0_shifted_data_in_reg[7][60]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][61]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][61]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[27]),
        .Q(\n_0_shifted_data_in_reg[7][61]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][62]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][62]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[28]),
        .Q(\n_0_shifted_data_in_reg[7][62]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][63]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][63]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[29]),
        .Q(\n_0_shifted_data_in_reg[7][63]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][64]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][64]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[30]),
        .Q(\n_0_shifted_data_in_reg[7][64]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][65]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][65]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe3[31]),
        .Q(\n_0_shifted_data_in_reg[7][65]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][66]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][66]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe4),
        .Q(\n_0_shifted_data_in_reg[7][66]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][67]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][67]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe5),
        .Q(\n_0_shifted_data_in_reg[7][67]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][68]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][68]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[0]),
        .Q(\n_0_shifted_data_in_reg[7][68]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][69]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][69]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[1]),
        .Q(\n_0_shifted_data_in_reg[7][69]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][6]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][6]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[6]),
        .Q(\n_0_shifted_data_in_reg[7][6]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][70]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][70]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[2]),
        .Q(\n_0_shifted_data_in_reg[7][70]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][71]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][71]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[3]),
        .Q(\n_0_shifted_data_in_reg[7][71]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][72]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][72]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[4]),
        .Q(\n_0_shifted_data_in_reg[7][72]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][73]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][73]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[5]),
        .Q(\n_0_shifted_data_in_reg[7][73]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][74]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][74]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[6]),
        .Q(\n_0_shifted_data_in_reg[7][74]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][75]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][75]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[7]),
        .Q(\n_0_shifted_data_in_reg[7][75]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][76]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][76]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[8]),
        .Q(\n_0_shifted_data_in_reg[7][76]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][77]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][77]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[9]),
        .Q(\n_0_shifted_data_in_reg[7][77]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][78]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][78]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[10]),
        .Q(\n_0_shifted_data_in_reg[7][78]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][79]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][79]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[11]),
        .Q(\n_0_shifted_data_in_reg[7][79]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][7]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][7]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[7]),
        .Q(\n_0_shifted_data_in_reg[7][7]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][80]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][80]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[12]),
        .Q(\n_0_shifted_data_in_reg[7][80]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][81]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][81]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[13]),
        .Q(\n_0_shifted_data_in_reg[7][81]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][82]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][82]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[14]),
        .Q(\n_0_shifted_data_in_reg[7][82]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][83]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][83]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[15]),
        .Q(\n_0_shifted_data_in_reg[7][83]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][84]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][84]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[16]),
        .Q(\n_0_shifted_data_in_reg[7][84]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][85]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][85]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[17]),
        .Q(\n_0_shifted_data_in_reg[7][85]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][86]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][86]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[18]),
        .Q(\n_0_shifted_data_in_reg[7][86]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][87]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][87]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[19]),
        .Q(\n_0_shifted_data_in_reg[7][87]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][88]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][88]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[20]),
        .Q(\n_0_shifted_data_in_reg[7][88]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][89]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][89]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[21]),
        .Q(\n_0_shifted_data_in_reg[7][89]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][8]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][8]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[8]),
        .Q(\n_0_shifted_data_in_reg[7][8]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][90]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][90]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[22]),
        .Q(\n_0_shifted_data_in_reg[7][90]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][91]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][91]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[23]),
        .Q(\n_0_shifted_data_in_reg[7][91]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][92]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][92]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[24]),
        .Q(\n_0_shifted_data_in_reg[7][92]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][93]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][93]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[25]),
        .Q(\n_0_shifted_data_in_reg[7][93]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][94]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][94]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[26]),
        .Q(\n_0_shifted_data_in_reg[7][94]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][95]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][95]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[27]),
        .Q(\n_0_shifted_data_in_reg[7][95]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][96]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][96]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[28]),
        .Q(\n_0_shifted_data_in_reg[7][96]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][97]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][97]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[29]),
        .Q(\n_0_shifted_data_in_reg[7][97]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][98]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][98]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[30]),
        .Q(\n_0_shifted_data_in_reg[7][98]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][99]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][99]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe6[31]),
        .Q(\n_0_shifted_data_in_reg[7][99]_srl8 ));
(* srl_bus_name = "U0/\ila_core_inst/shifted_data_in_reg[7] " *) 
   (* srl_name = "U0/\ila_core_inst/shifted_data_in_reg[7][9]_srl8 " *) 
   SRL16E \shifted_data_in_reg[7][9]_srl8 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(clk),
        .D(probe0[9]),
        .Q(\n_0_shifted_data_in_reg[7][9]_srl8 ));
FDRE \shifted_data_in_reg[8][0] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][0]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][0] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][100] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][100]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][100] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][101] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][101]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][101] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][102] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][102]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][102] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][103] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][103]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][103] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][104] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][104]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][104] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][105] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][105]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][105] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][106] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][106]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][106] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][107] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][107]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][107] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][108] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][108]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][108] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][109] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][109]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][109] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][10] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][10]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][10] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][110] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][110]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][110] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][111] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][111]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][111] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][112] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][112]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][112] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][113] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][113]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][113] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][114] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][114]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][114] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][115] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][115]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][115] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][116] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][116]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][116] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][117] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][117]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][117] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][118] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][118]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][118] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][119] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][119]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][119] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][11] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][11]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][11] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][120] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][120]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][120] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][121] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][121]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][121] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][122] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][122]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][122] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][123] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][123]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][123] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][124] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][124]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][124] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][125] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][125]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][125] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][126] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][126]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][126] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][127] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][127]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][127] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][128] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][128]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][128] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][129] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][129]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][129] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][12] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][12]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][12] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][130] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][130]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][130] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][131] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][131]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][131] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][132] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][132]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][132] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][133] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][133]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][133] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][134] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][134]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][134] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][135] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][135]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][135] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][136] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][136]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][136] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][137] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][137]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][137] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][138] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][138]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][138] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][139] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][139]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][139] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][13] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][13]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][13] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][14] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][14]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][14] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][15] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][15]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][15] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][16] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][16]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][16] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][17] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][17]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][17] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][18] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][18]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][18] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][19] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][19]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][19] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][1] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][1]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][1] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][20] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][20]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][20] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][21] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][21]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][21] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][22] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][22]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][22] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][23] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][23]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][23] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][24] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][24]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][24] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][25] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][25]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][25] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][26] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][26]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][26] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][27] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][27]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][27] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][28] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][28]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][28] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][29] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][29]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][29] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][2] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][2]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][2] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][30] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][30]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][30] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][31] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][31]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][31] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][32] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][32]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][32] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][33] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][33]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][33] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][34] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][34]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][34] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][35] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][35]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][35] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][36] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][36]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][36] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][37] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][37]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][37] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][38] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][38]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][38] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][39] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][39]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][39] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][3] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][3]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][3] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][40] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][40]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][40] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][41] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][41]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][41] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][42] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][42]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][42] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][43] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][43]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][43] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][44] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][44]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][44] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][45] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][45]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][45] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][46] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][46]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][46] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][47] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][47]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][47] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][48] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][48]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][48] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][49] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][49]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][49] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][4] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][4]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][4] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][50] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][50]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][50] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][51] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][51]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][51] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][52] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][52]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][52] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][53] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][53]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][53] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][54] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][54]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][54] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][55] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][55]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][55] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][56] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][56]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][56] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][57] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][57]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][57] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][58] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][58]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][58] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][59] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][59]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][59] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][5] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][5]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][5] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][60] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][60]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][60] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][61] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][61]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][61] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][62] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][62]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][62] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][63] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][63]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][63] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][64] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][64]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][64] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][65] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][65]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][65] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][66] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][66]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][66] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][67] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][67]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][67] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][68] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][68]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][68] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][69] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][69]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][69] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][6] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][6]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][6] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][70] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][70]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][70] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][71] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][71]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][71] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][72] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][72]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][72] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][73] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][73]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][73] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][74] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][74]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][74] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][75] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][75]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][75] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][76] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][76]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][76] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][77] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][77]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][77] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][78] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][78]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][78] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][79] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][79]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][79] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][7] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][7]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][7] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][80] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][80]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][80] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][81] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][81]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][81] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][82] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][82]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][82] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][83] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][83]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][83] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][84] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][84]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][84] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][85] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][85]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][85] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][86] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][86]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][86] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][87] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][87]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][87] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][88] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][88]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][88] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][89] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][89]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][89] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][8] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][8]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][8] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][90] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][90]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][90] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][91] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][91]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][91] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][92] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][92]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][92] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][93] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][93]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][93] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][94] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][94]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][94] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][95] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][95]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][95] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][96] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][96]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][96] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][97] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][97]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][97] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][98] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][98]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][98] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][99] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][99]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][99] ),
        .R(1'b0));
FDRE \shifted_data_in_reg[8][9] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_shifted_data_in_reg[7][9]_srl8 ),
        .Q(\n_0_shifted_data_in_reg[8][9] ),
        .R(1'b0));
FDRE \trace_data_ack_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(trace_read_en),
        .Q(\n_0_trace_data_ack_reg[0] ),
        .R(1'b0));
FDRE \trace_data_ack_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_trace_data_ack_reg[0] ),
        .Q(trace_data_ack),
        .R(1'b0));
ila_0_ila_v5_0_ila_cap_ctrl_legacy u_ila_cap_ctrl
       (.A({capture_i,n_30_u_ila_regs}),
        .CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(capture_ctrl_config_en),
        .D(capture_ctrl_config_cs_serial_input),
        .E(n_8_u_ila_reset_ctrl),
        .I1(\n_14_ADV_TRIG.u_adv_trig ),
        .I2(\n_15_ADV_TRIG.u_adv_trig ),
        .O1(n_5_u_ila_cap_ctrl),
        .O2(n_7_u_ila_cap_ctrl),
        .O3(n_9_u_ila_cap_ctrl),
        .O4(n_10_u_ila_cap_ctrl),
        .O5(cap_wr_addr),
        .O6({n_21_u_ila_cap_ctrl,n_22_u_ila_cap_ctrl,n_23_u_ila_cap_ctrl,n_24_u_ila_cap_ctrl,n_25_u_ila_cap_ctrl,n_26_u_ila_cap_ctrl,n_27_u_ila_cap_ctrl,n_28_u_ila_cap_ctrl,n_29_u_ila_cap_ctrl,n_30_u_ila_cap_ctrl}),
        .O_reg(O_reg),
        .Q(reset),
        .SR(scnt_reset),
        .S_DCLK_O(s_dclk),
        .TRIGGERED_SL_I(cap_trigger_out),
        .arm_status(arm_status),
        .basic_trigger(basic_trigger),
        .cap_done(cap_done),
        .cap_state(cap_state),
        .cap_wr_en(cap_wr_en),
        .capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
        .capture_fsm_temp(capture_fsm_temp),
        .clk(clk),
        .en_adv_trigger(en_adv_trigger),
        .trig_out_fsm_temp(trig_out_fsm_temp));
ila_0_ila_v5_0_ila_register u_ila_regs
       (.A({capture_i,n_30_u_ila_regs}),
        .CFG_CNT_DIN(cnt_config_cs_serial_output),
        .CFG_CNT_DOUT(cnt_config_cs_serial_input),
        .CNT_CONFIG_CS_SHIFT_EN_O(cnt_config_cs_shift_en),
        .D(config_fsm_data),
        .E(data_out_en_0),
        .I1(n_0_adv_drdy_i_1),
        .I10(capture_ctrl_config_cs_serial_input),
        .I2(toggle),
        .I3(config_fsm_data_rd_temp),
        .I4(data_word_out),
        .I5({cap_done,cap_trigger_out,halt_status,arm_status}),
        .I6({n_21_u_ila_cap_ctrl,n_22_u_ila_cap_ctrl,n_23_u_ila_cap_ctrl,n_24_u_ila_cap_ctrl,n_25_u_ila_cap_ctrl,n_26_u_ila_cap_ctrl,n_27_u_ila_cap_ctrl,n_28_u_ila_cap_ctrl,n_29_u_ila_cap_ctrl,n_30_u_ila_cap_ctrl}),
        .I7({O_reg,cap_state}),
        .I8({flag3_temp,flag2_temp,flag1_temp,flag0_temp}),
        .I9(sequencer_state_temp),
        .O1(n_23_u_ila_regs),
        .O10(n_42_u_ila_regs),
        .O11(n_43_u_ila_regs),
        .O12(n_44_u_ila_regs),
        .O13(n_45_u_ila_regs),
        .O14(n_46_u_ila_regs),
        .O15(n_79_u_ila_regs),
        .O16(n_80_u_ila_regs),
        .O2(n_25_u_ila_regs),
        .O3(n_26_u_ila_regs),
        .O4(n_33_u_ila_regs),
        .O5(n_34_u_ila_regs),
        .O6(n_38_u_ila_regs),
        .O7(n_39_u_ila_regs),
        .O8(n_40_u_ila_regs),
        .O9(n_41_u_ila_regs),
        .SL_IPORT_I(SL_IPORT_I),
        .SL_OPORT_O(SL_OPORT_O),
        .SR(read_addr_reset),
        .adv_drdy(adv_drdy),
        .arm_ctrl(arm_ctrl),
        .basic_trigger(basic_trigger),
        .bram_en(bram_en),
        .bram_rd_en(bram_rd_en),
        .capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
        .capture_fsm_temp(capture_fsm_temp),
        .capture_strg_qual(capture_strg_qual),
        .debug_data_in(debug_data_in),
        .den(den),
        .en_adv_trigger(en_adv_trigger),
        .halt_ctrl(halt_ctrl),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .read_data_en(read_data_en),
        .s_daddr_o({n_2_u_ila_regs,n_3_u_ila_regs,n_4_u_ila_regs}),
        .s_dclk(s_dclk),
        .shift_en_o(capture_ctrl_config_en),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en),
        .toggle_rd(toggle_rd),
        .trig_out_fsm_temp(trig_out_fsm_temp),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ila_v5_0_ila_reset_ctrl u_ila_reset_ctrl
       (.E(n_8_u_ila_reset_ctrl),
        .I1(cap_done),
        .I5({halt_status,arm_status}),
        .Q({n_2_u_ila_reset_ctrl,p_0_out,reset}),
        .arm_ctrl(arm_ctrl),
        .cap_state(cap_state),
        .clk(clk),
        .halt_ctrl(halt_ctrl),
        .p_2_out(p_2_out),
        .s_dclk(s_dclk));
ila_0_ila_v5_0_ila_trigger u_trig
       (.ADDRA(addra[2:1]),
        .D(probe_data),
        .O1(n_48_u_trig),
        .Q({n_2_u_ila_reset_ctrl,p_0_out,reset}),
        .addra(addra[6:3]),
        .capture_strg_qual(capture_strg_qual),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe0(probe0[31:16]),
        .probe1(probe1),
        .probe10(probe10),
        .probe11(probe11),
        .probe12(probe12),
        .probe2(probe2),
        .probe3(probe3),
        .probe4(probe4),
        .probe5(probe5),
        .probe6(probe6),
        .probe7(probe7),
        .probe8(probe8),
        .probe9(probe9),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_generic_memrd xsdb_memory_read_inst
       (.D(trace_read_en),
        .E(data_out_en_0),
        .I1(n_26_u_ila_regs),
        .I10(n_23_u_ila_regs),
        .I11(n_42_u_ila_regs),
        .I12(n_43_u_ila_regs),
        .I13(n_44_u_ila_regs),
        .I14(n_45_u_ila_regs),
        .I15(n_46_u_ila_regs),
        .I2(n_80_u_ila_regs),
        .I3(n_25_u_ila_regs),
        .I4(data_word_out),
        .I5(mem_data_out),
        .I6(n_38_u_ila_regs),
        .I7(n_39_u_ila_regs),
        .I8(n_40_u_ila_regs),
        .I9(n_41_u_ila_regs),
        .O1(trace_read_addr),
        .Q(trace_data_ack),
        .SR(read_addr_reset),
        .read_data_en(read_data_en),
        .s_dclk(s_dclk));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_counter" *) 
module ila_0_ila_v5_0_ila_counter
   (ADDRA,
    CFG_CNT_DOUT,
    cntcmpsel,
    clk,
    S_DCLK_O,
    Q,
    SR,
    CNT_CTRL,
    CFG_CNT_DIN,
    CNT_CONFIG_CS_SHIFT_EN_O);
  output [0:0]ADDRA;
  output [3:0]CFG_CNT_DOUT;
  input [1:0]cntcmpsel;
  input clk;
  input S_DCLK_O;
  input [1:0]Q;
  input [0:0]SR;
  input [7:0]CNT_CTRL;
  input [3:0]CFG_CNT_DIN;
  input [3:0]CNT_CONFIG_CS_SHIFT_EN_O;

  wire [0:0]ADDRA;
  wire [3:0]CFG_CNT_DIN;
  wire [3:0]CFG_CNT_DOUT;
  wire [3:0]CNT_CONFIG_CS_SHIFT_EN_O;
  wire [7:0]CNT_CTRL;
  wire [1:0]Q;
  wire [0:0]SR;
  wire S_DCLK_O;
  wire clk;
  wire [1:0]cntcmpsel;
  wire [3:0]counter_out_temp;

(* CNT_MAX = "17'b10000000000000000" *) 
   (* C_COUNTER_WIDTH = "17" *) 
   (* DONT_TOUCH *) 
   ila_0_ila_v5_0_generic_counter__4 \G_COUNTER[0].U_COUNTER 
       (.CFG_CLK(S_DCLK_O),
        .CLK(clk),
        .CNT_CTRL(CNT_CTRL[1:0]),
        .CNT_LOAD_DOUT(CFG_CNT_DOUT[0]),
        .CNT_LOAD_EN(CNT_CONFIG_CS_SHIFT_EN_O[0]),
        .CNT_LOAD_IN(CFG_CNT_DIN[0]),
        .COUNTER_MATCH(counter_out_temp[0]),
        .RESET(Q),
        .SCNT_RESET(SR));
(* CNT_MAX = "17'b10000000000000000" *) 
   (* C_COUNTER_WIDTH = "17" *) 
   (* DONT_TOUCH *) 
   ila_0_ila_v5_0_generic_counter__5 \G_COUNTER[1].U_COUNTER 
       (.CFG_CLK(S_DCLK_O),
        .CLK(clk),
        .CNT_CTRL(CNT_CTRL[3:2]),
        .CNT_LOAD_DOUT(CFG_CNT_DOUT[1]),
        .CNT_LOAD_EN(CNT_CONFIG_CS_SHIFT_EN_O[1]),
        .CNT_LOAD_IN(CFG_CNT_DIN[1]),
        .COUNTER_MATCH(counter_out_temp[1]),
        .RESET(Q),
        .SCNT_RESET(SR));
(* CNT_MAX = "17'b10000000000000000" *) 
   (* C_COUNTER_WIDTH = "17" *) 
   (* DONT_TOUCH *) 
   ila_0_ila_v5_0_generic_counter__6 \G_COUNTER[2].U_COUNTER 
       (.CFG_CLK(S_DCLK_O),
        .CLK(clk),
        .CNT_CTRL(CNT_CTRL[5:4]),
        .CNT_LOAD_DOUT(CFG_CNT_DOUT[2]),
        .CNT_LOAD_EN(CNT_CONFIG_CS_SHIFT_EN_O[2]),
        .CNT_LOAD_IN(CFG_CNT_DIN[2]),
        .COUNTER_MATCH(counter_out_temp[2]),
        .RESET(Q),
        .SCNT_RESET(SR));
(* CNT_MAX = "17'b10000000000000000" *) 
   (* C_COUNTER_WIDTH = "17" *) 
   (* DONT_TOUCH *) 
   ila_0_ila_v5_0_generic_counter \G_COUNTER[3].U_COUNTER 
       (.CFG_CLK(S_DCLK_O),
        .CLK(clk),
        .CNT_CTRL(CNT_CTRL[7:6]),
        .CNT_LOAD_DOUT(CFG_CNT_DOUT[3]),
        .CNT_LOAD_EN(CNT_CONFIG_CS_SHIFT_EN_O[3]),
        .CNT_LOAD_IN(CFG_CNT_DIN[3]),
        .COUNTER_MATCH(counter_out_temp[3]),
        .RESET(Q),
        .SCNT_RESET(SR));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_4
       (.I0(counter_out_temp[3]),
        .I1(counter_out_temp[1]),
        .I2(cntcmpsel[0]),
        .I3(counter_out_temp[2]),
        .I4(cntcmpsel[1]),
        .I5(counter_out_temp[0]),
        .O(ADDRA));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_fsm_memory_read" *) 
module ila_0_ila_v5_0_ila_fsm_memory_read
   (toggle_rd,
    E,
    CFG_BRAM_DATA,
    FSM_BRAM_CONFIG_DATA_I,
    I1,
    S_DCLK_O,
    I2,
    D,
    O3);
  output toggle_rd;
  output [0:0]E;
  output [23:0]CFG_BRAM_DATA;
  output [15:0]FSM_BRAM_CONFIG_DATA_I;
  input I1;
  input S_DCLK_O;
  input I2;
  input [15:0]D;
  input [23:0]O3;

  wire [23:0]CFG_BRAM_DATA;
  wire [15:0]D;
  wire [0:0]E;
  wire [15:0]FSM_BRAM_CONFIG_DATA_I;
  wire I1;
  wire I2;
  wire [23:0]O3;
  wire S_DCLK_O;
  wire \n_0_BRAM_DATA[15]_i_1 ;
  wire \n_0_CFG_DATA_O[0]_i_1 ;
  wire \n_0_CFG_DATA_O[15]_i_1 ;
  wire \n_0_CFG_DATA_O[1]_i_1 ;
  wire \n_0_CFG_DATA_O[2]_i_1 ;
  wire \n_0_CFG_DATA_O[3]_i_1 ;
  wire \n_0_CFG_DATA_O[4]_i_1 ;
  wire \n_0_CFG_DATA_O[5]_i_1 ;
  wire \n_0_CFG_DATA_O[6]_i_1 ;
  wire \n_0_CFG_DATA_O[7]_i_1 ;
  wire toggle_rd;

LUT1 #(
    .INIT(2'h1)) 
     \BRAM_DATA[15]_i_1 
       (.I0(E),
        .O(\n_0_BRAM_DATA[15]_i_1 ));
FDRE \BRAM_DATA_reg[0] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[0]),
        .Q(CFG_BRAM_DATA[0]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[10] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[10]),
        .Q(CFG_BRAM_DATA[10]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[11] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[11]),
        .Q(CFG_BRAM_DATA[11]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[12] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[12]),
        .Q(CFG_BRAM_DATA[12]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[13] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[13]),
        .Q(CFG_BRAM_DATA[13]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[14] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[14]),
        .Q(CFG_BRAM_DATA[14]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[15] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[15]),
        .Q(CFG_BRAM_DATA[15]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[16] 
       (.C(S_DCLK_O),
        .CE(E),
        .D(D[0]),
        .Q(CFG_BRAM_DATA[16]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[17] 
       (.C(S_DCLK_O),
        .CE(E),
        .D(D[1]),
        .Q(CFG_BRAM_DATA[17]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[18] 
       (.C(S_DCLK_O),
        .CE(E),
        .D(D[2]),
        .Q(CFG_BRAM_DATA[18]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[19] 
       (.C(S_DCLK_O),
        .CE(E),
        .D(D[3]),
        .Q(CFG_BRAM_DATA[19]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[1] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[1]),
        .Q(CFG_BRAM_DATA[1]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[20] 
       (.C(S_DCLK_O),
        .CE(E),
        .D(D[4]),
        .Q(CFG_BRAM_DATA[20]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[21] 
       (.C(S_DCLK_O),
        .CE(E),
        .D(D[5]),
        .Q(CFG_BRAM_DATA[21]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[22] 
       (.C(S_DCLK_O),
        .CE(E),
        .D(D[6]),
        .Q(CFG_BRAM_DATA[22]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[23] 
       (.C(S_DCLK_O),
        .CE(E),
        .D(D[7]),
        .Q(CFG_BRAM_DATA[23]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[2] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[2]),
        .Q(CFG_BRAM_DATA[2]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[3] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[3]),
        .Q(CFG_BRAM_DATA[3]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[4] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[4]),
        .Q(CFG_BRAM_DATA[4]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[5] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[5]),
        .Q(CFG_BRAM_DATA[5]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[6] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[6]),
        .Q(CFG_BRAM_DATA[6]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[7] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[7]),
        .Q(CFG_BRAM_DATA[7]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[8] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[8]),
        .Q(CFG_BRAM_DATA[8]),
        .R(1'b0));
FDRE \BRAM_DATA_reg[9] 
       (.C(S_DCLK_O),
        .CE(\n_0_BRAM_DATA[15]_i_1 ),
        .D(D[9]),
        .Q(CFG_BRAM_DATA[9]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair21" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \CFG_DATA_O[0]_i_1 
       (.I0(O3[0]),
        .I1(O3[16]),
        .I2(toggle_rd),
        .O(\n_0_CFG_DATA_O[0]_i_1 ));
LUT1 #(
    .INIT(2'h1)) 
     \CFG_DATA_O[15]_i_1 
       (.I0(toggle_rd),
        .O(\n_0_CFG_DATA_O[15]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair21" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \CFG_DATA_O[1]_i_1 
       (.I0(O3[1]),
        .I1(O3[17]),
        .I2(toggle_rd),
        .O(\n_0_CFG_DATA_O[1]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair22" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \CFG_DATA_O[2]_i_1 
       (.I0(O3[2]),
        .I1(O3[18]),
        .I2(toggle_rd),
        .O(\n_0_CFG_DATA_O[2]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair22" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \CFG_DATA_O[3]_i_1 
       (.I0(O3[3]),
        .I1(O3[19]),
        .I2(toggle_rd),
        .O(\n_0_CFG_DATA_O[3]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair23" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \CFG_DATA_O[4]_i_1 
       (.I0(O3[4]),
        .I1(O3[20]),
        .I2(toggle_rd),
        .O(\n_0_CFG_DATA_O[4]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair23" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \CFG_DATA_O[5]_i_1 
       (.I0(O3[5]),
        .I1(O3[21]),
        .I2(toggle_rd),
        .O(\n_0_CFG_DATA_O[5]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair24" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \CFG_DATA_O[6]_i_1 
       (.I0(O3[6]),
        .I1(O3[22]),
        .I2(toggle_rd),
        .O(\n_0_CFG_DATA_O[6]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair24" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \CFG_DATA_O[7]_i_1 
       (.I0(O3[7]),
        .I1(O3[23]),
        .I2(toggle_rd),
        .O(\n_0_CFG_DATA_O[7]_i_1 ));
FDRE \CFG_DATA_O_reg[0] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(\n_0_CFG_DATA_O[0]_i_1 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[0]),
        .R(1'b0));
FDRE \CFG_DATA_O_reg[10] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(O3[10]),
        .Q(FSM_BRAM_CONFIG_DATA_I[10]),
        .R(\n_0_CFG_DATA_O[15]_i_1 ));
FDRE \CFG_DATA_O_reg[11] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(O3[11]),
        .Q(FSM_BRAM_CONFIG_DATA_I[11]),
        .R(\n_0_CFG_DATA_O[15]_i_1 ));
FDRE \CFG_DATA_O_reg[12] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(O3[12]),
        .Q(FSM_BRAM_CONFIG_DATA_I[12]),
        .R(\n_0_CFG_DATA_O[15]_i_1 ));
FDRE \CFG_DATA_O_reg[13] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(O3[13]),
        .Q(FSM_BRAM_CONFIG_DATA_I[13]),
        .R(\n_0_CFG_DATA_O[15]_i_1 ));
FDRE \CFG_DATA_O_reg[14] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(O3[14]),
        .Q(FSM_BRAM_CONFIG_DATA_I[14]),
        .R(\n_0_CFG_DATA_O[15]_i_1 ));
FDRE \CFG_DATA_O_reg[15] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(O3[15]),
        .Q(FSM_BRAM_CONFIG_DATA_I[15]),
        .R(\n_0_CFG_DATA_O[15]_i_1 ));
FDRE \CFG_DATA_O_reg[1] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(\n_0_CFG_DATA_O[1]_i_1 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[1]),
        .R(1'b0));
FDRE \CFG_DATA_O_reg[2] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(\n_0_CFG_DATA_O[2]_i_1 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[2]),
        .R(1'b0));
FDRE \CFG_DATA_O_reg[3] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(\n_0_CFG_DATA_O[3]_i_1 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[3]),
        .R(1'b0));
FDRE \CFG_DATA_O_reg[4] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(\n_0_CFG_DATA_O[4]_i_1 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[4]),
        .R(1'b0));
FDRE \CFG_DATA_O_reg[5] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(\n_0_CFG_DATA_O[5]_i_1 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[5]),
        .R(1'b0));
FDRE \CFG_DATA_O_reg[6] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(\n_0_CFG_DATA_O[6]_i_1 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[6]),
        .R(1'b0));
FDRE \CFG_DATA_O_reg[7] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(\n_0_CFG_DATA_O[7]_i_1 ),
        .Q(FSM_BRAM_CONFIG_DATA_I[7]),
        .R(1'b0));
FDRE \CFG_DATA_O_reg[8] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(O3[8]),
        .Q(FSM_BRAM_CONFIG_DATA_I[8]),
        .R(\n_0_CFG_DATA_O[15]_i_1 ));
FDRE \CFG_DATA_O_reg[9] 
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(O3[9]),
        .Q(FSM_BRAM_CONFIG_DATA_I[9]),
        .R(\n_0_CFG_DATA_O[15]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     toggle_rd_reg
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(I1),
        .Q(toggle_rd),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     toggle_reg
       (.C(S_DCLK_O),
        .CE(1'b1),
        .D(I2),
        .Q(E),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_register" *) 
module ila_0_ila_v5_0_ila_register
   (s_dclk,
    den,
    s_daddr_o,
    SL_OPORT_O,
    adv_drdy,
    O1,
    read_data_en,
    O2,
    O3,
    use_probe_debug_circuit,
    en_adv_trigger,
    A,
    bram_en,
    bram_rd_en,
    O4,
    O5,
    halt_ctrl,
    arm_ctrl,
    SR,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    D,
    debug_data_in,
    O15,
    O16,
    shift_en_o,
    capture_ctrl_config_serial_output,
    mu_config_cs_shift_en,
    mu_config_cs_serial_output,
    tc_config_cs_shift_en,
    tc_config_cs_serial_output,
    CNT_CONFIG_CS_SHIFT_EN_O,
    CFG_CNT_DIN,
    SL_IPORT_I,
    E,
    I1,
    basic_trigger,
    trig_out_fsm_temp,
    capture_strg_qual,
    capture_fsm_temp,
    I2,
    toggle_rd,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    mu_config_cs_serial_input,
    tc_config_cs_serial_input,
    CFG_CNT_DOUT);
  output s_dclk;
  output den;
  output [2:0]s_daddr_o;
  output [16:0]SL_OPORT_O;
  output adv_drdy;
  output O1;
  output read_data_en;
  output O2;
  output O3;
  output use_probe_debug_circuit;
  output en_adv_trigger;
  output [1:0]A;
  output bram_en;
  output bram_rd_en;
  output O4;
  output O5;
  output halt_ctrl;
  output arm_ctrl;
  output [0:0]SR;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output [15:0]D;
  output [15:0]debug_data_in;
  output O15;
  output O16;
  output shift_en_o;
  output capture_ctrl_config_serial_output;
  output [12:0]mu_config_cs_shift_en;
  output [12:0]mu_config_cs_serial_output;
  output [31:0]tc_config_cs_shift_en;
  output [31:0]tc_config_cs_serial_output;
  output [3:0]CNT_CONFIG_CS_SHIFT_EN_O;
  output [3:0]CFG_CNT_DIN;
  input [36:0]SL_IPORT_I;
  input [0:0]E;
  input I1;
  input basic_trigger;
  input trig_out_fsm_temp;
  input capture_strg_qual;
  input capture_fsm_temp;
  input [0:0]I2;
  input toggle_rd;
  input [15:0]I3;
  input [15:0]I4;
  input [3:0]I5;
  input [9:0]I6;
  input [1:0]I7;
  input [3:0]I8;
  input [15:0]I9;
  input [0:0]I10;
  input [12:0]mu_config_cs_serial_input;
  input [31:0]tc_config_cs_serial_input;
  input [3:0]CFG_CNT_DOUT;

  wire [1:0]A;
  wire [3:0]CFG_CNT_DIN;
  wire [3:0]CFG_CNT_DOUT;
  wire [3:0]CNT_CONFIG_CS_SHIFT_EN_O;
  wire [15:0]D;
  wire [0:0]E;
  wire I1;
  wire [0:0]I10;
  wire [0:0]I2;
  wire [15:0]I3;
  wire [15:0]I4;
  wire [3:0]I5;
  wire [9:0]I6;
  wire [1:0]I7;
  wire [3:0]I8;
  wire [15:0]I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [36:0]SL_IPORT_I;
  wire [16:0]SL_OPORT_O;
  wire [0:0]SR;
  wire adv_drdy;
  wire adv_rb_drdy;
  wire adv_rb_drdy1;
  wire adv_rb_drdy4;
  wire arm_ctrl;
  wire basic_trigger;
  wire bram_en;
  wire bram_rd_en;
  wire capture_ctrl_config_serial_output;
  wire capture_fsm_temp;
  wire capture_strg_qual;
  wire [16:0]config_fsm_addr;
  wire config_fsm_en_rb;
  wire config_fsm_we;
  wire [15:0]debug_data_in;
  wire den;
  wire [5:0]drdyCount;
  wire drdy_mux_ff;
  wire drdy_mux_ff1;
  wire drdy_mux_temp;
  wire dwe;
  wire en_adv_trigger;
  wire halt_ctrl;
  wire [12:0]mu_config_cs_serial_input;
  wire [12:0]mu_config_cs_serial_output;
  wire [12:0]mu_config_cs_shift_en;
  wire \n_0_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_0_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire n_0_FSM_BRAM_EN_RB_O_i_2;
  wire \n_0_MU_SRL[11].mu_srl_reg ;
  wire \n_0_MU_SRL[12].mu_srl_reg ;
  wire \n_0_MU_SRL[3].mu_srl_reg ;
  wire \n_0_MU_SRL[7].mu_srl_reg ;
  wire \n_0_MU_STATUS[11].mu_tpid_reg ;
  wire \n_0_MU_STATUS[12].mu_tpid_reg ;
  wire \n_0_MU_STATUS[1].mu_width_reg ;
  wire \n_0_MU_STATUS[2].mu_tpid_reg ;
  wire \n_0_MU_STATUS[3].mu_tpid_reg ;
  wire \n_0_MU_STATUS[5].mu_tpid_reg ;
  wire \n_0_MU_STATUS[6].mu_tpid_reg ;
  wire \n_0_MU_STATUS[7].mu_tpid_reg ;
  wire \n_0_MU_STATUS[8].mu_tpid_reg ;
  wire \n_0_MU_STATUS[9].mu_tpid_reg ;
  wire \n_0_TC_SRL[11].tc_srl_reg ;
  wire \n_0_TC_SRL[15].tc_srl_reg ;
  wire \n_0_TC_SRL[19].tc_srl_reg ;
  wire \n_0_TC_SRL[23].tc_srl_reg ;
  wire \n_0_TC_SRL[27].tc_srl_reg ;
  wire \n_0_TC_SRL[31].tc_srl_reg ;
  wire \n_0_TC_SRL[3].tc_srl_reg ;
  wire \n_0_TC_SRL[7].tc_srl_reg ;
  wire n_0_adv_rb_drdy3_reg_srl2;
  wire n_0_bram_en_i_2;
  wire n_0_bram_rd_en_i_2;
  wire n_0_bram_rd_en_i_3;
  wire n_0_bram_rd_en_i_4;
  wire \n_0_drdyCount[0]_i_1 ;
  wire \n_0_drdyCount[0]_i_2 ;
  wire \n_0_drdyCount[1]_i_1 ;
  wire \n_0_drdyCount[2]_i_1 ;
  wire \n_0_drdyCount[3]_i_1 ;
  wire \n_0_drdyCount[3]_i_2 ;
  wire \n_0_drdyCount[4]_i_1 ;
  wire \n_0_drdyCount[4]_i_2 ;
  wire \n_0_drdyCount[4]_i_3 ;
  wire \n_0_drdyCount[4]_i_4 ;
  wire \n_0_drdyCount[5]_i_1 ;
  wire \n_0_drdyCount[5]_i_2 ;
  wire \n_0_drdyCount[5]_i_3 ;
  wire \n_0_drdyCount[5]_i_4 ;
  wire \n_0_regAck_reg[1] ;
  wire n_0_regDrdy_i_1;
  wire n_0_regDrdy_i_2;
  wire n_0_regDrdy_reg;
  wire n_0_reg_0;
  wire n_0_reg_1;
  wire n_0_reg_10;
  wire n_0_reg_11;
  wire n_0_reg_12;
  wire n_0_reg_13;
  wire n_0_reg_14;
  wire n_0_reg_15;
  wire n_0_reg_16;
  wire n_0_reg_17;
  wire n_0_reg_18;
  wire n_0_reg_19;
  wire n_0_reg_1a;
  wire n_0_reg_2;
  wire n_0_reg_3;
  wire n_0_reg_4;
  wire n_0_reg_6;
  wire n_0_reg_7;
  wire n_0_reg_8;
  wire n_0_reg_82;
  wire n_0_reg_83;
  wire n_0_reg_85;
  wire n_0_reg_887;
  wire n_0_reg_88d;
  wire n_0_reg_88f;
  wire n_0_reg_892;
  wire n_0_reg_9;
  wire n_0_reg_a;
  wire n_0_reg_b;
  wire n_0_reg_c;
  wire n_0_reg_d;
  wire n_0_reg_e;
  wire n_0_reg_f;
  wire n_0_reg_srl_fff;
  wire n_0_reg_stream_ffe;
  wire \n_0_slaveRegDo_mux[0]_i_2 ;
  wire \n_0_slaveRegDo_mux[0]_i_3 ;
  wire \n_0_slaveRegDo_mux[10]_i_2 ;
  wire \n_0_slaveRegDo_mux[10]_i_3 ;
  wire \n_0_slaveRegDo_mux[11]_i_2 ;
  wire \n_0_slaveRegDo_mux[11]_i_3 ;
  wire \n_0_slaveRegDo_mux[12]_i_2 ;
  wire \n_0_slaveRegDo_mux[12]_i_3 ;
  wire \n_0_slaveRegDo_mux[13]_i_2 ;
  wire \n_0_slaveRegDo_mux[13]_i_3 ;
  wire \n_0_slaveRegDo_mux[14]_i_2 ;
  wire \n_0_slaveRegDo_mux[14]_i_3 ;
  wire \n_0_slaveRegDo_mux[15]_i_2 ;
  wire \n_0_slaveRegDo_mux[15]_i_3 ;
  wire \n_0_slaveRegDo_mux[1]_i_2 ;
  wire \n_0_slaveRegDo_mux[1]_i_3 ;
  wire \n_0_slaveRegDo_mux[2]_i_2 ;
  wire \n_0_slaveRegDo_mux[2]_i_3 ;
  wire \n_0_slaveRegDo_mux[3]_i_2 ;
  wire \n_0_slaveRegDo_mux[3]_i_3 ;
  wire \n_0_slaveRegDo_mux[4]_i_2 ;
  wire \n_0_slaveRegDo_mux[4]_i_3 ;
  wire \n_0_slaveRegDo_mux[5]_i_2 ;
  wire \n_0_slaveRegDo_mux[5]_i_3 ;
  wire \n_0_slaveRegDo_mux[6]_i_2 ;
  wire \n_0_slaveRegDo_mux[6]_i_3 ;
  wire \n_0_slaveRegDo_mux[7]_i_2 ;
  wire \n_0_slaveRegDo_mux[7]_i_3 ;
  wire \n_0_slaveRegDo_mux[8]_i_2 ;
  wire \n_0_slaveRegDo_mux[8]_i_3 ;
  wire \n_0_slaveRegDo_mux[9]_i_2 ;
  wire \n_0_slaveRegDo_mux[9]_i_3 ;
  wire \n_0_slaveRegDo_mux_0[11]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[12]_i_14 ;
  wire \n_0_slaveRegDo_mux_0[12]_i_4 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_15 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_20 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_22 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_6 ;
  wire \n_0_slaveRegDo_mux_0[3]_i_4 ;
  wire \n_0_slaveRegDo_mux_0_reg[0] ;
  wire \n_0_slaveRegDo_mux_0_reg[10] ;
  wire \n_0_slaveRegDo_mux_0_reg[11] ;
  wire \n_0_slaveRegDo_mux_0_reg[12] ;
  wire \n_0_slaveRegDo_mux_0_reg[13] ;
  wire \n_0_slaveRegDo_mux_0_reg[14] ;
  wire \n_0_slaveRegDo_mux_0_reg[15] ;
  wire \n_0_slaveRegDo_mux_0_reg[1] ;
  wire \n_0_slaveRegDo_mux_0_reg[2] ;
  wire \n_0_slaveRegDo_mux_0_reg[3] ;
  wire \n_0_slaveRegDo_mux_0_reg[4] ;
  wire \n_0_slaveRegDo_mux_0_reg[5] ;
  wire \n_0_slaveRegDo_mux_0_reg[6] ;
  wire \n_0_slaveRegDo_mux_0_reg[7] ;
  wire \n_0_slaveRegDo_mux_0_reg[8] ;
  wire \n_0_slaveRegDo_mux_0_reg[9] ;
  wire \n_0_slaveRegDo_mux_1[15]_i_10 ;
  wire \n_0_slaveRegDo_mux_1[15]_i_5 ;
  wire \n_0_slaveRegDo_mux_2[15]_i_2 ;
  wire \n_0_slaveRegDo_mux_2_reg[0] ;
  wire \n_0_slaveRegDo_mux_2_reg[10] ;
  wire \n_0_slaveRegDo_mux_2_reg[11] ;
  wire \n_0_slaveRegDo_mux_2_reg[12] ;
  wire \n_0_slaveRegDo_mux_2_reg[13] ;
  wire \n_0_slaveRegDo_mux_2_reg[14] ;
  wire \n_0_slaveRegDo_mux_2_reg[15] ;
  wire \n_0_slaveRegDo_mux_2_reg[1] ;
  wire \n_0_slaveRegDo_mux_2_reg[2] ;
  wire \n_0_slaveRegDo_mux_2_reg[3] ;
  wire \n_0_slaveRegDo_mux_2_reg[4] ;
  wire \n_0_slaveRegDo_mux_2_reg[5] ;
  wire \n_0_slaveRegDo_mux_2_reg[6] ;
  wire \n_0_slaveRegDo_mux_2_reg[7] ;
  wire \n_0_slaveRegDo_mux_2_reg[8] ;
  wire \n_0_slaveRegDo_mux_2_reg[9] ;
  wire \n_0_slaveRegDo_mux_3[15]_i_1 ;
  wire \n_0_slaveRegDo_mux_3[15]_i_3 ;
  wire \n_0_slaveRegDo_mux_3_reg[0] ;
  wire \n_0_slaveRegDo_mux_3_reg[10] ;
  wire \n_0_slaveRegDo_mux_3_reg[11] ;
  wire \n_0_slaveRegDo_mux_3_reg[12] ;
  wire \n_0_slaveRegDo_mux_3_reg[13] ;
  wire \n_0_slaveRegDo_mux_3_reg[14] ;
  wire \n_0_slaveRegDo_mux_3_reg[15] ;
  wire \n_0_slaveRegDo_mux_3_reg[1] ;
  wire \n_0_slaveRegDo_mux_3_reg[2] ;
  wire \n_0_slaveRegDo_mux_3_reg[3] ;
  wire \n_0_slaveRegDo_mux_3_reg[4] ;
  wire \n_0_slaveRegDo_mux_3_reg[5] ;
  wire \n_0_slaveRegDo_mux_3_reg[6] ;
  wire \n_0_slaveRegDo_mux_3_reg[7] ;
  wire \n_0_slaveRegDo_mux_3_reg[8] ;
  wire \n_0_slaveRegDo_mux_3_reg[9] ;
  wire \n_0_slaveRegDo_mux_6[15]_i_1 ;
  wire \n_0_slaveRegDo_mux_6[15]_i_3 ;
  wire \n_0_slaveRegDo_mux_6[15]_i_4 ;
  wire \n_0_slaveRegDo_mux_reg[0] ;
  wire \n_0_slaveRegDo_mux_reg[10] ;
  wire \n_0_slaveRegDo_mux_reg[11] ;
  wire \n_0_slaveRegDo_mux_reg[12] ;
  wire \n_0_slaveRegDo_mux_reg[13] ;
  wire \n_0_slaveRegDo_mux_reg[14] ;
  wire \n_0_slaveRegDo_mux_reg[15] ;
  wire \n_0_slaveRegDo_mux_reg[1] ;
  wire \n_0_slaveRegDo_mux_reg[2] ;
  wire \n_0_slaveRegDo_mux_reg[3] ;
  wire \n_0_slaveRegDo_mux_reg[4] ;
  wire \n_0_slaveRegDo_mux_reg[5] ;
  wire \n_0_slaveRegDo_mux_reg[6] ;
  wire \n_0_slaveRegDo_mux_reg[7] ;
  wire \n_0_slaveRegDo_mux_reg[8] ;
  wire \n_0_slaveRegDo_mux_reg[9] ;
  wire \n_10_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_10_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_10_MU_SRL[11].mu_srl_reg ;
  wire \n_10_MU_SRL[12].mu_srl_reg ;
  wire \n_10_MU_SRL[3].mu_srl_reg ;
  wire \n_10_MU_SRL[7].mu_srl_reg ;
  wire \n_10_MU_STATUS[10].mu_tpid_reg ;
  wire \n_10_MU_STATUS[11].mu_tpid_reg ;
  wire \n_10_MU_STATUS[12].mu_tpid_reg ;
  wire \n_10_MU_STATUS[1].mu_width_reg ;
  wire \n_10_MU_STATUS[2].mu_tpid_reg ;
  wire \n_10_MU_STATUS[3].mu_tpid_reg ;
  wire \n_10_MU_STATUS[5].mu_tpid_reg ;
  wire \n_10_MU_STATUS[6].mu_tpid_reg ;
  wire \n_10_MU_STATUS[7].mu_tpid_reg ;
  wire \n_10_MU_STATUS[8].mu_tpid_reg ;
  wire \n_10_MU_STATUS[9].mu_tpid_reg ;
  wire \n_10_TC_SRL[11].tc_srl_reg ;
  wire \n_10_TC_SRL[15].tc_srl_reg ;
  wire \n_10_TC_SRL[19].tc_srl_reg ;
  wire \n_10_TC_SRL[23].tc_srl_reg ;
  wire \n_10_TC_SRL[27].tc_srl_reg ;
  wire \n_10_TC_SRL[31].tc_srl_reg ;
  wire \n_10_TC_SRL[3].tc_srl_reg ;
  wire \n_10_TC_SRL[7].tc_srl_reg ;
  wire n_10_U_XSDB_SLAVE;
  wire n_10_reg_0;
  wire n_10_reg_1;
  wire n_10_reg_10;
  wire n_10_reg_11;
  wire n_10_reg_12;
  wire n_10_reg_13;
  wire n_10_reg_14;
  wire n_10_reg_15;
  wire n_10_reg_17;
  wire n_10_reg_19;
  wire n_10_reg_1a;
  wire n_10_reg_2;
  wire n_10_reg_3;
  wire n_10_reg_4;
  wire n_10_reg_7;
  wire n_10_reg_83;
  wire n_10_reg_85;
  wire n_10_reg_887;
  wire n_10_reg_88d;
  wire n_10_reg_88f;
  wire n_10_reg_9;
  wire n_10_reg_a;
  wire n_10_reg_b;
  wire n_10_reg_c;
  wire n_10_reg_d;
  wire n_10_reg_e;
  wire n_10_reg_f;
  wire n_10_reg_srl_fff;
  wire n_10_reg_stream_ffe;
  wire \n_11_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_11_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_11_MU_SRL[11].mu_srl_reg ;
  wire \n_11_MU_SRL[12].mu_srl_reg ;
  wire \n_11_MU_SRL[3].mu_srl_reg ;
  wire \n_11_MU_SRL[7].mu_srl_reg ;
  wire \n_11_MU_STATUS[10].mu_tpid_reg ;
  wire \n_11_MU_STATUS[11].mu_tpid_reg ;
  wire \n_11_MU_STATUS[12].mu_tpid_reg ;
  wire \n_11_MU_STATUS[1].mu_width_reg ;
  wire \n_11_MU_STATUS[2].mu_tpid_reg ;
  wire \n_11_MU_STATUS[3].mu_tpid_reg ;
  wire \n_11_MU_STATUS[5].mu_tpid_reg ;
  wire \n_11_MU_STATUS[6].mu_tpid_reg ;
  wire \n_11_MU_STATUS[7].mu_tpid_reg ;
  wire \n_11_MU_STATUS[8].mu_tpid_reg ;
  wire \n_11_MU_STATUS[9].mu_tpid_reg ;
  wire \n_11_TC_SRL[11].tc_srl_reg ;
  wire \n_11_TC_SRL[15].tc_srl_reg ;
  wire \n_11_TC_SRL[19].tc_srl_reg ;
  wire \n_11_TC_SRL[23].tc_srl_reg ;
  wire \n_11_TC_SRL[27].tc_srl_reg ;
  wire \n_11_TC_SRL[31].tc_srl_reg ;
  wire \n_11_TC_SRL[3].tc_srl_reg ;
  wire \n_11_TC_SRL[7].tc_srl_reg ;
  wire n_11_U_XSDB_SLAVE;
  wire n_11_reg_0;
  wire n_11_reg_1;
  wire n_11_reg_10;
  wire n_11_reg_11;
  wire n_11_reg_12;
  wire n_11_reg_13;
  wire n_11_reg_14;
  wire n_11_reg_15;
  wire n_11_reg_17;
  wire n_11_reg_19;
  wire n_11_reg_1a;
  wire n_11_reg_2;
  wire n_11_reg_3;
  wire n_11_reg_4;
  wire n_11_reg_7;
  wire n_11_reg_83;
  wire n_11_reg_85;
  wire n_11_reg_887;
  wire n_11_reg_88d;
  wire n_11_reg_88f;
  wire n_11_reg_9;
  wire n_11_reg_a;
  wire n_11_reg_b;
  wire n_11_reg_c;
  wire n_11_reg_d;
  wire n_11_reg_e;
  wire n_11_reg_f;
  wire n_11_reg_srl_fff;
  wire n_11_reg_stream_ffe;
  wire \n_12_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_12_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_12_MU_SRL[11].mu_srl_reg ;
  wire \n_12_MU_SRL[12].mu_srl_reg ;
  wire \n_12_MU_SRL[3].mu_srl_reg ;
  wire \n_12_MU_SRL[7].mu_srl_reg ;
  wire \n_12_MU_STATUS[10].mu_tpid_reg ;
  wire \n_12_MU_STATUS[11].mu_tpid_reg ;
  wire \n_12_MU_STATUS[12].mu_tpid_reg ;
  wire \n_12_MU_STATUS[1].mu_width_reg ;
  wire \n_12_MU_STATUS[2].mu_tpid_reg ;
  wire \n_12_MU_STATUS[3].mu_tpid_reg ;
  wire \n_12_MU_STATUS[5].mu_tpid_reg ;
  wire \n_12_MU_STATUS[6].mu_tpid_reg ;
  wire \n_12_MU_STATUS[7].mu_tpid_reg ;
  wire \n_12_MU_STATUS[8].mu_tpid_reg ;
  wire \n_12_MU_STATUS[9].mu_tpid_reg ;
  wire \n_12_TC_SRL[11].tc_srl_reg ;
  wire \n_12_TC_SRL[15].tc_srl_reg ;
  wire \n_12_TC_SRL[19].tc_srl_reg ;
  wire \n_12_TC_SRL[23].tc_srl_reg ;
  wire \n_12_TC_SRL[27].tc_srl_reg ;
  wire \n_12_TC_SRL[31].tc_srl_reg ;
  wire \n_12_TC_SRL[3].tc_srl_reg ;
  wire \n_12_TC_SRL[7].tc_srl_reg ;
  wire n_12_U_XSDB_SLAVE;
  wire n_12_reg_0;
  wire n_12_reg_1;
  wire n_12_reg_10;
  wire n_12_reg_11;
  wire n_12_reg_12;
  wire n_12_reg_13;
  wire n_12_reg_14;
  wire n_12_reg_15;
  wire n_12_reg_17;
  wire n_12_reg_19;
  wire n_12_reg_1a;
  wire n_12_reg_2;
  wire n_12_reg_3;
  wire n_12_reg_4;
  wire n_12_reg_7;
  wire n_12_reg_83;
  wire n_12_reg_85;
  wire n_12_reg_887;
  wire n_12_reg_88d;
  wire n_12_reg_88f;
  wire n_12_reg_9;
  wire n_12_reg_a;
  wire n_12_reg_b;
  wire n_12_reg_c;
  wire n_12_reg_d;
  wire n_12_reg_e;
  wire n_12_reg_f;
  wire n_12_reg_srl_fff;
  wire n_12_reg_stream_ffe;
  wire \n_13_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_13_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_13_MU_SRL[11].mu_srl_reg ;
  wire \n_13_MU_SRL[12].mu_srl_reg ;
  wire \n_13_MU_SRL[3].mu_srl_reg ;
  wire \n_13_MU_SRL[7].mu_srl_reg ;
  wire \n_13_MU_STATUS[10].mu_tpid_reg ;
  wire \n_13_MU_STATUS[11].mu_tpid_reg ;
  wire \n_13_MU_STATUS[12].mu_tpid_reg ;
  wire \n_13_MU_STATUS[1].mu_width_reg ;
  wire \n_13_MU_STATUS[2].mu_tpid_reg ;
  wire \n_13_MU_STATUS[3].mu_tpid_reg ;
  wire \n_13_MU_STATUS[5].mu_tpid_reg ;
  wire \n_13_MU_STATUS[6].mu_tpid_reg ;
  wire \n_13_MU_STATUS[7].mu_tpid_reg ;
  wire \n_13_MU_STATUS[8].mu_tpid_reg ;
  wire \n_13_MU_STATUS[9].mu_tpid_reg ;
  wire \n_13_TC_SRL[11].tc_srl_reg ;
  wire \n_13_TC_SRL[15].tc_srl_reg ;
  wire \n_13_TC_SRL[19].tc_srl_reg ;
  wire \n_13_TC_SRL[23].tc_srl_reg ;
  wire \n_13_TC_SRL[27].tc_srl_reg ;
  wire \n_13_TC_SRL[31].tc_srl_reg ;
  wire \n_13_TC_SRL[3].tc_srl_reg ;
  wire \n_13_TC_SRL[7].tc_srl_reg ;
  wire n_13_U_XSDB_SLAVE;
  wire n_13_reg_0;
  wire n_13_reg_1;
  wire n_13_reg_10;
  wire n_13_reg_11;
  wire n_13_reg_12;
  wire n_13_reg_13;
  wire n_13_reg_14;
  wire n_13_reg_15;
  wire n_13_reg_17;
  wire n_13_reg_18;
  wire n_13_reg_19;
  wire n_13_reg_1a;
  wire n_13_reg_2;
  wire n_13_reg_3;
  wire n_13_reg_4;
  wire n_13_reg_7;
  wire n_13_reg_83;
  wire n_13_reg_85;
  wire n_13_reg_887;
  wire n_13_reg_88d;
  wire n_13_reg_88f;
  wire n_13_reg_9;
  wire n_13_reg_a;
  wire n_13_reg_b;
  wire n_13_reg_c;
  wire n_13_reg_d;
  wire n_13_reg_e;
  wire n_13_reg_f;
  wire n_13_reg_srl_fff;
  wire n_13_reg_stream_ffe;
  wire \n_14_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_14_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_14_MU_SRL[11].mu_srl_reg ;
  wire \n_14_MU_SRL[12].mu_srl_reg ;
  wire \n_14_MU_SRL[3].mu_srl_reg ;
  wire \n_14_MU_SRL[7].mu_srl_reg ;
  wire \n_14_MU_STATUS[10].mu_tpid_reg ;
  wire \n_14_MU_STATUS[11].mu_tpid_reg ;
  wire \n_14_MU_STATUS[12].mu_tpid_reg ;
  wire \n_14_MU_STATUS[1].mu_width_reg ;
  wire \n_14_MU_STATUS[2].mu_tpid_reg ;
  wire \n_14_MU_STATUS[3].mu_tpid_reg ;
  wire \n_14_MU_STATUS[5].mu_tpid_reg ;
  wire \n_14_MU_STATUS[6].mu_tpid_reg ;
  wire \n_14_MU_STATUS[7].mu_tpid_reg ;
  wire \n_14_MU_STATUS[8].mu_tpid_reg ;
  wire \n_14_MU_STATUS[9].mu_tpid_reg ;
  wire \n_14_TC_SRL[11].tc_srl_reg ;
  wire \n_14_TC_SRL[15].tc_srl_reg ;
  wire \n_14_TC_SRL[19].tc_srl_reg ;
  wire \n_14_TC_SRL[23].tc_srl_reg ;
  wire \n_14_TC_SRL[27].tc_srl_reg ;
  wire \n_14_TC_SRL[31].tc_srl_reg ;
  wire \n_14_TC_SRL[3].tc_srl_reg ;
  wire \n_14_TC_SRL[7].tc_srl_reg ;
  wire n_14_U_XSDB_SLAVE;
  wire n_14_reg_0;
  wire n_14_reg_1;
  wire n_14_reg_10;
  wire n_14_reg_11;
  wire n_14_reg_12;
  wire n_14_reg_13;
  wire n_14_reg_14;
  wire n_14_reg_15;
  wire n_14_reg_17;
  wire n_14_reg_18;
  wire n_14_reg_19;
  wire n_14_reg_1a;
  wire n_14_reg_2;
  wire n_14_reg_3;
  wire n_14_reg_4;
  wire n_14_reg_7;
  wire n_14_reg_83;
  wire n_14_reg_85;
  wire n_14_reg_887;
  wire n_14_reg_88d;
  wire n_14_reg_88f;
  wire n_14_reg_9;
  wire n_14_reg_a;
  wire n_14_reg_b;
  wire n_14_reg_c;
  wire n_14_reg_d;
  wire n_14_reg_e;
  wire n_14_reg_f;
  wire n_14_reg_srl_fff;
  wire n_14_reg_stream_ffe;
  wire \n_15_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_15_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_15_MU_SRL[11].mu_srl_reg ;
  wire \n_15_MU_SRL[12].mu_srl_reg ;
  wire \n_15_MU_SRL[3].mu_srl_reg ;
  wire \n_15_MU_SRL[7].mu_srl_reg ;
  wire \n_15_MU_STATUS[10].mu_tpid_reg ;
  wire \n_15_MU_STATUS[11].mu_tpid_reg ;
  wire \n_15_MU_STATUS[12].mu_tpid_reg ;
  wire \n_15_MU_STATUS[1].mu_width_reg ;
  wire \n_15_MU_STATUS[2].mu_tpid_reg ;
  wire \n_15_MU_STATUS[3].mu_tpid_reg ;
  wire \n_15_MU_STATUS[5].mu_tpid_reg ;
  wire \n_15_MU_STATUS[6].mu_tpid_reg ;
  wire \n_15_MU_STATUS[7].mu_tpid_reg ;
  wire \n_15_MU_STATUS[8].mu_tpid_reg ;
  wire \n_15_MU_STATUS[9].mu_tpid_reg ;
  wire \n_15_TC_SRL[11].tc_srl_reg ;
  wire \n_15_TC_SRL[15].tc_srl_reg ;
  wire \n_15_TC_SRL[19].tc_srl_reg ;
  wire \n_15_TC_SRL[23].tc_srl_reg ;
  wire \n_15_TC_SRL[27].tc_srl_reg ;
  wire \n_15_TC_SRL[31].tc_srl_reg ;
  wire \n_15_TC_SRL[3].tc_srl_reg ;
  wire \n_15_TC_SRL[7].tc_srl_reg ;
  wire n_15_U_XSDB_SLAVE;
  wire n_15_reg_0;
  wire n_15_reg_1;
  wire n_15_reg_10;
  wire n_15_reg_11;
  wire n_15_reg_12;
  wire n_15_reg_13;
  wire n_15_reg_14;
  wire n_15_reg_15;
  wire n_15_reg_17;
  wire n_15_reg_18;
  wire n_15_reg_19;
  wire n_15_reg_1a;
  wire n_15_reg_2;
  wire n_15_reg_3;
  wire n_15_reg_4;
  wire n_15_reg_7;
  wire n_15_reg_82;
  wire n_15_reg_83;
  wire n_15_reg_85;
  wire n_15_reg_887;
  wire n_15_reg_88d;
  wire n_15_reg_88f;
  wire n_15_reg_9;
  wire n_15_reg_a;
  wire n_15_reg_b;
  wire n_15_reg_c;
  wire n_15_reg_d;
  wire n_15_reg_e;
  wire n_15_reg_f;
  wire n_15_reg_srl_fff;
  wire n_15_reg_stream_ffe;
  wire \n_16_MU_STATUS[10].mu_tpid_reg ;
  wire \n_16_MU_STATUS[1].mu_width_reg ;
  wire n_16_U_XSDB_SLAVE;
  wire n_16_reg_19;
  wire n_16_reg_1a;
  wire n_16_reg_2;
  wire n_16_reg_4;
  wire n_16_reg_7;
  wire n_16_reg_83;
  wire n_16_reg_887;
  wire \n_17_MU_STATUS[10].mu_tpid_reg ;
  wire \n_17_MU_STATUS[1].mu_width_reg ;
  wire n_17_U_XSDB_SLAVE;
  wire n_17_reg_15;
  wire n_17_reg_19;
  wire n_17_reg_1a;
  wire n_17_reg_2;
  wire n_17_reg_4;
  wire n_17_reg_7;
  wire n_17_reg_83;
  wire n_17_reg_887;
  wire \n_18_MU_STATUS[10].mu_tpid_reg ;
  wire \n_18_MU_STATUS[1].mu_width_reg ;
  wire n_18_reg_15;
  wire n_18_reg_1a;
  wire n_18_reg_2;
  wire n_18_reg_4;
  wire n_18_reg_7;
  wire n_18_reg_83;
  wire n_18_reg_887;
  wire \n_19_MU_STATUS[10].mu_tpid_reg ;
  wire n_19_reg_2;
  wire n_19_reg_4;
  wire n_19_reg_83;
  wire n_19_reg_887;
  wire \n_1_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_1_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_1_MU_SRL[11].mu_srl_reg ;
  wire \n_1_MU_SRL[12].mu_srl_reg ;
  wire \n_1_MU_SRL[3].mu_srl_reg ;
  wire \n_1_MU_SRL[7].mu_srl_reg ;
  wire \n_1_MU_STATUS[11].mu_tpid_reg ;
  wire \n_1_MU_STATUS[12].mu_tpid_reg ;
  wire \n_1_MU_STATUS[1].mu_width_reg ;
  wire \n_1_MU_STATUS[2].mu_tpid_reg ;
  wire \n_1_MU_STATUS[3].mu_tpid_reg ;
  wire \n_1_MU_STATUS[5].mu_tpid_reg ;
  wire \n_1_MU_STATUS[6].mu_tpid_reg ;
  wire \n_1_MU_STATUS[7].mu_tpid_reg ;
  wire \n_1_MU_STATUS[8].mu_tpid_reg ;
  wire \n_1_MU_STATUS[9].mu_tpid_reg ;
  wire \n_1_TC_SRL[11].tc_srl_reg ;
  wire \n_1_TC_SRL[15].tc_srl_reg ;
  wire \n_1_TC_SRL[19].tc_srl_reg ;
  wire \n_1_TC_SRL[23].tc_srl_reg ;
  wire \n_1_TC_SRL[27].tc_srl_reg ;
  wire \n_1_TC_SRL[31].tc_srl_reg ;
  wire \n_1_TC_SRL[3].tc_srl_reg ;
  wire \n_1_TC_SRL[7].tc_srl_reg ;
  wire n_1_reg_0;
  wire n_1_reg_1;
  wire n_1_reg_10;
  wire n_1_reg_12;
  wire n_1_reg_13;
  wire n_1_reg_14;
  wire n_1_reg_15;
  wire n_1_reg_16;
  wire n_1_reg_17;
  wire n_1_reg_18;
  wire n_1_reg_19;
  wire n_1_reg_1a;
  wire n_1_reg_2;
  wire n_1_reg_3;
  wire n_1_reg_4;
  wire n_1_reg_7;
  wire n_1_reg_8;
  wire n_1_reg_83;
  wire n_1_reg_85;
  wire n_1_reg_887;
  wire n_1_reg_88d;
  wire n_1_reg_88f;
  wire n_1_reg_892;
  wire n_1_reg_9;
  wire n_1_reg_a;
  wire n_1_reg_b;
  wire n_1_reg_c;
  wire n_1_reg_d;
  wire n_1_reg_e;
  wire n_1_reg_f;
  wire n_1_reg_srl_fff;
  wire n_1_reg_stream_ffe;
  wire \n_20_MU_STATUS[10].mu_tpid_reg ;
  wire n_20_reg_2;
  wire n_20_reg_4;
  wire n_20_reg_887;
  wire \n_21_MU_STATUS[10].mu_tpid_reg ;
  wire n_21_reg_2;
  wire n_21_reg_4;
  wire n_21_reg_887;
  wire n_22_reg_2;
  wire n_22_reg_4;
  wire n_22_reg_887;
  wire n_23_reg_2;
  wire n_23_reg_4;
  wire n_23_reg_887;
  wire n_24_reg_2;
  wire n_24_reg_4;
  wire n_24_reg_887;
  wire n_25_reg_2;
  wire n_25_reg_4;
  wire n_25_reg_887;
  wire n_26_reg_2;
  wire n_26_reg_4;
  wire n_26_reg_887;
  wire n_27_reg_2;
  wire n_27_reg_4;
  wire n_27_reg_887;
  wire n_28_reg_2;
  wire n_28_reg_4;
  wire n_28_reg_887;
  wire n_29_reg_2;
  wire n_29_reg_4;
  wire n_29_reg_887;
  wire \n_2_ADV_TRIG_STREAM.reg_stream_ffc ;
  wire \n_2_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_2_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_2_MU_SRL[11].mu_srl_reg ;
  wire \n_2_MU_SRL[12].mu_srl_reg ;
  wire \n_2_MU_SRL[3].mu_srl_reg ;
  wire \n_2_MU_SRL[7].mu_srl_reg ;
  wire \n_2_MU_STATUS[11].mu_tpid_reg ;
  wire \n_2_MU_STATUS[12].mu_tpid_reg ;
  wire \n_2_MU_STATUS[1].mu_width_reg ;
  wire \n_2_MU_STATUS[2].mu_tpid_reg ;
  wire \n_2_MU_STATUS[3].mu_tpid_reg ;
  wire \n_2_MU_STATUS[5].mu_tpid_reg ;
  wire \n_2_MU_STATUS[6].mu_tpid_reg ;
  wire \n_2_MU_STATUS[7].mu_tpid_reg ;
  wire \n_2_MU_STATUS[8].mu_tpid_reg ;
  wire \n_2_MU_STATUS[9].mu_tpid_reg ;
  wire \n_2_TC_SRL[11].tc_srl_reg ;
  wire \n_2_TC_SRL[15].tc_srl_reg ;
  wire \n_2_TC_SRL[19].tc_srl_reg ;
  wire \n_2_TC_SRL[23].tc_srl_reg ;
  wire \n_2_TC_SRL[27].tc_srl_reg ;
  wire \n_2_TC_SRL[31].tc_srl_reg ;
  wire \n_2_TC_SRL[3].tc_srl_reg ;
  wire \n_2_TC_SRL[7].tc_srl_reg ;
  wire n_2_reg_0;
  wire n_2_reg_1;
  wire n_2_reg_10;
  wire n_2_reg_12;
  wire n_2_reg_13;
  wire n_2_reg_14;
  wire n_2_reg_15;
  wire n_2_reg_17;
  wire n_2_reg_18;
  wire n_2_reg_19;
  wire n_2_reg_1a;
  wire n_2_reg_2;
  wire n_2_reg_3;
  wire n_2_reg_4;
  wire n_2_reg_8;
  wire n_2_reg_83;
  wire n_2_reg_85;
  wire n_2_reg_887;
  wire n_2_reg_88d;
  wire n_2_reg_88f;
  wire n_2_reg_892;
  wire n_2_reg_9;
  wire n_2_reg_a;
  wire n_2_reg_b;
  wire n_2_reg_c;
  wire n_2_reg_d;
  wire n_2_reg_e;
  wire n_2_reg_f;
  wire n_2_reg_srl_fff;
  wire n_2_reg_stream_ffe;
  wire n_30_reg_2;
  wire n_30_reg_4;
  wire n_30_reg_887;
  wire n_31_reg_4;
  wire n_31_reg_887;
  wire n_32_reg_4;
  wire n_32_reg_887;
  wire n_33_reg_4;
  wire n_33_reg_887;
  wire n_34_reg_4;
  wire n_34_reg_887;
  wire n_35_reg_4;
  wire n_35_reg_887;
  wire n_36_reg_4;
  wire n_36_reg_887;
  wire n_37_reg_2;
  wire n_37_reg_887;
  wire n_38_reg_2;
  wire n_38_reg_887;
  wire n_39_reg_2;
  wire n_39_reg_887;
  wire \n_3_ADV_TRIG_STREAM.reg_stream_ffc ;
  wire \n_3_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_3_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_3_MU_SRL[11].mu_srl_reg ;
  wire \n_3_MU_SRL[12].mu_srl_reg ;
  wire \n_3_MU_SRL[3].mu_srl_reg ;
  wire \n_3_MU_SRL[7].mu_srl_reg ;
  wire \n_3_MU_STATUS[11].mu_tpid_reg ;
  wire \n_3_MU_STATUS[12].mu_tpid_reg ;
  wire \n_3_MU_STATUS[1].mu_width_reg ;
  wire \n_3_MU_STATUS[2].mu_tpid_reg ;
  wire \n_3_MU_STATUS[3].mu_tpid_reg ;
  wire \n_3_MU_STATUS[5].mu_tpid_reg ;
  wire \n_3_MU_STATUS[6].mu_tpid_reg ;
  wire \n_3_MU_STATUS[7].mu_tpid_reg ;
  wire \n_3_MU_STATUS[8].mu_tpid_reg ;
  wire \n_3_MU_STATUS[9].mu_tpid_reg ;
  wire \n_3_TC_SRL[11].tc_srl_reg ;
  wire \n_3_TC_SRL[15].tc_srl_reg ;
  wire \n_3_TC_SRL[19].tc_srl_reg ;
  wire \n_3_TC_SRL[23].tc_srl_reg ;
  wire \n_3_TC_SRL[27].tc_srl_reg ;
  wire \n_3_TC_SRL[31].tc_srl_reg ;
  wire \n_3_TC_SRL[3].tc_srl_reg ;
  wire \n_3_TC_SRL[7].tc_srl_reg ;
  wire n_3_reg_0;
  wire n_3_reg_1;
  wire n_3_reg_10;
  wire n_3_reg_11;
  wire n_3_reg_12;
  wire n_3_reg_13;
  wire n_3_reg_14;
  wire n_3_reg_16;
  wire n_3_reg_17;
  wire n_3_reg_18;
  wire n_3_reg_19;
  wire n_3_reg_1a;
  wire n_3_reg_2;
  wire n_3_reg_3;
  wire n_3_reg_4;
  wire n_3_reg_7;
  wire n_3_reg_8;
  wire n_3_reg_83;
  wire n_3_reg_85;
  wire n_3_reg_887;
  wire n_3_reg_88d;
  wire n_3_reg_88f;
  wire n_3_reg_892;
  wire n_3_reg_9;
  wire n_3_reg_a;
  wire n_3_reg_b;
  wire n_3_reg_c;
  wire n_3_reg_d;
  wire n_3_reg_e;
  wire n_3_reg_f;
  wire n_3_reg_srl_fff;
  wire n_3_reg_stream_ffe;
  wire n_40_reg_2;
  wire n_40_reg_887;
  wire n_41_reg_2;
  wire n_41_reg_887;
  wire n_42_reg_2;
  wire n_42_reg_887;
  wire n_43_reg_2;
  wire n_43_reg_887;
  wire n_44_reg_2;
  wire n_44_reg_887;
  wire n_45_reg_2;
  wire n_45_reg_887;
  wire n_46_reg_2;
  wire n_46_reg_887;
  wire n_47_reg_2;
  wire n_47_reg_887;
  wire n_48_reg_2;
  wire n_49_reg_2;
  wire \n_4_ADV_TRIG_STREAM.reg_stream_ffc ;
  wire \n_4_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_4_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_4_MU_SRL[11].mu_srl_reg ;
  wire \n_4_MU_SRL[12].mu_srl_reg ;
  wire \n_4_MU_SRL[3].mu_srl_reg ;
  wire \n_4_MU_SRL[7].mu_srl_reg ;
  wire \n_4_MU_STATUS[11].mu_tpid_reg ;
  wire \n_4_MU_STATUS[12].mu_tpid_reg ;
  wire \n_4_MU_STATUS[1].mu_width_reg ;
  wire \n_4_MU_STATUS[2].mu_tpid_reg ;
  wire \n_4_MU_STATUS[3].mu_tpid_reg ;
  wire \n_4_MU_STATUS[5].mu_tpid_reg ;
  wire \n_4_MU_STATUS[6].mu_tpid_reg ;
  wire \n_4_MU_STATUS[7].mu_tpid_reg ;
  wire \n_4_MU_STATUS[8].mu_tpid_reg ;
  wire \n_4_MU_STATUS[9].mu_tpid_reg ;
  wire \n_4_TC_SRL[11].tc_srl_reg ;
  wire \n_4_TC_SRL[15].tc_srl_reg ;
  wire \n_4_TC_SRL[19].tc_srl_reg ;
  wire \n_4_TC_SRL[23].tc_srl_reg ;
  wire \n_4_TC_SRL[27].tc_srl_reg ;
  wire \n_4_TC_SRL[31].tc_srl_reg ;
  wire \n_4_TC_SRL[3].tc_srl_reg ;
  wire \n_4_TC_SRL[7].tc_srl_reg ;
  wire n_4_U_XSDB_SLAVE;
  wire n_4_reg_0;
  wire n_4_reg_1;
  wire n_4_reg_10;
  wire n_4_reg_11;
  wire n_4_reg_12;
  wire n_4_reg_13;
  wire n_4_reg_14;
  wire n_4_reg_15;
  wire n_4_reg_16;
  wire n_4_reg_17;
  wire n_4_reg_19;
  wire n_4_reg_2;
  wire n_4_reg_3;
  wire n_4_reg_4;
  wire n_4_reg_83;
  wire n_4_reg_85;
  wire n_4_reg_887;
  wire n_4_reg_88d;
  wire n_4_reg_88f;
  wire n_4_reg_9;
  wire n_4_reg_a;
  wire n_4_reg_b;
  wire n_4_reg_c;
  wire n_4_reg_d;
  wire n_4_reg_e;
  wire n_4_reg_f;
  wire n_4_reg_srl_fff;
  wire n_4_reg_stream_ffe;
  wire n_50_reg_2;
  wire n_51_reg_2;
  wire n_52_reg_2;
  wire n_53_reg_2;
  wire n_54_reg_2;
  wire n_55_reg_2;
  wire n_56_reg_2;
  wire n_57_reg_2;
  wire n_58_reg_2;
  wire n_59_reg_2;
  wire \n_5_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_5_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_5_MU_SRL[11].mu_srl_reg ;
  wire \n_5_MU_SRL[12].mu_srl_reg ;
  wire \n_5_MU_SRL[3].mu_srl_reg ;
  wire \n_5_MU_SRL[7].mu_srl_reg ;
  wire \n_5_MU_STATUS[11].mu_tpid_reg ;
  wire \n_5_MU_STATUS[12].mu_tpid_reg ;
  wire \n_5_MU_STATUS[1].mu_width_reg ;
  wire \n_5_MU_STATUS[2].mu_tpid_reg ;
  wire \n_5_MU_STATUS[3].mu_tpid_reg ;
  wire \n_5_MU_STATUS[5].mu_tpid_reg ;
  wire \n_5_MU_STATUS[6].mu_tpid_reg ;
  wire \n_5_MU_STATUS[7].mu_tpid_reg ;
  wire \n_5_MU_STATUS[8].mu_tpid_reg ;
  wire \n_5_MU_STATUS[9].mu_tpid_reg ;
  wire \n_5_TC_SRL[11].tc_srl_reg ;
  wire \n_5_TC_SRL[15].tc_srl_reg ;
  wire \n_5_TC_SRL[19].tc_srl_reg ;
  wire \n_5_TC_SRL[23].tc_srl_reg ;
  wire \n_5_TC_SRL[27].tc_srl_reg ;
  wire \n_5_TC_SRL[31].tc_srl_reg ;
  wire \n_5_TC_SRL[3].tc_srl_reg ;
  wire \n_5_TC_SRL[7].tc_srl_reg ;
  wire n_5_U_XSDB_SLAVE;
  wire n_5_reg_0;
  wire n_5_reg_1;
  wire n_5_reg_10;
  wire n_5_reg_11;
  wire n_5_reg_12;
  wire n_5_reg_13;
  wire n_5_reg_14;
  wire n_5_reg_15;
  wire n_5_reg_16;
  wire n_5_reg_17;
  wire n_5_reg_19;
  wire n_5_reg_2;
  wire n_5_reg_3;
  wire n_5_reg_4;
  wire n_5_reg_7;
  wire n_5_reg_83;
  wire n_5_reg_85;
  wire n_5_reg_887;
  wire n_5_reg_88d;
  wire n_5_reg_88f;
  wire n_5_reg_9;
  wire n_5_reg_a;
  wire n_5_reg_b;
  wire n_5_reg_c;
  wire n_5_reg_d;
  wire n_5_reg_e;
  wire n_5_reg_f;
  wire n_5_reg_srl_fff;
  wire n_5_reg_stream_ffe;
  wire n_60_reg_2;
  wire n_61_reg_2;
  wire n_62_reg_2;
  wire n_63_reg_2;
  wire n_64_reg_2;
  wire n_65_reg_2;
  wire \n_6_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_6_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_6_MU_SRL[11].mu_srl_reg ;
  wire \n_6_MU_SRL[12].mu_srl_reg ;
  wire \n_6_MU_SRL[3].mu_srl_reg ;
  wire \n_6_MU_SRL[7].mu_srl_reg ;
  wire \n_6_MU_STATUS[10].mu_tpid_reg ;
  wire \n_6_MU_STATUS[11].mu_tpid_reg ;
  wire \n_6_MU_STATUS[12].mu_tpid_reg ;
  wire \n_6_MU_STATUS[1].mu_width_reg ;
  wire \n_6_MU_STATUS[2].mu_tpid_reg ;
  wire \n_6_MU_STATUS[3].mu_tpid_reg ;
  wire \n_6_MU_STATUS[5].mu_tpid_reg ;
  wire \n_6_MU_STATUS[6].mu_tpid_reg ;
  wire \n_6_MU_STATUS[7].mu_tpid_reg ;
  wire \n_6_MU_STATUS[8].mu_tpid_reg ;
  wire \n_6_MU_STATUS[9].mu_tpid_reg ;
  wire \n_6_TC_SRL[11].tc_srl_reg ;
  wire \n_6_TC_SRL[15].tc_srl_reg ;
  wire \n_6_TC_SRL[19].tc_srl_reg ;
  wire \n_6_TC_SRL[23].tc_srl_reg ;
  wire \n_6_TC_SRL[27].tc_srl_reg ;
  wire \n_6_TC_SRL[31].tc_srl_reg ;
  wire \n_6_TC_SRL[3].tc_srl_reg ;
  wire \n_6_TC_SRL[7].tc_srl_reg ;
  wire n_6_U_XSDB_SLAVE;
  wire n_6_reg_0;
  wire n_6_reg_1;
  wire n_6_reg_10;
  wire n_6_reg_11;
  wire n_6_reg_12;
  wire n_6_reg_13;
  wire n_6_reg_14;
  wire n_6_reg_15;
  wire n_6_reg_16;
  wire n_6_reg_17;
  wire n_6_reg_19;
  wire n_6_reg_2;
  wire n_6_reg_3;
  wire n_6_reg_7;
  wire n_6_reg_83;
  wire n_6_reg_85;
  wire n_6_reg_887;
  wire n_6_reg_88d;
  wire n_6_reg_88f;
  wire n_6_reg_9;
  wire n_6_reg_a;
  wire n_6_reg_b;
  wire n_6_reg_c;
  wire n_6_reg_d;
  wire n_6_reg_e;
  wire n_6_reg_f;
  wire n_6_reg_srl_fff;
  wire n_6_reg_stream_ffe;
  wire \n_7_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_7_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_7_MU_SRL[11].mu_srl_reg ;
  wire \n_7_MU_SRL[12].mu_srl_reg ;
  wire \n_7_MU_SRL[3].mu_srl_reg ;
  wire \n_7_MU_SRL[7].mu_srl_reg ;
  wire \n_7_MU_STATUS[10].mu_tpid_reg ;
  wire \n_7_MU_STATUS[11].mu_tpid_reg ;
  wire \n_7_MU_STATUS[12].mu_tpid_reg ;
  wire \n_7_MU_STATUS[1].mu_width_reg ;
  wire \n_7_MU_STATUS[2].mu_tpid_reg ;
  wire \n_7_MU_STATUS[3].mu_tpid_reg ;
  wire \n_7_MU_STATUS[5].mu_tpid_reg ;
  wire \n_7_MU_STATUS[6].mu_tpid_reg ;
  wire \n_7_MU_STATUS[7].mu_tpid_reg ;
  wire \n_7_MU_STATUS[8].mu_tpid_reg ;
  wire \n_7_MU_STATUS[9].mu_tpid_reg ;
  wire \n_7_TC_SRL[11].tc_srl_reg ;
  wire \n_7_TC_SRL[15].tc_srl_reg ;
  wire \n_7_TC_SRL[19].tc_srl_reg ;
  wire \n_7_TC_SRL[23].tc_srl_reg ;
  wire \n_7_TC_SRL[27].tc_srl_reg ;
  wire \n_7_TC_SRL[31].tc_srl_reg ;
  wire \n_7_TC_SRL[3].tc_srl_reg ;
  wire \n_7_TC_SRL[7].tc_srl_reg ;
  wire n_7_U_XSDB_SLAVE;
  wire n_7_reg_0;
  wire n_7_reg_1;
  wire n_7_reg_10;
  wire n_7_reg_11;
  wire n_7_reg_12;
  wire n_7_reg_13;
  wire n_7_reg_14;
  wire n_7_reg_15;
  wire n_7_reg_16;
  wire n_7_reg_17;
  wire n_7_reg_19;
  wire n_7_reg_1a;
  wire n_7_reg_2;
  wire n_7_reg_3;
  wire n_7_reg_7;
  wire n_7_reg_83;
  wire n_7_reg_85;
  wire n_7_reg_887;
  wire n_7_reg_88d;
  wire n_7_reg_88f;
  wire n_7_reg_9;
  wire n_7_reg_a;
  wire n_7_reg_b;
  wire n_7_reg_c;
  wire n_7_reg_d;
  wire n_7_reg_e;
  wire n_7_reg_f;
  wire n_7_reg_srl_fff;
  wire n_7_reg_stream_ffe;
  wire \n_8_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_8_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_8_MU_SRL[11].mu_srl_reg ;
  wire \n_8_MU_SRL[12].mu_srl_reg ;
  wire \n_8_MU_SRL[3].mu_srl_reg ;
  wire \n_8_MU_SRL[7].mu_srl_reg ;
  wire \n_8_MU_STATUS[10].mu_tpid_reg ;
  wire \n_8_MU_STATUS[11].mu_tpid_reg ;
  wire \n_8_MU_STATUS[12].mu_tpid_reg ;
  wire \n_8_MU_STATUS[1].mu_width_reg ;
  wire \n_8_MU_STATUS[2].mu_tpid_reg ;
  wire \n_8_MU_STATUS[3].mu_tpid_reg ;
  wire \n_8_MU_STATUS[5].mu_tpid_reg ;
  wire \n_8_MU_STATUS[6].mu_tpid_reg ;
  wire \n_8_MU_STATUS[7].mu_tpid_reg ;
  wire \n_8_MU_STATUS[8].mu_tpid_reg ;
  wire \n_8_MU_STATUS[9].mu_tpid_reg ;
  wire \n_8_TC_SRL[11].tc_srl_reg ;
  wire \n_8_TC_SRL[15].tc_srl_reg ;
  wire \n_8_TC_SRL[19].tc_srl_reg ;
  wire \n_8_TC_SRL[23].tc_srl_reg ;
  wire \n_8_TC_SRL[27].tc_srl_reg ;
  wire \n_8_TC_SRL[31].tc_srl_reg ;
  wire \n_8_TC_SRL[3].tc_srl_reg ;
  wire \n_8_TC_SRL[7].tc_srl_reg ;
  wire n_8_U_XSDB_SLAVE;
  wire n_8_reg_0;
  wire n_8_reg_1;
  wire n_8_reg_10;
  wire n_8_reg_11;
  wire n_8_reg_12;
  wire n_8_reg_13;
  wire n_8_reg_14;
  wire n_8_reg_15;
  wire n_8_reg_17;
  wire n_8_reg_19;
  wire n_8_reg_1a;
  wire n_8_reg_2;
  wire n_8_reg_3;
  wire n_8_reg_4;
  wire n_8_reg_7;
  wire n_8_reg_83;
  wire n_8_reg_85;
  wire n_8_reg_887;
  wire n_8_reg_88d;
  wire n_8_reg_88f;
  wire n_8_reg_9;
  wire n_8_reg_a;
  wire n_8_reg_b;
  wire n_8_reg_c;
  wire n_8_reg_d;
  wire n_8_reg_e;
  wire n_8_reg_f;
  wire n_8_reg_srl_fff;
  wire n_8_reg_stream_ffe;
  wire \n_9_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ;
  wire \n_9_CNT_WIDTH_STATUS[0].cnt_width_reg ;
  wire \n_9_MU_SRL[11].mu_srl_reg ;
  wire \n_9_MU_SRL[12].mu_srl_reg ;
  wire \n_9_MU_SRL[3].mu_srl_reg ;
  wire \n_9_MU_SRL[7].mu_srl_reg ;
  wire \n_9_MU_STATUS[10].mu_tpid_reg ;
  wire \n_9_MU_STATUS[11].mu_tpid_reg ;
  wire \n_9_MU_STATUS[12].mu_tpid_reg ;
  wire \n_9_MU_STATUS[1].mu_width_reg ;
  wire \n_9_MU_STATUS[2].mu_tpid_reg ;
  wire \n_9_MU_STATUS[3].mu_tpid_reg ;
  wire \n_9_MU_STATUS[5].mu_tpid_reg ;
  wire \n_9_MU_STATUS[6].mu_tpid_reg ;
  wire \n_9_MU_STATUS[7].mu_tpid_reg ;
  wire \n_9_MU_STATUS[8].mu_tpid_reg ;
  wire \n_9_MU_STATUS[9].mu_tpid_reg ;
  wire \n_9_TC_SRL[11].tc_srl_reg ;
  wire \n_9_TC_SRL[15].tc_srl_reg ;
  wire \n_9_TC_SRL[19].tc_srl_reg ;
  wire \n_9_TC_SRL[23].tc_srl_reg ;
  wire \n_9_TC_SRL[27].tc_srl_reg ;
  wire \n_9_TC_SRL[31].tc_srl_reg ;
  wire \n_9_TC_SRL[3].tc_srl_reg ;
  wire \n_9_TC_SRL[7].tc_srl_reg ;
  wire n_9_U_XSDB_SLAVE;
  wire n_9_reg_0;
  wire n_9_reg_1;
  wire n_9_reg_10;
  wire n_9_reg_11;
  wire n_9_reg_12;
  wire n_9_reg_13;
  wire n_9_reg_14;
  wire n_9_reg_15;
  wire n_9_reg_17;
  wire n_9_reg_19;
  wire n_9_reg_1a;
  wire n_9_reg_2;
  wire n_9_reg_3;
  wire n_9_reg_4;
  wire n_9_reg_7;
  wire n_9_reg_83;
  wire n_9_reg_85;
  wire n_9_reg_887;
  wire n_9_reg_88d;
  wire n_9_reg_88f;
  wire n_9_reg_9;
  wire n_9_reg_a;
  wire n_9_reg_b;
  wire n_9_reg_c;
  wire n_9_reg_d;
  wire n_9_reg_e;
  wire n_9_reg_f;
  wire n_9_reg_srl_fff;
  wire n_9_reg_stream_ffe;
  wire [15:0]p_0_in;
  wire [15:0]p_1_in;
  wire read_data_en;
  wire regAck_reg;
  wire regAck_temp;
  wire regAck_temp_reg;
  wire reg_ce;
  wire [2:0]s_daddr_o;
  wire s_dclk;
  wire [15:0]s_di;
  wire s_rst;
  wire shift_en_o;
  wire [15:4]slaveRegDo_18;
  wire [15:0]slaveRegDo_6;
  wire [15:0]slaveRegDo_80;
  wire [15:0]slaveRegDo_81;
  wire [14:0]slaveRegDo_82;
  wire [15:0]slaveRegDo_84;
  wire [15:0]\slaveRegDo_cntConfig[6144]_46 ;
  wire [15:0]\slaveRegDo_cntConfig[6145]_47 ;
  wire [15:0]\slaveRegDo_cntConfig[6146]_48 ;
  wire [15:0]\slaveRegDo_muConfig[4096]_1 ;
  wire [15:0]\slaveRegDo_muConfig[4097]_2 ;
  wire [15:0]\slaveRegDo_muConfig[4098]_3 ;
  wire [15:0]\slaveRegDo_muConfig[4100]_5 ;
  wire [15:0]\slaveRegDo_muConfig[4101]_6 ;
  wire [15:0]\slaveRegDo_muConfig[4102]_7 ;
  wire [15:0]\slaveRegDo_muConfig[4104]_9 ;
  wire [15:0]\slaveRegDo_muConfig[4105]_10 ;
  wire [15:0]\slaveRegDo_muConfig[4106]_11 ;
  wire [15:0]slaveRegDo_mux;
  wire [15:0]slaveRegDo_mux_1;
  wire [15:0]slaveRegDo_mux_4;
  wire [15:0]slaveRegDo_mux_5;
  wire [15:0]slaveRegDo_mux_6;
  wire [15:0]\slaveRegDo_tcConfig[5120]_14 ;
  wire [15:0]\slaveRegDo_tcConfig[5121]_15 ;
  wire [15:0]\slaveRegDo_tcConfig[5122]_16 ;
  wire [15:0]\slaveRegDo_tcConfig[5124]_18 ;
  wire [15:0]\slaveRegDo_tcConfig[5125]_19 ;
  wire [15:0]\slaveRegDo_tcConfig[5126]_20 ;
  wire [15:0]\slaveRegDo_tcConfig[5128]_22 ;
  wire [15:0]\slaveRegDo_tcConfig[5129]_23 ;
  wire [15:0]\slaveRegDo_tcConfig[5130]_24 ;
  wire [15:0]\slaveRegDo_tcConfig[5132]_26 ;
  wire [15:0]\slaveRegDo_tcConfig[5133]_27 ;
  wire [15:0]\slaveRegDo_tcConfig[5134]_28 ;
  wire [15:0]\slaveRegDo_tcConfig[5136]_30 ;
  wire [15:0]\slaveRegDo_tcConfig[5137]_31 ;
  wire [15:0]\slaveRegDo_tcConfig[5138]_32 ;
  wire [15:0]\slaveRegDo_tcConfig[5140]_34 ;
  wire [15:0]\slaveRegDo_tcConfig[5141]_35 ;
  wire [15:0]\slaveRegDo_tcConfig[5142]_36 ;
  wire [15:0]\slaveRegDo_tcConfig[5144]_38 ;
  wire [15:0]\slaveRegDo_tcConfig[5145]_39 ;
  wire [15:0]\slaveRegDo_tcConfig[5146]_40 ;
  wire [15:0]\slaveRegDo_tcConfig[5148]_42 ;
  wire [15:0]\slaveRegDo_tcConfig[5149]_43 ;
  wire [15:0]\slaveRegDo_tcConfig[5150]_44 ;
  wire [31:0]tc_config_cs_serial_input;
  wire [31:0]tc_config_cs_serial_output;
  wire [31:0]tc_config_cs_shift_en;
  wire toggle_rd;
  wire trig_out_fsm_temp;
  wire use_probe_debug_circuit;

ila_0_xsdbs_v1_0_reg_stream__parameterized0 \ADV_TRIG_STREAM.reg_stream_ffc 
       (.D({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .E(den),
        .I1(s_dclk),
        .I2(n_0_bram_rd_en_i_2),
        .I3(n_0_bram_en_i_2),
        .I4(I2),
        .I5(O3),
        .O1(\n_2_ADV_TRIG_STREAM.reg_stream_ffc ),
        .O2(\n_3_ADV_TRIG_STREAM.reg_stream_ffc ),
        .O3(\n_4_ADV_TRIG_STREAM.reg_stream_ffc ),
        .O4(O4),
        .O5(D),
        .Q({config_fsm_addr[14:13],config_fsm_addr[10:8],config_fsm_addr[4:3],config_fsm_addr[0]}),
        .bram_en(bram_en),
        .dwe(dwe),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg_stream \ADV_TRIG_STREAM_READBACK.reg_stream_ffb 
       (.D(s_daddr_o),
        .E(adv_rb_drdy1),
        .I1(n_15_reg_srl_fff),
        .I10(n_6_reg_srl_fff),
        .I11(n_5_reg_srl_fff),
        .I12(n_4_reg_srl_fff),
        .I13(n_3_reg_srl_fff),
        .I14(n_2_reg_srl_fff),
        .I15(n_1_reg_srl_fff),
        .I16(n_0_reg_srl_fff),
        .I17(I3),
        .I18(s_dclk),
        .I2(n_14_reg_srl_fff),
        .I3(n_13_reg_srl_fff),
        .I4(n_12_reg_srl_fff),
        .I5(n_11_reg_srl_fff),
        .I6(n_10_reg_srl_fff),
        .I7(n_9_reg_srl_fff),
        .I8(n_8_reg_srl_fff),
        .I9(n_7_reg_srl_fff),
        .O1(\n_0_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O10(\n_9_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O11(\n_10_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O12(\n_11_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O13(\n_12_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O14(\n_13_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O15(\n_14_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O16(\n_15_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O2(\n_1_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O3(\n_2_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O4(\n_3_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O5(\n_4_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O6(\n_5_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O7(\n_6_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O8(\n_7_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .O9(\n_8_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ));
ila_0_xsdbs_v1_0_reg_p2s__parameterized45 \CNT.CNT_SRL[0].cnt_srl_reg 
       (.CFG_CNT_DIN(CFG_CNT_DIN[0]),
        .CFG_CNT_DOUT(CFG_CNT_DOUT[0]),
        .D({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_cntConfig[6144]_46 ),
        .shift_en_o(CNT_CONFIG_CS_SHIFT_EN_O[0]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized46 \CNT.CNT_SRL[1].cnt_srl_reg 
       (.CFG_CNT_DIN(CFG_CNT_DIN[1]),
        .CFG_CNT_DOUT(CFG_CNT_DOUT[1]),
        .E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_cntConfig[6145]_47 ),
        .shift_en_o(CNT_CONFIG_CS_SHIFT_EN_O[1]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized47 \CNT.CNT_SRL[2].cnt_srl_reg 
       (.CFG_CNT_DIN(CFG_CNT_DIN[2]),
        .CFG_CNT_DOUT(CFG_CNT_DOUT[2]),
        .E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_cntConfig[6146]_48 ),
        .shift_en_o(CNT_CONFIG_CS_SHIFT_EN_O[2]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized48 \CNT.CNT_SRL[3].cnt_srl_reg 
       (.CFG_CNT_DIN(CFG_CNT_DIN[3]),
        .CFG_CNT_DOUT(CFG_CNT_DOUT[3]),
        .D(p_1_in),
        .E(den),
        .I1(\slaveRegDo_cntConfig[6146]_48 ),
        .I2(\slaveRegDo_cntConfig[6144]_46 ),
        .I3(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_cntConfig[6145]_47 ),
        .shift_en_o(CNT_CONFIG_CS_SHIFT_EN_O[3]));
ila_0_xsdbs_v1_0_reg__parameterized60 \CNT_WIDTH_STATUS[0].cnt_width_reg 
       (.E(den),
        .I1(s_dclk),
        .Q({\n_0_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_1_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_2_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_3_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_4_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_5_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_6_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_7_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_8_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_9_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_10_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_11_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_12_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_13_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_14_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_15_CNT_WIDTH_STATUS[0].cnt_width_reg }));
FDRE \FSM_BRAM_ADDR_O_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(s_daddr_o[0]),
        .Q(config_fsm_addr[0]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_10_U_XSDB_SLAVE),
        .Q(config_fsm_addr[10]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_9_U_XSDB_SLAVE),
        .Q(config_fsm_addr[11]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_8_U_XSDB_SLAVE),
        .Q(config_fsm_addr[12]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_7_U_XSDB_SLAVE),
        .Q(config_fsm_addr[13]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_6_U_XSDB_SLAVE),
        .Q(config_fsm_addr[14]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_5_U_XSDB_SLAVE),
        .Q(config_fsm_addr[15]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[16] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_4_U_XSDB_SLAVE),
        .Q(config_fsm_addr[16]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(s_daddr_o[1]),
        .Q(config_fsm_addr[1]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(s_daddr_o[2]),
        .Q(config_fsm_addr[2]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_17_U_XSDB_SLAVE),
        .Q(config_fsm_addr[3]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_16_U_XSDB_SLAVE),
        .Q(config_fsm_addr[4]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_15_U_XSDB_SLAVE),
        .Q(config_fsm_addr[5]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_14_U_XSDB_SLAVE),
        .Q(config_fsm_addr[6]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_13_U_XSDB_SLAVE),
        .Q(config_fsm_addr[7]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_12_U_XSDB_SLAVE),
        .Q(config_fsm_addr[8]),
        .R(1'b0));
FDRE \FSM_BRAM_ADDR_O_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_11_U_XSDB_SLAVE),
        .Q(config_fsm_addr[9]),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0000800000000000)) 
     FSM_BRAM_EN_RB_O_i_1
       (.I0(\n_4_ADV_TRIG_STREAM.reg_stream_ffc ),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(n_0_FSM_BRAM_EN_RB_O_i_2),
        .I4(n_8_U_XSDB_SLAVE),
        .I5(n_9_U_XSDB_SLAVE),
        .O(reg_ce));
(* SOFT_HLUTNM = "soft_lutpair253" *) 
   LUT2 #(
    .INIT(4'h2)) 
     FSM_BRAM_EN_RB_O_i_2
       (.I0(n_17_U_XSDB_SLAVE),
        .I1(s_daddr_o[2]),
        .O(n_0_FSM_BRAM_EN_RB_O_i_2));
FDRE FSM_BRAM_EN_RB_O_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(reg_ce),
        .Q(config_fsm_en_rb),
        .R(1'b0));
FDRE FSM_BRAM_WE_O_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(dwe),
        .Q(config_fsm_we),
        .R(1'b0));
ila_0_xsdbs_v1_0_reg_p2s__parameterized0 \MU_SRL[0].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[0]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[0]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4096]_1 ),
        .shift_en_o(mu_config_cs_shift_en[0]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized10 \MU_SRL[10].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[10]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[10]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4106]_11 ),
        .shift_en_o(mu_config_cs_shift_en[10]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized11 \MU_SRL[11].mu_srl_reg 
       (.E(den),
        .I1(\slaveRegDo_muConfig[4104]_9 ),
        .I2(s_dclk),
        .O1(\n_0_MU_SRL[11].mu_srl_reg ),
        .O10(\n_9_MU_SRL[11].mu_srl_reg ),
        .O11(\n_10_MU_SRL[11].mu_srl_reg ),
        .O12(\n_11_MU_SRL[11].mu_srl_reg ),
        .O13(\n_12_MU_SRL[11].mu_srl_reg ),
        .O14(\n_13_MU_SRL[11].mu_srl_reg ),
        .O15(\n_14_MU_SRL[11].mu_srl_reg ),
        .O16(\n_15_MU_SRL[11].mu_srl_reg ),
        .O2(\n_1_MU_SRL[11].mu_srl_reg ),
        .O3(\n_2_MU_SRL[11].mu_srl_reg ),
        .O4(\n_3_MU_SRL[11].mu_srl_reg ),
        .O5(\n_4_MU_SRL[11].mu_srl_reg ),
        .O6(\n_5_MU_SRL[11].mu_srl_reg ),
        .O7(\n_6_MU_SRL[11].mu_srl_reg ),
        .O8(\n_7_MU_SRL[11].mu_srl_reg ),
        .O9(\n_8_MU_SRL[11].mu_srl_reg ),
        .Q(\slaveRegDo_muConfig[4105]_10 ),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[11]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[11]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4106]_11 ),
        .shift_en_o(mu_config_cs_shift_en[11]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized12 \MU_SRL[12].mu_srl_reg 
       (.D({\n_0_MU_SRL[12].mu_srl_reg ,\n_1_MU_SRL[12].mu_srl_reg ,\n_2_MU_SRL[12].mu_srl_reg ,\n_3_MU_SRL[12].mu_srl_reg ,\n_4_MU_SRL[12].mu_srl_reg ,\n_5_MU_SRL[12].mu_srl_reg ,\n_6_MU_SRL[12].mu_srl_reg ,\n_7_MU_SRL[12].mu_srl_reg ,\n_8_MU_SRL[12].mu_srl_reg ,\n_9_MU_SRL[12].mu_srl_reg ,\n_10_MU_SRL[12].mu_srl_reg ,\n_11_MU_SRL[12].mu_srl_reg ,\n_12_MU_SRL[12].mu_srl_reg ,\n_13_MU_SRL[12].mu_srl_reg ,\n_14_MU_SRL[12].mu_srl_reg ,\n_15_MU_SRL[12].mu_srl_reg }),
        .E(den),
        .I1(\n_0_MU_SRL[11].mu_srl_reg ),
        .I10(\n_3_MU_SRL[11].mu_srl_reg ),
        .I11(\n_3_MU_SRL[7].mu_srl_reg ),
        .I12(\n_3_MU_SRL[3].mu_srl_reg ),
        .I13(\n_4_MU_SRL[11].mu_srl_reg ),
        .I14(\n_4_MU_SRL[7].mu_srl_reg ),
        .I15(\n_4_MU_SRL[3].mu_srl_reg ),
        .I16(\n_5_MU_SRL[11].mu_srl_reg ),
        .I17(\n_5_MU_SRL[7].mu_srl_reg ),
        .I18(\n_5_MU_SRL[3].mu_srl_reg ),
        .I19(\n_6_MU_SRL[11].mu_srl_reg ),
        .I2(\n_0_MU_SRL[7].mu_srl_reg ),
        .I20(\n_6_MU_SRL[7].mu_srl_reg ),
        .I21(\n_6_MU_SRL[3].mu_srl_reg ),
        .I22(\n_7_MU_SRL[11].mu_srl_reg ),
        .I23(\n_7_MU_SRL[7].mu_srl_reg ),
        .I24(\n_7_MU_SRL[3].mu_srl_reg ),
        .I25(\n_8_MU_SRL[11].mu_srl_reg ),
        .I26(\n_8_MU_SRL[7].mu_srl_reg ),
        .I27(\n_8_MU_SRL[3].mu_srl_reg ),
        .I28(\n_9_MU_SRL[11].mu_srl_reg ),
        .I29(\n_9_MU_SRL[7].mu_srl_reg ),
        .I3(\n_0_MU_SRL[3].mu_srl_reg ),
        .I30(\n_9_MU_SRL[3].mu_srl_reg ),
        .I31(\n_10_MU_SRL[11].mu_srl_reg ),
        .I32(\n_10_MU_SRL[7].mu_srl_reg ),
        .I33(\n_10_MU_SRL[3].mu_srl_reg ),
        .I34(\n_11_MU_SRL[11].mu_srl_reg ),
        .I35(\n_11_MU_SRL[7].mu_srl_reg ),
        .I36(\n_11_MU_SRL[3].mu_srl_reg ),
        .I37(\n_12_MU_SRL[11].mu_srl_reg ),
        .I38(\n_12_MU_SRL[7].mu_srl_reg ),
        .I39(\n_12_MU_SRL[3].mu_srl_reg ),
        .I4(\n_1_MU_SRL[11].mu_srl_reg ),
        .I40(\n_13_MU_SRL[11].mu_srl_reg ),
        .I41(\n_13_MU_SRL[7].mu_srl_reg ),
        .I42(\n_13_MU_SRL[3].mu_srl_reg ),
        .I43(\n_14_MU_SRL[11].mu_srl_reg ),
        .I44(\n_14_MU_SRL[7].mu_srl_reg ),
        .I45(\n_14_MU_SRL[3].mu_srl_reg ),
        .I46(\n_15_MU_SRL[11].mu_srl_reg ),
        .I47(\n_15_MU_SRL[7].mu_srl_reg ),
        .I48(\n_15_MU_SRL[3].mu_srl_reg ),
        .I49(s_dclk),
        .I5(\n_1_MU_SRL[7].mu_srl_reg ),
        .I6(\n_1_MU_SRL[3].mu_srl_reg ),
        .I7(\n_2_MU_SRL[11].mu_srl_reg ),
        .I8(\n_2_MU_SRL[7].mu_srl_reg ),
        .I9(\n_2_MU_SRL[3].mu_srl_reg ),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[12]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[12]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .shift_en_o(mu_config_cs_shift_en[12]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized1 \MU_SRL[1].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[1]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[1]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4097]_2 ),
        .shift_en_o(mu_config_cs_shift_en[1]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized2 \MU_SRL[2].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[2]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[2]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4098]_3 ),
        .shift_en_o(mu_config_cs_shift_en[2]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized3 \MU_SRL[3].mu_srl_reg 
       (.E(den),
        .I1(\slaveRegDo_muConfig[4097]_2 ),
        .I2(\slaveRegDo_muConfig[4096]_1 ),
        .I3(s_dclk),
        .O1(\n_0_MU_SRL[3].mu_srl_reg ),
        .O10(\n_9_MU_SRL[3].mu_srl_reg ),
        .O11(\n_10_MU_SRL[3].mu_srl_reg ),
        .O12(\n_11_MU_SRL[3].mu_srl_reg ),
        .O13(\n_12_MU_SRL[3].mu_srl_reg ),
        .O14(\n_13_MU_SRL[3].mu_srl_reg ),
        .O15(\n_14_MU_SRL[3].mu_srl_reg ),
        .O16(\n_15_MU_SRL[3].mu_srl_reg ),
        .O2(\n_1_MU_SRL[3].mu_srl_reg ),
        .O3(\n_2_MU_SRL[3].mu_srl_reg ),
        .O4(\n_3_MU_SRL[3].mu_srl_reg ),
        .O5(\n_4_MU_SRL[3].mu_srl_reg ),
        .O6(\n_5_MU_SRL[3].mu_srl_reg ),
        .O7(\n_6_MU_SRL[3].mu_srl_reg ),
        .O8(\n_7_MU_SRL[3].mu_srl_reg ),
        .O9(\n_8_MU_SRL[3].mu_srl_reg ),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[3]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[3]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4098]_3 ),
        .shift_en_o(mu_config_cs_shift_en[3]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized4 \MU_SRL[4].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[4]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[4]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4100]_5 ),
        .shift_en_o(mu_config_cs_shift_en[4]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized5 \MU_SRL[5].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[5]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[5]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4101]_6 ),
        .shift_en_o(mu_config_cs_shift_en[5]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized6 \MU_SRL[6].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[6]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[6]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4102]_7 ),
        .shift_en_o(mu_config_cs_shift_en[6]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized7 \MU_SRL[7].mu_srl_reg 
       (.E(den),
        .I1(\slaveRegDo_muConfig[4101]_6 ),
        .I2(\slaveRegDo_muConfig[4100]_5 ),
        .I3(s_dclk),
        .O1(\n_0_MU_SRL[7].mu_srl_reg ),
        .O10(\n_9_MU_SRL[7].mu_srl_reg ),
        .O11(\n_10_MU_SRL[7].mu_srl_reg ),
        .O12(\n_11_MU_SRL[7].mu_srl_reg ),
        .O13(\n_12_MU_SRL[7].mu_srl_reg ),
        .O14(\n_13_MU_SRL[7].mu_srl_reg ),
        .O15(\n_14_MU_SRL[7].mu_srl_reg ),
        .O16(\n_15_MU_SRL[7].mu_srl_reg ),
        .O2(\n_1_MU_SRL[7].mu_srl_reg ),
        .O3(\n_2_MU_SRL[7].mu_srl_reg ),
        .O4(\n_3_MU_SRL[7].mu_srl_reg ),
        .O5(\n_4_MU_SRL[7].mu_srl_reg ),
        .O6(\n_5_MU_SRL[7].mu_srl_reg ),
        .O7(\n_6_MU_SRL[7].mu_srl_reg ),
        .O8(\n_7_MU_SRL[7].mu_srl_reg ),
        .O9(\n_8_MU_SRL[7].mu_srl_reg ),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[7]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[7]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4102]_7 ),
        .shift_en_o(mu_config_cs_shift_en[7]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized8 \MU_SRL[8].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[8]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[8]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4104]_9 ),
        .shift_en_o(mu_config_cs_shift_en[8]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized9 \MU_SRL[9].mu_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[9]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[9]),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_muConfig[4105]_10 ),
        .shift_en_o(mu_config_cs_shift_en[9]));
ila_0_xsdbs_v1_0_reg__parameterized54 \MU_STATUS[10].mu_tpid_reg 
       (.D({p_0_in[13],p_0_in[11],p_0_in[9],p_0_in[7:6],p_0_in[4]}),
        .E(den),
        .I1(\n_0_slaveRegDo_mux_0[15]_i_6 ),
        .I10(n_12_reg_1a),
        .I11(n_2_reg_19),
        .I12(n_1_reg_4),
        .I13(n_13_reg_1a),
        .I14(n_40_reg_2),
        .I15(n_5_reg_83),
        .I16(n_0_reg_4),
        .I17(n_14_reg_1a),
        .I18(n_39_reg_2),
        .I19(n_6_reg_83),
        .I2(n_4_reg_4),
        .I20(n_0_reg_6),
        .I21(n_43_reg_2),
        .I22(n_1_reg_83),
        .I23(n_1_reg_f),
        .I24(\n_0_MU_STATUS[12].mu_tpid_reg ),
        .I25(\n_14_MU_STATUS[7].mu_tpid_reg ),
        .I26(\n_0_slaveRegDo_mux_1[15]_i_5 ),
        .I27(n_25_reg_4),
        .I28(n_45_reg_2),
        .I29(\n_12_MU_STATUS[7].mu_tpid_reg ),
        .I3(n_8_reg_1a),
        .I30(n_26_reg_4),
        .I31(n_47_reg_2),
        .I32(\n_10_MU_STATUS[7].mu_tpid_reg ),
        .I33(n_27_reg_4),
        .I34(n_48_reg_2),
        .I35(\n_9_MU_STATUS[7].mu_tpid_reg ),
        .I36(\n_0_MU_STATUS[1].mu_width_reg ),
        .I37(n_49_reg_2),
        .I38(\n_8_MU_STATUS[7].mu_tpid_reg ),
        .I39(n_28_reg_4),
        .I4(n_1_reg_19),
        .I40(n_52_reg_2),
        .I41(\n_6_MU_STATUS[7].mu_tpid_reg ),
        .I42(n_29_reg_4),
        .I43(\n_1_MU_STATUS[12].mu_tpid_reg ),
        .I44(\n_5_MU_STATUS[7].mu_tpid_reg ),
        .I45(n_30_reg_4),
        .I46(n_54_reg_2),
        .I47(\n_3_MU_STATUS[7].mu_tpid_reg ),
        .I48(n_31_reg_4),
        .I49(n_55_reg_2),
        .I5(n_3_reg_4),
        .I50(\n_2_MU_STATUS[7].mu_tpid_reg ),
        .I51(\n_1_MU_STATUS[1].mu_width_reg ),
        .I52(n_56_reg_2),
        .I53(\n_1_MU_STATUS[7].mu_tpid_reg ),
        .I54(n_32_reg_4),
        .I55(n_57_reg_2),
        .I56(\n_0_MU_STATUS[7].mu_tpid_reg ),
        .I57(n_33_reg_4),
        .I58(n_53_reg_2),
        .I59(\n_4_MU_STATUS[7].mu_tpid_reg ),
        .I6(n_10_reg_1a),
        .I60(\n_18_MU_STATUS[1].mu_width_reg ),
        .I61(n_50_reg_2),
        .I62(\n_7_MU_STATUS[7].mu_tpid_reg ),
        .I63(n_34_reg_4),
        .I64(n_46_reg_2),
        .I65(\n_11_MU_STATUS[7].mu_tpid_reg ),
        .I66(n_35_reg_4),
        .I67(n_44_reg_2),
        .I68(\n_13_MU_STATUS[7].mu_tpid_reg ),
        .I69(n_36_reg_4),
        .I7(n_42_reg_2),
        .I70(n_51_reg_2),
        .I71(\n_15_MU_STATUS[7].mu_tpid_reg ),
        .I72(\n_15_MU_STATUS[11].mu_tpid_reg ),
        .I73(\n_14_MU_STATUS[11].mu_tpid_reg ),
        .I74(\n_13_MU_STATUS[11].mu_tpid_reg ),
        .I75(\n_12_MU_STATUS[11].mu_tpid_reg ),
        .I76(\n_11_MU_STATUS[11].mu_tpid_reg ),
        .I77(\n_10_MU_STATUS[11].mu_tpid_reg ),
        .I78(\n_9_MU_STATUS[11].mu_tpid_reg ),
        .I79(\n_8_MU_STATUS[11].mu_tpid_reg ),
        .I8(n_3_reg_83),
        .I80(\n_6_MU_STATUS[11].mu_tpid_reg ),
        .I81(\n_5_MU_STATUS[11].mu_tpid_reg ),
        .I82(\n_4_MU_STATUS[11].mu_tpid_reg ),
        .I83(\n_3_MU_STATUS[11].mu_tpid_reg ),
        .I84(\n_2_MU_STATUS[11].mu_tpid_reg ),
        .I85(\n_1_MU_STATUS[11].mu_tpid_reg ),
        .I86(\n_0_MU_STATUS[11].mu_tpid_reg ),
        .I87({\n_0_MU_STATUS[8].mu_tpid_reg ,\n_1_MU_STATUS[8].mu_tpid_reg ,\n_2_MU_STATUS[8].mu_tpid_reg ,\n_3_MU_STATUS[8].mu_tpid_reg ,\n_4_MU_STATUS[8].mu_tpid_reg ,\n_5_MU_STATUS[8].mu_tpid_reg ,\n_6_MU_STATUS[8].mu_tpid_reg ,\n_7_MU_STATUS[8].mu_tpid_reg ,\n_8_MU_STATUS[8].mu_tpid_reg ,\n_9_MU_STATUS[8].mu_tpid_reg ,\n_10_MU_STATUS[8].mu_tpid_reg ,\n_11_MU_STATUS[8].mu_tpid_reg ,\n_12_MU_STATUS[8].mu_tpid_reg ,\n_13_MU_STATUS[8].mu_tpid_reg ,\n_14_MU_STATUS[8].mu_tpid_reg ,\n_15_MU_STATUS[8].mu_tpid_reg }),
        .I88(\n_7_MU_STATUS[11].mu_tpid_reg ),
        .I89(s_dclk),
        .I9(n_2_reg_4),
        .O1({\n_6_MU_STATUS[10].mu_tpid_reg ,\n_7_MU_STATUS[10].mu_tpid_reg ,\n_8_MU_STATUS[10].mu_tpid_reg ,\n_9_MU_STATUS[10].mu_tpid_reg ,\n_10_MU_STATUS[10].mu_tpid_reg ,\n_11_MU_STATUS[10].mu_tpid_reg ,\n_12_MU_STATUS[10].mu_tpid_reg ,\n_13_MU_STATUS[10].mu_tpid_reg ,\n_14_MU_STATUS[10].mu_tpid_reg ,\n_15_MU_STATUS[10].mu_tpid_reg ,\n_16_MU_STATUS[10].mu_tpid_reg ,\n_17_MU_STATUS[10].mu_tpid_reg ,\n_18_MU_STATUS[10].mu_tpid_reg ,\n_19_MU_STATUS[10].mu_tpid_reg ,\n_20_MU_STATUS[10].mu_tpid_reg }),
        .O2(\n_21_MU_STATUS[10].mu_tpid_reg ),
        .Q({\n_0_MU_STATUS[2].mu_tpid_reg ,\n_1_MU_STATUS[2].mu_tpid_reg ,\n_2_MU_STATUS[2].mu_tpid_reg ,\n_3_MU_STATUS[2].mu_tpid_reg ,\n_4_MU_STATUS[2].mu_tpid_reg ,\n_5_MU_STATUS[2].mu_tpid_reg ,\n_6_MU_STATUS[2].mu_tpid_reg ,\n_7_MU_STATUS[2].mu_tpid_reg ,\n_8_MU_STATUS[2].mu_tpid_reg ,\n_9_MU_STATUS[2].mu_tpid_reg ,\n_10_MU_STATUS[2].mu_tpid_reg ,\n_11_MU_STATUS[2].mu_tpid_reg ,\n_12_MU_STATUS[2].mu_tpid_reg ,\n_13_MU_STATUS[2].mu_tpid_reg ,\n_14_MU_STATUS[2].mu_tpid_reg ,\n_15_MU_STATUS[2].mu_tpid_reg }),
        .s_daddr_o({n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2:1]}));
ila_0_xsdbs_v1_0_reg__parameterized56 \MU_STATUS[11].mu_tpid_reg 
       (.E(den),
        .I1({\n_0_MU_STATUS[3].mu_tpid_reg ,\n_1_MU_STATUS[3].mu_tpid_reg ,\n_2_MU_STATUS[3].mu_tpid_reg ,\n_3_MU_STATUS[3].mu_tpid_reg ,\n_4_MU_STATUS[3].mu_tpid_reg ,\n_5_MU_STATUS[3].mu_tpid_reg ,\n_6_MU_STATUS[3].mu_tpid_reg ,\n_7_MU_STATUS[3].mu_tpid_reg ,\n_8_MU_STATUS[3].mu_tpid_reg ,\n_9_MU_STATUS[3].mu_tpid_reg ,\n_10_MU_STATUS[3].mu_tpid_reg ,\n_11_MU_STATUS[3].mu_tpid_reg ,\n_12_MU_STATUS[3].mu_tpid_reg ,\n_13_MU_STATUS[3].mu_tpid_reg ,\n_14_MU_STATUS[3].mu_tpid_reg ,\n_15_MU_STATUS[3].mu_tpid_reg }),
        .I2(s_dclk),
        .O1(\n_0_MU_STATUS[11].mu_tpid_reg ),
        .O10(\n_9_MU_STATUS[11].mu_tpid_reg ),
        .O11(\n_10_MU_STATUS[11].mu_tpid_reg ),
        .O12(\n_11_MU_STATUS[11].mu_tpid_reg ),
        .O13(\n_12_MU_STATUS[11].mu_tpid_reg ),
        .O14(\n_13_MU_STATUS[11].mu_tpid_reg ),
        .O15(\n_14_MU_STATUS[11].mu_tpid_reg ),
        .O16(\n_15_MU_STATUS[11].mu_tpid_reg ),
        .O2(\n_1_MU_STATUS[11].mu_tpid_reg ),
        .O3(\n_2_MU_STATUS[11].mu_tpid_reg ),
        .O4(\n_3_MU_STATUS[11].mu_tpid_reg ),
        .O5(\n_4_MU_STATUS[11].mu_tpid_reg ),
        .O6(\n_5_MU_STATUS[11].mu_tpid_reg ),
        .O7(\n_6_MU_STATUS[11].mu_tpid_reg ),
        .O8(\n_7_MU_STATUS[11].mu_tpid_reg ),
        .O9(\n_8_MU_STATUS[11].mu_tpid_reg ),
        .Q({\n_0_MU_STATUS[9].mu_tpid_reg ,\n_1_MU_STATUS[9].mu_tpid_reg ,\n_2_MU_STATUS[9].mu_tpid_reg ,\n_3_MU_STATUS[9].mu_tpid_reg ,\n_4_MU_STATUS[9].mu_tpid_reg ,\n_5_MU_STATUS[9].mu_tpid_reg ,\n_6_MU_STATUS[9].mu_tpid_reg ,\n_7_MU_STATUS[9].mu_tpid_reg ,\n_8_MU_STATUS[9].mu_tpid_reg ,\n_9_MU_STATUS[9].mu_tpid_reg ,\n_10_MU_STATUS[9].mu_tpid_reg ,\n_11_MU_STATUS[9].mu_tpid_reg ,\n_12_MU_STATUS[9].mu_tpid_reg ,\n_13_MU_STATUS[9].mu_tpid_reg ,\n_14_MU_STATUS[9].mu_tpid_reg ,\n_15_MU_STATUS[9].mu_tpid_reg }),
        .s_daddr_o({n_16_U_XSDB_SLAVE,s_daddr_o[2]}));
ila_0_xsdbs_v1_0_reg__parameterized58 \MU_STATUS[12].mu_tpid_reg 
       (.E(den),
        .I1(s_dclk),
        .O1(\n_0_MU_STATUS[12].mu_tpid_reg ),
        .O2(\n_1_MU_STATUS[12].mu_tpid_reg ),
        .O3({\n_2_MU_STATUS[12].mu_tpid_reg ,\n_3_MU_STATUS[12].mu_tpid_reg ,\n_4_MU_STATUS[12].mu_tpid_reg ,\n_5_MU_STATUS[12].mu_tpid_reg ,\n_6_MU_STATUS[12].mu_tpid_reg ,\n_7_MU_STATUS[12].mu_tpid_reg ,\n_8_MU_STATUS[12].mu_tpid_reg ,\n_9_MU_STATUS[12].mu_tpid_reg ,\n_10_MU_STATUS[12].mu_tpid_reg ,\n_11_MU_STATUS[12].mu_tpid_reg ,\n_12_MU_STATUS[12].mu_tpid_reg ,\n_13_MU_STATUS[12].mu_tpid_reg ,\n_14_MU_STATUS[12].mu_tpid_reg ,\n_15_MU_STATUS[12].mu_tpid_reg }),
        .Q({n_6_reg_2,n_16_reg_2}),
        .s_daddr_o({n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}));
ila_0_xsdbs_v1_0_reg__parameterized35 \MU_STATUS[1].mu_width_reg 
       (.E(den),
        .I1(n_34_reg_887),
        .I2(n_41_reg_887),
        .I3({n_11_reg_4,n_13_reg_4,n_19_reg_4}),
        .I4(n_44_reg_887),
        .I5(s_dclk),
        .O1(\n_0_MU_STATUS[1].mu_width_reg ),
        .O2(\n_1_MU_STATUS[1].mu_width_reg ),
        .O3(\n_18_MU_STATUS[1].mu_width_reg ),
        .Q({\n_2_MU_STATUS[1].mu_width_reg ,\n_3_MU_STATUS[1].mu_width_reg ,\n_4_MU_STATUS[1].mu_width_reg ,\n_5_MU_STATUS[1].mu_width_reg ,\n_6_MU_STATUS[1].mu_width_reg ,\n_7_MU_STATUS[1].mu_width_reg ,\n_8_MU_STATUS[1].mu_width_reg ,\n_9_MU_STATUS[1].mu_width_reg ,\n_10_MU_STATUS[1].mu_width_reg ,\n_11_MU_STATUS[1].mu_width_reg ,\n_12_MU_STATUS[1].mu_width_reg ,\n_13_MU_STATUS[1].mu_width_reg ,\n_14_MU_STATUS[1].mu_width_reg ,\n_15_MU_STATUS[1].mu_width_reg ,\n_16_MU_STATUS[1].mu_width_reg ,\n_17_MU_STATUS[1].mu_width_reg }),
        .s_daddr_o({n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2:1]}));
ila_0_xsdbs_v1_0_reg__parameterized38 \MU_STATUS[2].mu_tpid_reg 
       (.E(den),
        .I1(s_dclk),
        .Q({\n_0_MU_STATUS[2].mu_tpid_reg ,\n_1_MU_STATUS[2].mu_tpid_reg ,\n_2_MU_STATUS[2].mu_tpid_reg ,\n_3_MU_STATUS[2].mu_tpid_reg ,\n_4_MU_STATUS[2].mu_tpid_reg ,\n_5_MU_STATUS[2].mu_tpid_reg ,\n_6_MU_STATUS[2].mu_tpid_reg ,\n_7_MU_STATUS[2].mu_tpid_reg ,\n_8_MU_STATUS[2].mu_tpid_reg ,\n_9_MU_STATUS[2].mu_tpid_reg ,\n_10_MU_STATUS[2].mu_tpid_reg ,\n_11_MU_STATUS[2].mu_tpid_reg ,\n_12_MU_STATUS[2].mu_tpid_reg ,\n_13_MU_STATUS[2].mu_tpid_reg ,\n_14_MU_STATUS[2].mu_tpid_reg ,\n_15_MU_STATUS[2].mu_tpid_reg }));
ila_0_xsdbs_v1_0_reg__parameterized40 \MU_STATUS[3].mu_tpid_reg 
       (.E(den),
        .I1(s_dclk),
        .Q({\n_0_MU_STATUS[3].mu_tpid_reg ,\n_1_MU_STATUS[3].mu_tpid_reg ,\n_2_MU_STATUS[3].mu_tpid_reg ,\n_3_MU_STATUS[3].mu_tpid_reg ,\n_4_MU_STATUS[3].mu_tpid_reg ,\n_5_MU_STATUS[3].mu_tpid_reg ,\n_6_MU_STATUS[3].mu_tpid_reg ,\n_7_MU_STATUS[3].mu_tpid_reg ,\n_8_MU_STATUS[3].mu_tpid_reg ,\n_9_MU_STATUS[3].mu_tpid_reg ,\n_10_MU_STATUS[3].mu_tpid_reg ,\n_11_MU_STATUS[3].mu_tpid_reg ,\n_12_MU_STATUS[3].mu_tpid_reg ,\n_13_MU_STATUS[3].mu_tpid_reg ,\n_14_MU_STATUS[3].mu_tpid_reg ,\n_15_MU_STATUS[3].mu_tpid_reg }));
ila_0_xsdbs_v1_0_reg__parameterized44 \MU_STATUS[5].mu_tpid_reg 
       (.E(den),
        .I1(s_dclk),
        .Q({\n_0_MU_STATUS[5].mu_tpid_reg ,\n_1_MU_STATUS[5].mu_tpid_reg ,\n_2_MU_STATUS[5].mu_tpid_reg ,\n_3_MU_STATUS[5].mu_tpid_reg ,\n_4_MU_STATUS[5].mu_tpid_reg ,\n_5_MU_STATUS[5].mu_tpid_reg ,\n_6_MU_STATUS[5].mu_tpid_reg ,\n_7_MU_STATUS[5].mu_tpid_reg ,\n_8_MU_STATUS[5].mu_tpid_reg ,\n_9_MU_STATUS[5].mu_tpid_reg ,\n_10_MU_STATUS[5].mu_tpid_reg ,\n_11_MU_STATUS[5].mu_tpid_reg ,\n_12_MU_STATUS[5].mu_tpid_reg ,\n_13_MU_STATUS[5].mu_tpid_reg ,\n_14_MU_STATUS[5].mu_tpid_reg ,\n_15_MU_STATUS[5].mu_tpid_reg }));
ila_0_xsdbs_v1_0_reg__parameterized46 \MU_STATUS[6].mu_tpid_reg 
       (.E(den),
        .I1(s_dclk),
        .Q({\n_0_MU_STATUS[6].mu_tpid_reg ,\n_1_MU_STATUS[6].mu_tpid_reg ,\n_2_MU_STATUS[6].mu_tpid_reg ,\n_3_MU_STATUS[6].mu_tpid_reg ,\n_4_MU_STATUS[6].mu_tpid_reg ,\n_5_MU_STATUS[6].mu_tpid_reg ,\n_6_MU_STATUS[6].mu_tpid_reg ,\n_7_MU_STATUS[6].mu_tpid_reg ,\n_8_MU_STATUS[6].mu_tpid_reg ,\n_9_MU_STATUS[6].mu_tpid_reg ,\n_10_MU_STATUS[6].mu_tpid_reg ,\n_11_MU_STATUS[6].mu_tpid_reg ,\n_12_MU_STATUS[6].mu_tpid_reg ,\n_13_MU_STATUS[6].mu_tpid_reg ,\n_14_MU_STATUS[6].mu_tpid_reg ,\n_15_MU_STATUS[6].mu_tpid_reg }));
ila_0_xsdbs_v1_0_reg__parameterized48 \MU_STATUS[7].mu_tpid_reg 
       (.E(den),
        .I1(n_0_reg_887),
        .I10(n_8_reg_887),
        .I11(n_9_reg_887),
        .I12(n_10_reg_887),
        .I13(n_11_reg_887),
        .I14(n_12_reg_887),
        .I15(n_13_reg_887),
        .I16(n_14_reg_887),
        .I17(\n_7_MU_STATUS[5].mu_tpid_reg ),
        .I18(n_37_reg_887),
        .I19(s_dclk),
        .I2(\n_0_slaveRegDo_mux_1[15]_i_10 ),
        .I3(n_1_reg_887),
        .I4(n_2_reg_887),
        .I5(n_3_reg_887),
        .I6(n_4_reg_887),
        .I7(n_5_reg_887),
        .I8(n_6_reg_887),
        .I9(n_7_reg_887),
        .O1(\n_0_MU_STATUS[7].mu_tpid_reg ),
        .O10(\n_9_MU_STATUS[7].mu_tpid_reg ),
        .O11(\n_10_MU_STATUS[7].mu_tpid_reg ),
        .O12(\n_11_MU_STATUS[7].mu_tpid_reg ),
        .O13(\n_12_MU_STATUS[7].mu_tpid_reg ),
        .O14(\n_13_MU_STATUS[7].mu_tpid_reg ),
        .O15(\n_14_MU_STATUS[7].mu_tpid_reg ),
        .O16(\n_15_MU_STATUS[7].mu_tpid_reg ),
        .O2(\n_1_MU_STATUS[7].mu_tpid_reg ),
        .O3(\n_2_MU_STATUS[7].mu_tpid_reg ),
        .O4(\n_3_MU_STATUS[7].mu_tpid_reg ),
        .O5(\n_4_MU_STATUS[7].mu_tpid_reg ),
        .O6(\n_5_MU_STATUS[7].mu_tpid_reg ),
        .O7(\n_6_MU_STATUS[7].mu_tpid_reg ),
        .O8(\n_7_MU_STATUS[7].mu_tpid_reg ),
        .O9(\n_8_MU_STATUS[7].mu_tpid_reg ),
        .Q({\n_0_MU_STATUS[6].mu_tpid_reg ,\n_1_MU_STATUS[6].mu_tpid_reg ,\n_2_MU_STATUS[6].mu_tpid_reg ,\n_3_MU_STATUS[6].mu_tpid_reg ,\n_4_MU_STATUS[6].mu_tpid_reg ,\n_5_MU_STATUS[6].mu_tpid_reg ,\n_6_MU_STATUS[6].mu_tpid_reg ,\n_7_MU_STATUS[6].mu_tpid_reg ,\n_8_MU_STATUS[6].mu_tpid_reg ,\n_9_MU_STATUS[6].mu_tpid_reg ,\n_10_MU_STATUS[6].mu_tpid_reg ,\n_11_MU_STATUS[6].mu_tpid_reg ,\n_12_MU_STATUS[6].mu_tpid_reg ,\n_13_MU_STATUS[6].mu_tpid_reg ,\n_14_MU_STATUS[6].mu_tpid_reg ,\n_15_MU_STATUS[6].mu_tpid_reg }),
        .s_daddr_o(s_daddr_o[2:1]));
ila_0_xsdbs_v1_0_reg__parameterized50 \MU_STATUS[8].mu_tpid_reg 
       (.E(den),
        .I1(s_dclk),
        .Q({\n_0_MU_STATUS[8].mu_tpid_reg ,\n_1_MU_STATUS[8].mu_tpid_reg ,\n_2_MU_STATUS[8].mu_tpid_reg ,\n_3_MU_STATUS[8].mu_tpid_reg ,\n_4_MU_STATUS[8].mu_tpid_reg ,\n_5_MU_STATUS[8].mu_tpid_reg ,\n_6_MU_STATUS[8].mu_tpid_reg ,\n_7_MU_STATUS[8].mu_tpid_reg ,\n_8_MU_STATUS[8].mu_tpid_reg ,\n_9_MU_STATUS[8].mu_tpid_reg ,\n_10_MU_STATUS[8].mu_tpid_reg ,\n_11_MU_STATUS[8].mu_tpid_reg ,\n_12_MU_STATUS[8].mu_tpid_reg ,\n_13_MU_STATUS[8].mu_tpid_reg ,\n_14_MU_STATUS[8].mu_tpid_reg ,\n_15_MU_STATUS[8].mu_tpid_reg }));
ila_0_xsdbs_v1_0_reg__parameterized52 \MU_STATUS[9].mu_tpid_reg 
       (.E(den),
        .I1(s_dclk),
        .Q({\n_0_MU_STATUS[9].mu_tpid_reg ,\n_1_MU_STATUS[9].mu_tpid_reg ,\n_2_MU_STATUS[9].mu_tpid_reg ,\n_3_MU_STATUS[9].mu_tpid_reg ,\n_4_MU_STATUS[9].mu_tpid_reg ,\n_5_MU_STATUS[9].mu_tpid_reg ,\n_6_MU_STATUS[9].mu_tpid_reg ,\n_7_MU_STATUS[9].mu_tpid_reg ,\n_8_MU_STATUS[9].mu_tpid_reg ,\n_9_MU_STATUS[9].mu_tpid_reg ,\n_10_MU_STATUS[9].mu_tpid_reg ,\n_11_MU_STATUS[9].mu_tpid_reg ,\n_12_MU_STATUS[9].mu_tpid_reg ,\n_13_MU_STATUS[9].mu_tpid_reg ,\n_14_MU_STATUS[9].mu_tpid_reg ,\n_15_MU_STATUS[9].mu_tpid_reg }));
ila_0_xsdbs_v1_0_reg_p2s__parameterized13 \TC_SRL[0].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5120]_14 ),
        .shift_en_o(tc_config_cs_shift_en[0]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[0]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[0]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized23 \TC_SRL[10].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5130]_24 ),
        .shift_en_o(tc_config_cs_shift_en[10]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[10]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[10]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized24 \TC_SRL[11].tc_srl_reg 
       (.E(den),
        .I1(\n_0_TC_SRL[15].tc_srl_reg ),
        .I10(\n_8_TC_SRL[15].tc_srl_reg ),
        .I11(\n_9_TC_SRL[15].tc_srl_reg ),
        .I12(\n_10_TC_SRL[15].tc_srl_reg ),
        .I13(\n_11_TC_SRL[15].tc_srl_reg ),
        .I14(\n_12_TC_SRL[15].tc_srl_reg ),
        .I15(\n_13_TC_SRL[15].tc_srl_reg ),
        .I16(\n_14_TC_SRL[15].tc_srl_reg ),
        .I17(\n_15_TC_SRL[15].tc_srl_reg ),
        .I18(s_dclk),
        .I2(\slaveRegDo_tcConfig[5128]_22 ),
        .I3(\n_1_TC_SRL[15].tc_srl_reg ),
        .I4(\n_2_TC_SRL[15].tc_srl_reg ),
        .I5(\n_3_TC_SRL[15].tc_srl_reg ),
        .I6(\n_4_TC_SRL[15].tc_srl_reg ),
        .I7(\n_5_TC_SRL[15].tc_srl_reg ),
        .I8(\n_6_TC_SRL[15].tc_srl_reg ),
        .I9(\n_7_TC_SRL[15].tc_srl_reg ),
        .O1(\n_0_TC_SRL[11].tc_srl_reg ),
        .O10(\n_9_TC_SRL[11].tc_srl_reg ),
        .O11(\n_10_TC_SRL[11].tc_srl_reg ),
        .O12(\n_11_TC_SRL[11].tc_srl_reg ),
        .O13(\n_12_TC_SRL[11].tc_srl_reg ),
        .O14(\n_13_TC_SRL[11].tc_srl_reg ),
        .O15(\n_14_TC_SRL[11].tc_srl_reg ),
        .O16(\n_15_TC_SRL[11].tc_srl_reg ),
        .O2(\n_1_TC_SRL[11].tc_srl_reg ),
        .O3(\n_2_TC_SRL[11].tc_srl_reg ),
        .O4(\n_3_TC_SRL[11].tc_srl_reg ),
        .O5(\n_4_TC_SRL[11].tc_srl_reg ),
        .O6(\n_5_TC_SRL[11].tc_srl_reg ),
        .O7(\n_6_TC_SRL[11].tc_srl_reg ),
        .O8(\n_7_TC_SRL[11].tc_srl_reg ),
        .O9(\n_8_TC_SRL[11].tc_srl_reg ),
        .Q(\slaveRegDo_tcConfig[5129]_23 ),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5130]_24 ),
        .shift_en_o(tc_config_cs_shift_en[11]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[11]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[11]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized25 \TC_SRL[12].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5132]_26 ),
        .shift_en_o(tc_config_cs_shift_en[12]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[12]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[12]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized26 \TC_SRL[13].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5133]_27 ),
        .shift_en_o(tc_config_cs_shift_en[13]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[13]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[13]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized27 \TC_SRL[14].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5134]_28 ),
        .shift_en_o(tc_config_cs_shift_en[14]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[14]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[14]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized28 \TC_SRL[15].tc_srl_reg 
       (.E(den),
        .I1(\slaveRegDo_tcConfig[5133]_27 ),
        .I2(\slaveRegDo_tcConfig[5132]_26 ),
        .I3(s_dclk),
        .O1(\n_0_TC_SRL[15].tc_srl_reg ),
        .O10(\n_9_TC_SRL[15].tc_srl_reg ),
        .O11(\n_10_TC_SRL[15].tc_srl_reg ),
        .O12(\n_11_TC_SRL[15].tc_srl_reg ),
        .O13(\n_12_TC_SRL[15].tc_srl_reg ),
        .O14(\n_13_TC_SRL[15].tc_srl_reg ),
        .O15(\n_14_TC_SRL[15].tc_srl_reg ),
        .O16(\n_15_TC_SRL[15].tc_srl_reg ),
        .O2(\n_1_TC_SRL[15].tc_srl_reg ),
        .O3(\n_2_TC_SRL[15].tc_srl_reg ),
        .O4(\n_3_TC_SRL[15].tc_srl_reg ),
        .O5(\n_4_TC_SRL[15].tc_srl_reg ),
        .O6(\n_5_TC_SRL[15].tc_srl_reg ),
        .O7(\n_6_TC_SRL[15].tc_srl_reg ),
        .O8(\n_7_TC_SRL[15].tc_srl_reg ),
        .O9(\n_8_TC_SRL[15].tc_srl_reg ),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5134]_28 ),
        .shift_en_o(tc_config_cs_shift_en[15]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[15]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[15]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized29 \TC_SRL[16].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5136]_30 ),
        .shift_en_o(tc_config_cs_shift_en[16]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[16]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[16]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized30 \TC_SRL[17].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5137]_31 ),
        .shift_en_o(tc_config_cs_shift_en[17]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[17]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[17]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized31 \TC_SRL[18].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5138]_32 ),
        .shift_en_o(tc_config_cs_shift_en[18]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[18]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[18]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized32 \TC_SRL[19].tc_srl_reg 
       (.E(den),
        .I1(\n_0_TC_SRL[23].tc_srl_reg ),
        .I10(\n_7_TC_SRL[23].tc_srl_reg ),
        .I11(\n_8_TC_SRL[23].tc_srl_reg ),
        .I12(\n_9_TC_SRL[23].tc_srl_reg ),
        .I13(\n_10_TC_SRL[23].tc_srl_reg ),
        .I14(\n_11_TC_SRL[23].tc_srl_reg ),
        .I15(\n_12_TC_SRL[23].tc_srl_reg ),
        .I16(\n_13_TC_SRL[23].tc_srl_reg ),
        .I17(\n_14_TC_SRL[23].tc_srl_reg ),
        .I18(\n_15_TC_SRL[23].tc_srl_reg ),
        .I19(s_dclk),
        .I2(\slaveRegDo_tcConfig[5137]_31 ),
        .I3(\slaveRegDo_tcConfig[5136]_30 ),
        .I4(\n_1_TC_SRL[23].tc_srl_reg ),
        .I5(\n_2_TC_SRL[23].tc_srl_reg ),
        .I6(\n_3_TC_SRL[23].tc_srl_reg ),
        .I7(\n_4_TC_SRL[23].tc_srl_reg ),
        .I8(\n_5_TC_SRL[23].tc_srl_reg ),
        .I9(\n_6_TC_SRL[23].tc_srl_reg ),
        .O1(\n_0_TC_SRL[19].tc_srl_reg ),
        .O10(\n_9_TC_SRL[19].tc_srl_reg ),
        .O11(\n_10_TC_SRL[19].tc_srl_reg ),
        .O12(\n_11_TC_SRL[19].tc_srl_reg ),
        .O13(\n_12_TC_SRL[19].tc_srl_reg ),
        .O14(\n_13_TC_SRL[19].tc_srl_reg ),
        .O15(\n_14_TC_SRL[19].tc_srl_reg ),
        .O16(\n_15_TC_SRL[19].tc_srl_reg ),
        .O2(\n_1_TC_SRL[19].tc_srl_reg ),
        .O3(\n_2_TC_SRL[19].tc_srl_reg ),
        .O4(\n_3_TC_SRL[19].tc_srl_reg ),
        .O5(\n_4_TC_SRL[19].tc_srl_reg ),
        .O6(\n_5_TC_SRL[19].tc_srl_reg ),
        .O7(\n_6_TC_SRL[19].tc_srl_reg ),
        .O8(\n_7_TC_SRL[19].tc_srl_reg ),
        .O9(\n_8_TC_SRL[19].tc_srl_reg ),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5138]_32 ),
        .shift_en_o(tc_config_cs_shift_en[19]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[19]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[19]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized14 \TC_SRL[1].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5121]_15 ),
        .shift_en_o(tc_config_cs_shift_en[1]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[1]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[1]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized33 \TC_SRL[20].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5140]_34 ),
        .shift_en_o(tc_config_cs_shift_en[20]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[20]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[20]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized34 \TC_SRL[21].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5141]_35 ),
        .shift_en_o(tc_config_cs_shift_en[21]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[21]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[21]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized35 \TC_SRL[22].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5142]_36 ),
        .shift_en_o(tc_config_cs_shift_en[22]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[22]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[22]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized36 \TC_SRL[23].tc_srl_reg 
       (.E(den),
        .I1(\slaveRegDo_tcConfig[5141]_35 ),
        .I2(\slaveRegDo_tcConfig[5140]_34 ),
        .I3(s_dclk),
        .O1(\n_0_TC_SRL[23].tc_srl_reg ),
        .O10(\n_9_TC_SRL[23].tc_srl_reg ),
        .O11(\n_10_TC_SRL[23].tc_srl_reg ),
        .O12(\n_11_TC_SRL[23].tc_srl_reg ),
        .O13(\n_12_TC_SRL[23].tc_srl_reg ),
        .O14(\n_13_TC_SRL[23].tc_srl_reg ),
        .O15(\n_14_TC_SRL[23].tc_srl_reg ),
        .O16(\n_15_TC_SRL[23].tc_srl_reg ),
        .O2(\n_1_TC_SRL[23].tc_srl_reg ),
        .O3(\n_2_TC_SRL[23].tc_srl_reg ),
        .O4(\n_3_TC_SRL[23].tc_srl_reg ),
        .O5(\n_4_TC_SRL[23].tc_srl_reg ),
        .O6(\n_5_TC_SRL[23].tc_srl_reg ),
        .O7(\n_6_TC_SRL[23].tc_srl_reg ),
        .O8(\n_7_TC_SRL[23].tc_srl_reg ),
        .O9(\n_8_TC_SRL[23].tc_srl_reg ),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5142]_36 ),
        .shift_en_o(tc_config_cs_shift_en[23]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[23]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[23]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized37 \TC_SRL[24].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5144]_38 ),
        .shift_en_o(tc_config_cs_shift_en[24]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[24]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[24]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized38 \TC_SRL[25].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5145]_39 ),
        .shift_en_o(tc_config_cs_shift_en[25]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[25]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[25]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized39 \TC_SRL[26].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5146]_40 ),
        .shift_en_o(tc_config_cs_shift_en[26]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[26]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[26]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized40 \TC_SRL[27].tc_srl_reg 
       (.D({\n_0_TC_SRL[27].tc_srl_reg ,\n_1_TC_SRL[27].tc_srl_reg ,\n_2_TC_SRL[27].tc_srl_reg ,\n_3_TC_SRL[27].tc_srl_reg ,\n_4_TC_SRL[27].tc_srl_reg ,\n_5_TC_SRL[27].tc_srl_reg ,\n_6_TC_SRL[27].tc_srl_reg ,\n_7_TC_SRL[27].tc_srl_reg ,\n_8_TC_SRL[27].tc_srl_reg ,\n_9_TC_SRL[27].tc_srl_reg ,\n_10_TC_SRL[27].tc_srl_reg ,\n_11_TC_SRL[27].tc_srl_reg ,\n_12_TC_SRL[27].tc_srl_reg ,\n_13_TC_SRL[27].tc_srl_reg ,\n_14_TC_SRL[27].tc_srl_reg ,\n_15_TC_SRL[27].tc_srl_reg }),
        .E(den),
        .I1(\n_0_TC_SRL[19].tc_srl_reg ),
        .I10(\n_1_TC_SRL[31].tc_srl_reg ),
        .I11(\n_2_TC_SRL[19].tc_srl_reg ),
        .I12(\n_2_TC_SRL[11].tc_srl_reg ),
        .I13(\n_2_TC_SRL[3].tc_srl_reg ),
        .I14(\n_2_TC_SRL[31].tc_srl_reg ),
        .I15(\n_3_TC_SRL[19].tc_srl_reg ),
        .I16(\n_3_TC_SRL[11].tc_srl_reg ),
        .I17(\n_3_TC_SRL[3].tc_srl_reg ),
        .I18(\n_3_TC_SRL[31].tc_srl_reg ),
        .I19(\n_4_TC_SRL[19].tc_srl_reg ),
        .I2(\n_0_TC_SRL[11].tc_srl_reg ),
        .I20(\n_4_TC_SRL[11].tc_srl_reg ),
        .I21(\n_4_TC_SRL[3].tc_srl_reg ),
        .I22(\n_4_TC_SRL[31].tc_srl_reg ),
        .I23(\n_5_TC_SRL[19].tc_srl_reg ),
        .I24(\n_5_TC_SRL[11].tc_srl_reg ),
        .I25(\n_5_TC_SRL[3].tc_srl_reg ),
        .I26(\n_5_TC_SRL[31].tc_srl_reg ),
        .I27(\n_6_TC_SRL[19].tc_srl_reg ),
        .I28(\n_6_TC_SRL[11].tc_srl_reg ),
        .I29(\n_6_TC_SRL[3].tc_srl_reg ),
        .I3(\n_0_TC_SRL[3].tc_srl_reg ),
        .I30(\n_6_TC_SRL[31].tc_srl_reg ),
        .I31(\n_7_TC_SRL[19].tc_srl_reg ),
        .I32(\n_7_TC_SRL[11].tc_srl_reg ),
        .I33(\n_7_TC_SRL[3].tc_srl_reg ),
        .I34(\n_7_TC_SRL[31].tc_srl_reg ),
        .I35(\n_8_TC_SRL[19].tc_srl_reg ),
        .I36(\n_8_TC_SRL[11].tc_srl_reg ),
        .I37(\n_8_TC_SRL[3].tc_srl_reg ),
        .I38(\n_8_TC_SRL[31].tc_srl_reg ),
        .I39(\n_9_TC_SRL[19].tc_srl_reg ),
        .I4(\n_0_TC_SRL[31].tc_srl_reg ),
        .I40(\n_9_TC_SRL[11].tc_srl_reg ),
        .I41(\n_9_TC_SRL[3].tc_srl_reg ),
        .I42(\n_9_TC_SRL[31].tc_srl_reg ),
        .I43(\n_10_TC_SRL[19].tc_srl_reg ),
        .I44(\n_10_TC_SRL[11].tc_srl_reg ),
        .I45(\n_10_TC_SRL[3].tc_srl_reg ),
        .I46(\n_10_TC_SRL[31].tc_srl_reg ),
        .I47(\n_11_TC_SRL[19].tc_srl_reg ),
        .I48(\n_11_TC_SRL[11].tc_srl_reg ),
        .I49(\n_11_TC_SRL[3].tc_srl_reg ),
        .I5(\slaveRegDo_tcConfig[5145]_39 ),
        .I50(\n_11_TC_SRL[31].tc_srl_reg ),
        .I51(\n_12_TC_SRL[19].tc_srl_reg ),
        .I52(\n_12_TC_SRL[11].tc_srl_reg ),
        .I53(\n_12_TC_SRL[3].tc_srl_reg ),
        .I54(\n_12_TC_SRL[31].tc_srl_reg ),
        .I55(\n_13_TC_SRL[19].tc_srl_reg ),
        .I56(\n_13_TC_SRL[11].tc_srl_reg ),
        .I57(\n_13_TC_SRL[3].tc_srl_reg ),
        .I58(\n_13_TC_SRL[31].tc_srl_reg ),
        .I59(\n_14_TC_SRL[19].tc_srl_reg ),
        .I6(\slaveRegDo_tcConfig[5144]_38 ),
        .I60(\n_14_TC_SRL[11].tc_srl_reg ),
        .I61(\n_14_TC_SRL[3].tc_srl_reg ),
        .I62(\n_14_TC_SRL[31].tc_srl_reg ),
        .I63(\n_15_TC_SRL[19].tc_srl_reg ),
        .I64(\n_15_TC_SRL[11].tc_srl_reg ),
        .I65(\n_15_TC_SRL[3].tc_srl_reg ),
        .I66(\n_15_TC_SRL[31].tc_srl_reg ),
        .I67(s_dclk),
        .I7(\n_1_TC_SRL[19].tc_srl_reg ),
        .I8(\n_1_TC_SRL[11].tc_srl_reg ),
        .I9(\n_1_TC_SRL[3].tc_srl_reg ),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5146]_40 ),
        .shift_en_o(tc_config_cs_shift_en[27]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[27]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[27]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized41 \TC_SRL[28].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5148]_42 ),
        .shift_en_o(tc_config_cs_shift_en[28]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[28]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[28]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized42 \TC_SRL[29].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5149]_43 ),
        .shift_en_o(tc_config_cs_shift_en[29]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[29]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[29]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized15 \TC_SRL[2].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5122]_16 ),
        .shift_en_o(tc_config_cs_shift_en[2]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[2]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[2]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized43 \TC_SRL[30].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5150]_44 ),
        .shift_en_o(tc_config_cs_shift_en[30]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[30]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[30]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized44 \TC_SRL[31].tc_srl_reg 
       (.E(den),
        .I1(\slaveRegDo_tcConfig[5149]_43 ),
        .I2(\slaveRegDo_tcConfig[5148]_42 ),
        .I3(s_dclk),
        .O1(\n_0_TC_SRL[31].tc_srl_reg ),
        .O10(\n_9_TC_SRL[31].tc_srl_reg ),
        .O11(\n_10_TC_SRL[31].tc_srl_reg ),
        .O12(\n_11_TC_SRL[31].tc_srl_reg ),
        .O13(\n_12_TC_SRL[31].tc_srl_reg ),
        .O14(\n_13_TC_SRL[31].tc_srl_reg ),
        .O15(\n_14_TC_SRL[31].tc_srl_reg ),
        .O16(\n_15_TC_SRL[31].tc_srl_reg ),
        .O2(\n_1_TC_SRL[31].tc_srl_reg ),
        .O3(\n_2_TC_SRL[31].tc_srl_reg ),
        .O4(\n_3_TC_SRL[31].tc_srl_reg ),
        .O5(\n_4_TC_SRL[31].tc_srl_reg ),
        .O6(\n_5_TC_SRL[31].tc_srl_reg ),
        .O7(\n_6_TC_SRL[31].tc_srl_reg ),
        .O8(\n_7_TC_SRL[31].tc_srl_reg ),
        .O9(\n_8_TC_SRL[31].tc_srl_reg ),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5150]_44 ),
        .shift_en_o(tc_config_cs_shift_en[31]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[31]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[31]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized16 \TC_SRL[3].tc_srl_reg 
       (.E(den),
        .I1(\n_0_TC_SRL[7].tc_srl_reg ),
        .I10(\n_7_TC_SRL[7].tc_srl_reg ),
        .I11(\n_8_TC_SRL[7].tc_srl_reg ),
        .I12(\n_9_TC_SRL[7].tc_srl_reg ),
        .I13(\n_10_TC_SRL[7].tc_srl_reg ),
        .I14(\n_11_TC_SRL[7].tc_srl_reg ),
        .I15(\n_12_TC_SRL[7].tc_srl_reg ),
        .I16(\n_13_TC_SRL[7].tc_srl_reg ),
        .I17(\n_14_TC_SRL[7].tc_srl_reg ),
        .I18(\n_15_TC_SRL[7].tc_srl_reg ),
        .I19(s_dclk),
        .I2(\slaveRegDo_tcConfig[5121]_15 ),
        .I3(\slaveRegDo_tcConfig[5120]_14 ),
        .I4(\n_1_TC_SRL[7].tc_srl_reg ),
        .I5(\n_2_TC_SRL[7].tc_srl_reg ),
        .I6(\n_3_TC_SRL[7].tc_srl_reg ),
        .I7(\n_4_TC_SRL[7].tc_srl_reg ),
        .I8(\n_5_TC_SRL[7].tc_srl_reg ),
        .I9(\n_6_TC_SRL[7].tc_srl_reg ),
        .O1(\n_0_TC_SRL[3].tc_srl_reg ),
        .O10(\n_9_TC_SRL[3].tc_srl_reg ),
        .O11(\n_10_TC_SRL[3].tc_srl_reg ),
        .O12(\n_11_TC_SRL[3].tc_srl_reg ),
        .O13(\n_12_TC_SRL[3].tc_srl_reg ),
        .O14(\n_13_TC_SRL[3].tc_srl_reg ),
        .O15(\n_14_TC_SRL[3].tc_srl_reg ),
        .O16(\n_15_TC_SRL[3].tc_srl_reg ),
        .O2(\n_1_TC_SRL[3].tc_srl_reg ),
        .O3(\n_2_TC_SRL[3].tc_srl_reg ),
        .O4(\n_3_TC_SRL[3].tc_srl_reg ),
        .O5(\n_4_TC_SRL[3].tc_srl_reg ),
        .O6(\n_5_TC_SRL[3].tc_srl_reg ),
        .O7(\n_6_TC_SRL[3].tc_srl_reg ),
        .O8(\n_7_TC_SRL[3].tc_srl_reg ),
        .O9(\n_8_TC_SRL[3].tc_srl_reg ),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5122]_16 ),
        .shift_en_o(tc_config_cs_shift_en[3]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[3]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[3]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized17 \TC_SRL[4].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5124]_18 ),
        .shift_en_o(tc_config_cs_shift_en[4]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[4]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[4]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized18 \TC_SRL[5].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5125]_19 ),
        .shift_en_o(tc_config_cs_shift_en[5]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[5]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[5]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized19 \TC_SRL[6].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5126]_20 ),
        .shift_en_o(tc_config_cs_shift_en[6]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[6]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[6]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized20 \TC_SRL[7].tc_srl_reg 
       (.E(den),
        .I1(\slaveRegDo_tcConfig[5125]_19 ),
        .I2(\slaveRegDo_tcConfig[5124]_18 ),
        .I3(s_dclk),
        .O1(\n_0_TC_SRL[7].tc_srl_reg ),
        .O10(\n_9_TC_SRL[7].tc_srl_reg ),
        .O11(\n_10_TC_SRL[7].tc_srl_reg ),
        .O12(\n_11_TC_SRL[7].tc_srl_reg ),
        .O13(\n_12_TC_SRL[7].tc_srl_reg ),
        .O14(\n_13_TC_SRL[7].tc_srl_reg ),
        .O15(\n_14_TC_SRL[7].tc_srl_reg ),
        .O16(\n_15_TC_SRL[7].tc_srl_reg ),
        .O2(\n_1_TC_SRL[7].tc_srl_reg ),
        .O3(\n_2_TC_SRL[7].tc_srl_reg ),
        .O4(\n_3_TC_SRL[7].tc_srl_reg ),
        .O5(\n_4_TC_SRL[7].tc_srl_reg ),
        .O6(\n_5_TC_SRL[7].tc_srl_reg ),
        .O7(\n_6_TC_SRL[7].tc_srl_reg ),
        .O8(\n_7_TC_SRL[7].tc_srl_reg ),
        .O9(\n_8_TC_SRL[7].tc_srl_reg ),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5126]_20 ),
        .shift_en_o(tc_config_cs_shift_en[7]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[7]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[7]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized21 \TC_SRL[8].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5128]_22 ),
        .shift_en_o(tc_config_cs_shift_en[8]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[8]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[8]));
ila_0_xsdbs_v1_0_reg_p2s__parameterized22 \TC_SRL[9].tc_srl_reg 
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .s_do_o(\slaveRegDo_tcConfig[5129]_23 ),
        .shift_en_o(tc_config_cs_shift_en[9]),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[9]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[9]));
(* C_BUILD_REVISION = "0" *) 
   (* C_CORE_INFO1 = "0" *) 
   (* C_CORE_INFO2 = "0" *) 
   (* C_CORE_MAJOR_VER = "4" *) 
   (* C_CORE_MINOR_VER = "0" *) 
   (* C_CORE_TYPE = "1" *) 
   (* C_CSE_DRV_VER = "1" *) 
   (* C_MAJOR_VERSION = "2013" *) 
   (* C_MINOR_VERSION = "3" *) 
   (* C_NEXT_SLAVE = "0" *) 
   (* C_PIPE_IFACE = "1" *) 
   (* C_USE_TEST_REG = "1" *) 
   (* C_XDEVICEFAMILY = "artix7" *) 
   (* C_XSDB_SLAVE_TYPE = "17" *) 
   (* DONT_TOUCH *) 
   ila_0_xsdbs_v1_0_xsdbs U_XSDB_SLAVE
       (.s_daddr_o({n_4_U_XSDB_SLAVE,n_5_U_XSDB_SLAVE,n_6_U_XSDB_SLAVE,n_7_U_XSDB_SLAVE,n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_dclk_o(s_dclk),
        .s_den_o(den),
        .s_di_o(s_di),
        .s_do_i({\n_0_slaveRegDo_mux_reg[15] ,\n_0_slaveRegDo_mux_reg[14] ,\n_0_slaveRegDo_mux_reg[13] ,\n_0_slaveRegDo_mux_reg[12] ,\n_0_slaveRegDo_mux_reg[11] ,\n_0_slaveRegDo_mux_reg[10] ,\n_0_slaveRegDo_mux_reg[9] ,\n_0_slaveRegDo_mux_reg[8] ,\n_0_slaveRegDo_mux_reg[7] ,\n_0_slaveRegDo_mux_reg[6] ,\n_0_slaveRegDo_mux_reg[5] ,\n_0_slaveRegDo_mux_reg[4] ,\n_0_slaveRegDo_mux_reg[3] ,\n_0_slaveRegDo_mux_reg[2] ,\n_0_slaveRegDo_mux_reg[1] ,\n_0_slaveRegDo_mux_reg[0] }),
        .s_drdy_i(n_0_regDrdy_reg),
        .s_dwe_o(dwe),
        .s_rst_o(s_rst),
        .sl_iport_i(SL_IPORT_I),
        .sl_oport_o(SL_OPORT_O));
FDRE adv_drdy_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(I1),
        .Q(adv_drdy),
        .R(1'b0));
FDRE adv_rb_drdy1_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(adv_rb_drdy),
        .Q(adv_rb_drdy1),
        .R(1'b0));
(* srl_name = "U0/\ila_core_inst/u_ila_regs/adv_rb_drdy3_reg_srl2 " *) 
   SRL16E adv_rb_drdy3_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(s_dclk),
        .D(adv_rb_drdy1),
        .Q(n_0_adv_rb_drdy3_reg_srl2));
FDRE adv_rb_drdy4_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_0_adv_rb_drdy3_reg_srl2),
        .Q(adv_rb_drdy4),
        .R(1'b0));
FDRE adv_rb_drdy_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(drdy_mux_ff1),
        .Q(adv_rb_drdy),
        .R(1'b0));
LUT6 #(
    .INIT(64'h4000000000000000)) 
     bram_en_i_2
       (.I0(config_fsm_addr[1]),
        .I1(config_fsm_addr[2]),
        .I2(config_fsm_addr[11]),
        .I3(config_fsm_we),
        .I4(config_fsm_addr[5]),
        .I5(config_fsm_addr[6]),
        .O(n_0_bram_en_i_2));
LUT6 #(
    .INIT(64'h0004000000000000)) 
     bram_rd_en_i_1
       (.I0(n_0_bram_rd_en_i_2),
        .I1(config_fsm_addr[3]),
        .I2(config_fsm_addr[13]),
        .I3(config_fsm_addr[14]),
        .I4(n_0_bram_rd_en_i_3),
        .I5(n_0_bram_rd_en_i_4),
        .O(bram_rd_en));
LUT4 #(
    .INIT(16'hFFFB)) 
     bram_rd_en_i_2
       (.I0(config_fsm_addr[16]),
        .I1(config_fsm_addr[7]),
        .I2(config_fsm_addr[15]),
        .I3(config_fsm_addr[12]),
        .O(n_0_bram_rd_en_i_2));
LUT6 #(
    .INIT(64'h0040000000000000)) 
     bram_rd_en_i_3
       (.I0(config_fsm_addr[2]),
        .I1(config_fsm_addr[1]),
        .I2(config_fsm_addr[11]),
        .I3(config_fsm_we),
        .I4(config_fsm_addr[5]),
        .I5(config_fsm_addr[6]),
        .O(n_0_bram_rd_en_i_3));
LUT6 #(
    .INIT(64'h8000000000000000)) 
     bram_rd_en_i_4
       (.I0(config_fsm_addr[10]),
        .I1(config_fsm_en_rb),
        .I2(config_fsm_addr[8]),
        .I3(config_fsm_addr[4]),
        .I4(config_fsm_addr[0]),
        .I5(config_fsm_addr[9]),
        .O(n_0_bram_rd_en_i_4));
LUT6 #(
    .INIT(64'h8000000000000000)) 
     \current_state[1]_i_2 
       (.I0(O2),
        .I1(n_10_U_XSDB_SLAVE),
        .I2(den),
        .I3(n_16_U_XSDB_SLAVE),
        .I4(n_15_U_XSDB_SLAVE),
        .I5(O3),
        .O(read_data_en));
(* SOFT_HLUTNM = "soft_lutpair251" *) 
   LUT4 #(
    .INIT(16'h8000)) 
     \current_state[6]_i_3 
       (.I0(n_14_U_XSDB_SLAVE),
        .I1(n_13_U_XSDB_SLAVE),
        .I2(n_12_U_XSDB_SLAVE),
        .I3(n_11_U_XSDB_SLAVE),
        .O(O3));
(* SOFT_HLUTNM = "soft_lutpair252" *) 
   LUT4 #(
    .INIT(16'h8000)) 
     \current_state[6]_i_4 
       (.I0(n_10_U_XSDB_SLAVE),
        .I1(den),
        .I2(n_16_U_XSDB_SLAVE),
        .I3(n_15_U_XSDB_SLAVE),
        .O(O16));
LUT6 #(
    .INIT(64'h0000400000000000)) 
     \current_state[6]_i_5 
       (.I0(n_8_U_XSDB_SLAVE),
        .I1(n_9_U_XSDB_SLAVE),
        .I2(s_daddr_o[2]),
        .I3(n_17_U_XSDB_SLAVE),
        .I4(s_daddr_o[0]),
        .I5(s_daddr_o[1]),
        .O(O2));
LUT6 #(
    .INIT(64'h00000000BABA000B)) 
     \drdyCount[0]_i_1 
       (.I0(den),
        .I1(drdyCount[0]),
        .I2(drdyCount[4]),
        .I3(drdyCount[5]),
        .I4(\n_0_drdyCount[0]_i_2 ),
        .I5(s_rst),
        .O(\n_0_drdyCount[0]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair248" *) 
   LUT4 #(
    .INIT(16'h0001)) 
     \drdyCount[0]_i_2 
       (.I0(drdyCount[1]),
        .I1(drdyCount[5]),
        .I2(drdyCount[3]),
        .I3(drdyCount[2]),
        .O(\n_0_drdyCount[0]_i_2 ));
LUT5 #(
    .INIT(32'h0000006A)) 
     \drdyCount[1]_i_1 
       (.I0(drdyCount[1]),
        .I1(\n_0_drdyCount[5]_i_2 ),
        .I2(drdyCount[0]),
        .I3(\n_0_drdyCount[5]_i_4 ),
        .I4(den),
        .O(\n_0_drdyCount[1]_i_1 ));
LUT6 #(
    .INIT(64'h0000000000006AAA)) 
     \drdyCount[2]_i_1 
       (.I0(drdyCount[2]),
        .I1(\n_0_drdyCount[5]_i_2 ),
        .I2(drdyCount[1]),
        .I3(drdyCount[0]),
        .I4(\n_0_drdyCount[5]_i_4 ),
        .I5(den),
        .O(\n_0_drdyCount[2]_i_1 ));
LUT5 #(
    .INIT(32'h0000006A)) 
     \drdyCount[3]_i_1 
       (.I0(drdyCount[3]),
        .I1(\n_0_drdyCount[5]_i_2 ),
        .I2(\n_0_drdyCount[3]_i_2 ),
        .I3(\n_0_drdyCount[5]_i_4 ),
        .I4(den),
        .O(\n_0_drdyCount[3]_i_1 ));
LUT3 #(
    .INIT(8'h80)) 
     \drdyCount[3]_i_2 
       (.I0(drdyCount[2]),
        .I1(drdyCount[0]),
        .I2(drdyCount[1]),
        .O(\n_0_drdyCount[3]_i_2 ));
LUT6 #(
    .INIT(64'h00000000FF6A006A)) 
     \drdyCount[4]_i_1 
       (.I0(drdyCount[4]),
        .I1(\n_0_drdyCount[5]_i_2 ),
        .I2(\n_0_drdyCount[5]_i_3 ),
        .I3(den),
        .I4(\n_0_drdyCount[4]_i_2 ),
        .I5(\n_0_drdyCount[5]_i_4 ),
        .O(\n_0_drdyCount[4]_i_1 ));
LUT6 #(
    .INIT(64'h4555555555555555)) 
     \drdyCount[4]_i_2 
       (.I0(n_8_U_XSDB_SLAVE),
        .I1(\n_0_drdyCount[4]_i_3 ),
        .I2(n_9_U_XSDB_SLAVE),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(n_15_U_XSDB_SLAVE),
        .I5(\n_0_drdyCount[4]_i_4 ),
        .O(\n_0_drdyCount[4]_i_2 ));
(* SOFT_HLUTNM = "soft_lutpair253" *) 
   LUT3 #(
    .INIT(8'h7F)) 
     \drdyCount[4]_i_3 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .O(\n_0_drdyCount[4]_i_3 ));
LUT6 #(
    .INIT(64'h8000000000000000)) 
     \drdyCount[4]_i_4 
       (.I0(n_11_U_XSDB_SLAVE),
        .I1(n_12_U_XSDB_SLAVE),
        .I2(n_13_U_XSDB_SLAVE),
        .I3(n_14_U_XSDB_SLAVE),
        .I4(n_16_U_XSDB_SLAVE),
        .I5(n_17_U_XSDB_SLAVE),
        .O(\n_0_drdyCount[4]_i_4 ));
LUT6 #(
    .INIT(64'h0000000000006AAA)) 
     \drdyCount[5]_i_1 
       (.I0(drdyCount[5]),
        .I1(\n_0_drdyCount[5]_i_2 ),
        .I2(\n_0_drdyCount[5]_i_3 ),
        .I3(drdyCount[4]),
        .I4(\n_0_drdyCount[5]_i_4 ),
        .I5(den),
        .O(\n_0_drdyCount[5]_i_1 ));
LUT4 #(
    .INIT(16'hFFFD)) 
     \drdyCount[5]_i_2 
       (.I0(\n_0_drdyCount[0]_i_2 ),
        .I1(den),
        .I2(drdyCount[0]),
        .I3(drdyCount[4]),
        .O(\n_0_drdyCount[5]_i_2 ));
(* SOFT_HLUTNM = "soft_lutpair248" *) 
   LUT4 #(
    .INIT(16'h8000)) 
     \drdyCount[5]_i_3 
       (.I0(drdyCount[3]),
        .I1(drdyCount[1]),
        .I2(drdyCount[0]),
        .I3(drdyCount[2]),
        .O(\n_0_drdyCount[5]_i_3 ));
LUT6 #(
    .INIT(64'hFFFFFFFEFAFAFAFA)) 
     \drdyCount[5]_i_4 
       (.I0(s_rst),
        .I1(drdyCount[1]),
        .I2(drdyCount[5]),
        .I3(drdyCount[3]),
        .I4(drdyCount[2]),
        .I5(drdyCount[4]),
        .O(\n_0_drdyCount[5]_i_4 ));
FDRE #(
    .INIT(1'b0)) 
     \drdyCount_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_drdyCount[0]_i_1 ),
        .Q(drdyCount[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \drdyCount_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_drdyCount[1]_i_1 ),
        .Q(drdyCount[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \drdyCount_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_drdyCount[2]_i_1 ),
        .Q(drdyCount[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \drdyCount_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_drdyCount[3]_i_1 ),
        .Q(drdyCount[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \drdyCount_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_drdyCount[4]_i_1 ),
        .Q(drdyCount[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \drdyCount_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_drdyCount[5]_i_1 ),
        .Q(drdyCount[5]),
        .R(1'b0));
FDRE drdy_mux_ff1_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(drdy_mux_ff),
        .Q(drdy_mux_ff1),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0001000000000000)) 
     drdy_mux_ff_i_1
       (.I0(drdyCount[2]),
        .I1(drdyCount[3]),
        .I2(drdyCount[5]),
        .I3(drdyCount[1]),
        .I4(drdyCount[0]),
        .I5(drdyCount[4]),
        .O(drdy_mux_temp));
FDRE drdy_mux_ff_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(drdy_mux_temp),
        .Q(drdy_mux_ff),
        .R(1'b0));
FDRE \regAck_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(regAck_temp),
        .Q(regAck_reg),
        .R(1'b0));
FDRE \regAck_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(regAck_temp_reg),
        .Q(\n_0_regAck_reg[1] ),
        .R(1'b0));
FDRE \regAck_temp_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(den),
        .Q(regAck_temp),
        .R(1'b0));
FDRE \regAck_temp_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(E),
        .Q(regAck_temp_reg),
        .R(1'b0));
LUT6 #(
    .INIT(64'h33AAAAAABB30AAAA)) 
     regDrdy_i_1
       (.I0(drdy_mux_ff1),
        .I1(n_0_regDrdy_i_2),
        .I2(adv_rb_drdy4),
        .I3(s_daddr_o[2]),
        .I4(O15),
        .I5(n_1_reg_83),
        .O(n_0_regDrdy_i_1));
LUT6 #(
    .INIT(64'hA0AF2020A0AF2F2F)) 
     regDrdy_i_2
       (.I0(s_daddr_o[2]),
        .I1(\n_0_regAck_reg[1] ),
        .I2(s_daddr_o[1]),
        .I3(regAck_reg),
        .I4(s_daddr_o[0]),
        .I5(adv_drdy),
        .O(n_0_regDrdy_i_2));
LUT5 #(
    .INIT(32'h00800000)) 
     regDrdy_i_3
       (.I0(\n_0_drdyCount[4]_i_4 ),
        .I1(n_10_U_XSDB_SLAVE),
        .I2(n_15_U_XSDB_SLAVE),
        .I3(n_8_U_XSDB_SLAVE),
        .I4(n_9_U_XSDB_SLAVE),
        .O(O15));
FDRE regDrdy_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_0_regDrdy_i_1),
        .Q(n_0_regDrdy_reg),
        .R(1'b0));
ila_0_xsdbs_v1_0_reg reg_0
       (.E(den),
        .I1(\n_0_slaveRegDo_mux_6[15]_i_3 ),
        .I2(n_9_reg_10),
        .I3(s_dclk),
        .O1(n_0_reg_0),
        .Q({n_1_reg_0,n_2_reg_0,n_3_reg_0,n_4_reg_0,n_5_reg_0,n_6_reg_0,n_7_reg_0,n_8_reg_0,n_9_reg_0,n_10_reg_0,n_11_reg_0,n_12_reg_0,n_13_reg_0,n_14_reg_0,n_15_reg_0}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,s_daddr_o[2]}),
        .slaveRegDo_80(slaveRegDo_80[15]));
ila_0_xsdbs_v1_0_reg__parameterized0 reg_1
       (.E(den),
        .I1(s_dclk),
        .O1(n_0_reg_1),
        .O2(n_1_reg_1),
        .O3({n_2_reg_1,n_3_reg_1,n_4_reg_1,n_5_reg_1,n_6_reg_1,n_7_reg_1,n_8_reg_1,n_9_reg_1,n_10_reg_1,n_11_reg_1,n_12_reg_1,n_13_reg_1,n_14_reg_1,n_15_reg_1}),
        .Q({n_14_reg_11,n_15_reg_11}),
        .s_daddr_o({n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}));
ila_0_xsdbs_v1_0_reg__parameterized15 reg_10
       (.E(den),
        .I1(n_13_reg_14),
        .I2(s_dclk),
        .O1(n_0_reg_10),
        .O10(n_9_reg_10),
        .O11(n_10_reg_10),
        .O12({n_11_reg_10,n_12_reg_10,n_13_reg_10,n_14_reg_10,n_15_reg_10}),
        .O2(n_1_reg_10),
        .O3(n_2_reg_10),
        .O4(n_3_reg_10),
        .O5(n_4_reg_10),
        .O6(n_5_reg_10),
        .O7(n_6_reg_10),
        .O8(n_7_reg_10),
        .O9(n_8_reg_10),
        .Q({n_1_reg_0,n_2_reg_0,n_3_reg_0,n_4_reg_0,n_6_reg_0,n_7_reg_0,n_8_reg_0,n_10_reg_0,n_11_reg_0,n_13_reg_0}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}),
        .slaveRegDo_18({slaveRegDo_18[15:13],slaveRegDo_18[11],slaveRegDo_18[9:7],slaveRegDo_18[5:4]}),
        .slaveRegDo_80({slaveRegDo_80[14:11],slaveRegDo_80[9:7],slaveRegDo_80[5:4]}));
ila_0_xsdbs_v1_0_reg__parameterized16 reg_11
       (.D({p_0_in[14],p_0_in[3]}),
        .E(den),
        .I1(n_0_reg_15),
        .I10(n_30_reg_2),
        .I11(n_38_reg_2),
        .I12(n_0_reg_f),
        .I13(n_1_reg_83),
        .I14(n_15_reg_19),
        .I15(n_28_reg_2),
        .I16(n_1_reg_15),
        .I17(n_2_reg_15),
        .I18(n_4_reg_15),
        .I19(n_5_reg_15),
        .I2(n_18_reg_15),
        .I20(n_6_reg_15),
        .I21(n_7_reg_15),
        .I22(n_8_reg_15),
        .I23(n_9_reg_15),
        .I24(n_10_reg_15),
        .I25(n_11_reg_15),
        .I26(n_0_reg_d),
        .I27(s_dclk),
        .I3(n_7_reg_83),
        .I4(\n_0_slaveRegDo_mux_0[3]_i_4 ),
        .I5(n_37_reg_2),
        .I6({\n_7_MU_STATUS[10].mu_tpid_reg ,\n_17_MU_STATUS[10].mu_tpid_reg }),
        .I7(\n_0_slaveRegDo_mux_0[15]_i_6 ),
        .I8(\n_0_slaveRegDo_mux_0[12]_i_4 ),
        .I9(n_6_reg_19),
        .O1(n_0_reg_11),
        .O10(n_10_reg_11),
        .O11(n_11_reg_11),
        .O12(n_12_reg_11),
        .O13(n_13_reg_11),
        .O14({n_14_reg_11,n_15_reg_11}),
        .O2(n_3_reg_11),
        .O3({n_2_reg_1,n_3_reg_1,n_4_reg_1,n_5_reg_1,n_6_reg_1,n_7_reg_1,n_8_reg_1,n_9_reg_1,n_10_reg_1,n_11_reg_1,n_12_reg_1,n_13_reg_1,n_14_reg_1,n_15_reg_1}),
        .O4(n_4_reg_11),
        .O5(n_5_reg_11),
        .O6(n_6_reg_11),
        .O7(n_7_reg_11),
        .O8(n_8_reg_11),
        .O9(n_9_reg_11),
        .Q(n_5_reg_d),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}));
ila_0_xsdbs_v1_0_reg__parameterized17 reg_12
       (.E(den),
        .I1(n_0_reg_16),
        .I10(n_15_reg_82),
        .I11(n_3_reg_16),
        .I12(n_18_reg_1a),
        .I13(n_0_reg_a),
        .I14(s_dclk),
        .I2(n_3_reg_e),
        .I3(n_4_reg_e),
        .I4(n_5_reg_e),
        .I5(n_6_reg_e),
        .I6(n_7_reg_e),
        .I7({n_12_reg_e,n_14_reg_e,n_15_reg_e}),
        .I8(n_5_reg_16),
        .I9(n_4_reg_16),
        .O1(n_0_reg_12),
        .O10(n_9_reg_12),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(n_10_reg_12),
        .O16(n_11_reg_12),
        .O17(n_12_reg_12),
        .O18(n_13_reg_12),
        .O19(n_14_reg_12),
        .O2(n_1_reg_12),
        .O20(n_15_reg_12),
        .O3(n_2_reg_12),
        .O4(n_3_reg_12),
        .O5(n_4_reg_12),
        .O6(n_5_reg_12),
        .O7(n_6_reg_12),
        .O8(n_7_reg_12),
        .O9(n_8_reg_12),
        .Q({n_1_reg_2,n_2_reg_2,n_3_reg_2,n_5_reg_2,n_6_reg_2,n_7_reg_2,n_8_reg_2,n_9_reg_2,n_10_reg_2,n_11_reg_2,n_12_reg_2,n_13_reg_2,n_14_reg_2,n_15_reg_2,n_16_reg_2}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2:1]}));
ila_0_xsdbs_v1_0_reg__parameterized18 reg_13
       (.E(den),
        .I1(n_17_reg_83),
        .I2(n_19_reg_83),
        .I3(s_dclk),
        .O1(n_0_reg_13),
        .O2(n_1_reg_13),
        .O3({n_2_reg_13,n_3_reg_13,n_4_reg_13,n_5_reg_13,n_6_reg_13,n_7_reg_13,n_8_reg_13,n_9_reg_13,n_10_reg_13,n_11_reg_13,n_12_reg_13,n_13_reg_13,n_14_reg_13,n_15_reg_13}),
        .Q({n_6_reg_3,n_15_reg_3}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE}));
ila_0_xsdbs_v1_0_reg__parameterized19 reg_14
       (.E(den),
        .I1(\n_0_slaveRegDo_mux_0[15]_i_15 ),
        .I2({n_10_reg_4,n_11_reg_4,n_12_reg_4,n_19_reg_4}),
        .I3(s_dclk),
        .O1(n_0_reg_14),
        .O2(n_1_reg_14),
        .O3(n_2_reg_14),
        .O4(n_3_reg_14),
        .O5({n_4_reg_14,n_5_reg_14,n_6_reg_14,n_7_reg_14,n_8_reg_14,n_9_reg_14,n_10_reg_14,n_11_reg_14,n_12_reg_14,n_13_reg_14,n_14_reg_14,n_15_reg_14}),
        .Q({n_5_reg_c,n_6_reg_c,n_13_reg_c}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2:1]}),
        .slaveRegDo_84({slaveRegDo_84[14:12],slaveRegDo_84[5]}));
ila_0_xsdbs_v1_0_reg__parameterized20 reg_15
       (.E(den),
        .I1(n_0_reg_7),
        .I2(n_11_reg_11),
        .I3(n_12_reg_19),
        .I4(n_29_reg_2),
        .I5(n_0_reg_19),
        .I6(n_1_reg_1),
        .I7(s_dclk),
        .O1(n_0_reg_15),
        .O10(n_10_reg_15),
        .O11(n_11_reg_15),
        .O12(n_12_reg_15),
        .O13(n_13_reg_15),
        .O14(n_14_reg_15),
        .O15(n_15_reg_15),
        .O16(n_17_reg_15),
        .O17(n_18_reg_15),
        .O2(n_1_reg_15),
        .O3(n_2_reg_15),
        .O4(n_4_reg_15),
        .O5(n_5_reg_15),
        .O6(n_6_reg_15),
        .O7(n_7_reg_15),
        .O8(n_8_reg_15),
        .O9(n_9_reg_15),
        .Q({n_1_reg_d,n_2_reg_d,n_4_reg_d,n_6_reg_d,n_7_reg_d,n_8_reg_d,n_9_reg_d,n_10_reg_d,n_11_reg_d,n_12_reg_d,n_13_reg_d,n_14_reg_d,n_15_reg_d}),
        .SR(SR),
        .dwe(dwe),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_xsdbs_v1_0_reg__parameterized21 reg_16
       (.E(den),
        .I1(n_0_reg_7),
        .I2(n_10_reg_12),
        .I3(n_15_reg_1a),
        .I4(n_13_reg_15),
        .I5(s_dclk),
        .O1(n_0_reg_16),
        .O10(O7),
        .O11(O8),
        .O12(O9),
        .O13(O10),
        .O14(O11),
        .O15(O12),
        .O16(O13),
        .O17(O14),
        .O2(n_1_reg_16),
        .O3(O1),
        .O4(n_3_reg_16),
        .O5(n_4_reg_16),
        .O6(n_5_reg_16),
        .O7(n_6_reg_16),
        .O8(n_7_reg_16),
        .O9(O6),
        .Q(n_13_reg_e),
        .dwe(dwe),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg__parameterized22 reg_17
       (.I1(n_3_reg_19),
        .I2(s_dclk),
        .O1(n_0_reg_17),
        .O10(n_9_reg_17),
        .O11(n_10_reg_17),
        .O12(n_11_reg_17),
        .O13(n_12_reg_17),
        .O14(n_13_reg_17),
        .O15(n_14_reg_17),
        .O16(n_15_reg_17),
        .O2(n_1_reg_17),
        .O3(n_2_reg_17),
        .O4(n_3_reg_17),
        .O5(n_4_reg_17),
        .O6(n_5_reg_17),
        .O7(n_6_reg_17),
        .O8(n_7_reg_17),
        .O9(n_8_reg_17),
        .s_daddr_o({n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg__parameterized23 reg_18
       (.E(den),
        .I1(n_0_reg_10),
        .I10({n_0_reg_8,n_1_reg_8,n_2_reg_8,n_3_reg_8}),
        .I11(\n_0_slaveRegDo_mux_6[15]_i_3 ),
        .I12({n_5_reg_0,n_9_reg_0}),
        .I13(s_dclk),
        .I2(\n_3_ADV_TRIG_STREAM.reg_stream_ffc ),
        .I3(n_0_reg_c),
        .I4(\n_0_slaveRegDo_mux_0[15]_i_22 ),
        .I5(n_1_reg_c),
        .I6(n_2_reg_c),
        .I7(n_10_reg_10),
        .I8(n_3_reg_c),
        .I9(n_3_reg_14),
        .O1(n_0_reg_18),
        .O12({n_11_reg_10,n_12_reg_10}),
        .O2(n_1_reg_18),
        .O3(n_2_reg_18),
        .O4(n_3_reg_18),
        .O5({n_12_reg_14,n_14_reg_14,n_15_reg_14}),
        .O6({slaveRegDo_18[15:13],slaveRegDo_18[11],slaveRegDo_18[9:7],slaveRegDo_18[5:4]}),
        .O7(n_13_reg_18),
        .O8(n_14_reg_18),
        .O9(n_15_reg_18),
        .Q(n_15_reg_c),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .slaveRegDo_80({slaveRegDo_80[10],slaveRegDo_80[6]}));
ila_0_xsdbs_v1_0_reg__parameterized24 reg_19
       (.E(den),
        .I1(n_12_reg_11),
        .I2(n_65_reg_2),
        .I3(\n_0_slaveRegDo_mux_0[12]_i_4 ),
        .I4(n_0_reg_b),
        .I5(n_8_reg_11),
        .I6(n_60_reg_2),
        .I7(n_2_reg_b),
        .I8(s_dclk),
        .O1(n_0_reg_19),
        .O10(n_9_reg_19),
        .O11(n_10_reg_19),
        .O12(n_11_reg_19),
        .O13(n_12_reg_19),
        .O14(n_13_reg_19),
        .O15(n_14_reg_19),
        .O16(n_15_reg_19),
        .O17(n_16_reg_19),
        .O18(n_17_reg_19),
        .O2(n_1_reg_19),
        .O3(n_2_reg_19),
        .O4(n_3_reg_19),
        .O5(n_4_reg_19),
        .O6(n_5_reg_19),
        .O7(n_6_reg_19),
        .O8(n_7_reg_19),
        .O9(n_8_reg_19),
        .Q({n_1_reg_9,n_2_reg_9,n_3_reg_9,n_4_reg_9,n_5_reg_9,n_6_reg_9,n_7_reg_9,n_8_reg_9,n_9_reg_9,n_10_reg_9,n_11_reg_9,n_12_reg_9,n_13_reg_9,n_14_reg_9,n_15_reg_9}),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg__parameterized25 reg_1a
       (.A(A),
        .I1(n_2_reg_e),
        .I10(n_3_reg_12),
        .I11(n_61_reg_2),
        .I12(n_0_reg_82),
        .I13(n_11_reg_12),
        .I14(O8),
        .I15(n_4_reg_12),
        .I16(n_59_reg_2),
        .I17(n_5_reg_12),
        .I18(n_58_reg_2),
        .I19(n_3_reg_19),
        .I2(n_4_reg_2),
        .I20(s_dclk),
        .I3(n_12_reg_83),
        .I4(n_1_reg_12),
        .I5(n_64_reg_2),
        .I6(n_0_reg_12),
        .I7(n_63_reg_2),
        .I8(n_2_reg_12),
        .I9(n_62_reg_2),
        .O1(n_0_reg_1a),
        .O10(n_12_reg_1a),
        .O11(n_13_reg_1a),
        .O12(n_14_reg_1a),
        .O13(n_15_reg_1a),
        .O14(n_16_reg_1a),
        .O15(n_17_reg_1a),
        .O16(n_18_reg_1a),
        .O2(n_1_reg_1a),
        .O20(n_15_reg_12),
        .O3(n_2_reg_1a),
        .O4(n_3_reg_1a),
        .O5(n_7_reg_1a),
        .O6(n_8_reg_1a),
        .O7(n_9_reg_1a),
        .O8(n_10_reg_1a),
        .O9(n_11_reg_1a),
        .Q({n_1_reg_a,n_2_reg_a,n_3_reg_a,n_4_reg_a,n_5_reg_a,n_6_reg_a,n_7_reg_a,n_8_reg_a,n_9_reg_a,n_10_reg_a,n_11_reg_a,n_12_reg_a,n_13_reg_a,n_14_reg_a,n_15_reg_a}),
        .basic_trigger(basic_trigger),
        .capture_fsm_temp(capture_fsm_temp),
        .capture_strg_qual(capture_strg_qual),
        .en_adv_trigger(en_adv_trigger),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .trig_out_fsm_temp(trig_out_fsm_temp));
ila_0_xsdbs_v1_0_reg__parameterized1 reg_2
       (.D({p_0_in[15],p_0_in[12],p_0_in[5],p_0_in[2:0]}),
        .E(den),
        .I1({n_0_reg_88d,n_1_reg_88d,n_2_reg_88d,n_3_reg_88d,n_4_reg_88d,n_5_reg_88d,n_6_reg_88d,n_7_reg_88d,n_8_reg_88d,n_9_reg_88d,n_10_reg_88d,n_11_reg_88d}),
        .I10(n_1_reg_85),
        .I11(\n_0_slaveRegDo_mux_6[15]_i_3 ),
        .I12(n_3_reg_85),
        .I13(n_5_reg_85),
        .I14(n_12_reg_85),
        .I15(n_2_reg_83),
        .I16({\n_6_MU_STATUS[10].mu_tpid_reg ,\n_9_MU_STATUS[10].mu_tpid_reg ,\n_15_MU_STATUS[10].mu_tpid_reg ,\n_18_MU_STATUS[10].mu_tpid_reg ,\n_19_MU_STATUS[10].mu_tpid_reg ,\n_20_MU_STATUS[10].mu_tpid_reg }),
        .I17(\n_0_slaveRegDo_mux_0[15]_i_6 ),
        .I18(n_7_reg_1a),
        .I19(\n_0_slaveRegDo_mux_0[3]_i_4 ),
        .I2({n_4_reg_88f,n_5_reg_88f,n_6_reg_88f,n_7_reg_88f,n_8_reg_88f,n_9_reg_88f,n_10_reg_88f,n_11_reg_88f,n_12_reg_88f,n_13_reg_88f,n_14_reg_88f,n_15_reg_88f}),
        .I20(n_13_reg_18),
        .I21(n_13_reg_19),
        .I22(n_0_reg_11),
        .I23(n_3_reg_d),
        .I24(\n_0_slaveRegDo_mux_0[12]_i_14 ),
        .I25(n_1_reg_83),
        .I26(n_2_reg_f),
        .I27(n_1_reg_16),
        .I28(n_7_reg_10),
        .I29(n_0_reg_14),
        .I3(\n_0_slaveRegDo_mux_0[12]_i_4 ),
        .I30(n_3_reg_18),
        .I31(n_3_reg_1a),
        .I32(n_8_reg_e),
        .I33(n_8_reg_83),
        .I34(n_0_reg_18),
        .I35(n_2_reg_1a),
        .I36(n_9_reg_e),
        .I37(n_9_reg_83),
        .I38(n_2_reg_18),
        .I39(n_1_reg_1a),
        .I4(n_3_reg_11),
        .I40(n_10_reg_e),
        .I41(n_3_reg_b),
        .I42(n_1_reg_18),
        .I43(n_0_reg_1a),
        .I44(n_11_reg_e),
        .I45(n_1_reg_e),
        .I46(n_1_reg_10),
        .I47(n_2_reg_14),
        .I48(n_0_reg_83),
        .I49(n_14_reg_12),
        .I5(n_4_reg_19),
        .I50(n_5_reg_4),
        .I51(n_15_reg_15),
        .I52(n_0_reg_9),
        .I53(n_5_reg_11),
        .I54(n_7_reg_19),
        .I55(n_6_reg_11),
        .I56(n_8_reg_19),
        .I57(n_7_reg_11),
        .I58(n_9_reg_19),
        .I59(n_9_reg_11),
        .I6(n_4_reg_11),
        .I60(n_10_reg_19),
        .I61(n_10_reg_11),
        .I62(n_11_reg_19),
        .I63(n_13_reg_11),
        .I64(n_14_reg_19),
        .I65({\n_2_MU_STATUS[12].mu_tpid_reg ,\n_3_MU_STATUS[12].mu_tpid_reg ,\n_4_MU_STATUS[12].mu_tpid_reg ,\n_5_MU_STATUS[12].mu_tpid_reg ,\n_6_MU_STATUS[12].mu_tpid_reg ,\n_7_MU_STATUS[12].mu_tpid_reg ,\n_8_MU_STATUS[12].mu_tpid_reg ,\n_9_MU_STATUS[12].mu_tpid_reg ,\n_10_MU_STATUS[12].mu_tpid_reg ,\n_11_MU_STATUS[12].mu_tpid_reg ,\n_12_MU_STATUS[12].mu_tpid_reg ,\n_13_MU_STATUS[12].mu_tpid_reg ,\n_14_MU_STATUS[12].mu_tpid_reg ,\n_15_MU_STATUS[12].mu_tpid_reg }),
        .I66(n_15_reg_85),
        .I67(n_14_reg_85),
        .I68(n_13_reg_85),
        .I69(n_11_reg_85),
        .I7(n_5_reg_19),
        .I70(n_10_reg_85),
        .I71(n_9_reg_85),
        .I72(n_8_reg_85),
        .I73(n_7_reg_85),
        .I74(n_6_reg_85),
        .I75(n_4_reg_85),
        .I76(n_2_reg_85),
        .I77(n_0_reg_85),
        .I78({n_21_reg_4,n_22_reg_4,n_23_reg_4,n_24_reg_4}),
        .I79(s_dclk),
        .I8(n_14_reg_15),
        .I9(n_16_reg_19),
        .O1(n_0_reg_2),
        .O10(n_25_reg_2),
        .O11(n_26_reg_2),
        .O12(n_27_reg_2),
        .O13(n_28_reg_2),
        .O14(n_29_reg_2),
        .O15(n_30_reg_2),
        .O16(n_37_reg_2),
        .O17(n_38_reg_2),
        .O18(n_39_reg_2),
        .O19(n_40_reg_2),
        .O2(n_17_reg_2),
        .O20(n_41_reg_2),
        .O21(n_42_reg_2),
        .O22(n_43_reg_2),
        .O23(n_44_reg_2),
        .O24(n_45_reg_2),
        .O25(n_46_reg_2),
        .O26(n_47_reg_2),
        .O27(n_48_reg_2),
        .O28(n_49_reg_2),
        .O29(n_50_reg_2),
        .O3(n_18_reg_2),
        .O30(n_51_reg_2),
        .O31(n_52_reg_2),
        .O32(n_53_reg_2),
        .O33(n_54_reg_2),
        .O34(n_55_reg_2),
        .O35(n_56_reg_2),
        .O36(n_57_reg_2),
        .O37(n_58_reg_2),
        .O38(n_59_reg_2),
        .O39(n_60_reg_2),
        .O4(n_19_reg_2),
        .O40(n_61_reg_2),
        .O41(n_62_reg_2),
        .O42(n_63_reg_2),
        .O43(n_64_reg_2),
        .O44(n_65_reg_2),
        .O5(n_20_reg_2),
        .O6(n_21_reg_2),
        .O7(n_22_reg_2),
        .O8(n_23_reg_2),
        .O9(n_24_reg_2),
        .Q({n_1_reg_2,n_2_reg_2,n_3_reg_2,n_4_reg_2,n_5_reg_2,n_6_reg_2,n_7_reg_2,n_8_reg_2,n_9_reg_2,n_10_reg_2,n_11_reg_2,n_12_reg_2,n_13_reg_2,n_14_reg_2,n_15_reg_2,n_16_reg_2}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .slaveRegDo_6({slaveRegDo_6[14],slaveRegDo_6[12:8],slaveRegDo_6[6:0]}),
        .slaveRegDo_80(slaveRegDo_80[3:0]),
        .slaveRegDo_81(slaveRegDo_81),
        .slaveRegDo_82({slaveRegDo_82[14],slaveRegDo_82[12:8],slaveRegDo_82[6:0]}),
        .slaveRegDo_84(slaveRegDo_84[3:0]));
ila_0_xsdbs_v1_0_reg__parameterized2 reg_3
       (.E(den),
        .I1(n_18_reg_83),
        .I2(n_16_reg_83),
        .I3(s_dclk),
        .O1(n_0_reg_3),
        .O2(n_1_reg_3),
        .Q({n_2_reg_3,n_3_reg_3,n_4_reg_3,n_5_reg_3,n_6_reg_3,n_7_reg_3,n_8_reg_3,n_9_reg_3,n_10_reg_3,n_11_reg_3,n_12_reg_3,n_13_reg_3,n_14_reg_3,n_15_reg_3}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE}));
ila_0_xsdbs_v1_0_reg__parameterized3 reg_4
       (.D({p_0_in[10],p_0_in[8]}),
        .E(den),
        .I1(\n_0_slaveRegDo_mux_0[15]_i_15 ),
        .I10(n_36_reg_887),
        .I11(n_0_reg_0),
        .I12(n_9_reg_1a),
        .I13(n_1_reg_b),
        .I14(n_12_reg_15),
        .I15(\n_11_MU_STATUS[10].mu_tpid_reg ),
        .I16(\n_0_slaveRegDo_mux_0[15]_i_6 ),
        .I17(n_11_reg_1a),
        .I18(n_41_reg_2),
        .I19(n_4_reg_83),
        .I2(n_8_reg_10),
        .I20({n_4_reg_14,n_5_reg_14,n_6_reg_14,n_7_reg_14,n_8_reg_14,n_9_reg_14,n_10_reg_14,n_11_reg_14}),
        .I21(n_0_reg_7),
        .I22(n_31_reg_887),
        .I23(n_32_reg_887),
        .I24(n_33_reg_887),
        .I25(n_35_reg_887),
        .I26(\n_0_slaveRegDo_mux_1[15]_i_5 ),
        .I27(\n_21_MU_STATUS[10].mu_tpid_reg ),
        .I28(n_38_reg_887),
        .I29(n_39_reg_887),
        .I3(\n_0_slaveRegDo_mux_0[3]_i_4 ),
        .I30(n_40_reg_887),
        .I31(n_42_reg_887),
        .I32(n_43_reg_887),
        .I33({\n_2_MU_STATUS[1].mu_width_reg ,\n_3_MU_STATUS[1].mu_width_reg ,\n_5_MU_STATUS[1].mu_width_reg ,\n_7_MU_STATUS[1].mu_width_reg ,\n_8_MU_STATUS[1].mu_width_reg ,\n_9_MU_STATUS[1].mu_width_reg ,\n_10_MU_STATUS[1].mu_width_reg ,\n_11_MU_STATUS[1].mu_width_reg ,\n_13_MU_STATUS[1].mu_width_reg ,\n_14_MU_STATUS[1].mu_width_reg ,\n_15_MU_STATUS[1].mu_width_reg ,\n_16_MU_STATUS[1].mu_width_reg ,\n_17_MU_STATUS[1].mu_width_reg }),
        .I34(n_47_reg_887),
        .I35(n_46_reg_887),
        .I36(n_45_reg_887),
        .I37(\n_0_slaveRegDo_mux_0[15]_i_22 ),
        .I38(s_dclk),
        .I4(n_14_reg_18),
        .I5(n_6_reg_10),
        .I6(n_5_reg_10),
        .I7(n_4_reg_10),
        .I8(n_15_reg_18),
        .I9(n_3_reg_10),
        .O1(n_0_reg_4),
        .O10(n_26_reg_4),
        .O11(n_27_reg_4),
        .O12(n_28_reg_4),
        .O13(n_29_reg_4),
        .O14(n_30_reg_4),
        .O15(n_31_reg_4),
        .O16(n_32_reg_4),
        .O17(n_33_reg_4),
        .O18(n_34_reg_4),
        .O19(n_35_reg_4),
        .O2(n_1_reg_4),
        .O20(n_36_reg_4),
        .O3(n_2_reg_4),
        .O4(n_3_reg_4),
        .O5(n_4_reg_4),
        .O6(n_5_reg_4),
        .O7(n_8_reg_4),
        .O8({n_9_reg_4,n_10_reg_4,n_11_reg_4,n_12_reg_4,n_13_reg_4,n_14_reg_4,n_15_reg_4,n_16_reg_4,n_17_reg_4,n_18_reg_4,n_19_reg_4,n_20_reg_4,n_21_reg_4,n_22_reg_4,n_23_reg_4,n_24_reg_4}),
        .O9(n_25_reg_4),
        .Q({n_4_reg_c,n_7_reg_c,n_8_reg_c,n_9_reg_c,n_10_reg_c,n_11_reg_c,n_12_reg_c,n_14_reg_c}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2:1]}),
        .slaveRegDo_84({slaveRegDo_84[15],slaveRegDo_84[11:6],slaveRegDo_84[4]}));
ila_0_xsdbs_v1_0_reg__parameterized5 reg_6
       (.E(den),
        .I1(n_0_reg_e),
        .I2(\n_0_slaveRegDo_mux_0[3]_i_4 ),
        .I3(n_2_reg_10),
        .I4(n_1_reg_14),
        .I5(\n_0_slaveRegDo_mux_6[15]_i_3 ),
        .I6(s_dclk),
        .O1(n_0_reg_6),
        .O2({slaveRegDo_6[15:14],slaveRegDo_6[12:0]}),
        .Q(n_3_reg_2),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .slaveRegDo_82(slaveRegDo_82[13]));
ila_0_xsdbs_v1_0_reg__parameterized6 reg_7
       (.E(den),
        .I1(n_0_reg_19),
        .I10(n_9_reg_17),
        .I11(n_7_reg_17),
        .I12(n_6_reg_17),
        .I13(n_5_reg_17),
        .I14(n_3_reg_17),
        .I15(n_0_reg_17),
        .I16(s_dclk),
        .I2(n_1_reg_83),
        .I3(n_10_reg_83),
        .I4(\n_0_slaveRegDo_mux_0[15]_i_20 ),
        .I5(n_15_reg_17),
        .I6(n_14_reg_17),
        .I7(n_13_reg_17),
        .I8(n_12_reg_17),
        .I9(n_11_reg_17),
        .O1(n_0_reg_7),
        .O10(n_11_reg_7),
        .O11(n_12_reg_7),
        .O12(n_13_reg_7),
        .O13(n_14_reg_7),
        .O14(n_15_reg_7),
        .O15(n_16_reg_7),
        .O16(n_17_reg_7),
        .O17(n_18_reg_7),
        .O2(n_1_reg_7),
        .O3(n_3_reg_7),
        .O4(n_5_reg_7),
        .O5(n_6_reg_7),
        .O6(n_7_reg_7),
        .O7(n_8_reg_7),
        .O8(n_9_reg_7),
        .O9(n_10_reg_7),
        .Q({n_5_reg_f,n_6_reg_f,n_7_reg_f,n_8_reg_f,n_9_reg_f,n_10_reg_f,n_11_reg_f,n_12_reg_f,n_13_reg_f,n_14_reg_f,n_15_reg_f}),
        .arm_ctrl(arm_ctrl),
        .dwe(dwe),
        .halt_ctrl(halt_ctrl),
        .s_daddr_o({n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg__parameterized7 reg_8
       (.E(den),
        .I1(s_dclk),
        .I5(I5),
        .Q({n_0_reg_8,n_1_reg_8,n_2_reg_8,n_3_reg_8}));
ila_0_xsdbs_v1_0_reg__parameterized26 reg_80
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .slaveRegDo_80(slaveRegDo_80));
ila_0_xsdbs_v1_0_reg__parameterized27 reg_81
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .slaveRegDo_81(slaveRegDo_81));
ila_0_xsdbs_v1_0_reg__parameterized28 reg_82
       (.E(den),
        .I1({slaveRegDo_6[15],slaveRegDo_6[7]}),
        .I2(s_dclk),
        .O1(n_0_reg_82),
        .O2({slaveRegDo_82[14:8],slaveRegDo_82[6:0]}),
        .O3(n_15_reg_82),
        .Q({n_1_reg_2,n_9_reg_2}),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg__parameterized29 reg_83
       (.E(den),
        .I1(n_13_reg_7),
        .I10(n_4_reg_b),
        .I11(n_5_reg_b),
        .I12(n_6_reg_b),
        .I13(n_7_reg_b),
        .I14(n_8_reg_b),
        .I15(n_9_reg_b),
        .I16(n_10_reg_b),
        .I17(n_11_reg_b),
        .I18(n_12_reg_b),
        .I19(n_13_reg_b),
        .I2(n_12_reg_7),
        .I20(n_14_reg_b),
        .I21(n_15_reg_b),
        .I22(s_dclk),
        .I3(n_10_reg_7),
        .I4(n_9_reg_7),
        .I5(n_8_reg_7),
        .I6(n_7_reg_7),
        .I7(n_6_reg_7),
        .I8(n_5_reg_7),
        .I9(n_3_reg_7),
        .O1(n_0_reg_83),
        .O10(n_9_reg_83),
        .O11(n_10_reg_83),
        .O12(n_11_reg_83),
        .O13(n_12_reg_83),
        .O14(n_13_reg_83),
        .O15(n_14_reg_83),
        .O16(n_15_reg_83),
        .O17(n_16_reg_83),
        .O18(n_17_reg_83),
        .O19(n_18_reg_83),
        .O2(n_1_reg_83),
        .O20(n_19_reg_83),
        .O3(n_2_reg_83),
        .O4(n_3_reg_83),
        .O5(n_4_reg_83),
        .O6(n_5_reg_83),
        .O7(n_6_reg_83),
        .O8(n_7_reg_83),
        .O9(n_8_reg_83),
        .Q({n_2_reg_3,n_3_reg_3,n_4_reg_3,n_5_reg_3,n_7_reg_3,n_8_reg_3,n_9_reg_3,n_10_reg_3,n_11_reg_3,n_12_reg_3,n_13_reg_3,n_14_reg_3}),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg__parameterized30 reg_84
       (.E(den),
        .I1(s_dclk),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .slaveRegDo_84(slaveRegDo_84));
ila_0_xsdbs_v1_0_reg__parameterized31 reg_85
       (.E(den),
        .I1(n_11_reg_83),
        .I2(s_dclk),
        .O1(n_0_reg_85),
        .O10(n_9_reg_85),
        .O11(n_10_reg_85),
        .O12(n_11_reg_85),
        .O13(n_12_reg_85),
        .O14(n_13_reg_85),
        .O15(n_14_reg_85),
        .O16(n_15_reg_85),
        .O2(n_1_reg_85),
        .O3(n_2_reg_85),
        .O4(n_3_reg_85),
        .O5(n_4_reg_85),
        .O6(n_5_reg_85),
        .O7(n_6_reg_85),
        .O8(n_7_reg_85),
        .O9(n_8_reg_85),
        .dwe(dwe),
        .s_daddr_o({n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg__parameterized59 reg_887
       (.D({n_15_reg_887,n_16_reg_887,n_17_reg_887,n_18_reg_887,n_19_reg_887,n_20_reg_887,n_21_reg_887,n_22_reg_887,n_23_reg_887,n_24_reg_887,n_25_reg_887,n_26_reg_887,n_27_reg_887,n_28_reg_887,n_29_reg_887,n_30_reg_887}),
        .E(den),
        .I1(\n_0_slaveRegDo_mux_2[15]_i_2 ),
        .I10(n_18_reg_2),
        .I11(n_19_reg_2),
        .I12(n_20_reg_2),
        .I13(n_21_reg_2),
        .I14(n_22_reg_2),
        .I15(n_23_reg_2),
        .I16(n_24_reg_2),
        .I17(n_25_reg_2),
        .I18(n_26_reg_2),
        .I19(n_27_reg_2),
        .I2({\n_0_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_1_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_2_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_3_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_4_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_5_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_6_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_7_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_8_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_9_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_10_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_11_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_12_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_13_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_14_CNT_WIDTH_STATUS[0].cnt_width_reg ,\n_15_CNT_WIDTH_STATUS[0].cnt_width_reg }),
        .I20(n_3_reg_88f),
        .I21(n_2_reg_88f),
        .I22(n_1_reg_88f),
        .I23(n_0_reg_88f),
        .I24(s_dclk),
        .I3(n_0_FSM_BRAM_EN_RB_O_i_2),
        .I4(\n_0_slaveRegDo_mux_0[15]_i_6 ),
        .I5({\n_6_MU_STATUS[10].mu_tpid_reg ,\n_7_MU_STATUS[10].mu_tpid_reg ,\n_8_MU_STATUS[10].mu_tpid_reg ,\n_9_MU_STATUS[10].mu_tpid_reg ,\n_10_MU_STATUS[10].mu_tpid_reg ,\n_11_MU_STATUS[10].mu_tpid_reg ,\n_12_MU_STATUS[10].mu_tpid_reg ,n_8_reg_4,\n_13_MU_STATUS[10].mu_tpid_reg ,\n_14_MU_STATUS[10].mu_tpid_reg ,\n_15_MU_STATUS[10].mu_tpid_reg ,\n_16_MU_STATUS[10].mu_tpid_reg ,\n_17_MU_STATUS[10].mu_tpid_reg ,\n_18_MU_STATUS[10].mu_tpid_reg ,\n_19_MU_STATUS[10].mu_tpid_reg ,\n_20_MU_STATUS[10].mu_tpid_reg }),
        .I6({\n_2_MU_STATUS[1].mu_width_reg ,\n_3_MU_STATUS[1].mu_width_reg ,\n_4_MU_STATUS[1].mu_width_reg ,\n_5_MU_STATUS[1].mu_width_reg ,\n_6_MU_STATUS[1].mu_width_reg ,\n_7_MU_STATUS[1].mu_width_reg ,\n_8_MU_STATUS[1].mu_width_reg ,\n_9_MU_STATUS[1].mu_width_reg ,\n_10_MU_STATUS[1].mu_width_reg ,\n_11_MU_STATUS[1].mu_width_reg ,\n_12_MU_STATUS[1].mu_width_reg ,\n_13_MU_STATUS[1].mu_width_reg ,\n_14_MU_STATUS[1].mu_width_reg ,\n_15_MU_STATUS[1].mu_width_reg ,\n_16_MU_STATUS[1].mu_width_reg ,\n_17_MU_STATUS[1].mu_width_reg }),
        .I7({n_9_reg_4,n_10_reg_4,n_11_reg_4,n_12_reg_4,n_13_reg_4,n_14_reg_4,n_15_reg_4,n_16_reg_4,n_17_reg_4,n_18_reg_4,n_19_reg_4,n_20_reg_4,n_21_reg_4,n_22_reg_4,n_23_reg_4,n_24_reg_4}),
        .I8(n_0_reg_2),
        .I9(n_17_reg_2),
        .O1(n_0_reg_887),
        .O10(n_9_reg_887),
        .O11(n_10_reg_887),
        .O12(n_11_reg_887),
        .O13(n_12_reg_887),
        .O14(n_13_reg_887),
        .O15(n_14_reg_887),
        .O16(n_31_reg_887),
        .O17(n_32_reg_887),
        .O18(n_33_reg_887),
        .O19(n_34_reg_887),
        .O2(n_1_reg_887),
        .O20(n_35_reg_887),
        .O21(n_36_reg_887),
        .O22(n_37_reg_887),
        .O23(n_38_reg_887),
        .O24(n_39_reg_887),
        .O25(n_40_reg_887),
        .O26(n_41_reg_887),
        .O27(n_42_reg_887),
        .O28(n_43_reg_887),
        .O29(n_44_reg_887),
        .O3(n_2_reg_887),
        .O30(n_45_reg_887),
        .O31(n_46_reg_887),
        .O32(n_47_reg_887),
        .O4(n_3_reg_887),
        .O5(n_4_reg_887),
        .O6(n_5_reg_887),
        .O7(n_6_reg_887),
        .O8(n_7_reg_887),
        .O9(n_8_reg_887),
        .Q({\n_0_MU_STATUS[5].mu_tpid_reg ,\n_1_MU_STATUS[5].mu_tpid_reg ,\n_2_MU_STATUS[5].mu_tpid_reg ,\n_3_MU_STATUS[5].mu_tpid_reg ,\n_4_MU_STATUS[5].mu_tpid_reg ,\n_5_MU_STATUS[5].mu_tpid_reg ,\n_6_MU_STATUS[5].mu_tpid_reg ,\n_8_MU_STATUS[5].mu_tpid_reg ,\n_9_MU_STATUS[5].mu_tpid_reg ,\n_10_MU_STATUS[5].mu_tpid_reg ,\n_11_MU_STATUS[5].mu_tpid_reg ,\n_12_MU_STATUS[5].mu_tpid_reg ,\n_13_MU_STATUS[5].mu_tpid_reg ,\n_14_MU_STATUS[5].mu_tpid_reg ,\n_15_MU_STATUS[5].mu_tpid_reg }),
        .s_daddr_o({n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}));
ila_0_xsdbs_v1_0_reg__parameterized65 reg_88d
       (.E(den),
        .I1(s_dclk),
        .I7(I7),
        .Q({n_0_reg_88d,n_1_reg_88d,n_2_reg_88d,n_3_reg_88d,n_4_reg_88d,n_5_reg_88d,n_6_reg_88d,n_7_reg_88d,n_8_reg_88d,n_9_reg_88d,n_10_reg_88d,n_11_reg_88d,n_12_reg_88d,n_13_reg_88d,n_14_reg_88d,n_15_reg_88d}));
ila_0_xsdbs_v1_0_reg__parameterized67 reg_88f
       (.E(den),
        .I1({n_12_reg_88d,n_13_reg_88d,n_14_reg_88d,n_15_reg_88d}),
        .I2({n_13_reg_2,n_14_reg_2,n_15_reg_2,n_16_reg_2}),
        .I3(s_dclk),
        .I9(I9),
        .O1(n_0_reg_88f),
        .O2(n_1_reg_88f),
        .O3(n_2_reg_88f),
        .O4(n_3_reg_88f),
        .O5({n_4_reg_88f,n_5_reg_88f,n_6_reg_88f,n_7_reg_88f,n_8_reg_88f,n_9_reg_88f,n_10_reg_88f,n_11_reg_88f,n_12_reg_88f,n_13_reg_88f,n_14_reg_88f,n_15_reg_88f}),
        .Q({n_0_reg_892,n_1_reg_892,n_2_reg_892,n_3_reg_892}),
        .s_daddr_o(s_daddr_o[1:0]));
ila_0_xsdbs_v1_0_reg__parameterized66 reg_892
       (.E(den),
        .I1(s_dclk),
        .I8(I8),
        .Q({n_0_reg_892,n_1_reg_892,n_2_reg_892,n_3_reg_892}));
ila_0_xsdbs_v1_0_reg__parameterized8 reg_9
       (.E(den),
        .I1(n_17_reg_19),
        .I2(n_0_reg_1),
        .I3(s_dclk),
        .I6(I6),
        .O1(n_0_reg_9),
        .Q({n_1_reg_9,n_2_reg_9,n_3_reg_9,n_4_reg_9,n_5_reg_9,n_6_reg_9,n_7_reg_9,n_8_reg_9,n_9_reg_9,n_10_reg_9,n_11_reg_9,n_12_reg_9,n_13_reg_9,n_14_reg_9,n_15_reg_9}),
        .s_daddr_o({n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}));
ila_0_xsdbs_v1_0_reg__parameterized9 reg_a
       (.E(den),
        .I1(s_dclk),
        .Q({n_0_reg_a,n_1_reg_a,n_2_reg_a,n_3_reg_a,n_4_reg_a,n_5_reg_a,n_6_reg_a,n_7_reg_a,n_8_reg_a,n_9_reg_a,n_10_reg_a,n_11_reg_a,n_12_reg_a,n_13_reg_a,n_14_reg_a,n_15_reg_a}));
ila_0_xsdbs_v1_0_reg__parameterized10 reg_b
       (.E(den),
        .I1(n_1_reg_83),
        .I10({n_2_reg_13,n_3_reg_13,n_4_reg_13,n_5_reg_13,n_6_reg_13,n_7_reg_13,n_8_reg_13,n_9_reg_13,n_10_reg_13,n_11_reg_13,n_12_reg_13,n_13_reg_13,n_14_reg_13,n_15_reg_13}),
        .I11(n_1_reg_13),
        .I12(n_0_reg_13),
        .I13(s_dclk),
        .I2(\n_0_slaveRegDo_mux_0[11]_i_17 ),
        .I3(n_1_reg_3),
        .I4(\n_0_slaveRegDo_mux_0[15]_i_20 ),
        .I5(n_3_reg_f),
        .I6(n_11_reg_7),
        .I7(n_0_reg_3),
        .I8(n_4_reg_f),
        .I9(n_1_reg_7),
        .O1(n_0_reg_b),
        .O10(n_9_reg_b),
        .O11(n_10_reg_b),
        .O12(n_11_reg_b),
        .O13(n_12_reg_b),
        .O14(n_13_reg_b),
        .O15(n_14_reg_b),
        .O16(n_15_reg_b),
        .O2(n_1_reg_b),
        .O3(n_2_reg_b),
        .O4(n_3_reg_b),
        .O5(n_4_reg_b),
        .O6(n_5_reg_b),
        .O7(n_6_reg_b),
        .O8(n_7_reg_b),
        .O9(n_8_reg_b),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}));
ila_0_xsdbs_v1_0_reg__parameterized11 reg_c
       (.E(den),
        .I1(s_dclk),
        .O1(n_0_reg_c),
        .O12({n_13_reg_10,n_14_reg_10,n_15_reg_10}),
        .O2(n_1_reg_c),
        .O3(n_2_reg_c),
        .O4(n_3_reg_c),
        .O5({n_4_reg_c,n_5_reg_c,n_6_reg_c,n_7_reg_c,n_8_reg_c,n_9_reg_c,n_10_reg_c,n_11_reg_c,n_12_reg_c,n_13_reg_c,n_14_reg_c,n_15_reg_c}),
        .Q({n_12_reg_0,n_14_reg_0,n_15_reg_0}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2:1]}));
ila_0_xsdbs_v1_0_reg__parameterized12 reg_d
       (.E(den),
        .I1(n_17_reg_15),
        .I2(s_dclk),
        .O1(n_0_reg_d),
        .Q({n_1_reg_d,n_2_reg_d,n_3_reg_d,n_4_reg_d,n_5_reg_d,n_6_reg_d,n_7_reg_d,n_8_reg_d,n_9_reg_d,n_10_reg_d,n_11_reg_d,n_12_reg_d,n_13_reg_d,n_14_reg_d,n_15_reg_d}),
        .s_daddr_o({n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}));
ila_0_xsdbs_v1_0_reg__parameterized13 reg_e
       (.E(den),
        .I1(\n_0_slaveRegDo_mux_0[12]_i_14 ),
        .I10(n_6_reg_12),
        .I11(n_7_reg_12),
        .I12(n_8_reg_12),
        .I13(n_9_reg_12),
        .I14(s_dclk),
        .I2(n_12_reg_12),
        .I3(n_16_reg_1a),
        .I4(n_13_reg_12),
        .I5(n_17_reg_1a),
        .I6(n_6_reg_16),
        .I7(n_7_reg_16),
        .I8(O7),
        .I9(O10),
        .O1(n_0_reg_e),
        .O10(n_7_reg_e),
        .O11(n_8_reg_e),
        .O12(n_9_reg_e),
        .O13(n_10_reg_e),
        .O14(n_11_reg_e),
        .O2(n_1_reg_e),
        .O3(n_2_reg_e),
        .O4(n_3_reg_e),
        .O5(n_4_reg_e),
        .O6(O6),
        .O7(n_5_reg_e),
        .O8(n_6_reg_e),
        .O9(O9),
        .Q({n_12_reg_e,n_13_reg_e,n_14_reg_e,n_15_reg_e}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2:1]}));
ila_0_xsdbs_v1_0_reg__parameterized14 reg_f
       (.E(den),
        .I1(n_15_reg_83),
        .I10(n_8_reg_17),
        .I11(n_17_reg_7),
        .I12(n_10_reg_17),
        .I13(n_18_reg_7),
        .I14(s_dclk),
        .I2(n_14_reg_83),
        .I3(n_13_reg_83),
        .I4(n_1_reg_17),
        .I5(n_14_reg_7),
        .I6(n_2_reg_17),
        .I7(n_15_reg_7),
        .I8(n_4_reg_17),
        .I9(n_16_reg_7),
        .O1(n_0_reg_f),
        .O2(n_1_reg_f),
        .O3(n_2_reg_f),
        .O4(n_3_reg_f),
        .O5(n_4_reg_f),
        .Q({n_5_reg_f,n_6_reg_f,n_7_reg_f,n_8_reg_f,n_9_reg_f,n_10_reg_f,n_11_reg_f,n_12_reg_f,n_13_reg_f,n_14_reg_f,n_15_reg_f}),
        .s_daddr_o({n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o[2]}));
ila_0_xsdbs_v1_0_reg_p2s reg_srl_fff
       (.D(D),
        .E(den),
        .I1(s_dclk),
        .I10(I10),
        .O1(n_0_reg_srl_fff),
        .O10(n_9_reg_srl_fff),
        .O11(n_10_reg_srl_fff),
        .O12(n_11_reg_srl_fff),
        .O13(n_12_reg_srl_fff),
        .O14(n_13_reg_srl_fff),
        .O15(n_14_reg_srl_fff),
        .O16(n_15_reg_srl_fff),
        .O2(n_1_reg_srl_fff),
        .O3(n_2_reg_srl_fff),
        .O4(n_3_reg_srl_fff),
        .O5(n_4_reg_srl_fff),
        .O6(n_5_reg_srl_fff),
        .O7(n_6_reg_srl_fff),
        .O8(n_7_reg_srl_fff),
        .O9(n_8_reg_srl_fff),
        .Q({n_0_reg_stream_ffe,n_1_reg_stream_ffe,n_2_reg_stream_ffe,n_3_reg_stream_ffe,n_4_reg_stream_ffe,n_5_reg_stream_ffe,n_6_reg_stream_ffe,n_7_reg_stream_ffe,n_8_reg_stream_ffe,n_9_reg_stream_ffe,n_10_reg_stream_ffe,n_11_reg_stream_ffe,n_12_reg_stream_ffe,n_13_reg_stream_ffe,n_14_reg_stream_ffe,n_15_reg_stream_ffe}),
        .capture_ctrl_config_serial_output(capture_ctrl_config_serial_output),
        .debug_data_in(debug_data_in),
        .dwe(dwe),
        .s_daddr_o({n_8_U_XSDB_SLAVE,n_9_U_XSDB_SLAVE,n_10_U_XSDB_SLAVE,n_11_U_XSDB_SLAVE,n_12_U_XSDB_SLAVE,n_13_U_XSDB_SLAVE,n_14_U_XSDB_SLAVE,n_15_U_XSDB_SLAVE,n_16_U_XSDB_SLAVE,n_17_U_XSDB_SLAVE,s_daddr_o}),
        .s_di_o(s_di),
        .shift_en_o(shift_en_o));
ila_0_xsdbs_v1_0_reg_stream__parameterized1 reg_stream_ffd
       (.I1(\n_2_ADV_TRIG_STREAM.reg_stream_ffc ),
        .I2(s_dclk),
        .debug_data_in(debug_data_in),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o[1:0]),
        .s_di_o(s_di));
ila_0_xsdbs_v1_0_reg_stream__parameterized2 reg_stream_ffe
       (.E(E),
        .I1(s_dclk),
        .I4(I4),
        .Q({n_0_reg_stream_ffe,n_1_reg_stream_ffe,n_2_reg_stream_ffe,n_3_reg_stream_ffe,n_4_reg_stream_ffe,n_5_reg_stream_ffe,n_6_reg_stream_ffe,n_7_reg_stream_ffe,n_8_reg_stream_ffe,n_9_reg_stream_ffe,n_10_reg_stream_ffe,n_11_reg_stream_ffe,n_12_reg_stream_ffe,n_13_reg_stream_ffe,n_14_reg_stream_ffe,n_15_reg_stream_ffe}));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[0]_i_2 
       (.I0(\n_0_slaveRegDo_mux_3_reg[0] ),
        .I1(\n_0_slaveRegDo_mux_2_reg[0] ),
        .I2(n_9_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[0]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[0] ),
        .O(\n_0_slaveRegDo_mux[0]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[0]_i_3 
       (.I0(slaveRegDo_mux_6[0]),
        .I1(n_9_U_XSDB_SLAVE),
        .I2(slaveRegDo_mux_5[0]),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(slaveRegDo_mux_4[0]),
        .O(\n_0_slaveRegDo_mux[0]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[10]_i_2 
       (.I0(slaveRegDo_mux_5[10]),
        .I1(slaveRegDo_mux_4[10]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[10]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[10] ),
        .O(\n_0_slaveRegDo_mux[10]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[10]_i_3 
       (.I0(slaveRegDo_mux_6[10]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[10] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[10] ),
        .O(\n_0_slaveRegDo_mux[10]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[11]_i_2 
       (.I0(slaveRegDo_mux_5[11]),
        .I1(slaveRegDo_mux_4[11]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[11]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[11] ),
        .O(\n_0_slaveRegDo_mux[11]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[11]_i_3 
       (.I0(slaveRegDo_mux_6[11]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[11] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[11] ),
        .O(\n_0_slaveRegDo_mux[11]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[12]_i_2 
       (.I0(\n_0_slaveRegDo_mux_3_reg[12] ),
        .I1(\n_0_slaveRegDo_mux_2_reg[12] ),
        .I2(n_9_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[12]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[12] ),
        .O(\n_0_slaveRegDo_mux[12]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[12]_i_3 
       (.I0(slaveRegDo_mux_6[12]),
        .I1(n_9_U_XSDB_SLAVE),
        .I2(slaveRegDo_mux_5[12]),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(slaveRegDo_mux_4[12]),
        .O(\n_0_slaveRegDo_mux[12]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[13]_i_2 
       (.I0(slaveRegDo_mux_5[13]),
        .I1(slaveRegDo_mux_4[13]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[13]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[13] ),
        .O(\n_0_slaveRegDo_mux[13]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[13]_i_3 
       (.I0(slaveRegDo_mux_6[13]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[13] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[13] ),
        .O(\n_0_slaveRegDo_mux[13]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[14]_i_2 
       (.I0(slaveRegDo_mux_5[14]),
        .I1(slaveRegDo_mux_4[14]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[14]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[14] ),
        .O(\n_0_slaveRegDo_mux[14]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[14]_i_3 
       (.I0(slaveRegDo_mux_6[14]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[14] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[14] ),
        .O(\n_0_slaveRegDo_mux[14]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[15]_i_2 
       (.I0(\n_0_slaveRegDo_mux_3_reg[15] ),
        .I1(\n_0_slaveRegDo_mux_2_reg[15] ),
        .I2(n_9_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[15]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[15] ),
        .O(\n_0_slaveRegDo_mux[15]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[15]_i_3 
       (.I0(slaveRegDo_mux_6[15]),
        .I1(n_9_U_XSDB_SLAVE),
        .I2(slaveRegDo_mux_5[15]),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(slaveRegDo_mux_4[15]),
        .O(\n_0_slaveRegDo_mux[15]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[1]_i_2 
       (.I0(slaveRegDo_mux_5[1]),
        .I1(slaveRegDo_mux_4[1]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[1]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[1] ),
        .O(\n_0_slaveRegDo_mux[1]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[1]_i_3 
       (.I0(slaveRegDo_mux_6[1]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[1] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[1] ),
        .O(\n_0_slaveRegDo_mux[1]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[2]_i_2 
       (.I0(slaveRegDo_mux_5[2]),
        .I1(slaveRegDo_mux_4[2]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[2]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[2] ),
        .O(\n_0_slaveRegDo_mux[2]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[2]_i_3 
       (.I0(slaveRegDo_mux_6[2]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[2] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[2] ),
        .O(\n_0_slaveRegDo_mux[2]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[3]_i_2 
       (.I0(\n_0_slaveRegDo_mux_3_reg[3] ),
        .I1(\n_0_slaveRegDo_mux_2_reg[3] ),
        .I2(n_9_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[3]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[3] ),
        .O(\n_0_slaveRegDo_mux[3]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[3]_i_3 
       (.I0(slaveRegDo_mux_6[3]),
        .I1(n_9_U_XSDB_SLAVE),
        .I2(slaveRegDo_mux_5[3]),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(slaveRegDo_mux_4[3]),
        .O(\n_0_slaveRegDo_mux[3]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[4]_i_2 
       (.I0(slaveRegDo_mux_5[4]),
        .I1(slaveRegDo_mux_4[4]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[4]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[4] ),
        .O(\n_0_slaveRegDo_mux[4]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[4]_i_3 
       (.I0(slaveRegDo_mux_6[4]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[4] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[4] ),
        .O(\n_0_slaveRegDo_mux[4]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[5]_i_2 
       (.I0(\n_0_slaveRegDo_mux_3_reg[5] ),
        .I1(\n_0_slaveRegDo_mux_2_reg[5] ),
        .I2(n_9_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[5]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[5] ),
        .O(\n_0_slaveRegDo_mux[5]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[5]_i_3 
       (.I0(slaveRegDo_mux_6[5]),
        .I1(n_9_U_XSDB_SLAVE),
        .I2(slaveRegDo_mux_5[5]),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(slaveRegDo_mux_4[5]),
        .O(\n_0_slaveRegDo_mux[5]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[6]_i_2 
       (.I0(slaveRegDo_mux_5[6]),
        .I1(slaveRegDo_mux_4[6]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[6]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[6] ),
        .O(\n_0_slaveRegDo_mux[6]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[6]_i_3 
       (.I0(slaveRegDo_mux_6[6]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[6] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[6] ),
        .O(\n_0_slaveRegDo_mux[6]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[7]_i_2 
       (.I0(slaveRegDo_mux_5[7]),
        .I1(slaveRegDo_mux_4[7]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[7]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[7] ),
        .O(\n_0_slaveRegDo_mux[7]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[7]_i_3 
       (.I0(slaveRegDo_mux_6[7]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[7] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[7] ),
        .O(\n_0_slaveRegDo_mux[7]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[8]_i_2 
       (.I0(slaveRegDo_mux_5[8]),
        .I1(slaveRegDo_mux_4[8]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[8]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[8] ),
        .O(\n_0_slaveRegDo_mux[8]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[8]_i_3 
       (.I0(slaveRegDo_mux_6[8]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[8] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[8] ),
        .O(\n_0_slaveRegDo_mux[8]_i_3 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux[9]_i_2 
       (.I0(slaveRegDo_mux_5[9]),
        .I1(slaveRegDo_mux_4[9]),
        .I2(n_8_U_XSDB_SLAVE),
        .I3(slaveRegDo_mux_1[9]),
        .I4(n_10_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_0_reg[9] ),
        .O(\n_0_slaveRegDo_mux[9]_i_2 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux[9]_i_3 
       (.I0(slaveRegDo_mux_6[9]),
        .I1(n_8_U_XSDB_SLAVE),
        .I2(\n_0_slaveRegDo_mux_3_reg[9] ),
        .I3(n_10_U_XSDB_SLAVE),
        .I4(\n_0_slaveRegDo_mux_2_reg[9] ),
        .O(\n_0_slaveRegDo_mux[9]_i_3 ));
(* SOFT_HLUTNM = "soft_lutpair250" *) 
   LUT3 #(
    .INIT(8'h01)) 
     \slaveRegDo_mux_0[11]_i_17 
       (.I0(s_daddr_o[2]),
        .I1(n_15_U_XSDB_SLAVE),
        .I2(n_14_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_0[11]_i_17 ));
(* SOFT_HLUTNM = "soft_lutpair247" *) 
   LUT3 #(
    .INIT(8'hBF)) 
     \slaveRegDo_mux_0[12]_i_14 
       (.I0(n_16_U_XSDB_SLAVE),
        .I1(n_17_U_XSDB_SLAVE),
        .I2(s_daddr_o[2]),
        .O(\n_0_slaveRegDo_mux_0[12]_i_14 ));
(* SOFT_HLUTNM = "soft_lutpair249" *) 
   LUT4 #(
    .INIT(16'h0004)) 
     \slaveRegDo_mux_0[12]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .I2(n_15_U_XSDB_SLAVE),
        .I3(n_14_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_0[12]_i_4 ));
(* SOFT_HLUTNM = "soft_lutpair247" *) 
   LUT4 #(
    .INIT(16'hFFF7)) 
     \slaveRegDo_mux_0[15]_i_15 
       (.I0(n_17_U_XSDB_SLAVE),
        .I1(s_daddr_o[2]),
        .I2(n_16_U_XSDB_SLAVE),
        .I3(n_13_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_0[15]_i_15 ));
LUT2 #(
    .INIT(4'hE)) 
     \slaveRegDo_mux_0[15]_i_17 
       (.I0(n_14_U_XSDB_SLAVE),
        .I1(n_15_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_0[15]_i_17 ));
(* SOFT_HLUTNM = "soft_lutpair250" *) 
   LUT4 #(
    .INIT(16'h0004)) 
     \slaveRegDo_mux_0[15]_i_20 
       (.I0(n_13_U_XSDB_SLAVE),
        .I1(s_daddr_o[2]),
        .I2(n_15_U_XSDB_SLAVE),
        .I3(n_14_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_0[15]_i_20 ));
LUT2 #(
    .INIT(4'h2)) 
     \slaveRegDo_mux_0[15]_i_22 
       (.I0(s_daddr_o[2]),
        .I1(n_17_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_0[15]_i_22 ));
LUT6 #(
    .INIT(64'hFF2F0000FFFFFFFF)) 
     \slaveRegDo_mux_0[15]_i_6 
       (.I0(s_daddr_o[2]),
        .I1(n_1_reg_83),
        .I2(\n_0_slaveRegDo_mux_6[15]_i_3 ),
        .I3(\n_0_slaveRegDo_mux_0[15]_i_17 ),
        .I4(n_13_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_6[15]_i_4 ),
        .O(\n_0_slaveRegDo_mux_0[15]_i_6 ));
(* SOFT_HLUTNM = "soft_lutpair249" *) 
   LUT3 #(
    .INIT(8'h01)) 
     \slaveRegDo_mux_0[3]_i_4 
       (.I0(s_daddr_o[0]),
        .I1(n_15_U_XSDB_SLAVE),
        .I2(n_14_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_0[3]_i_4 ));
FDRE \slaveRegDo_mux_0_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(\n_0_slaveRegDo_mux_0_reg[0] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[10]),
        .Q(\n_0_slaveRegDo_mux_0_reg[10] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[11]),
        .Q(\n_0_slaveRegDo_mux_0_reg[11] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[12]),
        .Q(\n_0_slaveRegDo_mux_0_reg[12] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[13]),
        .Q(\n_0_slaveRegDo_mux_0_reg[13] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[14]),
        .Q(\n_0_slaveRegDo_mux_0_reg[14] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[15]),
        .Q(\n_0_slaveRegDo_mux_0_reg[15] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(\n_0_slaveRegDo_mux_0_reg[1] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(\n_0_slaveRegDo_mux_0_reg[2] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(\n_0_slaveRegDo_mux_0_reg[3] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(\n_0_slaveRegDo_mux_0_reg[4] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[5]),
        .Q(\n_0_slaveRegDo_mux_0_reg[5] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[6]),
        .Q(\n_0_slaveRegDo_mux_0_reg[6] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[7]),
        .Q(\n_0_slaveRegDo_mux_0_reg[7] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[8]),
        .Q(\n_0_slaveRegDo_mux_0_reg[8] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_0_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in[9]),
        .Q(\n_0_slaveRegDo_mux_0_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair252" *) 
   LUT3 #(
    .INIT(8'hEF)) 
     \slaveRegDo_mux_1[15]_i_10 
       (.I0(n_15_U_XSDB_SLAVE),
        .I1(n_17_U_XSDB_SLAVE),
        .I2(n_16_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_1[15]_i_10 ));
LUT4 #(
    .INIT(16'h5545)) 
     \slaveRegDo_mux_1[15]_i_5 
       (.I0(s_daddr_o[0]),
        .I1(n_16_U_XSDB_SLAVE),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .O(\n_0_slaveRegDo_mux_1[15]_i_5 ));
FDRE \slaveRegDo_mux_1_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_20_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[0]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_11_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[10]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_10_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[11]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_9_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[12]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_8_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[13]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_7_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[14]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_6_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[15]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_19_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[1]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_18_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[2]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_17_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[3]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_16_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[4]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_15_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[5]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_14_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[6]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_13_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[7]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_8_reg_4),
        .Q(slaveRegDo_mux_1[8]),
        .R(1'b0));
FDRE \slaveRegDo_mux_1_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_12_MU_STATUS[10].mu_tpid_reg ),
        .Q(slaveRegDo_mux_1[9]),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0000000100000000)) 
     \slaveRegDo_mux_2[15]_i_2 
       (.I0(n_14_U_XSDB_SLAVE),
        .I1(n_15_U_XSDB_SLAVE),
        .I2(n_16_U_XSDB_SLAVE),
        .I3(n_11_U_XSDB_SLAVE),
        .I4(n_12_U_XSDB_SLAVE),
        .I5(n_13_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_2[15]_i_2 ));
FDRE \slaveRegDo_mux_2_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_30_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[0] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_20_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[10] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_19_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[11] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_18_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[12] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_17_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[13] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_16_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[14] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_15_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[15] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_29_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[1] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_28_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[2] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_27_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[3] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_26_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[4] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_25_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[5] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_24_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[6] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_23_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[7] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_22_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[8] ),
        .R(1'b0));
FDRE \slaveRegDo_mux_2_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_21_reg_887),
        .Q(\n_0_slaveRegDo_mux_2_reg[9] ),
        .R(1'b0));
LUT6 #(
    .INIT(64'hDFFFFFFFFFFFFFFF)) 
     \slaveRegDo_mux_3[15]_i_1 
       (.I0(n_15_U_XSDB_SLAVE),
        .I1(\n_0_slaveRegDo_mux_3[15]_i_3 ),
        .I2(n_14_U_XSDB_SLAVE),
        .I3(n_13_U_XSDB_SLAVE),
        .I4(n_12_U_XSDB_SLAVE),
        .I5(n_11_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_3[15]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair254" *) 
   LUT2 #(
    .INIT(4'h7)) 
     \slaveRegDo_mux_3[15]_i_3 
       (.I0(n_17_U_XSDB_SLAVE),
        .I1(n_16_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_3[15]_i_3 ));
FDRE \slaveRegDo_mux_3_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_15_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[0] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_5_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[10] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_4_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[11] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_3_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[12] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_2_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[13] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_1_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[14] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[15] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_14_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[1] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_13_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[2] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_12_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[3] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_11_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[4] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_10_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[5] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_9_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[6] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_8_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[7] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_7_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[8] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_3_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_6_ADV_TRIG_STREAM_READBACK.reg_stream_ffb ),
        .Q(\n_0_slaveRegDo_mux_3_reg[9] ),
        .R(\n_0_slaveRegDo_mux_3[15]_i_1 ));
FDRE \slaveRegDo_mux_4_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_15_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[0]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_5_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[10]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_4_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[11]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_3_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[12]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_2_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[13]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_1_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[14]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[15]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_14_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[1]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_13_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[2]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_12_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[3]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_11_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[4]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_10_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[5]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_9_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[6]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_8_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[7]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_7_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[8]),
        .R(1'b0));
FDRE \slaveRegDo_mux_4_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_6_MU_SRL[12].mu_srl_reg ),
        .Q(slaveRegDo_mux_4[9]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_15_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[0]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_5_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[10]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_4_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[11]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_3_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[12]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_2_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[13]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_1_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[14]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[15]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_14_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[1]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_13_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[2]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_12_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[3]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_11_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[4]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_10_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[5]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_9_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[6]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_8_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[7]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_7_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[8]),
        .R(1'b0));
FDRE \slaveRegDo_mux_5_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_6_TC_SRL[27].tc_srl_reg ),
        .Q(slaveRegDo_mux_5[9]),
        .R(1'b0));
LUT6 #(
    .INIT(64'hFFFFFFFDFFFFFFFF)) 
     \slaveRegDo_mux_6[15]_i_1 
       (.I0(\n_0_slaveRegDo_mux_6[15]_i_3 ),
        .I1(s_daddr_o[2]),
        .I2(n_15_U_XSDB_SLAVE),
        .I3(n_13_U_XSDB_SLAVE),
        .I4(n_14_U_XSDB_SLAVE),
        .I5(\n_0_slaveRegDo_mux_6[15]_i_4 ),
        .O(\n_0_slaveRegDo_mux_6[15]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair254" *) 
   LUT2 #(
    .INIT(4'h1)) 
     \slaveRegDo_mux_6[15]_i_3 
       (.I0(n_17_U_XSDB_SLAVE),
        .I1(n_16_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_6[15]_i_3 ));
(* SOFT_HLUTNM = "soft_lutpair251" *) 
   LUT2 #(
    .INIT(4'h1)) 
     \slaveRegDo_mux_6[15]_i_4 
       (.I0(n_11_U_XSDB_SLAVE),
        .I1(n_12_U_XSDB_SLAVE),
        .O(\n_0_slaveRegDo_mux_6[15]_i_4 ));
FDRE \slaveRegDo_mux_6_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[0]),
        .Q(slaveRegDo_mux_6[0]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[10]),
        .Q(slaveRegDo_mux_6[10]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[11]),
        .Q(slaveRegDo_mux_6[11]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[12]),
        .Q(slaveRegDo_mux_6[12]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[13]),
        .Q(slaveRegDo_mux_6[13]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[14]),
        .Q(slaveRegDo_mux_6[14]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[15]),
        .Q(slaveRegDo_mux_6[15]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[1]),
        .Q(slaveRegDo_mux_6[1]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[2]),
        .Q(slaveRegDo_mux_6[2]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[3]),
        .Q(slaveRegDo_mux_6[3]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[4]),
        .Q(slaveRegDo_mux_6[4]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[5]),
        .Q(slaveRegDo_mux_6[5]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[6]),
        .Q(slaveRegDo_mux_6[6]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[7]),
        .Q(slaveRegDo_mux_6[7]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[8]),
        .Q(slaveRegDo_mux_6[8]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_6_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_1_in[9]),
        .Q(slaveRegDo_mux_6[9]),
        .R(\n_0_slaveRegDo_mux_6[15]_i_1 ));
FDRE \slaveRegDo_mux_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[0]),
        .Q(\n_0_slaveRegDo_mux_reg[0] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[0]_i_1 
       (.I0(\n_0_slaveRegDo_mux[0]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[0]_i_3 ),
        .O(slaveRegDo_mux[0]),
        .S(n_8_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[10]),
        .Q(\n_0_slaveRegDo_mux_reg[10] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[10]_i_1 
       (.I0(\n_0_slaveRegDo_mux[10]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[10]_i_3 ),
        .O(slaveRegDo_mux[10]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[11]),
        .Q(\n_0_slaveRegDo_mux_reg[11] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[11]_i_1 
       (.I0(\n_0_slaveRegDo_mux[11]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[11]_i_3 ),
        .O(slaveRegDo_mux[11]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[12]),
        .Q(\n_0_slaveRegDo_mux_reg[12] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[12]_i_1 
       (.I0(\n_0_slaveRegDo_mux[12]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[12]_i_3 ),
        .O(slaveRegDo_mux[12]),
        .S(n_8_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[13]),
        .Q(\n_0_slaveRegDo_mux_reg[13] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[13]_i_1 
       (.I0(\n_0_slaveRegDo_mux[13]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[13]_i_3 ),
        .O(slaveRegDo_mux[13]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[14]),
        .Q(\n_0_slaveRegDo_mux_reg[14] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[14]_i_1 
       (.I0(\n_0_slaveRegDo_mux[14]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[14]_i_3 ),
        .O(slaveRegDo_mux[14]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[15]),
        .Q(\n_0_slaveRegDo_mux_reg[15] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[15]_i_1 
       (.I0(\n_0_slaveRegDo_mux[15]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[15]_i_3 ),
        .O(slaveRegDo_mux[15]),
        .S(n_8_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[1]),
        .Q(\n_0_slaveRegDo_mux_reg[1] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[1]_i_1 
       (.I0(\n_0_slaveRegDo_mux[1]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[1]_i_3 ),
        .O(slaveRegDo_mux[1]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[2]),
        .Q(\n_0_slaveRegDo_mux_reg[2] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[2]_i_1 
       (.I0(\n_0_slaveRegDo_mux[2]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[2]_i_3 ),
        .O(slaveRegDo_mux[2]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[3]),
        .Q(\n_0_slaveRegDo_mux_reg[3] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[3]_i_1 
       (.I0(\n_0_slaveRegDo_mux[3]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[3]_i_3 ),
        .O(slaveRegDo_mux[3]),
        .S(n_8_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[4]),
        .Q(\n_0_slaveRegDo_mux_reg[4] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[4]_i_1 
       (.I0(\n_0_slaveRegDo_mux[4]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[4]_i_3 ),
        .O(slaveRegDo_mux[4]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[5]),
        .Q(\n_0_slaveRegDo_mux_reg[5] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[5]_i_1 
       (.I0(\n_0_slaveRegDo_mux[5]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[5]_i_3 ),
        .O(slaveRegDo_mux[5]),
        .S(n_8_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[6]),
        .Q(\n_0_slaveRegDo_mux_reg[6] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[6]_i_1 
       (.I0(\n_0_slaveRegDo_mux[6]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[6]_i_3 ),
        .O(slaveRegDo_mux[6]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[7]),
        .Q(\n_0_slaveRegDo_mux_reg[7] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[7]_i_1 
       (.I0(\n_0_slaveRegDo_mux[7]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[7]_i_3 ),
        .O(slaveRegDo_mux[7]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[8]),
        .Q(\n_0_slaveRegDo_mux_reg[8] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[8]_i_1 
       (.I0(\n_0_slaveRegDo_mux[8]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[8]_i_3 ),
        .O(slaveRegDo_mux[8]),
        .S(n_9_U_XSDB_SLAVE));
FDRE \slaveRegDo_mux_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(slaveRegDo_mux[9]),
        .Q(\n_0_slaveRegDo_mux_reg[9] ),
        .R(1'b0));
MUXF7 \slaveRegDo_mux_reg[9]_i_1 
       (.I0(\n_0_slaveRegDo_mux[9]_i_2 ),
        .I1(\n_0_slaveRegDo_mux[9]_i_3 ),
        .O(slaveRegDo_mux[9]),
        .S(n_9_U_XSDB_SLAVE));
LUT2 #(
    .INIT(4'h6)) 
     toggle_rd_i_1
       (.I0(bram_rd_en),
        .I1(toggle_rd),
        .O(O5));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_reset_ctrl" *) 
module ila_0_ila_v5_0_ila_reset_ctrl
   (I5,
    Q,
    p_2_out,
    E,
    s_dclk,
    clk,
    I1,
    cap_state,
    halt_ctrl,
    arm_ctrl);
  output [1:0]I5;
  output [4:0]Q;
  output [0:0]p_2_out;
  output [0:0]E;
  input s_dclk;
  input clk;
  input [0:0]I1;
  input [0:0]cap_state;
  input halt_ctrl;
  input arm_ctrl;

  wire [0:0]E;
  wire [0:0]I1;
  wire [1:0]I5;
  wire [4:0]Q;
  wire arm_ctrl;
  wire arm_in_detection;
  wire arm_in_transferred;
  wire [0:0]cap_state;
  wire clk;
  wire halt_ctrl;
  wire halt_in_detection;
  wire halt_in_transferred;
  wire halt_out;
  wire last_din;
  wire last_din_0;
  wire n_0_halt_out_i_1;
  wire n_1_arm_detection_inst;
  wire \n_1_asyncrounous_transfer.arm_in_transfer_inst ;
  wire \n_1_asyncrounous_transfer.halt_in_transfer_inst ;
  wire n_1_halt_detection_inst;
  wire [3:3]p_0_out;
  wire [0:0]p_2_out;
  wire prev_cap_done;
  wire s_dclk;

ila_0_ltlib_v1_0_rising_edge_detection arm_detection_inst
       (.D(n_1_arm_detection_inst),
        .I1(\n_1_asyncrounous_transfer.arm_in_transfer_inst ),
        .O1(arm_in_detection),
        .Q(Q[1]),
        .arm_in_transferred(arm_in_transferred),
        .clk(clk),
        .last_din(last_din));
ila_0_ltlib_v1_0_async_edge_xfer \asyncrounous_transfer.arm_in_transfer_inst 
       (.I1(\n_1_asyncrounous_transfer.arm_in_transfer_inst ),
        .arm_ctrl(arm_ctrl),
        .arm_in_transferred(arm_in_transferred),
        .clk(clk),
        .last_din(last_din),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_async_edge_xfer_211 \asyncrounous_transfer.arm_out_transfer_inst 
       (.I5(I5[0]),
        .Q(Q[0]),
        .cap_state(cap_state),
        .clk(clk),
        .p_2_out(p_2_out),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_async_edge_xfer_212 \asyncrounous_transfer.halt_in_transfer_inst 
       (.D(\n_1_asyncrounous_transfer.halt_in_transfer_inst ),
        .clk(clk),
        .halt_ctrl(halt_ctrl),
        .halt_in_transferred(halt_in_transferred),
        .last_din(last_din_0),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_async_edge_xfer_213 \asyncrounous_transfer.halt_out_transfer_inst 
       (.I5(I5[1]),
        .clk(clk),
        .halt_out(halt_out),
        .s_dclk(s_dclk));
(* SOFT_HLUTNM = "soft_lutpair258" *) 
   LUT1 #(
    .INIT(2'h1)) 
     \captured_samples[9]_i_1 
       (.I0(Q[0]),
        .O(E));
ila_0_ltlib_v1_0_rising_edge_detection_214 halt_detection_inst
       (.D(\n_1_asyncrounous_transfer.halt_in_transfer_inst ),
        .I1(I1),
        .Q(halt_in_detection),
        .SS(n_1_halt_detection_inst),
        .clk(clk),
        .halt_in_transferred(halt_in_transferred),
        .last_din(last_din_0),
        .prev_cap_done(prev_cap_done));
(* SOFT_HLUTNM = "soft_lutpair258" *) 
   LUT4 #(
    .INIT(16'h00BA)) 
     halt_out_i_1
       (.I0(halt_out),
        .I1(Q[0]),
        .I2(halt_in_detection),
        .I3(arm_in_detection),
        .O(n_0_halt_out_i_1));
FDRE #(
    .INIT(1'b0)) 
     halt_out_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_halt_out_i_1),
        .Q(halt_out),
        .R(1'b0));
FDRE prev_cap_done_reg
       (.C(clk),
        .CE(1'b1),
        .D(I1),
        .Q(prev_cap_done),
        .R(1'b0));
FDSE #(
    .INIT(1'b1)) 
     \reset_out_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(n_1_arm_detection_inst),
        .Q(Q[0]),
        .S(n_1_halt_detection_inst));
FDSE #(
    .INIT(1'b1)) 
     \reset_out_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[0]),
        .Q(Q[1]),
        .S(n_1_halt_detection_inst));
FDSE #(
    .INIT(1'b1)) 
     \reset_out_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[1]),
        .Q(p_0_out),
        .S(n_1_halt_detection_inst));
FDSE #(
    .INIT(1'b1)) 
     \reset_out_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(p_0_out),
        .Q(Q[2]),
        .S(n_1_halt_detection_inst));
FDSE #(
    .INIT(1'b1)) 
     \reset_out_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[2]),
        .Q(Q[3]),
        .S(n_1_halt_detection_inst));
FDSE #(
    .INIT(1'b1)) 
     \reset_out_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[3]),
        .Q(Q[4]),
        .S(n_1_halt_detection_inst));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_trace_memory" *) 
module ila_0_ila_v5_0_ila_trace_memory
   (DOUTB,
    cap_wr_en,
    clk,
    D,
    S_DCLK_O,
    Q,
    I1,
    DINA);
  output [140:0]DOUTB;
  input cap_wr_en;
  input clk;
  input [0:0]D;
  input S_DCLK_O;
  input [9:0]Q;
  input [9:0]I1;
  input [140:0]DINA;

  wire [0:0]D;
  wire [140:0]DINA;
  wire [140:0]DOUTB;
  wire [9:0]I1;
  wire [9:0]Q;
  wire S_DCLK_O;
  wire cap_wr_en;
  wire clk;

ila_0_blk_mem_gen_v8_2 \SUBCORE_RAM_BLK_MEM_1.trace_block_memory 
       (.D(D),
        .DINA(DINA),
        .DOUTB(DOUTB),
        .I1(I1),
        .Q(Q),
        .S_DCLK_O(S_DCLK_O),
        .cap_wr_en(cap_wr_en),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_trig_match" *) 
module ila_0_ila_v5_0_ila_trig_match
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe1,
    probe2,
    probe4,
    probe5,
    probe7,
    probe8,
    probe10,
    probe11,
    I1,
    probe0,
    probe3,
    probe6,
    probe9,
    probe12);
  output [12:0]mu_config_cs_serial_input;
  output [12:0]D;
  input [12:0]mu_config_cs_shift_en;
  input s_dclk;
  input [12:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe1;
  input [0:0]probe2;
  input [0:0]probe4;
  input [0:0]probe5;
  input [0:0]probe7;
  input [0:0]probe8;
  input [0:0]probe10;
  input [0:0]probe11;
  input [15:0]I1;
  input [15:0]probe0;
  input [31:0]probe3;
  input [31:0]probe6;
  input [31:0]probe9;
  input [3:0]probe12;

  wire [12:0]D;
  wire [15:0]I1;
  wire [1:0]Q;
  wire clk;
  wire [12:0]mu_config_cs_serial_input;
  wire [12:0]mu_config_cs_serial_output;
  wire [12:0]mu_config_cs_shift_en;
  wire [15:0]probe0;
  wire [0:0]probe1;
  wire [0:0]probe10;
  wire [0:0]probe11;
  wire [3:0]probe12;
  wire [0:0]probe2;
  wire [31:0]probe3;
  wire [0:0]probe4;
  wire [0:0]probe5;
  wire [31:0]probe6;
  wire [0:0]probe7;
  wire [0:0]probe8;
  wire [31:0]probe9;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_match \G_NMU[0].U_M 
       (.D(D[0]),
        .I1(I1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[0]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[0]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[0]),
        .probe0(probe0),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized0 \G_NMU[10].U_M 
       (.D(D[10]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[10]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[10]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[10]),
        .probe10(probe10),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized0_155 \G_NMU[11].U_M 
       (.D(D[11]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[11]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[11]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[11]),
        .probe11(probe11),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized1 \G_NMU[12].U_M 
       (.D(D[12]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[12]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[12]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[12]),
        .probe12(probe12),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized0_156 \G_NMU[1].U_M 
       (.D(D[1]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[1]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[1]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[1]),
        .probe1(probe1),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized0_157 \G_NMU[2].U_M 
       (.D(D[2]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[2]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[2]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[2]),
        .probe2(probe2),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match_158 \G_NMU[3].U_M 
       (.D(D[3]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[3]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[3]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[3]),
        .probe3(probe3),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized0_159 \G_NMU[4].U_M 
       (.D(D[4]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[4]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[4]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[4]),
        .probe4(probe4),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized0_160 \G_NMU[5].U_M 
       (.D(D[5]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[5]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[5]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[5]),
        .probe5(probe5),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match_161 \G_NMU[6].U_M 
       (.D(D[6]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[6]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[6]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[6]),
        .probe6(probe6),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized0_162 \G_NMU[7].U_M 
       (.D(D[7]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[7]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[7]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[7]),
        .probe7(probe7),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match__parameterized0_163 \G_NMU[8].U_M 
       (.D(D[8]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[8]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[8]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[8]),
        .probe8(probe8),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
ila_0_ltlib_v1_0_match_164 \G_NMU[9].U_M 
       (.D(D[9]),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input[9]),
        .mu_config_cs_serial_output(mu_config_cs_serial_output[9]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en[9]),
        .probe9(probe9),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ila_v5_0_ila_trigger" *) 
module ila_0_ila_v5_0_ila_trigger
   (mu_config_cs_serial_input,
    tc_config_cs_serial_input,
    capture_strg_qual,
    ADDRA,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    tc_config_cs_shift_en,
    tc_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe1,
    probe2,
    probe4,
    probe5,
    probe7,
    probe8,
    probe10,
    probe11,
    addra,
    D,
    probe0,
    probe3,
    probe6,
    probe9,
    probe12);
  output [12:0]mu_config_cs_serial_input;
  output [31:0]tc_config_cs_serial_input;
  output capture_strg_qual;
  output [1:0]ADDRA;
  output [0:0]O1;
  input [12:0]mu_config_cs_shift_en;
  input s_dclk;
  input [12:0]mu_config_cs_serial_output;
  input [31:0]tc_config_cs_shift_en;
  input [31:0]tc_config_cs_serial_output;
  input [4:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe1;
  input [0:0]probe2;
  input [0:0]probe4;
  input [0:0]probe5;
  input [0:0]probe7;
  input [0:0]probe8;
  input [0:0]probe10;
  input [0:0]probe11;
  input [3:0]addra;
  input [15:0]D;
  input [15:0]probe0;
  input [31:0]probe3;
  input [31:0]probe6;
  input [31:0]probe9;
  input [3:0]probe12;

  wire [1:0]ADDRA;
  wire [15:0]D;
  wire [0:0]O1;
  wire [4:0]Q;
  wire [3:0]addra;
  wire [7:0]\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 ;
  wire [12:8]\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ;
  wire capture_strg_qual;
  wire clk;
  wire data0;
  wire data1;
  wire data10;
  wire data11;
  wire data12;
  wire data13;
  wire data14;
  wire data15;
  wire data2;
  wire data3;
  wire data4;
  wire data5;
  wire data6;
  wire data7;
  wire data8;
  wire data9;
  wire [12:0]mu_config_cs_serial_input;
  wire [12:0]mu_config_cs_serial_output;
  wire [12:0]mu_config_cs_shift_en;
  wire \n_0_TRIGGER_EQ_reg[10] ;
  wire \n_0_TRIGGER_EQ_reg[11] ;
  wire \n_0_TRIGGER_EQ_reg[12] ;
  wire \n_0_TRIGGER_EQ_reg[13] ;
  wire \n_0_TRIGGER_EQ_reg[14] ;
  wire \n_0_TRIGGER_EQ_reg[15] ;
  wire \n_0_TRIGGER_EQ_reg[1] ;
  wire \n_0_TRIGGER_EQ_reg[2] ;
  wire \n_0_TRIGGER_EQ_reg[3] ;
  wire \n_0_TRIGGER_EQ_reg[4] ;
  wire \n_0_TRIGGER_EQ_reg[5] ;
  wire \n_0_TRIGGER_EQ_reg[6] ;
  wire \n_0_TRIGGER_EQ_reg[7] ;
  wire \n_0_TRIGGER_EQ_reg[8] ;
  wire \n_0_TRIGGER_EQ_reg[9] ;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_10;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_11;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_12;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_13;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_14;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_15;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_16;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_5;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_6;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_7;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_8;
  wire n_0_fsm_mem_data_reg_r1_0_63_0_2_i_9;
  wire [15:0]probe0;
  wire [0:0]probe1;
  wire [0:0]probe10;
  wire [0:0]probe11;
  wire [3:0]probe12;
  wire [0:0]probe2;
  wire [31:0]probe3;
  wire [0:0]probe4;
  wire [0:0]probe5;
  wire [31:0]probe6;
  wire [0:0]probe7;
  wire [0:0]probe8;
  wire [31:0]probe9;
  wire s_dclk;
  wire shift_cap_strg_qual;
  wire [31:0]tc_config_cs_serial_input;
  wire [31:0]tc_config_cs_serial_output;
  wire [31:0]tc_config_cs_shift_en;
  wire [12:0]trigCondIn;
  wire [31:0]trigEqOut;
  wire use_probe_debug_circuit;

FDRE CAP_QUAL_STRG_reg
       (.C(clk),
        .CE(1'b1),
        .D(shift_cap_strg_qual),
        .Q(capture_strg_qual),
        .R(1'b0));
FDRE \TRIGGER_EQ_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[0]),
        .Q(O1),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[10]),
        .Q(\n_0_TRIGGER_EQ_reg[10] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[11]),
        .Q(\n_0_TRIGGER_EQ_reg[11] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[12]),
        .Q(\n_0_TRIGGER_EQ_reg[12] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[13]),
        .Q(\n_0_TRIGGER_EQ_reg[13] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[14]),
        .Q(\n_0_TRIGGER_EQ_reg[14] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[15]),
        .Q(\n_0_TRIGGER_EQ_reg[15] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[16]),
        .Q(data0),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[17]),
        .Q(data1),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[18]),
        .Q(data2),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[19]),
        .Q(data3),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[1]),
        .Q(\n_0_TRIGGER_EQ_reg[1] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[20]),
        .Q(data4),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[21]),
        .Q(data5),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[22]),
        .Q(data6),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[23]),
        .Q(data7),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[24]),
        .Q(data8),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[25]),
        .Q(data9),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[26]),
        .Q(data10),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[27]),
        .Q(data11),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[28]),
        .Q(data12),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[29]),
        .Q(data13),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[2]),
        .Q(\n_0_TRIGGER_EQ_reg[2] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[30]),
        .Q(data14),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[31]),
        .Q(data15),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[3]),
        .Q(\n_0_TRIGGER_EQ_reg[3] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[4]),
        .Q(\n_0_TRIGGER_EQ_reg[4] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[5]),
        .Q(\n_0_TRIGGER_EQ_reg[5] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[6]),
        .Q(\n_0_TRIGGER_EQ_reg[6] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[7]),
        .Q(\n_0_TRIGGER_EQ_reg[7] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[8]),
        .Q(\n_0_TRIGGER_EQ_reg[8] ),
        .R(Q[4]));
FDRE \TRIGGER_EQ_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(trigEqOut[9]),
        .Q(\n_0_TRIGGER_EQ_reg[9] ),
        .R(Q[4]));
ila_0_ila_v5_0_ila_trig_match U_TM
       (.D(trigCondIn),
        .I1(D),
        .Q(Q[1:0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe0(probe0),
        .probe1(probe1),
        .probe10(probe10),
        .probe11(probe11),
        .probe12(probe12),
        .probe2(probe2),
        .probe3(probe3),
        .probe4(probe4),
        .probe5(probe5),
        .probe6(probe6),
        .probe7(probe7),
        .probe8(probe8),
        .probe9(probe9),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_10
       (.I0(\n_0_TRIGGER_EQ_reg[7] ),
        .I1(\n_0_TRIGGER_EQ_reg[6] ),
        .I2(addra[1]),
        .I3(\n_0_TRIGGER_EQ_reg[5] ),
        .I4(addra[0]),
        .I5(\n_0_TRIGGER_EQ_reg[4] ),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_10));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_11
       (.I0(\n_0_TRIGGER_EQ_reg[11] ),
        .I1(\n_0_TRIGGER_EQ_reg[10] ),
        .I2(addra[1]),
        .I3(\n_0_TRIGGER_EQ_reg[9] ),
        .I4(addra[0]),
        .I5(\n_0_TRIGGER_EQ_reg[8] ),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_12
       (.I0(\n_0_TRIGGER_EQ_reg[15] ),
        .I1(\n_0_TRIGGER_EQ_reg[14] ),
        .I2(addra[1]),
        .I3(\n_0_TRIGGER_EQ_reg[13] ),
        .I4(addra[0]),
        .I5(\n_0_TRIGGER_EQ_reg[12] ),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_13
       (.I0(data3),
        .I1(data2),
        .I2(addra[1]),
        .I3(data1),
        .I4(addra[0]),
        .I5(data0),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_14
       (.I0(data7),
        .I1(data6),
        .I2(addra[1]),
        .I3(data5),
        .I4(addra[0]),
        .I5(data4),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_15
       (.I0(data11),
        .I1(data10),
        .I2(addra[1]),
        .I3(data9),
        .I4(addra[0]),
        .I5(data8),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_16
       (.I0(data15),
        .I1(data14),
        .I2(addra[1]),
        .I3(data13),
        .I4(addra[0]),
        .I5(data12),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_16));
MUXF8 fsm_mem_data_reg_r1_0_63_0_2_i_2
       (.I0(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_5),
        .I1(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_6),
        .O(ADDRA[1]),
        .S(addra[3]));
MUXF8 fsm_mem_data_reg_r1_0_63_0_2_i_3
       (.I0(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_7),
        .I1(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_8),
        .O(ADDRA[0]),
        .S(addra[3]));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_5
       (.I0(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_9),
        .I1(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_10),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_5),
        .S(addra[2]));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_6
       (.I0(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_11),
        .I1(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_12),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_6),
        .S(addra[2]));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_7
       (.I0(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_13),
        .I1(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_14),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_7),
        .S(addra[2]));
MUXF7 fsm_mem_data_reg_r1_0_63_0_2_i_8
       (.I0(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_15),
        .I1(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_16),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_8),
        .S(addra[2]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     fsm_mem_data_reg_r1_0_63_0_2_i_9
       (.I0(\n_0_TRIGGER_EQ_reg[3] ),
        .I1(\n_0_TRIGGER_EQ_reg[2] ),
        .I2(addra[1]),
        .I3(\n_0_TRIGGER_EQ_reg[1] ),
        .I4(addra[0]),
        .I5(O1),
        .O(n_0_fsm_mem_data_reg_r1_0_63_0_2_i_9));
ila_0_ltlib_v1_0_match__parameterized2 \genblk1[0].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[0]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[0]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[0]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[0]));
ila_0_ltlib_v1_0_match__parameterized2_0 \genblk1[10].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[10]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[10]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[10]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[10]));
ila_0_ltlib_v1_0_match__parameterized2_1 \genblk1[11].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[11]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[11]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[11]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[11]));
ila_0_ltlib_v1_0_match__parameterized2_2 \genblk1[12].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[12]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[12]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[12]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[12]));
ila_0_ltlib_v1_0_match__parameterized2_3 \genblk1[13].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[13]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[13]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[13]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[13]));
ila_0_ltlib_v1_0_match__parameterized2_4 \genblk1[14].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[14]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[14]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[14]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[14]));
ila_0_ltlib_v1_0_match__parameterized2_5 \genblk1[15].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[15]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[15]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[15]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[15]));
ila_0_ltlib_v1_0_match__parameterized2_6 \genblk1[16].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[16]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[16]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[16]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[16]));
ila_0_ltlib_v1_0_match__parameterized2_7 \genblk1[17].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[17]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[17]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[17]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[17]));
ila_0_ltlib_v1_0_match__parameterized2_8 \genblk1[18].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[18]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[18]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[18]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[18]));
ila_0_ltlib_v1_0_match__parameterized2_9 \genblk1[19].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[19]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[19]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[19]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[19]));
ila_0_ltlib_v1_0_match__parameterized2_10 \genblk1[1].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[1]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[1]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[1]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[1]));
ila_0_ltlib_v1_0_match__parameterized2_11 \genblk1[20].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[20]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[20]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[20]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[20]));
ila_0_ltlib_v1_0_match__parameterized2_12 \genblk1[21].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[21]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[21]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[21]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[21]));
ila_0_ltlib_v1_0_match__parameterized2_13 \genblk1[22].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[22]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[22]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[22]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[22]));
ila_0_ltlib_v1_0_match__parameterized2_14 \genblk1[23].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[23]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[23]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[23]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[23]));
ila_0_ltlib_v1_0_match__parameterized2_15 \genblk1[24].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[24]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[24]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[24]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[24]));
ila_0_ltlib_v1_0_match__parameterized2_16 \genblk1[25].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[25]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[25]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[25]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[25]));
ila_0_ltlib_v1_0_match__parameterized2_17 \genblk1[26].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[26]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[26]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[26]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[26]));
ila_0_ltlib_v1_0_match__parameterized2_18 \genblk1[27].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[27]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[27]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[27]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[27]));
ila_0_ltlib_v1_0_match__parameterized2_19 \genblk1[28].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[28]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[28]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[28]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[28]));
ila_0_ltlib_v1_0_match__parameterized2_20 \genblk1[29].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[29]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[29]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[29]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[29]));
ila_0_ltlib_v1_0_match__parameterized2_21 \genblk1[2].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[2]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[2]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[2]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[2]));
ila_0_ltlib_v1_0_match__parameterized2_22 \genblk1[30].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[30]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[30]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[30]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[30]));
ila_0_ltlib_v1_0_match__parameterized2_23 \genblk1[31].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[31]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[31]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[31]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[31]));
ila_0_ltlib_v1_0_match__parameterized2_24 \genblk1[3].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[3]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[3]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[3]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[3]));
ila_0_ltlib_v1_0_match__parameterized2_25 \genblk1[4].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[4]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[4]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[4]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[4]));
ila_0_ltlib_v1_0_match__parameterized2_26 \genblk1[5].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[5]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[5]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[5]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[5]));
ila_0_ltlib_v1_0_match__parameterized2_27 \genblk1[6].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[6]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[6]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[6]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[6]));
ila_0_ltlib_v1_0_match__parameterized2_28 \genblk1[7].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[7]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[7]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[7]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[7]));
ila_0_ltlib_v1_0_match__parameterized2_29 \genblk1[8].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[8]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[8]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[8]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[8]));
ila_0_ltlib_v1_0_match__parameterized2_30 \genblk1[9].U_TC 
       (.D(trigCondIn),
        .I1(Q[3:2]),
        .O1(trigEqOut[9]),
        .Q({\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1_0 ,\allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst/probeDelay1 }),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input[9]),
        .tc_config_cs_serial_output(tc_config_cs_serial_output[9]),
        .tc_config_cs_shift_en(tc_config_cs_shift_en[9]));
FDRE shift_cap_strg_qual_reg
       (.C(clk),
        .CE(1'b1),
        .D(1'b0),
        .Q(shift_cap_strg_qual),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    all_in,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [63:0]all_in;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire [63:0]all_in;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_165 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .O1(p_0_out),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .all_in(all_in[15:0]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice_166 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .all_in(all_in[31:16]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice_167 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .all_in(all_in[47:32]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_168 \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE 
       (.I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q),
        .all_in(all_in[63:48]),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA_174
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    all_in,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [63:0]all_in;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire [63:0]all_in;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_175 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .O1(p_0_out),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .all_in(all_in[15:0]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice_176 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .all_in(all_in[31:16]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice_177 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .all_in(all_in[47:32]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_178 \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE 
       (.I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q),
        .all_in(all_in[63:48]),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA_186
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    all_in,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [63:0]all_in;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire [63:0]all_in;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_187 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .O1(p_0_out),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .all_in(all_in[15:0]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice_188 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .all_in(all_in[31:16]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice_189 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .all_in(all_in[47:32]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_190 \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE 
       (.I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q),
        .all_in(all_in[63:48]),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA_206
   (mu_config_cs_serial_input,
    DOUT_O,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    all_in,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output DOUT_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [63:0]all_in;
  input [0:0]Q;
  input clk;

  wire DOUT_O;
  wire [0:0]Q;
  wire [63:0]all_in;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_207 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .O1(p_0_out),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .all_in(all_in[15:0]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice_208 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .all_in(all_in[31:16]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice_209 \I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE 
       (.CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .all_in(all_in[47:32]),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_210 \I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE 
       (.DOUT_O(DOUT_O),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[2].U_ALL_SRL_SLICE ),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[3].U_ALL_SRL_SLICE ),
        .Q(Q),
        .all_in(all_in[63:48]),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    probeDelay1,
    probeDelay2,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input probeDelay1;
  input probeDelay2;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_169 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0_171
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    probeDelay1,
    probeDelay2,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input probeDelay1;
  input probeDelay2;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_172 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0_180
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    probeDelay1,
    probeDelay2,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input probeDelay1;
  input probeDelay2;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_181 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0_183
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    probeDelay1,
    probeDelay2,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input probeDelay1;
  input probeDelay2;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_184 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0_192
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    probeDelay1,
    probeDelay2,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input probeDelay1;
  input probeDelay2;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_193 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0_195
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    probeDelay1,
    probeDelay2,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input probeDelay1;
  input probeDelay2;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_196 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0_197
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [3:0]D;
  input [3:0]Q;
  input [0:0]I1;
  input clk;

  wire [3:0]D;
  wire [0:0]I1;
  wire O1;
  wire [3:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_198 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0_200
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    probeDelay1,
    probeDelay2,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input probeDelay1;
  input probeDelay2;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_201 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized0_203
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    probeDelay1,
    probeDelay2,
    Q,
    clk);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input probeDelay1;
  input probeDelay2;
  input [0:0]Q;
  input clk;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire drive_ci;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire p_0_out;
  wire p_1_in;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_204 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CO(p_1_in),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .p_0_out(p_0_out),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(mu_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_100
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_101 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_102 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_104
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_105 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_106 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_108
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_109 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_110 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_112
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_113 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_114 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_116
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_117 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_118 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_120
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_121 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_122 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_124
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_125 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_126 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_128
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_129 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_130 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_132
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_133 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_134 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_136
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_137 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_138 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_140
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_141 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_142 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_144
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_145 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_146 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_148
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_149 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_150 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_152
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_153 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_154 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_32
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_33 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_34 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_36
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_37 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_38 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_40
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_41 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_42 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_44
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_45 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_46 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_48
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_49 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_50 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_52
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_53 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_54 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_56
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_57 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_58 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_60
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_61 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_62 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_64
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_65 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_66 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_68
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_69 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_70 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_72
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_73 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_74 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_76
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_77 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_78 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_80
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_81 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_82 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_84
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_85 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_86 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_88
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_89 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_90 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_92
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_93 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_94 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized1_96
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice_97 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .SRL_A_I({Q[7],D[7],Q[6],D[6],Q[5],D[5],Q[4],D[4],Q[3],D[3],Q[2],D[2],Q[1],D[1],Q[0],D[0]}),
        .SRL_D_I(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .SRL_Q_O(p_0_out),
        .s_dclk(s_dclk),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_98 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.D(D[12:8]),
        .I1(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .I2(I1),
        .O1(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .O2(O1),
        .Q(Q[12:8]),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(tc_config_cs_serial_input));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized2
   (SRL_Q_O,
    DOUT_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    SRL_D_I);
  output SRL_Q_O;
  output DOUT_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized1 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .O1(p_0_out),
        .PROBES_I(PROBES_I[15:0]),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .S_DCLK_O(S_DCLK_O));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized2 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .DOUT_O(DOUT_O),
        .PROBES_I(PROBES_I[19:16]),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .S_DCLK_O(S_DCLK_O));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(SRL_Q_O));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized2_266
   (SRL_Q_O,
    DOUT_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    SRL_D_I);
  output SRL_Q_O;
  output DOUT_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized1_267 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .O1(p_0_out),
        .PROBES_I(PROBES_I[15:0]),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .S_DCLK_O(S_DCLK_O));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized2_268 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .DOUT_O(DOUT_O),
        .PROBES_I(PROBES_I[19:16]),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .S_DCLK_O(S_DCLK_O));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(SRL_Q_O));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA" *) 
module ila_0_ltlib_v1_0_all_typeA__parameterized2_274
   (SRL_Q_O,
    DOUT_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    SRL_D_I);
  output SRL_Q_O;
  output DOUT_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire drive_ci;
  wire \n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ;
  wire \n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ;
  wire p_0_out;
  wire p_1_in;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

ila_0_ltlib_v1_0_all_typeA_slice__parameterized1_275 \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CI_I(p_1_in),
        .DOUT_O(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .O1(p_0_out),
        .PROBES_I(PROBES_I[15:0]),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .S_DCLK_O(S_DCLK_O));
ila_0_ltlib_v1_0_all_typeA_slice__parameterized2_276 \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CI_I(\n_1_I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE ),
        .DOUT_O(DOUT_O),
        .PROBES_I(PROBES_I[19:16]),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(\n_0_I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE ),
        .S_DCLK_O(S_DCLK_O));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(1'b0),
        .CO({p_1_in,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S({1'b1,1'b1,1'b1,drive_ci}));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* XILINX_LEGACY_PRIM = "CFGLUT5" *) 
   (* XILINX_TRANSFORM_PINMAP = "O6:Q I0:A[0] I1:A[1] I2:A[2] I3:A[3] I4:A[4] CDI:D CDO:Q31" *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srl_drive
       (.A({1'b1,1'b1,1'b1,1'b1,1'b1}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(p_0_out),
        .Q(drive_ci),
        .Q31(SRL_Q_O));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_101
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_105
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_109
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_113
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_117
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_121
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_125
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_129
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_133
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_137
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_141
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_145
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_149
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_153
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_165
   (O1,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_166
   (O1,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_167
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_175
   (O1,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_176
   (O1,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_177
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_187
   (O1,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_188
   (O1,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_189
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_207
   (O1,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_208
   (O1,
    DOUT_O,
    SRL_Q_O,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_209
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [15:0]all_in;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_33
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_37
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_41
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_45
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_49
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_53
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_57
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_61
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_65
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_69
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_73
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_77
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_81
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_85
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_89
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_93
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice_97
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    tc_config_cs_shift_en,
    s_dclk,
    SRL_A_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [15:0]SRL_A_I;
  input CI_I;

  wire CI_I;
  wire DOUT_O;
  wire [15:0]SRL_A_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[0]),
        .I1(SRL_A_I[1]),
        .I2(SRL_A_I[2]),
        .I3(SRL_A_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[4]),
        .I1(SRL_A_I[5]),
        .I2(SRL_A_I[6]),
        .I3(SRL_A_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[8]),
        .I1(SRL_A_I[9]),
        .I2(SRL_A_I[10]),
        .I3(SRL_A_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(SRL_A_I[12]),
        .I1(SRL_A_I[13]),
        .I2(SRL_A_I[14]),
        .I3(SRL_A_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_102
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_106
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_110
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_114
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_118
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_122
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_126
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_130
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_134
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_138
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_142
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_146
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_150
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_154
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_168
   (O1,
    O2,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    I1,
    Q,
    clk);
  output O1;
  output O2;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input I1;
  input [0:0]Q;
  input clk;

  wire I1;
  wire O1;
  wire O2;
  wire [0:0]Q;
  wire [15:0]all_in;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_169
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    probeDelay1,
    probeDelay2,
    CO,
    Q,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input probeDelay1;
  input probeDelay2;
  input [0:0]CO;
  input [0:0]Q;
  input clk;

  wire [0:0]CO;
  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(probeDelay1),
        .I1(probeDelay2),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_172
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    probeDelay1,
    probeDelay2,
    CO,
    Q,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input probeDelay1;
  input probeDelay2;
  input [0:0]CO;
  input [0:0]Q;
  input clk;

  wire [0:0]CO;
  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(probeDelay1),
        .I1(probeDelay2),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_178
   (O1,
    O2,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    I1,
    Q,
    clk);
  output O1;
  output O2;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input I1;
  input [0:0]Q;
  input clk;

  wire I1;
  wire O1;
  wire O2;
  wire [0:0]Q;
  wire [15:0]all_in;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_181
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    probeDelay1,
    probeDelay2,
    CO,
    Q,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input probeDelay1;
  input probeDelay2;
  input [0:0]CO;
  input [0:0]Q;
  input clk;

  wire [0:0]CO;
  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(probeDelay1),
        .I1(probeDelay2),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_184
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    probeDelay1,
    probeDelay2,
    CO,
    Q,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input probeDelay1;
  input probeDelay2;
  input [0:0]CO;
  input [0:0]Q;
  input clk;

  wire [0:0]CO;
  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(probeDelay1),
        .I1(probeDelay2),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_190
   (O1,
    O2,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    I1,
    Q,
    clk);
  output O1;
  output O2;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input I1;
  input [0:0]Q;
  input clk;

  wire I1;
  wire O1;
  wire O2;
  wire [0:0]Q;
  wire [15:0]all_in;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_193
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    probeDelay1,
    probeDelay2,
    CO,
    Q,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input probeDelay1;
  input probeDelay2;
  input [0:0]CO;
  input [0:0]Q;
  input clk;

  wire [0:0]CO;
  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(probeDelay1),
        .I1(probeDelay2),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_196
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    probeDelay1,
    probeDelay2,
    CO,
    Q,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input probeDelay1;
  input probeDelay2;
  input [0:0]CO;
  input [0:0]Q;
  input clk;

  wire [0:0]CO;
  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(probeDelay1),
        .I1(probeDelay2),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_198
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    CO,
    I1,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [3:0]D;
  input [3:0]Q;
  input [0:0]CO;
  input [0:0]I1;
  input clk;

  wire [0:0]CO;
  wire [3:0]D;
  wire [0:0]I1;
  wire O1;
  wire [3:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(I1));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_201
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    probeDelay1,
    probeDelay2,
    CO,
    Q,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input probeDelay1;
  input probeDelay2;
  input [0:0]CO;
  input [0:0]Q;
  input clk;

  wire [0:0]CO;
  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(probeDelay1),
        .I1(probeDelay2),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_204
   (p_0_out,
    O1,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    probeDelay1,
    probeDelay2,
    CO,
    Q,
    clk);
  output p_0_out;
  output O1;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input probeDelay1;
  input probeDelay2;
  input [0:0]CO;
  input [0:0]Q;
  input clk;

  wire [0:0]CO;
  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire p_0_out;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CO),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(p_0_out),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(probeDelay1),
        .I1(probeDelay2),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_210
   (O1,
    DOUT_O,
    mu_config_cs_serial_output,
    mu_config_cs_shift_en,
    s_dclk,
    all_in,
    I1,
    Q,
    clk);
  output O1;
  output DOUT_O;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [15:0]all_in;
  input I1;
  input [0:0]Q;
  input clk;

  wire DOUT_O;
  wire I1;
  wire O1;
  wire [0:0]Q;
  wire [15:0]all_in;
  wire clk;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(DOUT_O),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[0]),
        .I1(all_in[1]),
        .I2(all_in[2]),
        .I3(all_in[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[4]),
        .I1(all_in[5]),
        .I2(all_in[6]),
        .I3(all_in[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[8]),
        .I1(all_in[9]),
        .I2(all_in[10]),
        .I3(all_in[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(mu_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(mu_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(all_in[12]),
        .I1(all_in[13]),
        .I2(all_in[14]),
        .I3(all_in[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_34
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_38
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_42
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_46
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_50
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_54
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_58
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_62
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_66
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_70
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_74
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_78
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_82
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_86
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_90
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_94
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized0_98
   (O1,
    O2,
    tc_config_cs_serial_output,
    tc_config_cs_shift_en,
    s_dclk,
    D,
    Q,
    I1,
    I2,
    clk);
  output O1;
  output O2;
  input [0:0]tc_config_cs_serial_output;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [4:0]D;
  input [4:0]Q;
  input I1;
  input [0:0]I2;
  input clk;

  wire [4:0]D;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire O2;
  wire [4:0]Q;
  wire clk;
  wire [3:0]mux_di;
  wire n_0_u_carry4_inst;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire s_dclk;
  wire [3:0]sel;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

FDRE \I_IS_TERMINATION_SLICE_W_OUTPUT_REG.DOUT_O_reg 
       (.C(clk),
        .CE(1'b1),
        .D(n_0_u_carry4_inst),
        .Q(O2),
        .R(I2));
(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(I1),
        .CO({n_0_u_carry4_inst,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[0]),
        .I1(Q[0]),
        .I2(D[1]),
        .I3(Q[1]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[2]),
        .I1(Q[2]),
        .I2(D[3]),
        .I3(Q[3]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(D[4]),
        .I1(Q[4]),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(tc_config_cs_serial_output),
        .CDO(n_0_u_srlD),
        .CE(tc_config_cs_shift_en),
        .CLK(s_dclk),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized1
   (O1,
    DOUT_O,
    SRL_Q_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [15:0]PROBES_I;
  input CI_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire [15:0]PROBES_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[4]),
        .I1(PROBES_I[5]),
        .I2(PROBES_I[6]),
        .I3(PROBES_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[8]),
        .I1(PROBES_I[9]),
        .I2(PROBES_I[10]),
        .I3(PROBES_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[12]),
        .I1(PROBES_I[13]),
        .I2(PROBES_I[14]),
        .I3(PROBES_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized1_267
   (O1,
    DOUT_O,
    SRL_Q_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [15:0]PROBES_I;
  input CI_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire [15:0]PROBES_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[4]),
        .I1(PROBES_I[5]),
        .I2(PROBES_I[6]),
        .I3(PROBES_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[8]),
        .I1(PROBES_I[9]),
        .I2(PROBES_I[10]),
        .I3(PROBES_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[12]),
        .I1(PROBES_I[13]),
        .I2(PROBES_I[14]),
        .I3(PROBES_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized1_275
   (O1,
    DOUT_O,
    SRL_Q_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    CI_I);
  output O1;
  output DOUT_O;
  input SRL_Q_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [15:0]PROBES_I;
  input CI_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire CI_I;
  wire DOUT_O;
  wire O1;
  wire [15:0]PROBES_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(O1),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[4]),
        .I1(PROBES_I[5]),
        .I2(PROBES_I[6]),
        .I3(PROBES_I[7]),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[8]),
        .I1(PROBES_I[9]),
        .I2(PROBES_I[10]),
        .I3(PROBES_I[11]),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_Q_O),
        .CDO(n_0_u_srlD),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[12]),
        .I1(PROBES_I[13]),
        .I2(PROBES_I[14]),
        .I3(PROBES_I[15]),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized2
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [3:0]PROBES_I;
  input CI_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire CI_I;
  wire DOUT_O;
  wire [3:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized2_268
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [3:0]PROBES_I;
  input CI_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire CI_I;
  wire DOUT_O;
  wire [3:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_all_typeA_slice" *) 
module ila_0_ltlib_v1_0_all_typeA_slice__parameterized2_276
   (SRL_Q_O,
    DOUT_O,
    SRL_D_I,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    CI_I);
  output SRL_Q_O;
  output DOUT_O;
  input SRL_D_I;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [3:0]PROBES_I;
  input CI_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire CI_I;
  wire DOUT_O;
  wire [3:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire [3:0]mux_di;
  wire n_0_u_srlB;
  wire n_0_u_srlC;
  wire n_0_u_srlD;
  wire [3:0]sel;
  wire [2:0]NLW_u_carry4_inst_CO_UNCONNECTED;
  wire [3:0]NLW_u_carry4_inst_O_UNCONNECTED;

(* BOX_TYPE = "PRIMITIVE" *) 
   CARRY4 u_carry4_inst
       (.CI(CI_I),
        .CO({DOUT_O,NLW_u_carry4_inst_CO_UNCONNECTED[2:0]}),
        .CYINIT(1'b0),
        .DI(mux_di),
        .O(NLW_u_carry4_inst_O_UNCONNECTED[3:0]),
        .S(sel));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlA
       (.CDI(n_0_u_srlB),
        .CDO(SRL_Q_O),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(PROBES_I[0]),
        .I1(PROBES_I[1]),
        .I2(PROBES_I[2]),
        .I3(PROBES_I[3]),
        .I4(1'b1),
        .O5(mux_di[0]),
        .O6(sel[0]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlB
       (.CDI(n_0_u_srlC),
        .CDO(n_0_u_srlB),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[1]),
        .O6(sel[1]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlC
       (.CDI(n_0_u_srlD),
        .CDO(n_0_u_srlC),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[2]),
        .O6(sel[2]));
(* BOX_TYPE = "PRIMITIVE" *) 
   CFGLUT5 #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     u_srlD
       (.CDI(SRL_D_I),
        .CDO(n_0_u_srlD),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .I0(1'b1),
        .I1(1'b1),
        .I2(1'b1),
        .I3(1'b1),
        .I4(1'b1),
        .O5(mux_di[3]),
        .O6(sel[3]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe9);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [31:0]probe9;

  wire O1;
  wire [0:0]Q;
  wire [63:0]all_in;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [31:0]probe9;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA DUT
       (.O1(O1),
        .Q(Q),
        .all_in(all_in),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[0]),
        .Q(all_in[1]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[20]),
        .Q(all_in[21]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[22]),
        .Q(all_in[23]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[24]),
        .Q(all_in[25]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[26]),
        .Q(all_in[27]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[28]),
        .Q(all_in[29]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[30]),
        .Q(all_in[31]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[32]),
        .Q(all_in[33]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[34]),
        .Q(all_in[35]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[36]),
        .Q(all_in[37]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[38]),
        .Q(all_in[39]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[2]),
        .Q(all_in[3]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[40]),
        .Q(all_in[41]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[42]),
        .Q(all_in[43]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[44]),
        .Q(all_in[45]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[46]),
        .Q(all_in[47]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[48]),
        .Q(all_in[49]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[50]),
        .Q(all_in[51]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[52]),
        .Q(all_in[53]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[54]),
        .Q(all_in[55]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[56]),
        .Q(all_in[57]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[58]),
        .Q(all_in[59]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[4]),
        .Q(all_in[5]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[60]),
        .Q(all_in[61]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[62]),
        .Q(all_in[63]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[6]),
        .Q(all_in[7]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[8]),
        .Q(all_in[9]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[10]),
        .Q(all_in[11]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[12]),
        .Q(all_in[13]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[14]),
        .Q(all_in[15]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[16]),
        .Q(all_in[17]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[18]),
        .Q(all_in[19]),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[0]),
        .Q(all_in[0]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[10]),
        .Q(all_in[20]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[11]),
        .Q(all_in[22]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[12]),
        .Q(all_in[24]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[13]),
        .Q(all_in[26]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[14]),
        .Q(all_in[28]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[15]),
        .Q(all_in[30]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[16]),
        .Q(all_in[32]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[17]),
        .Q(all_in[34]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[18]),
        .Q(all_in[36]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[19]),
        .Q(all_in[38]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[1]),
        .Q(all_in[2]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[20]),
        .Q(all_in[40]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[21]),
        .Q(all_in[42]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[22]),
        .Q(all_in[44]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[23]),
        .Q(all_in[46]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[24]),
        .Q(all_in[48]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[25]),
        .Q(all_in[50]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[26]),
        .Q(all_in[52]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[27]),
        .Q(all_in[54]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[28]),
        .Q(all_in[56]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[29]),
        .Q(all_in[58]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[2]),
        .Q(all_in[4]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[30]),
        .Q(all_in[60]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[31]),
        .Q(all_in[62]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[3]),
        .Q(all_in[6]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[4]),
        .Q(all_in[8]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[5]),
        .Q(all_in[10]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[6]),
        .Q(all_in[12]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[7]),
        .Q(all_in[14]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[8]),
        .Q(all_in[16]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(probe9[9]),
        .Q(all_in[18]),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA_173
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe6);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [31:0]probe6;

  wire O1;
  wire [0:0]Q;
  wire [63:0]all_in;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [31:0]probe6;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA_174 DUT
       (.O1(O1),
        .Q(Q),
        .all_in(all_in),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[0]),
        .Q(all_in[1]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[20]),
        .Q(all_in[21]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[22]),
        .Q(all_in[23]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[24]),
        .Q(all_in[25]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[26]),
        .Q(all_in[27]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[28]),
        .Q(all_in[29]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[30]),
        .Q(all_in[31]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[32]),
        .Q(all_in[33]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[34]),
        .Q(all_in[35]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[36]),
        .Q(all_in[37]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[38]),
        .Q(all_in[39]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[2]),
        .Q(all_in[3]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[40]),
        .Q(all_in[41]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[42]),
        .Q(all_in[43]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[44]),
        .Q(all_in[45]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[46]),
        .Q(all_in[47]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[48]),
        .Q(all_in[49]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[50]),
        .Q(all_in[51]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[52]),
        .Q(all_in[53]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[54]),
        .Q(all_in[55]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[56]),
        .Q(all_in[57]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[58]),
        .Q(all_in[59]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[4]),
        .Q(all_in[5]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[60]),
        .Q(all_in[61]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[62]),
        .Q(all_in[63]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[6]),
        .Q(all_in[7]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[8]),
        .Q(all_in[9]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[10]),
        .Q(all_in[11]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[12]),
        .Q(all_in[13]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[14]),
        .Q(all_in[15]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[16]),
        .Q(all_in[17]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[18]),
        .Q(all_in[19]),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[0]),
        .Q(all_in[0]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[10]),
        .Q(all_in[20]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[11]),
        .Q(all_in[22]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[12]),
        .Q(all_in[24]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[13]),
        .Q(all_in[26]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[14]),
        .Q(all_in[28]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[15]),
        .Q(all_in[30]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[16]),
        .Q(all_in[32]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[17]),
        .Q(all_in[34]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[18]),
        .Q(all_in[36]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[19]),
        .Q(all_in[38]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[1]),
        .Q(all_in[2]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[20]),
        .Q(all_in[40]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[21]),
        .Q(all_in[42]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[22]),
        .Q(all_in[44]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[23]),
        .Q(all_in[46]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[24]),
        .Q(all_in[48]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[25]),
        .Q(all_in[50]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[26]),
        .Q(all_in[52]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[27]),
        .Q(all_in[54]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[28]),
        .Q(all_in[56]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[29]),
        .Q(all_in[58]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[2]),
        .Q(all_in[4]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[30]),
        .Q(all_in[60]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[31]),
        .Q(all_in[62]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[3]),
        .Q(all_in[6]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[4]),
        .Q(all_in[8]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[5]),
        .Q(all_in[10]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[6]),
        .Q(all_in[12]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[7]),
        .Q(all_in[14]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[8]),
        .Q(all_in[16]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(probe6[9]),
        .Q(all_in[18]),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA_185
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe3);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [31:0]probe3;

  wire O1;
  wire [0:0]Q;
  wire [63:0]all_in;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [31:0]probe3;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA_186 DUT
       (.O1(O1),
        .Q(Q),
        .all_in(all_in),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[0]),
        .Q(all_in[1]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[20]),
        .Q(all_in[21]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[22]),
        .Q(all_in[23]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[24]),
        .Q(all_in[25]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[26]),
        .Q(all_in[27]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[28]),
        .Q(all_in[29]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[30]),
        .Q(all_in[31]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[32]),
        .Q(all_in[33]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[34]),
        .Q(all_in[35]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[36]),
        .Q(all_in[37]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[38]),
        .Q(all_in[39]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[2]),
        .Q(all_in[3]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[40]),
        .Q(all_in[41]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[42]),
        .Q(all_in[43]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[44]),
        .Q(all_in[45]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[46]),
        .Q(all_in[47]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[48]),
        .Q(all_in[49]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[50]),
        .Q(all_in[51]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[52]),
        .Q(all_in[53]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[54]),
        .Q(all_in[55]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[56]),
        .Q(all_in[57]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[58]),
        .Q(all_in[59]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[4]),
        .Q(all_in[5]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[60]),
        .Q(all_in[61]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[62]),
        .Q(all_in[63]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[6]),
        .Q(all_in[7]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[8]),
        .Q(all_in[9]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[10]),
        .Q(all_in[11]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[12]),
        .Q(all_in[13]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[14]),
        .Q(all_in[15]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[16]),
        .Q(all_in[17]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[18]),
        .Q(all_in[19]),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[0]),
        .Q(all_in[0]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[10]),
        .Q(all_in[20]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[11]),
        .Q(all_in[22]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[12]),
        .Q(all_in[24]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[13]),
        .Q(all_in[26]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[14]),
        .Q(all_in[28]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[15]),
        .Q(all_in[30]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[16]),
        .Q(all_in[32]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[17]),
        .Q(all_in[34]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[18]),
        .Q(all_in[36]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[19]),
        .Q(all_in[38]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[1]),
        .Q(all_in[2]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[20]),
        .Q(all_in[40]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[21]),
        .Q(all_in[42]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[22]),
        .Q(all_in[44]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[23]),
        .Q(all_in[46]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[24]),
        .Q(all_in[48]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[25]),
        .Q(all_in[50]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[26]),
        .Q(all_in[52]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[27]),
        .Q(all_in[54]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[28]),
        .Q(all_in[56]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[29]),
        .Q(all_in[58]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[2]),
        .Q(all_in[4]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[30]),
        .Q(all_in[60]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[31]),
        .Q(all_in[62]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[3]),
        .Q(all_in[6]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[4]),
        .Q(all_in[8]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[5]),
        .Q(all_in[10]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[6]),
        .Q(all_in[12]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[7]),
        .Q(all_in[14]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[8]),
        .Q(all_in[16]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(probe3[9]),
        .Q(all_in[18]),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA_205
   (mu_config_cs_serial_input,
    DOUT_O,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    I1,
    use_probe_debug_circuit,
    probe0);
  output [0:0]mu_config_cs_serial_input;
  output DOUT_O;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input [15:0]I1;
  input use_probe_debug_circuit;
  input [15:0]probe0;

  wire DOUT_O;
  wire [15:0]I1;
  wire [0:0]Q;
  wire [63:0]all_in;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [15:0]probe0;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA_206 DUT
       (.DOUT_O(DOUT_O),
        .Q(Q),
        .all_in(all_in),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[0]),
        .Q(all_in[1]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[20]),
        .Q(all_in[21]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[22]),
        .Q(all_in[23]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[24]),
        .Q(all_in[25]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[26]),
        .Q(all_in[27]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[28]),
        .Q(all_in[29]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[30]),
        .Q(all_in[31]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[32]),
        .Q(all_in[33]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[34]),
        .Q(all_in[35]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[36]),
        .Q(all_in[37]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[38]),
        .Q(all_in[39]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[2]),
        .Q(all_in[3]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[40]),
        .Q(all_in[41]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[42]),
        .Q(all_in[43]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[44]),
        .Q(all_in[45]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[46]),
        .Q(all_in[47]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[48]),
        .Q(all_in[49]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[50]),
        .Q(all_in[51]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[52]),
        .Q(all_in[53]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[54]),
        .Q(all_in[55]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[56]),
        .Q(all_in[57]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[58]),
        .Q(all_in[59]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[4]),
        .Q(all_in[5]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[60]),
        .Q(all_in[61]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[62]),
        .Q(all_in[63]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[6]),
        .Q(all_in[7]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[8]),
        .Q(all_in[9]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[10]),
        .Q(all_in[11]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[12]),
        .Q(all_in[13]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[14]),
        .Q(all_in[15]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[16]),
        .Q(all_in[17]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(all_in[18]),
        .Q(all_in[19]),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[0]),
        .Q(all_in[0]),
        .R(1'b0));
FDRE \probeDelay1_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[10]),
        .Q(all_in[20]),
        .R(1'b0));
FDRE \probeDelay1_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[11]),
        .Q(all_in[22]),
        .R(1'b0));
FDRE \probeDelay1_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[12]),
        .Q(all_in[24]),
        .R(1'b0));
FDRE \probeDelay1_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[13]),
        .Q(all_in[26]),
        .R(1'b0));
FDRE \probeDelay1_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[14]),
        .Q(all_in[28]),
        .R(1'b0));
FDRE \probeDelay1_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[15]),
        .Q(all_in[30]),
        .R(1'b0));
FDRE \probeDelay1_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[0]),
        .Q(all_in[32]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[1]),
        .Q(all_in[34]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[2]),
        .Q(all_in[36]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[3]),
        .Q(all_in[38]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[1]),
        .Q(all_in[2]),
        .R(1'b0));
FDRE \probeDelay1_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[4]),
        .Q(all_in[40]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[5]),
        .Q(all_in[42]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[6]),
        .Q(all_in[44]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[7]),
        .Q(all_in[46]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[8]),
        .Q(all_in[48]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[9]),
        .Q(all_in[50]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[10]),
        .Q(all_in[52]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[11]),
        .Q(all_in[54]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[12]),
        .Q(all_in[56]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[13]),
        .Q(all_in[58]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[2]),
        .Q(all_in[4]),
        .R(1'b0));
FDRE \probeDelay1_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[14]),
        .Q(all_in[60]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(probe0[15]),
        .Q(all_in[62]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[3]),
        .Q(all_in[6]),
        .R(1'b0));
FDRE \probeDelay1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[4]),
        .Q(all_in[8]),
        .R(1'b0));
FDRE \probeDelay1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[5]),
        .Q(all_in[10]),
        .R(1'b0));
FDRE \probeDelay1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[6]),
        .Q(all_in[12]),
        .R(1'b0));
FDRE \probeDelay1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[7]),
        .Q(all_in[14]),
        .R(1'b0));
FDRE \probeDelay1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[8]),
        .Q(all_in[16]),
        .R(1'b0));
FDRE \probeDelay1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[9]),
        .Q(all_in[18]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized0
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe8);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe8;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]probe8;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0 DUT
       (.O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1),
        .Q(probeDelay2),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe8),
        .Q(probeDelay1),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized0_170
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe7);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe7;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]probe7;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0_171 DUT
       (.O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1),
        .Q(probeDelay2),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe7),
        .Q(probeDelay1),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized0_179
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe5);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe5;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]probe5;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0_180 DUT
       (.O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1),
        .Q(probeDelay2),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe5),
        .Q(probeDelay1),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized0_182
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe4);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe4;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]probe4;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0_183 DUT
       (.O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1),
        .Q(probeDelay2),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe4),
        .Q(probeDelay1),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized0_191
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe2);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe2;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]probe2;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0_192 DUT
       (.O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1),
        .Q(probeDelay2),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe2),
        .Q(probeDelay1),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized0_194
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe1);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe1;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]probe1;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0_195 DUT
       (.O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1),
        .Q(probeDelay2),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe1),
        .Q(probeDelay1),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized0_199
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe11);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe11;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]probe11;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0_200 DUT
       (.O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1),
        .Q(probeDelay2),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe11),
        .Q(probeDelay1),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized0_202
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe10);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe10;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [0:0]probe10;
  wire probeDelay1;
  wire probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0_203 DUT
       (.O1(O1),
        .Q(Q),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probeDelay1(probeDelay1),
        .probeDelay2(probeDelay2),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1),
        .Q(probeDelay2),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe10),
        .Q(probeDelay1),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized1
   (mu_config_cs_serial_input,
    O1,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe12);
  output [0:0]mu_config_cs_serial_input;
  output O1;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [0:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [3:0]probe12;

  wire O1;
  wire [0:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [3:0]probe12;
  wire [3:0]probeDelay1;
  wire [3:0]probeDelay2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_all_typeA__parameterized0_197 DUT
       (.D(probeDelay1),
        .I1(Q),
        .O1(O1),
        .Q(probeDelay2),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .s_dclk(s_dclk));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1[0]),
        .Q(probeDelay2[0]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1[1]),
        .Q(probeDelay2[1]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1[2]),
        .Q(probeDelay2[2]),
        .R(1'b0));
FDRE \i_use_input_reg_eq1.probeDelay2_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(probeDelay1[3]),
        .Q(probeDelay2[3]),
        .R(1'b0));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(probe12[0]),
        .Q(probeDelay1[0]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(probe12[1]),
        .Q(probeDelay1[1]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(probe12[2]),
        .Q(probeDelay1[2]),
        .R(use_probe_debug_circuit));
FDRE \probeDelay1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(probe12[3]),
        .Q(probeDelay1[3]),
        .R(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_103
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_104 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_107
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_108 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_111
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_112 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_115
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_116 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_119
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_120 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_123
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_124 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_127
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_128 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_131
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_132 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_135
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_136 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_139
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_140 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_143
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_144 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_147
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_148 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_151
   (tc_config_cs_serial_input,
    Q,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [12:0]Q;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_152 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(D[0]),
        .Q(Q[0]),
        .R(1'b0));
FDRE \probeDelay1_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(D[10]),
        .Q(Q[10]),
        .R(1'b0));
FDRE \probeDelay1_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(D[11]),
        .Q(Q[11]),
        .R(1'b0));
FDRE \probeDelay1_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(D[12]),
        .Q(Q[12]),
        .R(1'b0));
FDRE \probeDelay1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(D[1]),
        .Q(Q[1]),
        .R(1'b0));
FDRE \probeDelay1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(D[2]),
        .Q(Q[2]),
        .R(1'b0));
FDRE \probeDelay1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(D[3]),
        .Q(Q[3]),
        .R(1'b0));
FDRE \probeDelay1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(D[4]),
        .Q(Q[4]),
        .R(1'b0));
FDRE \probeDelay1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(D[5]),
        .Q(Q[5]),
        .R(1'b0));
FDRE \probeDelay1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(D[6]),
        .Q(Q[6]),
        .R(1'b0));
FDRE \probeDelay1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(D[7]),
        .Q(Q[7]),
        .R(1'b0));
FDRE \probeDelay1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(D[8]),
        .Q(Q[8]),
        .R(1'b0));
FDRE \probeDelay1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(D[9]),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_31
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_32 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_35
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_36 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_39
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_40 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_43
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_44 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_47
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_48 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_51
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_52 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_55
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_56 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_59
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_60 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_63
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_64 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_67
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_68 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_71
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_72 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_75
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_76 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_79
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_80 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_83
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_84 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_87
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_88 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_91
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_92 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_95
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_96 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA" *) 
module ila_0_ltlib_v1_0_allx_typeA__parameterized2_99
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [0:0]I1;
  input clk;

  wire [12:0]D;
  wire [0:0]I1;
  wire O1;
  wire [12:0]Q;
  wire clk;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_all_typeA__parameterized1_100 DUT
       (.D(D),
        .I1(I1),
        .O1(O1),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA_nodelay" *) 
module ila_0_ltlib_v1_0_allx_typeA_nodelay
   (Q,
    SRL_Q_O,
    DOUT_O,
    I1,
    clk,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    SRL_D_I);
  output [9:0]Q;
  output SRL_Q_O;
  output DOUT_O;
  input [9:0]I1;
  input clk;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [9:0]I1;
  wire [9:0]Q;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire clk;

ila_0_ltlib_v1_0_all_typeA__parameterized2 DUT
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(DOUT_O),
        .PROBES_I({Q[9],I1[9],Q[8],I1[8],Q[7],I1[7],Q[6],I1[6],Q[5],I1[5],Q[4],I1[4],Q[3],I1[3],Q[2],I1[2],Q[1],I1[1],Q[0],I1[0]}),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[0]),
        .Q(Q[0]),
        .R(1'b0));
FDRE \probeDelay1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[1]),
        .Q(Q[1]),
        .R(1'b0));
FDRE \probeDelay1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[2]),
        .Q(Q[2]),
        .R(1'b0));
FDRE \probeDelay1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[3]),
        .Q(Q[3]),
        .R(1'b0));
FDRE \probeDelay1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[4]),
        .Q(Q[4]),
        .R(1'b0));
FDRE \probeDelay1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[5]),
        .Q(Q[5]),
        .R(1'b0));
FDRE \probeDelay1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[6]),
        .Q(Q[6]),
        .R(1'b0));
FDRE \probeDelay1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[7]),
        .Q(Q[7]),
        .R(1'b0));
FDRE \probeDelay1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[8]),
        .Q(Q[8]),
        .R(1'b0));
FDRE \probeDelay1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(I1[9]),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA_nodelay" *) 
module ila_0_ltlib_v1_0_allx_typeA_nodelay_265
   (SRL_Q_O,
    DOUT_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    SRL_D_I);
  output SRL_Q_O;
  output DOUT_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;

ila_0_ltlib_v1_0_all_typeA__parameterized2_266 DUT
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(DOUT_O),
        .PROBES_I(PROBES_I),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_allx_typeA_nodelay" *) 
module ila_0_ltlib_v1_0_allx_typeA_nodelay_273
   (SRL_Q_O,
    DOUT_O,
    Q,
    clk,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    SRL_D_I);
  output SRL_Q_O;
  output DOUT_O;
  input [9:0]Q;
  input clk;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [9:0]Q;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire clk;
  wire [9:0]probeDelay1;

ila_0_ltlib_v1_0_all_typeA__parameterized2_274 DUT
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(DOUT_O),
        .PROBES_I({probeDelay1[9],Q[9],probeDelay1[8],Q[8],probeDelay1[7],Q[7],probeDelay1[6],Q[6],probeDelay1[5],Q[5],probeDelay1[4],Q[4],probeDelay1[3],Q[3],probeDelay1[2],Q[2],probeDelay1[1],Q[1],probeDelay1[0],Q[0]}),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O));
FDRE \probeDelay1_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[0]),
        .Q(probeDelay1[0]),
        .R(1'b0));
FDRE \probeDelay1_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[1]),
        .Q(probeDelay1[1]),
        .R(1'b0));
FDRE \probeDelay1_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[2]),
        .Q(probeDelay1[2]),
        .R(1'b0));
FDRE \probeDelay1_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[3]),
        .Q(probeDelay1[3]),
        .R(1'b0));
FDRE \probeDelay1_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[4]),
        .Q(probeDelay1[4]),
        .R(1'b0));
FDRE \probeDelay1_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[5]),
        .Q(probeDelay1[5]),
        .R(1'b0));
FDRE \probeDelay1_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[6]),
        .Q(probeDelay1[6]),
        .R(1'b0));
FDRE \probeDelay1_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[7]),
        .Q(probeDelay1[7]),
        .R(1'b0));
FDRE \probeDelay1_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[8]),
        .Q(probeDelay1[8]),
        .R(1'b0));
FDRE \probeDelay1_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(Q[9]),
        .Q(probeDelay1[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_async_edge_xfer" *) 
module ila_0_ltlib_v1_0_async_edge_xfer
   (arm_in_transferred,
    I1,
    clk,
    s_dclk,
    last_din,
    arm_ctrl);
  output arm_in_transferred;
  output [0:0]I1;
  input clk;
  input s_dclk;
  input last_din;
  input arm_ctrl;

  wire [0:0]I1;
  wire arm_ctrl;
  wire arm_in_transferred;
  wire clk;
  wire din_reg;
  wire last_din;
  wire n_0_din_reg_i_1__2;
  wire n_0_dout_reg0_reg;
  wire s_dclk;

(* SOFT_HLUTNM = "soft_lutpair255" *) 
   LUT3 #(
    .INIT(8'hB2)) 
     din_reg_i_1__2
       (.I0(din_reg),
        .I1(arm_in_transferred),
        .I2(arm_ctrl),
        .O(n_0_din_reg_i_1__2));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     din_reg_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_0_din_reg_i_1__2),
        .Q(din_reg),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair255" *) 
   LUT2 #(
    .INIT(4'h2)) 
     \dout_pulse[0]_i_1__0 
       (.I0(arm_in_transferred),
        .I1(last_din),
        .O(I1));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     dout_reg0_reg
       (.C(clk),
        .CE(1'b1),
        .D(din_reg),
        .Q(n_0_dout_reg0_reg),
        .R(1'b0));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     dout_reg1_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_dout_reg0_reg),
        .Q(arm_in_transferred),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_async_edge_xfer" *) 
module ila_0_ltlib_v1_0_async_edge_xfer_211
   (I5,
    p_2_out,
    s_dclk,
    clk,
    cap_state,
    Q);
  output [0:0]I5;
  output [0:0]p_2_out;
  input s_dclk;
  input clk;
  input [0:0]cap_state;
  input [0:0]Q;

  wire [0:0]I5;
  wire [0:0]Q;
  wire [0:0]cap_state;
  wire clk;
  wire din_reg;
  wire n_0_din_reg_i_1__0;
  wire n_0_dout_reg0_reg;
  wire [0:0]p_2_out;
  wire s_dclk;

(* SOFT_HLUTNM = "soft_lutpair256" *) 
   LUT2 #(
    .INIT(4'h2)) 
     \cntcmpsel[1]_i_2 
       (.I0(I5),
        .I1(cap_state),
        .O(p_2_out));
(* SOFT_HLUTNM = "soft_lutpair256" *) 
   LUT3 #(
    .INIT(8'h4D)) 
     din_reg_i_1__0
       (.I0(Q),
        .I1(din_reg),
        .I2(I5),
        .O(n_0_din_reg_i_1__0));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     din_reg_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_din_reg_i_1__0),
        .Q(din_reg),
        .R(1'b0));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     dout_reg0_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(din_reg),
        .Q(n_0_dout_reg0_reg),
        .R(1'b0));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     dout_reg1_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_0_dout_reg0_reg),
        .Q(I5),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_async_edge_xfer" *) 
module ila_0_ltlib_v1_0_async_edge_xfer_212
   (halt_in_transferred,
    D,
    clk,
    s_dclk,
    last_din,
    halt_ctrl);
  output halt_in_transferred;
  output [0:0]D;
  input clk;
  input s_dclk;
  input last_din;
  input halt_ctrl;

  wire [0:0]D;
  wire clk;
  wire din_reg;
  wire dout_reg0;
  wire halt_ctrl;
  wire halt_in_transferred;
  wire last_din;
  wire n_0_din_reg_i_1__1;
  wire s_dclk;

(* SOFT_HLUTNM = "soft_lutpair257" *) 
   LUT3 #(
    .INIT(8'hB2)) 
     din_reg_i_1__1
       (.I0(din_reg),
        .I1(halt_in_transferred),
        .I2(halt_ctrl),
        .O(n_0_din_reg_i_1__1));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     din_reg_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_0_din_reg_i_1__1),
        .Q(din_reg),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair257" *) 
   LUT2 #(
    .INIT(4'h2)) 
     \dout_pulse[0]_i_1 
       (.I0(halt_in_transferred),
        .I1(last_din),
        .O(D));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     dout_reg0_reg
       (.C(clk),
        .CE(1'b1),
        .D(din_reg),
        .Q(dout_reg0),
        .R(1'b0));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     dout_reg1_reg
       (.C(clk),
        .CE(1'b1),
        .D(dout_reg0),
        .Q(halt_in_transferred),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_async_edge_xfer" *) 
module ila_0_ltlib_v1_0_async_edge_xfer_213
   (I5,
    s_dclk,
    clk,
    halt_out);
  output [0:0]I5;
  input s_dclk;
  input clk;
  input halt_out;

  wire [0:0]I5;
  wire clk;
  wire din_reg;
  wire halt_out;
  wire n_0_din_reg_i_1;
  wire n_0_dout_reg0_reg;
  wire s_dclk;

LUT3 #(
    .INIT(8'hB2)) 
     din_reg_i_1
       (.I0(din_reg),
        .I1(I5),
        .I2(halt_out),
        .O(n_0_din_reg_i_1));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     din_reg_reg
       (.C(clk),
        .CE(1'b1),
        .D(n_0_din_reg_i_1),
        .Q(din_reg),
        .R(1'b0));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     dout_reg0_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(din_reg),
        .Q(n_0_dout_reg0_reg),
        .R(1'b0));
(* SHREG_EXTRACT = "no" *) 
   FDRE #(
    .INIT(1'b0)) 
     dout_reg1_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_0_dout_reg0_reg),
        .Q(I5),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut4" *) 
module ila_0_ltlib_v1_0_cfglut4
   (E,
    O1,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O);
  output [0:0]E;
  output O1;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [3:0]A;
  input S_DCLK_O;

  wire [3:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire [0:0]E;
  wire I1;
  wire O1;
  wire S_DCLK_O;

(* BOX_TYPE = "PRIMITIVE" *) 
   SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRLC16E 
       (.A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(I1),
        .Q(E),
        .Q15(O1));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut4" *) 
module ila_0_ltlib_v1_0_cfglut4_269
   (E,
    O1,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O);
  output [0:0]E;
  output O1;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [3:0]A;
  input S_DCLK_O;

  wire [3:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire [0:0]E;
  wire I1;
  wire O1;
  wire S_DCLK_O;

(* BOX_TYPE = "PRIMITIVE" *) 
   SRLC16E #(
    .INIT(16'h0000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRLC16E 
       (.A0(A[0]),
        .A1(A[1]),
        .A2(A[2]),
        .A3(A[3]),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(I1),
        .Q(E),
        .Q15(O1));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut5" *) 
module ila_0_ltlib_v1_0_cfglut5
   (wcnt_hcmp_ce,
    SRL_D_I,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    SRL_Q_O,
    A,
    S_DCLK_O);
  output wcnt_hcmp_ce;
  output SRL_D_I;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input SRL_Q_O;
  input [4:0]A;
  input S_DCLK_O;

  wire [4:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire wcnt_hcmp_ce;

(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/I_YESLUT6.U_SRL32 " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(SRL_Q_O),
        .Q(wcnt_hcmp_ce),
        .Q31(SRL_D_I));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut5" *) 
module ila_0_ltlib_v1_0_cfglut5_263
   (wcnt_lcmp_ce,
    SRL_D_I,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O);
  output wcnt_lcmp_ce;
  output SRL_D_I;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [4:0]A;
  input S_DCLK_O;

  wire [4:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire I1;
  wire SRL_D_I;
  wire S_DCLK_O;
  wire wcnt_lcmp_ce;

(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/I_YESLUT6.U_SRL32 " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(I1),
        .Q(wcnt_lcmp_ce),
        .Q31(SRL_D_I));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut5" *) 
module ila_0_ltlib_v1_0_cfglut5_270
   (scnt_cmp_ce,
    O1,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O);
  output scnt_cmp_ce;
  output O1;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [4:0]A;
  input S_DCLK_O;

  wire [4:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire I1;
  wire O1;
  wire S_DCLK_O;
  wire scnt_cmp_ce;

(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/I_YESLUT6.U_SRL32 " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(I1),
        .Q(scnt_cmp_ce),
        .Q31(O1));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut6" *) 
module ila_0_ltlib_v1_0_cfglut6
   (O1,
    cmp_reset,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O,
    I2);
  output O1;
  output cmp_reset;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [4:0]A;
  input S_DCLK_O;
  input [0:0]I2;

  wire [4:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire I1;
  wire [0:0]I2;
  wire O1;
  wire SRL_Q31;
  wire S_DCLK_O;
  wire cmp_reset;
  wire p_1_in;
  wire p_2_in;

(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_A " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_A 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(SRL_Q31),
        .Q(p_1_in),
        .Q31(O1));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/I_YESLUT6.U_SRL32_B " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_B 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(I1),
        .Q(p_2_in),
        .Q31(SRL_Q31));
LUT3 #(
    .INIT(8'hB8)) 
     u_scnt_cmp_q_i_1
       (.I0(p_1_in),
        .I1(I2),
        .I2(p_2_in),
        .O(cmp_reset));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut6" *) 
module ila_0_ltlib_v1_0_cfglut6_271
   (SRL_D_I,
    SR,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O,
    I2);
  output SRL_D_I;
  output [0:0]SR;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [4:0]A;
  input S_DCLK_O;
  input [0:0]I2;

  wire [4:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire I1;
  wire [0:0]I2;
  wire [0:0]SR;
  wire SRL_D_I;
  wire SRL_Q31;
  wire S_DCLK_O;
  wire p_1_in;
  wire p_2_in;

LUT3 #(
    .INIT(8'hB8)) 
     \G_COUNTER[0].U_COUNTER_i_1 
       (.I0(p_1_in),
        .I1(I2),
        .I2(p_2_in),
        .O(SR));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_A " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_A 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(SRL_Q31),
        .Q(p_1_in),
        .Q31(SRL_D_I));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/I_YESLUT6.U_SRL32_B " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_B 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(I1),
        .Q(p_2_in),
        .Q31(SRL_Q31));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut6" *) 
module ila_0_ltlib_v1_0_cfglut6__parameterized0
   (D,
    cap_done_i,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    SRL_Q_O,
    A,
    S_DCLK_O,
    clk,
    wcnt_hcmp);
  output [0:0]D;
  output cap_done_i;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input SRL_Q_O;
  input [4:0]A;
  input S_DCLK_O;
  input clk;
  input wcnt_hcmp;

  wire [4:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire [0:0]D;
  wire SRL_MUX;
  wire SRL_Q31;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire cap_done_i;
  wire clk;
  wire p_1_in;
  wire p_2_in;
  wire wcnt_hcmp;

LUT3 #(
    .INIT(8'hB8)) 
     \I_YESLUT6.I_YES_OREG.O_reg_i_1__1 
       (.I0(p_1_in),
        .I1(wcnt_hcmp),
        .I2(p_2_in),
        .O(SRL_MUX));
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(SRL_MUX),
        .Q(cap_done_i),
        .R(1'b0));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_A " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_A 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(SRL_Q31),
        .Q(p_1_in),
        .Q31(D));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_CDONE/I_YESLUT6.U_SRL32_B " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_B 
       (.A(A),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(SRL_Q_O),
        .Q(p_2_in),
        .Q31(SRL_Q31));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut7" *) 
module ila_0_ltlib_v1_0_cfglut7
   (O1,
    D,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    I1,
    A,
    S_DCLK_O,
    Q,
    clk,
    I2,
    wcnt_hcmp);
  output [0:0]O1;
  output [0:0]D;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input I1;
  input [3:0]A;
  input S_DCLK_O;
  input [0:0]Q;
  input clk;
  input [0:0]I2;
  input wcnt_hcmp;

  wire [3:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire [0:0]D;
  wire I1;
  wire [0:0]I2;
  wire [0:0]O1;
  wire [0:0]Q;
  wire S_DCLK_O;
  wire clk;
  wire \n_0_I_YESLUT6.I_YES_OREG.O_reg_i_1 ;
  wire \n_1_I_YESLUT6.U_SRL32_B ;
  wire \n_1_I_YESLUT6.U_SRL32_C ;
  wire \n_1_I_YESLUT6.U_SRL32_D ;
  wire p_1_in;
  wire p_2_in;
  wire p_3_in;
  wire p_4_in;
  wire wcnt_hcmp;

LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
     \I_YESLUT6.I_YES_OREG.O_reg_i_1 
       (.I0(p_1_in),
        .I1(p_2_in),
        .I2(p_3_in),
        .I3(I2),
        .I4(p_4_in),
        .I5(wcnt_hcmp),
        .O(\n_0_I_YESLUT6.I_YES_OREG.O_reg_i_1 ));
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_I_YESLUT6.I_YES_OREG.O_reg_i_1 ),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_A " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_A 
       (.A({A,O1}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(\n_1_I_YESLUT6.U_SRL32_B ),
        .Q(p_1_in),
        .Q31(D));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_B " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_B 
       (.A({A,O1}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(\n_1_I_YESLUT6.U_SRL32_C ),
        .Q(p_2_in),
        .Q31(\n_1_I_YESLUT6.U_SRL32_B ));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_C " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_C 
       (.A({A,O1}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(\n_1_I_YESLUT6.U_SRL32_D ),
        .Q(p_3_in),
        .Q31(\n_1_I_YESLUT6.U_SRL32_C ));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS0/I_YESLUT6.U_SRL32_D " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_D 
       (.A({A,O1}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(I1),
        .Q(p_4_in),
        .Q31(\n_1_I_YESLUT6.U_SRL32_D ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_cfglut7" *) 
module ila_0_ltlib_v1_0_cfglut7_262
   (O1,
    O2,
    O3,
    O4,
    itrigger_in,
    O5,
    O6,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    capture_ctrl_config_serial_output,
    A,
    I1,
    S_DCLK_O,
    Q,
    clk,
    trig_out_fsm_temp,
    I2,
    arm_status,
    en_adv_trigger,
    basic_trigger,
    I3,
    capture_fsm_temp,
    I4,
    wcnt_hcmp);
  output [0:0]O1;
  output O2;
  output O3;
  output O4;
  output itrigger_in;
  output O5;
  output O6;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input capture_ctrl_config_serial_output;
  input [2:0]A;
  input [1:0]I1;
  input S_DCLK_O;
  input [0:0]Q;
  input clk;
  input trig_out_fsm_temp;
  input I2;
  input arm_status;
  input en_adv_trigger;
  input basic_trigger;
  input I3;
  input capture_fsm_temp;
  input I4;
  input wcnt_hcmp;

  wire [2:0]A;
  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire [1:0]I1;
  wire I2;
  wire I3;
  wire I4;
  wire [0:0]O1;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire [0:0]Q;
  wire SRL_MUX8;
  wire S_DCLK_O;
  wire arm_status;
  wire basic_trigger;
  wire capture_ctrl_config_serial_output;
  wire capture_fsm_temp;
  wire clk;
  wire en_adv_trigger;
  wire itrigger_in;
  wire n_0_CAPTURE_O_i_2;
  wire \n_1_I_YESLUT6.U_SRL32_B ;
  wire \n_1_I_YESLUT6.U_SRL32_C ;
  wire \n_1_I_YESLUT6.U_SRL32_D ;
  wire p_1_in;
  wire p_2_in;
  wire p_3_in;
  wire p_4_in;
  wire trig_out_fsm_temp;
  wire wcnt_hcmp;

LUT5 #(
    .INIT(32'hF8880888)) 
     CAPTURE_O_i_1
       (.I0(n_0_CAPTURE_O_i_2),
        .I1(I3),
        .I2(I1[0]),
        .I3(arm_status),
        .I4(capture_fsm_temp),
        .O(O5));
LUT3 #(
    .INIT(8'h04)) 
     CAPTURE_O_i_2
       (.I0(trig_out_fsm_temp),
        .I1(O1),
        .I2(I2),
        .O(n_0_CAPTURE_O_i_2));
(* SOFT_HLUTNM = "soft_lutpair25" *) 
   LUT4 #(
    .INIT(16'h0004)) 
     \G_COUNTER[0].U_COUNTER_i_5 
       (.I0(I2),
        .I1(O1),
        .I2(trig_out_fsm_temp),
        .I3(I1[0]),
        .O(O4));
LUT6 #(
    .INIT(64'hAACCAACCF0FFF000)) 
     \I_YESLUT6.I_YES_OREG.O_reg_i_1__0 
       (.I0(p_1_in),
        .I1(p_2_in),
        .I2(p_3_in),
        .I3(I1[1]),
        .I4(p_4_in),
        .I5(wcnt_hcmp),
        .O(SRL_MUX8));
FDRE \I_YESLUT6.I_YES_OREG.O_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(SRL_MUX8),
        .Q(O1),
        .R(Q));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_A " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_A 
       (.A({A,O1,I1[0]}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(\n_1_I_YESLUT6.U_SRL32_B ),
        .Q(p_1_in),
        .Q31(O2));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_B " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_B 
       (.A({A,O1,I1[0]}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(\n_1_I_YESLUT6.U_SRL32_C ),
        .Q(p_2_in),
        .Q31(\n_1_I_YESLUT6.U_SRL32_B ));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_C " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_C 
       (.A({A,O1,I1[0]}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(\n_1_I_YESLUT6.U_SRL32_D ),
        .Q(p_3_in),
        .Q31(\n_1_I_YESLUT6.U_SRL32_C ));
(* BOX_TYPE = "PRIMITIVE" *) 
   (* srl_name = "U0/\ila_core_inst/u_ila_cap_ctrl/U_NS1/I_YESLUT6.U_SRL32_D " *) 
   SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
     \I_YESLUT6.U_SRL32_D 
       (.A({A,O1,I1[0]}),
        .CE(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .CLK(S_DCLK_O),
        .D(capture_ctrl_config_serial_output),
        .Q(p_4_in),
        .Q31(\n_1_I_YESLUT6.U_SRL32_D ));
(* SOFT_HLUTNM = "soft_lutpair25" *) 
   LUT5 #(
    .INIT(32'h0000FB00)) 
     \cntcmpsel[1]_i_1 
       (.I0(trig_out_fsm_temp),
        .I1(O1),
        .I2(I2),
        .I3(arm_status),
        .I4(I1[0]),
        .O(O3));
LUT5 #(
    .INIT(32'h0000B800)) 
     itrigger_out_i_1
       (.I0(trig_out_fsm_temp),
        .I1(en_adv_trigger),
        .I2(basic_trigger),
        .I3(O1),
        .I4(I1[0]),
        .O(itrigger_in));
LUT6 #(
    .INIT(64'hFF00000000202020)) 
     trigger_i_1
       (.I0(O1),
        .I1(I2),
        .I2(I4),
        .I3(I1[0]),
        .I4(arm_status),
        .I5(trig_out_fsm_temp),
        .O(O6));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_generic_memrd" *) 
module ila_0_ltlib_v1_0_generic_memrd
   (E,
    I4,
    D,
    O1,
    s_dclk,
    I1,
    I2,
    I3,
    read_data_en,
    Q,
    I5,
    SR,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15);
  output [0:0]E;
  output [15:0]I4;
  output [0:0]D;
  output [9:0]O1;
  input s_dclk;
  input I1;
  input I2;
  input I3;
  input read_data_en;
  input [0:0]Q;
  input [140:0]I5;
  input [0:0]SR;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;

  wire [0:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I2;
  wire I3;
  wire [15:0]I4;
  wire [140:0]I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire [9:0]O1;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [3:0]curr_read_block;
  wire data_out_en;
  wire data_out_en_0;
  wire [140:0]input_data;
  wire mahesh_temp;
  wire \n_0_curr_read_block[0]_i_1 ;
  wire \n_0_curr_read_block[1]_i_1 ;
  wire \n_0_curr_read_block[2]_i_1 ;
  wire \n_0_curr_read_block[3]_i_1 ;
  wire \n_0_curr_read_block[3]_i_2 ;
  wire \n_0_curr_read_block[3]_i_3 ;
  wire \n_0_current_state[6]_i_2 ;
  wire \n_0_current_state[6]_i_6 ;
  wire \n_0_current_state[6]_i_7 ;
  wire \n_0_current_state_reg[0] ;
  wire \n_0_current_state_reg[1] ;
  wire \n_0_current_state_reg[2] ;
  wire \n_0_current_state_reg[3] ;
  wire \n_0_current_state_reg[4] ;
  wire \n_0_current_state_reg[5] ;
  wire \n_0_current_state_reg[6] ;
  wire n_0_data_out_en_i_1;
  wire \n_0_multiple_enable_latency.enable_out_reg[2]_srl2 ;
  wire \n_0_multiple_read_latency.read_enable_out_reg[2]_srl2 ;
  wire \n_0_read_addr[0]_i_1 ;
  wire \n_0_read_addr[1]_i_1 ;
  wire \n_0_read_addr[2]_i_1 ;
  wire \n_0_read_addr[3]_i_1 ;
  wire \n_0_read_addr[3]_i_2 ;
  wire \n_0_read_addr[4]_i_1 ;
  wire \n_0_read_addr[4]_i_2 ;
  wire \n_0_read_addr[5]_i_1 ;
  wire \n_0_read_addr[5]_i_2 ;
  wire \n_0_read_addr[6]_i_1 ;
  wire \n_0_read_addr[7]_i_1 ;
  wire \n_0_read_addr[7]_i_2 ;
  wire \n_0_read_addr[8]_i_1 ;
  wire \n_0_read_addr[9]_i_1 ;
  wire \n_0_read_addr[9]_i_2 ;
  wire \n_0_read_addr[9]_i_3 ;
  wire n_0_read_en_i_1;
  wire n_0_read_en_i_2;
  wire n_0_read_en_i_3;
  wire n_0_read_en_i_4;
  wire n_0_read_en_i_5;
  wire \n_0_xsdb_reg[0]_i_2 ;
  wire \n_0_xsdb_reg[0]_i_3 ;
  wire \n_0_xsdb_reg[10]_i_2 ;
  wire \n_0_xsdb_reg[10]_i_3 ;
  wire \n_0_xsdb_reg[11]_i_2 ;
  wire \n_0_xsdb_reg[11]_i_3 ;
  wire \n_0_xsdb_reg[12]_i_2 ;
  wire \n_0_xsdb_reg[12]_i_3 ;
  wire \n_0_xsdb_reg[13]_i_2 ;
  wire \n_0_xsdb_reg[13]_i_3 ;
  wire \n_0_xsdb_reg[14]_i_2 ;
  wire \n_0_xsdb_reg[14]_i_3 ;
  wire \n_0_xsdb_reg[15]_i_2__4 ;
  wire \n_0_xsdb_reg[15]_i_3__1 ;
  wire \n_0_xsdb_reg[1]_i_2 ;
  wire \n_0_xsdb_reg[1]_i_3 ;
  wire \n_0_xsdb_reg[2]_i_2 ;
  wire \n_0_xsdb_reg[2]_i_3 ;
  wire \n_0_xsdb_reg[3]_i_2 ;
  wire \n_0_xsdb_reg[3]_i_3 ;
  wire \n_0_xsdb_reg[4]_i_2 ;
  wire \n_0_xsdb_reg[4]_i_3 ;
  wire \n_0_xsdb_reg[5]_i_2 ;
  wire \n_0_xsdb_reg[5]_i_3 ;
  wire \n_0_xsdb_reg[6]_i_2 ;
  wire \n_0_xsdb_reg[6]_i_3 ;
  wire \n_0_xsdb_reg[7]_i_2 ;
  wire \n_0_xsdb_reg[7]_i_3 ;
  wire \n_0_xsdb_reg[8]_i_2 ;
  wire \n_0_xsdb_reg[8]_i_3 ;
  wire \n_0_xsdb_reg[9]_i_2 ;
  wire \n_0_xsdb_reg[9]_i_3 ;
  wire [6:0]next_state;
  wire p_0_in;
  wire read_data_en;
  wire read_en;
  wire s_dclk;

LUT2 #(
    .INIT(4'hE)) 
     \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1 
       (.I0(p_0_in),
        .I1(mahesh_temp),
        .O(D));
(* SOFT_HLUTNM = "soft_lutpair264" *) 
   LUT2 #(
    .INIT(4'h2)) 
     \curr_read_block[0]_i_1 
       (.I0(next_state[5]),
        .I1(curr_read_block[0]),
        .O(\n_0_curr_read_block[0]_i_1 ));
LUT3 #(
    .INIT(8'h28)) 
     \curr_read_block[1]_i_1 
       (.I0(next_state[5]),
        .I1(curr_read_block[0]),
        .I2(curr_read_block[1]),
        .O(\n_0_curr_read_block[1]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair259" *) 
   LUT4 #(
    .INIT(16'h7080)) 
     \curr_read_block[2]_i_1 
       (.I0(curr_read_block[1]),
        .I1(curr_read_block[0]),
        .I2(next_state[5]),
        .I3(curr_read_block[2]),
        .O(\n_0_curr_read_block[2]_i_1 ));
LUT6 #(
    .INIT(64'h0000000100010100)) 
     \curr_read_block[3]_i_1 
       (.I0(\n_0_curr_read_block[3]_i_3 ),
        .I1(next_state[1]),
        .I2(next_state[4]),
        .I3(next_state[6]),
        .I4(next_state[5]),
        .I5(next_state[0]),
        .O(\n_0_curr_read_block[3]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair259" *) 
   LUT5 #(
    .INIT(32'h7F008000)) 
     \curr_read_block[3]_i_2 
       (.I0(curr_read_block[2]),
        .I1(curr_read_block[0]),
        .I2(curr_read_block[1]),
        .I3(next_state[5]),
        .I4(curr_read_block[3]),
        .O(\n_0_curr_read_block[3]_i_2 ));
(* SOFT_HLUTNM = "soft_lutpair262" *) 
   LUT4 #(
    .INIT(16'hAAA8)) 
     \curr_read_block[3]_i_3 
       (.I0(\n_0_current_state[6]_i_2 ),
        .I1(\n_0_current_state_reg[2] ),
        .I2(\n_0_current_state_reg[1] ),
        .I3(\n_0_current_state_reg[5] ),
        .O(\n_0_curr_read_block[3]_i_3 ));
FDRE \curr_read_block_reg[0] 
       (.C(s_dclk),
        .CE(\n_0_curr_read_block[3]_i_1 ),
        .D(\n_0_curr_read_block[0]_i_1 ),
        .Q(curr_read_block[0]),
        .R(1'b0));
FDRE \curr_read_block_reg[1] 
       (.C(s_dclk),
        .CE(\n_0_curr_read_block[3]_i_1 ),
        .D(\n_0_curr_read_block[1]_i_1 ),
        .Q(curr_read_block[1]),
        .R(1'b0));
FDRE \curr_read_block_reg[2] 
       (.C(s_dclk),
        .CE(\n_0_curr_read_block[3]_i_1 ),
        .D(\n_0_curr_read_block[2]_i_1 ),
        .Q(curr_read_block[2]),
        .R(1'b0));
FDRE \curr_read_block_reg[3] 
       (.C(s_dclk),
        .CE(\n_0_curr_read_block[3]_i_1 ),
        .D(\n_0_curr_read_block[3]_i_2 ),
        .Q(curr_read_block[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair265" *) 
   LUT3 #(
    .INIT(8'h4F)) 
     \current_state[0]_i_1__50 
       (.I0(read_data_en),
        .I1(\n_0_current_state_reg[0] ),
        .I2(\n_0_current_state[6]_i_2 ),
        .O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair265" *) 
   LUT4 #(
    .INIT(16'hA888)) 
     \current_state[1]_i_1__50 
       (.I0(\n_0_current_state[6]_i_2 ),
        .I1(\n_0_current_state_reg[6] ),
        .I2(\n_0_current_state_reg[0] ),
        .I3(read_data_en),
        .O(next_state[1]));
(* SOFT_HLUTNM = "soft_lutpair262" *) 
   LUT4 #(
    .INIT(16'h88A8)) 
     \current_state[2]_i_1__50 
       (.I0(\n_0_current_state[6]_i_2 ),
        .I1(\n_0_current_state_reg[1] ),
        .I2(\n_0_current_state_reg[2] ),
        .I3(Q),
        .O(next_state[2]));
(* SOFT_HLUTNM = "soft_lutpair263" *) 
   LUT4 #(
    .INIT(16'hA888)) 
     \current_state[3]_i_1__50 
       (.I0(\n_0_current_state[6]_i_2 ),
        .I1(\n_0_current_state_reg[5] ),
        .I2(\n_0_current_state_reg[2] ),
        .I3(Q),
        .O(data_out_en_0));
LUT6 #(
    .INIT(64'h88A8A8A8A8A8A8A8)) 
     \current_state[4]_i_1 
       (.I0(\n_0_current_state[6]_i_2 ),
        .I1(\n_0_current_state_reg[3] ),
        .I2(\n_0_current_state_reg[4] ),
        .I3(I1),
        .I4(I2),
        .I5(I3),
        .O(next_state[4]));
LUT6 #(
    .INIT(64'h0000800000000000)) 
     \current_state[5]_i_1 
       (.I0(\n_0_current_state[6]_i_2 ),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I4(curr_read_block[3]),
        .I5(\n_0_current_state_reg[4] ),
        .O(next_state[5]));
LUT6 #(
    .INIT(64'h8000000000000000)) 
     \current_state[6]_i_1 
       (.I0(\n_0_current_state[6]_i_2 ),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I4(curr_read_block[3]),
        .I5(\n_0_current_state_reg[4] ),
        .O(next_state[6]));
LUT5 #(
    .INIT(32'h00000116)) 
     \current_state[6]_i_2 
       (.I0(\n_0_current_state_reg[0] ),
        .I1(\n_0_current_state_reg[1] ),
        .I2(\n_0_current_state_reg[2] ),
        .I3(\n_0_current_state[6]_i_6 ),
        .I4(\n_0_current_state[6]_i_7 ),
        .O(\n_0_current_state[6]_i_2 ));
(* SOFT_HLUTNM = "soft_lutpair261" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[6]_i_6 
       (.I0(\n_0_current_state_reg[3] ),
        .I1(\n_0_current_state_reg[4] ),
        .I2(\n_0_current_state_reg[5] ),
        .I3(\n_0_current_state_reg[6] ),
        .O(\n_0_current_state[6]_i_6 ));
(* SOFT_HLUTNM = "soft_lutpair261" *) 
   LUT4 #(
    .INIT(16'hFEE8)) 
     \current_state[6]_i_7 
       (.I0(\n_0_current_state_reg[3] ),
        .I1(\n_0_current_state_reg[4] ),
        .I2(\n_0_current_state_reg[5] ),
        .I3(\n_0_current_state_reg[6] ),
        .O(\n_0_current_state[6]_i_7 ));
FDSE #(
    .INIT(1'b1)) 
     \current_state_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(\n_0_current_state_reg[0] ),
        .S(SR));
FDRE #(
    .INIT(1'b0)) 
     \current_state_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(\n_0_current_state_reg[1] ),
        .R(SR));
FDRE #(
    .INIT(1'b0)) 
     \current_state_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(\n_0_current_state_reg[2] ),
        .R(SR));
FDRE #(
    .INIT(1'b0)) 
     \current_state_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(data_out_en_0),
        .Q(\n_0_current_state_reg[3] ),
        .R(SR));
FDRE #(
    .INIT(1'b0)) 
     \current_state_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(next_state[4]),
        .Q(\n_0_current_state_reg[4] ),
        .R(SR));
FDRE #(
    .INIT(1'b0)) 
     \current_state_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(next_state[5]),
        .Q(\n_0_current_state_reg[5] ),
        .R(SR));
FDRE #(
    .INIT(1'b0)) 
     \current_state_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(next_state[6]),
        .Q(\n_0_current_state_reg[6] ),
        .R(SR));
LUT6 #(
    .INIT(64'hFFFAFABB000A0A88)) 
     data_out_en_i_1
       (.I0(data_out_en_0),
        .I1(n_0_read_en_i_2),
        .I2(n_0_read_en_i_3),
        .I3(next_state[0]),
        .I4(next_state[1]),
        .I5(data_out_en),
        .O(n_0_data_out_en_i_1));
FDRE data_out_en_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_0_data_out_en_i_1),
        .Q(data_out_en),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[0] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[0]),
        .Q(input_data[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[100] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[100]),
        .Q(input_data[100]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[101] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[101]),
        .Q(input_data[101]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[102] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[102]),
        .Q(input_data[102]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[103] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[103]),
        .Q(input_data[103]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[104] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[104]),
        .Q(input_data[104]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[105] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[105]),
        .Q(input_data[105]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[106] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[106]),
        .Q(input_data[106]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[107] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[107]),
        .Q(input_data[107]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[108] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[108]),
        .Q(input_data[108]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[109] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[109]),
        .Q(input_data[109]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[10] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[10]),
        .Q(input_data[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[110] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[110]),
        .Q(input_data[110]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[111] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[111]),
        .Q(input_data[111]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[112] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[112]),
        .Q(input_data[112]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[113] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[113]),
        .Q(input_data[113]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[114] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[114]),
        .Q(input_data[114]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[115] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[115]),
        .Q(input_data[115]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[116] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[116]),
        .Q(input_data[116]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[117] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[117]),
        .Q(input_data[117]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[118] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[118]),
        .Q(input_data[118]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[119] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[119]),
        .Q(input_data[119]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[11] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[11]),
        .Q(input_data[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[120] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[120]),
        .Q(input_data[120]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[121] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[121]),
        .Q(input_data[121]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[122] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[122]),
        .Q(input_data[122]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[123] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[123]),
        .Q(input_data[123]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[124] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[124]),
        .Q(input_data[124]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[125] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[125]),
        .Q(input_data[125]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[126] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[126]),
        .Q(input_data[126]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[127] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[127]),
        .Q(input_data[127]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[128] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[128]),
        .Q(input_data[128]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[129] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[129]),
        .Q(input_data[129]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[12] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[12]),
        .Q(input_data[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[130] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[130]),
        .Q(input_data[130]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[131] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[131]),
        .Q(input_data[131]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[132] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[132]),
        .Q(input_data[132]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[133] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[133]),
        .Q(input_data[133]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[134] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[134]),
        .Q(input_data[134]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[135] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[135]),
        .Q(input_data[135]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[136] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[136]),
        .Q(input_data[136]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[137] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[137]),
        .Q(input_data[137]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[138] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[138]),
        .Q(input_data[138]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[139] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[139]),
        .Q(input_data[139]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[13] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[13]),
        .Q(input_data[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[140] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[140]),
        .Q(input_data[140]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[14] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[14]),
        .Q(input_data[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[15] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[15]),
        .Q(input_data[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[16] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[16]),
        .Q(input_data[16]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[17] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[17]),
        .Q(input_data[17]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[18] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[18]),
        .Q(input_data[18]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[19] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[19]),
        .Q(input_data[19]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[1] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[1]),
        .Q(input_data[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[20] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[20]),
        .Q(input_data[20]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[21] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[21]),
        .Q(input_data[21]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[22] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[22]),
        .Q(input_data[22]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[23] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[23]),
        .Q(input_data[23]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[24] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[24]),
        .Q(input_data[24]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[25] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[25]),
        .Q(input_data[25]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[26] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[26]),
        .Q(input_data[26]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[27] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[27]),
        .Q(input_data[27]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[28] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[28]),
        .Q(input_data[28]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[29] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[29]),
        .Q(input_data[29]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[2] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[2]),
        .Q(input_data[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[30] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[30]),
        .Q(input_data[30]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[31] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[31]),
        .Q(input_data[31]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[32] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[32]),
        .Q(input_data[32]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[33] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[33]),
        .Q(input_data[33]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[34] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[34]),
        .Q(input_data[34]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[35] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[35]),
        .Q(input_data[35]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[36] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[36]),
        .Q(input_data[36]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[37] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[37]),
        .Q(input_data[37]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[38] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[38]),
        .Q(input_data[38]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[39] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[39]),
        .Q(input_data[39]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[3]),
        .Q(input_data[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[40] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[40]),
        .Q(input_data[40]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[41] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[41]),
        .Q(input_data[41]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[42] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[42]),
        .Q(input_data[42]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[43] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[43]),
        .Q(input_data[43]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[44] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[44]),
        .Q(input_data[44]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[45] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[45]),
        .Q(input_data[45]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[46] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[46]),
        .Q(input_data[46]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[47] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[47]),
        .Q(input_data[47]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[48] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[48]),
        .Q(input_data[48]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[49] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[49]),
        .Q(input_data[49]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[4] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[4]),
        .Q(input_data[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[50] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[50]),
        .Q(input_data[50]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[51] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[51]),
        .Q(input_data[51]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[52] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[52]),
        .Q(input_data[52]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[53] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[53]),
        .Q(input_data[53]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[54] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[54]),
        .Q(input_data[54]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[55] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[55]),
        .Q(input_data[55]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[56] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[56]),
        .Q(input_data[56]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[57] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[57]),
        .Q(input_data[57]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[58] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[58]),
        .Q(input_data[58]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[59] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[59]),
        .Q(input_data[59]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[5] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[5]),
        .Q(input_data[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[60] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[60]),
        .Q(input_data[60]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[61] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[61]),
        .Q(input_data[61]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[62] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[62]),
        .Q(input_data[62]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[63] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[63]),
        .Q(input_data[63]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[64] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[64]),
        .Q(input_data[64]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[65] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[65]),
        .Q(input_data[65]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[66] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[66]),
        .Q(input_data[66]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[67] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[67]),
        .Q(input_data[67]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[68] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[68]),
        .Q(input_data[68]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[69] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[69]),
        .Q(input_data[69]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[6] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[6]),
        .Q(input_data[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[70] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[70]),
        .Q(input_data[70]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[71] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[71]),
        .Q(input_data[71]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[72] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[72]),
        .Q(input_data[72]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[73] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[73]),
        .Q(input_data[73]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[74] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[74]),
        .Q(input_data[74]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[75] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[75]),
        .Q(input_data[75]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[76] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[76]),
        .Q(input_data[76]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[77] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[77]),
        .Q(input_data[77]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[78] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[78]),
        .Q(input_data[78]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[79] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[79]),
        .Q(input_data[79]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[7] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[7]),
        .Q(input_data[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[80] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[80]),
        .Q(input_data[80]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[81] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[81]),
        .Q(input_data[81]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[82] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[82]),
        .Q(input_data[82]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[83] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[83]),
        .Q(input_data[83]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[84] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[84]),
        .Q(input_data[84]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[85] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[85]),
        .Q(input_data[85]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[86] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[86]),
        .Q(input_data[86]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[87] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[87]),
        .Q(input_data[87]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[88] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[88]),
        .Q(input_data[88]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[89] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[89]),
        .Q(input_data[89]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[8] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[8]),
        .Q(input_data[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[90] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[90]),
        .Q(input_data[90]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[91] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[91]),
        .Q(input_data[91]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[92] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[92]),
        .Q(input_data[92]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[93] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[93]),
        .Q(input_data[93]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[94] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[94]),
        .Q(input_data[94]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[95] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[95]),
        .Q(input_data[95]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[96] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[96]),
        .Q(input_data[96]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[97] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[97]),
        .Q(input_data[97]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[98] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[98]),
        .Q(input_data[98]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[99] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[99]),
        .Q(input_data[99]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \input_data_reg[9] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(I5[9]),
        .Q(input_data[9]),
        .R(1'b0));
(* srl_bus_name = "U0/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg " *) 
   (* srl_name = "U0/\ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[2]_srl2 " *) 
   SRL16E \multiple_enable_latency.enable_out_reg[2]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(s_dclk),
        .D(data_out_en),
        .Q(\n_0_multiple_enable_latency.enable_out_reg[2]_srl2 ));
FDRE \multiple_enable_latency.enable_out_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_multiple_enable_latency.enable_out_reg[2]_srl2 ),
        .Q(E),
        .R(1'b0));
FDRE \multiple_read_latency.mahesh_temp_reg 
       (.C(s_dclk),
        .CE(1'b1),
        .D(p_0_in),
        .Q(mahesh_temp),
        .R(1'b0));
(* srl_bus_name = "U0/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg " *) 
   (* srl_name = "U0/\ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[2]_srl2 " *) 
   SRL16E \multiple_read_latency.read_enable_out_reg[2]_srl2 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(s_dclk),
        .D(read_en),
        .Q(\n_0_multiple_read_latency.read_enable_out_reg[2]_srl2 ));
FDRE \multiple_read_latency.read_enable_out_reg[3] 
       (.C(s_dclk),
        .CE(1'b1),
        .D(\n_0_multiple_read_latency.read_enable_out_reg[2]_srl2 ),
        .Q(p_0_in),
        .R(1'b0));
LUT4 #(
    .INIT(16'hF444)) 
     \read_addr[0]_i_1 
       (.I0(O1[0]),
        .I1(next_state[6]),
        .I2(I15),
        .I3(next_state[0]),
        .O(\n_0_read_addr[0]_i_1 ));
LUT5 #(
    .INIT(32'h8FF88888)) 
     \read_addr[1]_i_1 
       (.I0(next_state[0]),
        .I1(I14),
        .I2(O1[0]),
        .I3(O1[1]),
        .I4(next_state[6]),
        .O(\n_0_read_addr[1]_i_1 ));
LUT6 #(
    .INIT(64'h8FFFF88888888888)) 
     \read_addr[2]_i_1 
       (.I0(next_state[0]),
        .I1(I13),
        .I2(O1[1]),
        .I3(O1[0]),
        .I4(O1[2]),
        .I5(next_state[6]),
        .O(\n_0_read_addr[2]_i_1 ));
LUT5 #(
    .INIT(32'h8FF88888)) 
     \read_addr[3]_i_1 
       (.I0(next_state[0]),
        .I1(I12),
        .I2(\n_0_read_addr[3]_i_2 ),
        .I3(O1[3]),
        .I4(next_state[6]),
        .O(\n_0_read_addr[3]_i_1 ));
LUT3 #(
    .INIT(8'h80)) 
     \read_addr[3]_i_2 
       (.I0(O1[2]),
        .I1(O1[0]),
        .I2(O1[1]),
        .O(\n_0_read_addr[3]_i_2 ));
LUT5 #(
    .INIT(32'h8FF88888)) 
     \read_addr[4]_i_1 
       (.I0(next_state[0]),
        .I1(I11),
        .I2(\n_0_read_addr[4]_i_2 ),
        .I3(O1[4]),
        .I4(next_state[6]),
        .O(\n_0_read_addr[4]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair260" *) 
   LUT4 #(
    .INIT(16'h8000)) 
     \read_addr[4]_i_2 
       (.I0(O1[3]),
        .I1(O1[1]),
        .I2(O1[0]),
        .I3(O1[2]),
        .O(\n_0_read_addr[4]_i_2 ));
LUT5 #(
    .INIT(32'h8FF88888)) 
     \read_addr[5]_i_1 
       (.I0(next_state[0]),
        .I1(I10),
        .I2(\n_0_read_addr[5]_i_2 ),
        .I3(O1[5]),
        .I4(next_state[6]),
        .O(\n_0_read_addr[5]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair260" *) 
   LUT5 #(
    .INIT(32'h80000000)) 
     \read_addr[5]_i_2 
       (.I0(O1[4]),
        .I1(O1[2]),
        .I2(O1[0]),
        .I3(O1[1]),
        .I4(O1[3]),
        .O(\n_0_read_addr[5]_i_2 ));
LUT5 #(
    .INIT(32'h8FF88888)) 
     \read_addr[6]_i_1 
       (.I0(next_state[0]),
        .I1(I9),
        .I2(\n_0_read_addr[7]_i_2 ),
        .I3(O1[6]),
        .I4(next_state[6]),
        .O(\n_0_read_addr[6]_i_1 ));
LUT6 #(
    .INIT(64'h8FFFF88888888888)) 
     \read_addr[7]_i_1 
       (.I0(next_state[0]),
        .I1(I8),
        .I2(O1[6]),
        .I3(\n_0_read_addr[7]_i_2 ),
        .I4(O1[7]),
        .I5(next_state[6]),
        .O(\n_0_read_addr[7]_i_1 ));
LUT6 #(
    .INIT(64'h8000000000000000)) 
     \read_addr[7]_i_2 
       (.I0(O1[5]),
        .I1(O1[3]),
        .I2(O1[1]),
        .I3(O1[0]),
        .I4(O1[2]),
        .I5(O1[4]),
        .O(\n_0_read_addr[7]_i_2 ));
LUT5 #(
    .INIT(32'h8FF88888)) 
     \read_addr[8]_i_1 
       (.I0(next_state[0]),
        .I1(I7),
        .I2(\n_0_read_addr[9]_i_3 ),
        .I3(O1[8]),
        .I4(next_state[6]),
        .O(\n_0_read_addr[8]_i_1 ));
LUT6 #(
    .INIT(64'h0000000000000110)) 
     \read_addr[9]_i_1 
       (.I0(next_state[5]),
        .I1(next_state[4]),
        .I2(next_state[0]),
        .I3(next_state[6]),
        .I4(next_state[1]),
        .I5(\n_0_curr_read_block[3]_i_3 ),
        .O(\n_0_read_addr[9]_i_1 ));
LUT6 #(
    .INIT(64'h8FFFF88888888888)) 
     \read_addr[9]_i_2 
       (.I0(next_state[0]),
        .I1(I6),
        .I2(O1[8]),
        .I3(\n_0_read_addr[9]_i_3 ),
        .I4(O1[9]),
        .I5(next_state[6]),
        .O(\n_0_read_addr[9]_i_2 ));
LUT3 #(
    .INIT(8'h80)) 
     \read_addr[9]_i_3 
       (.I0(O1[7]),
        .I1(\n_0_read_addr[7]_i_2 ),
        .I2(O1[6]),
        .O(\n_0_read_addr[9]_i_3 ));
FDRE \read_addr_reg[0] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[0]_i_1 ),
        .Q(O1[0]),
        .R(1'b0));
FDRE \read_addr_reg[1] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[1]_i_1 ),
        .Q(O1[1]),
        .R(1'b0));
FDRE \read_addr_reg[2] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[2]_i_1 ),
        .Q(O1[2]),
        .R(1'b0));
FDRE \read_addr_reg[3] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[3]_i_1 ),
        .Q(O1[3]),
        .R(1'b0));
FDRE \read_addr_reg[4] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[4]_i_1 ),
        .Q(O1[4]),
        .R(1'b0));
FDRE \read_addr_reg[5] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[5]_i_1 ),
        .Q(O1[5]),
        .R(1'b0));
FDRE \read_addr_reg[6] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[6]_i_1 ),
        .Q(O1[6]),
        .R(1'b0));
FDRE \read_addr_reg[7] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[7]_i_1 ),
        .Q(O1[7]),
        .R(1'b0));
FDRE \read_addr_reg[8] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[8]_i_1 ),
        .Q(O1[8]),
        .R(1'b0));
FDRE \read_addr_reg[9] 
       (.C(s_dclk),
        .CE(\n_0_read_addr[9]_i_1 ),
        .D(\n_0_read_addr[9]_i_2 ),
        .Q(O1[9]),
        .R(1'b0));
LUT5 #(
    .INIT(32'hFFC50300)) 
     read_en_i_1
       (.I0(n_0_read_en_i_2),
        .I1(n_0_read_en_i_3),
        .I2(next_state[0]),
        .I3(next_state[1]),
        .I4(read_en),
        .O(n_0_read_en_i_1));
LUT6 #(
    .INIT(64'h0016011601161616)) 
     read_en_i_2
       (.I0(next_state[4]),
        .I1(next_state[6]),
        .I2(next_state[5]),
        .I3(\n_0_current_state[6]_i_2 ),
        .I4(n_0_read_en_i_4),
        .I5(n_0_read_en_i_5),
        .O(n_0_read_en_i_2));
(* SOFT_HLUTNM = "soft_lutpair264" *) 
   LUT4 #(
    .INIT(16'hFFFE)) 
     read_en_i_3
       (.I0(\n_0_curr_read_block[3]_i_3 ),
        .I1(next_state[4]),
        .I2(next_state[5]),
        .I3(next_state[6]),
        .O(n_0_read_en_i_3));
LUT3 #(
    .INIT(8'hF4)) 
     read_en_i_4
       (.I0(Q),
        .I1(\n_0_current_state_reg[2] ),
        .I2(\n_0_current_state_reg[1] ),
        .O(n_0_read_en_i_4));
(* SOFT_HLUTNM = "soft_lutpair263" *) 
   LUT3 #(
    .INIT(8'hF8)) 
     read_en_i_5
       (.I0(Q),
        .I1(\n_0_current_state_reg[2] ),
        .I2(\n_0_current_state_reg[5] ),
        .O(n_0_read_en_i_5));
FDRE read_en_reg
       (.C(s_dclk),
        .CE(1'b1),
        .D(n_0_read_en_i_1),
        .Q(read_en),
        .R(1'b0));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[0]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[0]_i_2 ),
        .I2(\n_0_xsdb_reg[0]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[128]),
        .O(I4[0]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[0]_i_2 
       (.I0(input_data[16]),
        .I1(input_data[48]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[0]),
        .I5(input_data[32]),
        .O(\n_0_xsdb_reg[0]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[0]_i_3 
       (.I0(input_data[80]),
        .I1(input_data[112]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[64]),
        .I5(input_data[96]),
        .O(\n_0_xsdb_reg[0]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[10]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[10]_i_2 ),
        .I2(\n_0_xsdb_reg[10]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[138]),
        .O(I4[10]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[10]_i_2 
       (.I0(input_data[26]),
        .I1(input_data[58]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[10]),
        .I5(input_data[42]),
        .O(\n_0_xsdb_reg[10]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[10]_i_3 
       (.I0(input_data[90]),
        .I1(input_data[122]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[74]),
        .I5(input_data[106]),
        .O(\n_0_xsdb_reg[10]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[11]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[11]_i_2 ),
        .I2(\n_0_xsdb_reg[11]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[139]),
        .O(I4[11]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[11]_i_2 
       (.I0(input_data[27]),
        .I1(input_data[59]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[11]),
        .I5(input_data[43]),
        .O(\n_0_xsdb_reg[11]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[11]_i_3 
       (.I0(input_data[91]),
        .I1(input_data[123]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[75]),
        .I5(input_data[107]),
        .O(\n_0_xsdb_reg[11]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[12]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[12]_i_2 ),
        .I2(\n_0_xsdb_reg[12]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[140]),
        .O(I4[12]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[12]_i_2 
       (.I0(input_data[28]),
        .I1(input_data[60]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[12]),
        .I5(input_data[44]),
        .O(\n_0_xsdb_reg[12]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[12]_i_3 
       (.I0(input_data[92]),
        .I1(input_data[124]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[76]),
        .I5(input_data[108]),
        .O(\n_0_xsdb_reg[12]_i_3 ));
LUT4 #(
    .INIT(16'h00E2)) 
     \xsdb_reg[13]_i_1 
       (.I0(\n_0_xsdb_reg[13]_i_2 ),
        .I1(curr_read_block[2]),
        .I2(\n_0_xsdb_reg[13]_i_3 ),
        .I3(curr_read_block[3]),
        .O(I4[13]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[13]_i_2 
       (.I0(input_data[29]),
        .I1(input_data[61]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[13]),
        .I5(input_data[45]),
        .O(\n_0_xsdb_reg[13]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[13]_i_3 
       (.I0(input_data[93]),
        .I1(input_data[125]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[77]),
        .I5(input_data[109]),
        .O(\n_0_xsdb_reg[13]_i_3 ));
LUT4 #(
    .INIT(16'h00E2)) 
     \xsdb_reg[14]_i_1 
       (.I0(\n_0_xsdb_reg[14]_i_2 ),
        .I1(curr_read_block[2]),
        .I2(\n_0_xsdb_reg[14]_i_3 ),
        .I3(curr_read_block[3]),
        .O(I4[14]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[14]_i_2 
       (.I0(input_data[30]),
        .I1(input_data[62]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[14]),
        .I5(input_data[46]),
        .O(\n_0_xsdb_reg[14]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[14]_i_3 
       (.I0(input_data[94]),
        .I1(input_data[126]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[78]),
        .I5(input_data[110]),
        .O(\n_0_xsdb_reg[14]_i_3 ));
LUT4 #(
    .INIT(16'h00E2)) 
     \xsdb_reg[15]_i_1__9 
       (.I0(\n_0_xsdb_reg[15]_i_2__4 ),
        .I1(curr_read_block[2]),
        .I2(\n_0_xsdb_reg[15]_i_3__1 ),
        .I3(curr_read_block[3]),
        .O(I4[15]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[15]_i_2__4 
       (.I0(input_data[31]),
        .I1(input_data[63]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[15]),
        .I5(input_data[47]),
        .O(\n_0_xsdb_reg[15]_i_2__4 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[15]_i_3__1 
       (.I0(input_data[95]),
        .I1(input_data[127]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[79]),
        .I5(input_data[111]),
        .O(\n_0_xsdb_reg[15]_i_3__1 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[1]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[1]_i_2 ),
        .I2(\n_0_xsdb_reg[1]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[129]),
        .O(I4[1]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[1]_i_2 
       (.I0(input_data[17]),
        .I1(input_data[49]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[1]),
        .I5(input_data[33]),
        .O(\n_0_xsdb_reg[1]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[1]_i_3 
       (.I0(input_data[81]),
        .I1(input_data[113]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[65]),
        .I5(input_data[97]),
        .O(\n_0_xsdb_reg[1]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[2]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[2]_i_2 ),
        .I2(\n_0_xsdb_reg[2]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[130]),
        .O(I4[2]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[2]_i_2 
       (.I0(input_data[18]),
        .I1(input_data[50]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[2]),
        .I5(input_data[34]),
        .O(\n_0_xsdb_reg[2]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[2]_i_3 
       (.I0(input_data[82]),
        .I1(input_data[114]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[66]),
        .I5(input_data[98]),
        .O(\n_0_xsdb_reg[2]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[3]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[3]_i_2 ),
        .I2(\n_0_xsdb_reg[3]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[131]),
        .O(I4[3]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[3]_i_2 
       (.I0(input_data[19]),
        .I1(input_data[51]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[3]),
        .I5(input_data[35]),
        .O(\n_0_xsdb_reg[3]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[3]_i_3 
       (.I0(input_data[83]),
        .I1(input_data[115]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[67]),
        .I5(input_data[99]),
        .O(\n_0_xsdb_reg[3]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[4]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[4]_i_2 ),
        .I2(\n_0_xsdb_reg[4]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[132]),
        .O(I4[4]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[4]_i_2 
       (.I0(input_data[20]),
        .I1(input_data[52]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[4]),
        .I5(input_data[36]),
        .O(\n_0_xsdb_reg[4]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[4]_i_3 
       (.I0(input_data[84]),
        .I1(input_data[116]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[68]),
        .I5(input_data[100]),
        .O(\n_0_xsdb_reg[4]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[5]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[5]_i_2 ),
        .I2(\n_0_xsdb_reg[5]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[133]),
        .O(I4[5]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[5]_i_2 
       (.I0(input_data[21]),
        .I1(input_data[53]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[5]),
        .I5(input_data[37]),
        .O(\n_0_xsdb_reg[5]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[5]_i_3 
       (.I0(input_data[85]),
        .I1(input_data[117]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[69]),
        .I5(input_data[101]),
        .O(\n_0_xsdb_reg[5]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[6]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[6]_i_2 ),
        .I2(\n_0_xsdb_reg[6]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[134]),
        .O(I4[6]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[6]_i_2 
       (.I0(input_data[22]),
        .I1(input_data[54]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[6]),
        .I5(input_data[38]),
        .O(\n_0_xsdb_reg[6]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[6]_i_3 
       (.I0(input_data[86]),
        .I1(input_data[118]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[70]),
        .I5(input_data[102]),
        .O(\n_0_xsdb_reg[6]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[7]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[7]_i_2 ),
        .I2(\n_0_xsdb_reg[7]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[135]),
        .O(I4[7]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[7]_i_2 
       (.I0(input_data[23]),
        .I1(input_data[55]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[7]),
        .I5(input_data[39]),
        .O(\n_0_xsdb_reg[7]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[7]_i_3 
       (.I0(input_data[87]),
        .I1(input_data[119]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[71]),
        .I5(input_data[103]),
        .O(\n_0_xsdb_reg[7]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[8]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[8]_i_2 ),
        .I2(\n_0_xsdb_reg[8]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[136]),
        .O(I4[8]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[8]_i_2 
       (.I0(input_data[24]),
        .I1(input_data[56]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[8]),
        .I5(input_data[40]),
        .O(\n_0_xsdb_reg[8]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[8]_i_3 
       (.I0(input_data[88]),
        .I1(input_data[120]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[72]),
        .I5(input_data[104]),
        .O(\n_0_xsdb_reg[8]_i_3 ));
LUT5 #(
    .INIT(32'hFFE400E4)) 
     \xsdb_reg[9]_i_1 
       (.I0(curr_read_block[2]),
        .I1(\n_0_xsdb_reg[9]_i_2 ),
        .I2(\n_0_xsdb_reg[9]_i_3 ),
        .I3(curr_read_block[3]),
        .I4(input_data[137]),
        .O(I4[9]));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[9]_i_2 
       (.I0(input_data[25]),
        .I1(input_data[57]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[9]),
        .I5(input_data[41]),
        .O(\n_0_xsdb_reg[9]_i_2 ));
LUT6 #(
    .INIT(64'hCFAFCFA0C0AFC0A0)) 
     \xsdb_reg[9]_i_3 
       (.I0(input_data[89]),
        .I1(input_data[121]),
        .I2(curr_read_block[0]),
        .I3(curr_read_block[1]),
        .I4(input_data[73]),
        .I5(input_data[105]),
        .O(\n_0_xsdb_reg[9]_i_3 ));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    I1,
    use_probe_debug_circuit,
    probe0);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input [15:0]I1;
  input use_probe_debug_circuit;
  input [15:0]probe0;

  wire [0:0]D;
  wire DOUT_O;
  wire [15:0]I1;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire [15:0]probe0;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA_205 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.DOUT_O(DOUT_O),
        .I1(I1),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe0(probe0),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(DOUT_O),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match_158
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe3);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [31:0]probe3;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [31:0]probe3;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA_185 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe3(probe3),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match_161
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe6);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [31:0]probe6;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [31:0]probe6;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA_173 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe6(probe6),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match_164
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe9);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [31:0]probe9;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [31:0]probe9;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe9(probe9),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized0
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe10);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe10;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [0:0]probe10;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized0_202 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe10(probe10),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized0_155
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe11);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe11;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [0:0]probe11;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized0_199 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe11(probe11),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized0_156
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe1);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe1;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [0:0]probe1;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized0_194 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe1(probe1),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized0_157
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe2);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe2;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [0:0]probe2;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized0_191 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe2(probe2),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized0_159
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe4);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe4;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [0:0]probe4;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized0_182 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe4(probe4),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized0_160
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe5);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe5;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [0:0]probe5;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized0_179 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe5(probe5),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized0_162
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe7);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe7;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [0:0]probe7;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized0_170 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe7(probe7),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized0_163
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe8);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [0:0]probe8;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [0:0]probe8;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized0 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe8(probe8),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized1
   (mu_config_cs_serial_input,
    D,
    mu_config_cs_shift_en,
    s_dclk,
    mu_config_cs_serial_output,
    Q,
    clk,
    use_probe_debug_circuit,
    probe12);
  output [0:0]mu_config_cs_serial_input;
  output [0:0]D;
  input [0:0]mu_config_cs_shift_en;
  input s_dclk;
  input [0:0]mu_config_cs_serial_output;
  input [1:0]Q;
  input clk;
  input use_probe_debug_circuit;
  input [3:0]probe12;

  wire [0:0]D;
  wire [1:0]Q;
  wire clk;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire [0:0]mu_config_cs_shift_en;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire [3:0]probe12;
  wire s_dclk;
  wire use_probe_debug_circuit;

ila_0_ltlib_v1_0_allx_typeA__parameterized1 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q[0]),
        .clk(clk),
        .mu_config_cs_serial_input(mu_config_cs_serial_input),
        .mu_config_cs_serial_output(mu_config_cs_serial_output),
        .mu_config_cs_shift_en(mu_config_cs_shift_en),
        .probe12(probe12),
        .s_dclk(s_dclk),
        .use_probe_debug_circuit(use_probe_debug_circuit));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(D),
        .R(Q[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2
   (tc_config_cs_serial_input,
    Q,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [12:0]Q;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_14_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_151 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_14_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_14_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_0
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_147 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_1
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_143 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_10
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_107 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_11
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_103 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_12
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_99 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_13
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_95 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_14
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_91 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_15
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_87 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_16
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_83 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_17
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_79 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_18
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_75 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_19
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_71 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_2
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_139 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_20
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_67 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_21
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_63 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_22
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_59 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_23
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_55 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_24
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_51 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_25
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_47 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_26
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_43 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_27
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_39 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_28
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_35 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_29
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_31 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_3
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_135 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_30
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_4
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_131 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_5
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_127 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_6
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_123 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_7
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_119 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_8
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_115 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match" *) 
module ila_0_ltlib_v1_0_match__parameterized2_9
   (tc_config_cs_serial_input,
    O1,
    tc_config_cs_shift_en,
    s_dclk,
    tc_config_cs_serial_output,
    D,
    Q,
    I1,
    clk);
  output [0:0]tc_config_cs_serial_input;
  output [0:0]O1;
  input [0:0]tc_config_cs_shift_en;
  input s_dclk;
  input [0:0]tc_config_cs_serial_output;
  input [12:0]D;
  input [12:0]Q;
  input [1:0]I1;
  input clk;

  wire [12:0]D;
  wire [1:0]I1;
  wire [0:0]O1;
  wire [12:0]Q;
  wire clk;
  wire \n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ;
  wire s_dclk;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;
  wire [0:0]tc_config_cs_shift_en;

ila_0_ltlib_v1_0_allx_typeA__parameterized2_111 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.D(D),
        .I1(I1[0]),
        .O1(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(Q),
        .clk(clk),
        .s_dclk(s_dclk),
        .tc_config_cs_serial_input(tc_config_cs_serial_input),
        .tc_config_cs_serial_output(tc_config_cs_serial_output),
        .tc_config_cs_shift_en(tc_config_cs_shift_en));
FDRE \yes_output_reg.dout_reg_reg 
       (.C(clk),
        .CE(1'b1),
        .D(\n_1_allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst ),
        .Q(O1),
        .R(I1[1]));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match_nodelay" *) 
module ila_0_ltlib_v1_0_match_nodelay
   (SRL_Q_O,
    DOUT_O,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    PROBES_I,
    SRL_D_I);
  output SRL_Q_O;
  output DOUT_O;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input [19:0]PROBES_I;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [19:0]PROBES_I;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;

ila_0_ltlib_v1_0_allx_typeA_nodelay_265 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(DOUT_O),
        .PROBES_I(PROBES_I),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match_nodelay" *) 
module ila_0_ltlib_v1_0_match_nodelay_264
   (Q,
    SRL_Q_O,
    DOUT_O,
    I1,
    clk,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    SRL_D_I);
  output [9:0]Q;
  output SRL_Q_O;
  output DOUT_O;
  input [9:0]I1;
  input clk;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [9:0]I1;
  wire [9:0]Q;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire clk;

ila_0_ltlib_v1_0_allx_typeA_nodelay \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(DOUT_O),
        .I1(I1),
        .Q(Q),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_match_nodelay" *) 
module ila_0_ltlib_v1_0_match_nodelay_272
   (SRL_Q_O,
    DOUT_O,
    Q,
    clk,
    CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O,
    S_DCLK_O,
    SRL_D_I);
  output SRL_Q_O;
  output DOUT_O;
  input [9:0]Q;
  input clk;
  input CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  input S_DCLK_O;
  input SRL_D_I;

  wire CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O;
  wire DOUT_O;
  wire [9:0]Q;
  wire SRL_D_I;
  wire SRL_Q_O;
  wire S_DCLK_O;
  wire clk;

ila_0_ltlib_v1_0_allx_typeA_nodelay_273 \allx_typeA_match_detection.ltlib_v1_0_allx_typeA_inst 
       (.CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O(CAPTURE_CTRL_CONFIG_CS_SHIFT_EN_O),
        .DOUT_O(DOUT_O),
        .Q(Q),
        .SRL_D_I(SRL_D_I),
        .SRL_Q_O(SRL_Q_O),
        .S_DCLK_O(S_DCLK_O),
        .clk(clk));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_rising_edge_detection" *) 
module ila_0_ltlib_v1_0_rising_edge_detection
   (last_din,
    D,
    O1,
    arm_in_transferred,
    clk,
    Q,
    I1);
  output last_din;
  output [0:0]D;
  output [0:0]O1;
  input arm_in_transferred;
  input clk;
  input [0:0]Q;
  input [0:0]I1;

  wire [0:0]D;
  wire [0:0]I1;
  wire [0:0]O1;
  wire [0:0]Q;
  wire arm_in_transferred;
  wire clk;
  wire [0:0]dout_pulse;
  wire last_din;
  wire \n_0_dout_pulse[1]_i_1__0 ;

LUT3 #(
    .INIT(8'hF4)) 
     \dout_pulse[1]_i_1__0 
       (.I0(last_din),
        .I1(arm_in_transferred),
        .I2(dout_pulse),
        .O(\n_0_dout_pulse[1]_i_1__0 ));
FDRE #(
    .INIT(1'b0)) 
     \dout_pulse_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(I1),
        .Q(dout_pulse),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \dout_pulse_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_dout_pulse[1]_i_1__0 ),
        .Q(O1),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     last_din_reg
       (.C(clk),
        .CE(1'b1),
        .D(arm_in_transferred),
        .Q(last_din),
        .R(1'b0));
LUT2 #(
    .INIT(4'h2)) 
     \reset_out[0]_i_1 
       (.I0(Q),
        .I1(O1),
        .O(D));
endmodule

(* ORIG_REF_NAME = "ltlib_v1_0_rising_edge_detection" *) 
module ila_0_ltlib_v1_0_rising_edge_detection_214
   (last_din,
    SS,
    Q,
    halt_in_transferred,
    clk,
    prev_cap_done,
    I1,
    D);
  output last_din;
  output [0:0]SS;
  output [0:0]Q;
  input halt_in_transferred;
  input clk;
  input prev_cap_done;
  input [0:0]I1;
  input [0:0]D;

  wire [0:0]D;
  wire [0:0]I1;
  wire [0:0]Q;
  wire [0:0]SS;
  wire clk;
  wire [0:0]dout_pulse;
  wire halt_in_transferred;
  wire last_din;
  wire \n_0_dout_pulse[1]_i_1 ;
  wire prev_cap_done;

LUT3 #(
    .INIT(8'hF4)) 
     \dout_pulse[1]_i_1 
       (.I0(last_din),
        .I1(halt_in_transferred),
        .I2(dout_pulse),
        .O(\n_0_dout_pulse[1]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \dout_pulse_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(D),
        .Q(dout_pulse),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \dout_pulse_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\n_0_dout_pulse[1]_i_1 ),
        .Q(Q),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     last_din_reg
       (.C(clk),
        .CE(1'b1),
        .D(halt_in_transferred),
        .Q(last_din),
        .R(1'b0));
LUT3 #(
    .INIT(8'hBA)) 
     \reset_out[5]_i_1 
       (.I0(Q),
        .I1(prev_cap_done),
        .I2(I1),
        .O(SS));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg
   (O1,
    Q,
    s_daddr_o,
    I1,
    slaveRegDo_80,
    I2,
    E,
    I3);
  output O1;
  output [14:0]Q;
  input [1:0]s_daddr_o;
  input I1;
  input [0:0]slaveRegDo_80;
  input I2;
  input [0:0]E;
  input I3;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire O1;
  wire [14:0]Q;
  wire [1:0]s_daddr_o;
  wire [0:0]slaveRegDo_80;

ila_0_xsdbs_v1_0_reg_stat_247 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .O1(O1),
        .Q(Q),
        .s_daddr_o(s_daddr_o),
        .slaveRegDo_80(slaveRegDo_80));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized0
   (O1,
    O2,
    O3,
    s_daddr_o,
    Q,
    E,
    I1);
  output O1;
  output O2;
  output [13:0]O3;
  input [2:0]s_daddr_o;
  input [1:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire O1;
  wire O2;
  wire [13:0]O3;
  wire [1:0]Q;
  wire [2:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_246 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .O1(O1),
        .O2(O2),
        .O3(O3),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized1
   (O1,
    Q,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    D,
    O16,
    O17,
    O18,
    O19,
    O20,
    O21,
    O22,
    O23,
    O24,
    O25,
    O26,
    O27,
    O28,
    O29,
    O30,
    O31,
    O32,
    O33,
    O34,
    O35,
    O36,
    O37,
    O38,
    O39,
    O40,
    O41,
    O42,
    O43,
    O44,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    slaveRegDo_81,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    I24,
    I25,
    I26,
    I27,
    I28,
    I29,
    I30,
    I31,
    I32,
    I33,
    I34,
    I35,
    I36,
    I37,
    I38,
    I39,
    I40,
    I41,
    I42,
    I43,
    I44,
    I45,
    I46,
    I47,
    I48,
    I49,
    I50,
    I51,
    I52,
    I53,
    I54,
    I55,
    I56,
    I57,
    I58,
    I59,
    I60,
    I61,
    I62,
    I63,
    I64,
    I65,
    I66,
    I67,
    I68,
    slaveRegDo_6,
    slaveRegDo_82,
    I69,
    I70,
    I71,
    I72,
    I73,
    I74,
    I75,
    I76,
    I77,
    slaveRegDo_80,
    slaveRegDo_84,
    I78,
    E,
    I79);
  output O1;
  output [15:0]Q;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output [5:0]D;
  output O16;
  output O17;
  output O18;
  output O19;
  output O20;
  output O21;
  output O22;
  output O23;
  output O24;
  output O25;
  output O26;
  output O27;
  output O28;
  output O29;
  output O30;
  output O31;
  output O32;
  output O33;
  output O34;
  output O35;
  output O36;
  output O37;
  output O38;
  output O39;
  output O40;
  output O41;
  output O42;
  output O43;
  output O44;
  input [6:0]s_daddr_o;
  input [11:0]I1;
  input [11:0]I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input [15:0]slaveRegDo_81;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input [5:0]I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input [0:0]I23;
  input I24;
  input I25;
  input I26;
  input I27;
  input I28;
  input I29;
  input I30;
  input I31;
  input I32;
  input I33;
  input I34;
  input I35;
  input I36;
  input I37;
  input I38;
  input I39;
  input I40;
  input I41;
  input I42;
  input I43;
  input I44;
  input I45;
  input I46;
  input I47;
  input I48;
  input I49;
  input I50;
  input I51;
  input I52;
  input I53;
  input I54;
  input I55;
  input I56;
  input I57;
  input I58;
  input I59;
  input I60;
  input I61;
  input I62;
  input I63;
  input I64;
  input [13:0]I65;
  input I66;
  input I67;
  input I68;
  input [12:0]slaveRegDo_6;
  input [12:0]slaveRegDo_82;
  input I69;
  input I70;
  input I71;
  input I72;
  input I73;
  input I74;
  input I75;
  input I76;
  input I77;
  input [3:0]slaveRegDo_80;
  input [3:0]slaveRegDo_84;
  input [3:0]I78;
  input [0:0]E;
  input I79;

  wire [5:0]D;
  wire [0:0]E;
  wire [11:0]I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire [5:0]I16;
  wire I17;
  wire I18;
  wire I19;
  wire [11:0]I2;
  wire I20;
  wire I21;
  wire I22;
  wire [0:0]I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I28;
  wire I29;
  wire I3;
  wire I30;
  wire I31;
  wire I32;
  wire I33;
  wire I34;
  wire I35;
  wire I36;
  wire I37;
  wire I38;
  wire I39;
  wire I4;
  wire I40;
  wire I41;
  wire I42;
  wire I43;
  wire I44;
  wire I45;
  wire I46;
  wire I47;
  wire I48;
  wire I49;
  wire I5;
  wire I50;
  wire I51;
  wire I52;
  wire I53;
  wire I54;
  wire I55;
  wire I56;
  wire I57;
  wire I58;
  wire I59;
  wire I6;
  wire I60;
  wire I61;
  wire I62;
  wire I63;
  wire I64;
  wire [13:0]I65;
  wire I66;
  wire I67;
  wire I68;
  wire I69;
  wire I7;
  wire I70;
  wire I71;
  wire I72;
  wire I73;
  wire I74;
  wire I75;
  wire I76;
  wire I77;
  wire [3:0]I78;
  wire I79;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire O20;
  wire O21;
  wire O22;
  wire O23;
  wire O24;
  wire O25;
  wire O26;
  wire O27;
  wire O28;
  wire O29;
  wire O3;
  wire O30;
  wire O31;
  wire O32;
  wire O33;
  wire O34;
  wire O35;
  wire O36;
  wire O37;
  wire O38;
  wire O39;
  wire O4;
  wire O40;
  wire O41;
  wire O42;
  wire O43;
  wire O44;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire [6:0]s_daddr_o;
  wire [12:0]slaveRegDo_6;
  wire [3:0]slaveRegDo_80;
  wire [15:0]slaveRegDo_81;
  wire [12:0]slaveRegDo_82;
  wire [3:0]slaveRegDo_84;

ila_0_xsdbs_v1_0_reg_stat_235 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I19(I19),
        .I2(I2),
        .I20(I20),
        .I21(I21),
        .I22(I22),
        .I23(I23),
        .I24(I24),
        .I25(I25),
        .I26(I26),
        .I27(I27),
        .I28(I28),
        .I29(I29),
        .I3(I3),
        .I30(I30),
        .I31(I31),
        .I32(I32),
        .I33(I33),
        .I34(I34),
        .I35(I35),
        .I36(I36),
        .I37(I37),
        .I38(I38),
        .I39(I39),
        .I4(I4),
        .I40(I40),
        .I41(I41),
        .I42(I42),
        .I43(I43),
        .I44(I44),
        .I45(I45),
        .I46(I46),
        .I47(I47),
        .I48(I48),
        .I49(I49),
        .I5(I5),
        .I50(I50),
        .I51(I51),
        .I52(I52),
        .I53(I53),
        .I54(I54),
        .I55(I55),
        .I56(I56),
        .I57(I57),
        .I58(I58),
        .I59(I59),
        .I6(I6),
        .I60(I60),
        .I61(I61),
        .I62(I62),
        .I63(I63),
        .I64(I64),
        .I65(I65),
        .I66(I66),
        .I67(I67),
        .I68(I68),
        .I69(I69),
        .I7(I7),
        .I70(I70),
        .I71(I71),
        .I72(I72),
        .I73(I73),
        .I74(I74),
        .I75(I75),
        .I76(I76),
        .I77(I77),
        .I78(I78),
        .I79(I79),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O18(O18),
        .O19(O19),
        .O2(O2),
        .O20(O20),
        .O21(O21),
        .O22(O22),
        .O23(O23),
        .O24(O24),
        .O25(O25),
        .O26(O26),
        .O27(O27),
        .O28(O28),
        .O29(O29),
        .O3(O3),
        .O30(O30),
        .O31(O31),
        .O32(O32),
        .O33(O33),
        .O34(O34),
        .O35(O35),
        .O36(O36),
        .O37(O37),
        .O38(O38),
        .O39(O39),
        .O4(O4),
        .O40(O40),
        .O41(O41),
        .O42(O42),
        .O43(O43),
        .O44(O44),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o),
        .slaveRegDo_6(slaveRegDo_6),
        .slaveRegDo_80(slaveRegDo_80),
        .slaveRegDo_81(slaveRegDo_81),
        .slaveRegDo_82(slaveRegDo_82),
        .slaveRegDo_84(slaveRegDo_84));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized10
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    I1,
    I2,
    I3,
    I4,
    I5,
    s_daddr_o,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    E,
    I13);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input [5:0]s_daddr_o;
  input I6;
  input I7;
  input I8;
  input I9;
  input [13:0]I10;
  input I11;
  input I12;
  input [0:0]E;
  input I13;

  wire [0:0]E;
  wire I1;
  wire [13:0]I10;
  wire I11;
  wire I12;
  wire I13;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [5:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_219 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized11
   (O1,
    O2,
    O3,
    O4,
    O5,
    s_daddr_o,
    O12,
    Q,
    E,
    I1);
  output O1;
  output O2;
  output O3;
  output O4;
  output [11:0]O5;
  input [4:0]s_daddr_o;
  input [2:0]O12;
  input [2:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire O1;
  wire [2:0]O12;
  wire O2;
  wire O3;
  wire O4;
  wire [11:0]O5;
  wire [2:0]Q;
  wire [4:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_218 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .O1(O1),
        .O12(O12),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized12
   (O1,
    Q,
    s_daddr_o,
    I1,
    E,
    I2);
  output O1;
  output [14:0]Q;
  input [2:0]s_daddr_o;
  input I1;
  input [0:0]E;
  input I2;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire O1;
  wire [14:0]Q;
  wire [2:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_217 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .O1(O1),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized13
   (O1,
    O2,
    O3,
    O4,
    O5,
    O7,
    O8,
    O10,
    O11,
    O12,
    O13,
    O14,
    Q,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    O6,
    I8,
    O9,
    I9,
    I10,
    I11,
    I12,
    I13,
    E,
    I14);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O7;
  output O8;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output [3:0]Q;
  input [4:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input O6;
  input I8;
  input O9;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input [0:0]E;
  input I14;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [3:0]Q;
  wire [4:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_216 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized14
   (O1,
    O2,
    O3,
    O4,
    O5,
    Q,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    E,
    I14);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output [10:0]Q;
  input [5:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input [0:0]E;
  input I14;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire [10:0]Q;
  wire [5:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_215 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized15
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    Q,
    s_daddr_o,
    I1,
    slaveRegDo_18,
    slaveRegDo_80,
    E,
    I2);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output [4:0]O12;
  input [9:0]Q;
  input [3:0]s_daddr_o;
  input [0:0]I1;
  input [8:0]slaveRegDo_18;
  input [8:0]slaveRegDo_80;
  input [0:0]E;
  input I2;

  wire [0:0]E;
  wire [0:0]I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire [4:0]O12;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [9:0]Q;
  wire [3:0]s_daddr_o;
  wire [8:0]slaveRegDo_18;
  wire [8:0]slaveRegDo_80;

ila_0_xsdbs_v1_0_reg_stat_245 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o),
        .slaveRegDo_18(slaveRegDo_18),
        .slaveRegDo_80(slaveRegDo_80));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized16
   (O1,
    D,
    O2,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    s_daddr_o,
    O3,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    Q,
    I24,
    I25,
    I26,
    E,
    I27);
  output O1;
  output [1:0]D;
  output O2;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output [1:0]O14;
  input [3:0]s_daddr_o;
  input [13:0]O3;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input [1:0]I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input I23;
  input [0:0]Q;
  input I24;
  input I25;
  input I26;
  input [0:0]E;
  input I27;

  wire [1:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I3;
  wire I4;
  wire I5;
  wire [1:0]I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire [1:0]O14;
  wire O2;
  wire [13:0]O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [0:0]Q;
  wire [3:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_244 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I19(I19),
        .I2(I2),
        .I20(I20),
        .I21(I21),
        .I22(I22),
        .I23(I23),
        .I24(I24),
        .I25(I25),
        .I26(I26),
        .I27(I27),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized17
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O15,
    O16,
    O17,
    O18,
    O19,
    O20,
    s_daddr_o,
    Q,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    O11,
    O12,
    O13,
    O14,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    E,
    I14);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O15;
  output O16;
  output O17;
  output O18;
  output O19;
  output [0:0]O20;
  input [4:0]s_daddr_o;
  input [14:0]Q;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input O11;
  input O12;
  input O13;
  input O14;
  input [2:0]I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input [0:0]I13;
  input [0:0]E;
  input I14;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire [0:0]I13;
  wire I14;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire [2:0]I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire [0:0]O20;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [14:0]Q;
  wire [4:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_243 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O18(O18),
        .O19(O19),
        .O2(O2),
        .O20(O20),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized18
   (O1,
    O2,
    O3,
    s_daddr_o,
    I1,
    Q,
    I2,
    E,
    I3);
  output O1;
  output O2;
  output [13:0]O3;
  input [1:0]s_daddr_o;
  input I1;
  input [1:0]Q;
  input I2;
  input [0:0]E;
  input I3;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire O1;
  wire O2;
  wire [13:0]O3;
  wire [1:0]Q;
  wire [1:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_242 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .O1(O1),
        .O2(O2),
        .O3(O3),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized19
   (O1,
    O2,
    O3,
    O4,
    O5,
    s_daddr_o,
    Q,
    I1,
    slaveRegDo_84,
    I2,
    E,
    I3);
  output O1;
  output O2;
  output O3;
  output O4;
  output [11:0]O5;
  input [4:0]s_daddr_o;
  input [2:0]Q;
  input I1;
  input [3:0]slaveRegDo_84;
  input [3:0]I2;
  input [0:0]E;
  input I3;

  wire [0:0]E;
  wire I1;
  wire [3:0]I2;
  wire I3;
  wire O1;
  wire O2;
  wire O3;
  wire O4;
  wire [11:0]O5;
  wire [2:0]Q;
  wire [4:0]s_daddr_o;
  wire [3:0]slaveRegDo_84;

ila_0_xsdbs_v1_0_reg_stat_241 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .O1(O1),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .Q(Q),
        .s_daddr_o(s_daddr_o),
        .slaveRegDo_84(slaveRegDo_84));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized2
   (O1,
    O2,
    Q,
    s_daddr_o,
    I1,
    I2,
    E,
    I3);
  output O1;
  output O2;
  output [13:0]Q;
  input [2:0]s_daddr_o;
  input I1;
  input I2;
  input [0:0]E;
  input I3;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire O1;
  wire O2;
  wire [13:0]Q;
  wire [2:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_234 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .O1(O1),
        .O2(O2),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized20
   (O1,
    O2,
    O3,
    use_probe_debug_circuit,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    SR,
    O16,
    O17,
    s_daddr_o,
    I1,
    I2,
    I3,
    Q,
    I4,
    E,
    dwe,
    I5,
    I6,
    s_di_o,
    I7);
  output O1;
  output O2;
  output O3;
  output use_probe_debug_circuit;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output [0:0]SR;
  output O16;
  output O17;
  input [7:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input [12:0]Q;
  input I4;
  input [0:0]E;
  input dwe;
  input I5;
  input I6;
  input [15:0]s_di_o;
  input I7;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [12:0]Q;
  wire [0:0]SR;
  wire dwe;
  wire [7:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire use_probe_debug_circuit;

ila_0_xsdbs_v1_0_reg_ctl_240 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .SR(SR),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o),
        .use_probe_debug_circuit(use_probe_debug_circuit));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized21
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    s_daddr_o,
    Q,
    I1,
    I2,
    I3,
    I4,
    E,
    dwe,
    s_di_o,
    I5);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  input [5:0]s_daddr_o;
  input [0:0]Q;
  input I1;
  input I2;
  input I3;
  input I4;
  input [0:0]E;
  input dwe;
  input [15:0]s_di_o;
  input I5;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [0:0]Q;
  wire dwe;
  wire [5:0]s_daddr_o;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl_239 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized22
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    I1,
    s_daddr_o,
    s_di_o,
    I2);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input I1;
  input [3:0]s_daddr_o;
  input [15:0]s_di_o;
  input I2;

  wire I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [3:0]s_daddr_o;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl_238 \I_EN_CTL_EQ1.U_CTL 
       (.I1(I1),
        .I2(I2),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized23
   (O1,
    O2,
    O3,
    O4,
    O6,
    O7,
    O8,
    O9,
    I1,
    s_daddr_o,
    I2,
    Q,
    I3,
    I4,
    O5,
    I5,
    I6,
    E,
    dwe,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    slaveRegDo_80,
    O12,
    s_di_o,
    I13);
  output O1;
  output O2;
  output O3;
  output O4;
  output [8:0]O6;
  output O7;
  output O8;
  output O9;
  input I1;
  input [12:0]s_daddr_o;
  input I2;
  input [0:0]Q;
  input I3;
  input I4;
  input [2:0]O5;
  input I5;
  input I6;
  input [0:0]E;
  input dwe;
  input I7;
  input I8;
  input I9;
  input [3:0]I10;
  input I11;
  input [1:0]I12;
  input [1:0]slaveRegDo_80;
  input [1:0]O12;
  input [15:0]s_di_o;
  input I13;

  wire [0:0]E;
  wire I1;
  wire [3:0]I10;
  wire I11;
  wire [1:0]I12;
  wire I13;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire [1:0]O12;
  wire O2;
  wire O3;
  wire O4;
  wire [2:0]O5;
  wire [8:0]O6;
  wire O7;
  wire O8;
  wire O9;
  wire [0:0]Q;
  wire dwe;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [1:0]slaveRegDo_80;

ila_0_xsdbs_v1_0_reg_ctl_237 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O12(O12),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o),
        .slaveRegDo_80(slaveRegDo_80));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized24
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    O18,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    dwe,
    E,
    Q,
    s_di_o,
    I8);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  output O18;
  input [12:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input dwe;
  input [0:0]E;
  input [14:0]Q;
  input [15:0]s_di_o;
  input I8;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [14:0]Q;
  wire dwe;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl_236 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O18(O18),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized25
   (O1,
    O2,
    O3,
    O4,
    en_adv_trigger,
    A,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    s_daddr_o,
    Q,
    basic_trigger,
    trig_out_fsm_temp,
    capture_strg_qual,
    capture_fsm_temp,
    I1,
    I2,
    O20,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    s_di_o,
    I20);
  output O1;
  output O2;
  output O3;
  output O4;
  output en_adv_trigger;
  output [1:0]A;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input [5:0]s_daddr_o;
  input [14:0]Q;
  input basic_trigger;
  input trig_out_fsm_temp;
  input capture_strg_qual;
  input capture_fsm_temp;
  input I1;
  input [0:0]I2;
  input [0:0]O20;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input [15:0]s_di_o;
  input I20;

  wire [1:0]A;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire [0:0]I2;
  wire I20;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire [0:0]O20;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [14:0]Q;
  wire basic_trigger;
  wire capture_fsm_temp;
  wire capture_strg_qual;
  wire en_adv_trigger;
  wire [5:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire trig_out_fsm_temp;

ila_0_xsdbs_v1_0_reg_ctl__parameterized1 \I_EN_CTL_EQ1.U_CTL 
       (.A(A),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I19(I19),
        .I2(I2),
        .I20(I20),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O2(O2),
        .O20(O20),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .basic_trigger(basic_trigger),
        .capture_fsm_temp(capture_fsm_temp),
        .capture_strg_qual(capture_strg_qual),
        .en_adv_trigger(en_adv_trigger),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o),
        .trig_out_fsm_temp(trig_out_fsm_temp));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized26
   (slaveRegDo_80,
    s_daddr_o,
    E,
    dwe,
    s_di_o,
    I1);
  output [15:0]slaveRegDo_80;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input [15:0]s_di_o;
  input I1;

  wire [0:0]E;
  wire I1;
  wire dwe;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_80;

ila_0_xsdbs_v1_0_reg_ctl__parameterized2_230 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o),
        .slaveRegDo_80(slaveRegDo_80));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized27
   (slaveRegDo_81,
    s_daddr_o,
    E,
    dwe,
    s_di_o,
    I1);
  output [15:0]slaveRegDo_81;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input [15:0]s_di_o;
  input I1;

  wire [0:0]E;
  wire I1;
  wire dwe;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_81;

ila_0_xsdbs_v1_0_reg_ctl_229 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o),
        .slaveRegDo_81(slaveRegDo_81));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized28
   (O1,
    O2,
    O3,
    s_daddr_o,
    E,
    dwe,
    I1,
    Q,
    s_di_o,
    I2);
  output O1;
  output [13:0]O2;
  output O3;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input [1:0]I1;
  input [1:0]Q;
  input [15:0]s_di_o;
  input I2;

  wire [0:0]E;
  wire [1:0]I1;
  wire I2;
  wire O1;
  wire [13:0]O2;
  wire O3;
  wire [1:0]Q;
  wire dwe;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl__parameterized2 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .O1(O1),
        .O2(O2),
        .O3(O3),
        .Q(Q),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized29
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    O18,
    O19,
    O20,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    E,
    dwe,
    Q,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    s_di_o,
    I22);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  output O18;
  output O19;
  output O20;
  input [12:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input [0:0]E;
  input dwe;
  input [11:0]Q;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input [15:0]s_di_o;
  input I22;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire I20;
  wire I21;
  wire I22;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire O20;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [11:0]Q;
  wire dwe;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl_228 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I19(I19),
        .I2(I2),
        .I20(I20),
        .I21(I21),
        .I22(I22),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O18(O18),
        .O19(O19),
        .O2(O2),
        .O20(O20),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized3
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    D,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    O18,
    O19,
    O20,
    Q,
    I1,
    s_daddr_o,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    slaveRegDo_84,
    I20,
    I21,
    I22,
    I23,
    I24,
    I25,
    I26,
    I27,
    I28,
    I29,
    I30,
    I31,
    I32,
    I33,
    I34,
    I35,
    I36,
    I37,
    E,
    I38);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output [1:0]D;
  output [0:0]O7;
  output [15:0]O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  output O18;
  output O19;
  output O20;
  input [7:0]Q;
  input I1;
  input [5:0]s_daddr_o;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input [0:0]I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input [7:0]slaveRegDo_84;
  input [7:0]I20;
  input I21;
  input I22;
  input I23;
  input I24;
  input I25;
  input I26;
  input I27;
  input I28;
  input I29;
  input I30;
  input I31;
  input I32;
  input [12:0]I33;
  input I34;
  input I35;
  input I36;
  input I37;
  input [0:0]E;
  input I38;

  wire [1:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire [0:0]I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire [7:0]I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I28;
  wire I29;
  wire I3;
  wire I30;
  wire I31;
  wire I32;
  wire [12:0]I33;
  wire I34;
  wire I35;
  wire I36;
  wire I37;
  wire I38;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire O20;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire [0:0]O7;
  wire [15:0]O8;
  wire O9;
  wire [7:0]Q;
  wire [5:0]s_daddr_o;
  wire [7:0]slaveRegDo_84;

ila_0_xsdbs_v1_0_reg_stat_233 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I19(I19),
        .I2(I2),
        .I20(I20),
        .I21(I21),
        .I22(I22),
        .I23(I23),
        .I24(I24),
        .I25(I25),
        .I26(I26),
        .I27(I27),
        .I28(I28),
        .I29(I29),
        .I3(I3),
        .I30(I30),
        .I31(I31),
        .I32(I32),
        .I33(I33),
        .I34(I34),
        .I35(I35),
        .I36(I36),
        .I37(I37),
        .I38(I38),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O18(O18),
        .O19(O19),
        .O2(O2),
        .O20(O20),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o),
        .slaveRegDo_84(slaveRegDo_84));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized30
   (slaveRegDo_84,
    s_daddr_o,
    E,
    dwe,
    s_di_o,
    I1);
  output [15:0]slaveRegDo_84;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input [15:0]s_di_o;
  input I1;

  wire [0:0]E;
  wire I1;
  wire dwe;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_84;

ila_0_xsdbs_v1_0_reg_ctl_227 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o),
        .slaveRegDo_84(slaveRegDo_84));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized31
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    I1,
    s_daddr_o,
    dwe,
    E,
    s_di_o,
    I2);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input I1;
  input [6:0]s_daddr_o;
  input dwe;
  input [0:0]E;
  input [15:0]s_di_o;
  input I2;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire dwe;
  wire [6:0]s_daddr_o;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl_226 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized35
   (O1,
    O2,
    Q,
    O3,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    E,
    I5);
  output O1;
  output O2;
  output [15:0]Q;
  output O3;
  input [3:0]s_daddr_o;
  input I1;
  input I2;
  input [2:0]I3;
  input I4;
  input [0:0]E;
  input I5;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire [2:0]I3;
  wire I4;
  wire I5;
  wire O1;
  wire O2;
  wire O3;
  wire [15:0]Q;
  wire [3:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_255 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .O1(O1),
        .O2(O2),
        .O3(O3),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized38
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_254 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized40
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_253 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized44
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_252 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized46
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_251 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized48
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    s_daddr_o,
    Q,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    E,
    I19);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input [1:0]s_daddr_o;
  input [15:0]Q;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input [0:0]I17;
  input [0:0]I18;
  input [0:0]E;
  input I19;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire [0:0]I17;
  wire [0:0]I18;
  wire I19;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire [1:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_250 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I19(I19),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized5
   (O1,
    O2,
    s_daddr_o,
    E,
    dwe,
    I1,
    I2,
    I3,
    I4,
    I5,
    Q,
    slaveRegDo_82,
    s_di_o,
    I6);
  output O1;
  output [14:0]O2;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input [0:0]Q;
  input [0:0]slaveRegDo_82;
  input [15:0]s_di_o;
  input I6;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire O1;
  wire [14:0]O2;
  wire [0:0]Q;
  wire dwe;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [0:0]slaveRegDo_82;

ila_0_xsdbs_v1_0_reg_ctl_232 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .O1(O1),
        .O2(O2),
        .Q(Q),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o),
        .slaveRegDo_82(slaveRegDo_82));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized50
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_249 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized52
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_248 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized54
   (D,
    O1,
    O2,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    I24,
    I25,
    I26,
    s_daddr_o,
    I27,
    I28,
    I29,
    I30,
    I31,
    I32,
    I33,
    I34,
    I35,
    I36,
    I37,
    I38,
    I39,
    I40,
    I41,
    I42,
    I43,
    I44,
    I45,
    I46,
    I47,
    I48,
    I49,
    I50,
    I51,
    I52,
    I53,
    I54,
    I55,
    I56,
    I57,
    I58,
    I59,
    I60,
    I61,
    I62,
    I63,
    I64,
    I65,
    I66,
    I67,
    I68,
    I69,
    I70,
    I71,
    I72,
    I73,
    I74,
    I75,
    I76,
    I77,
    I78,
    I79,
    I80,
    I81,
    I82,
    I83,
    I84,
    I85,
    I86,
    Q,
    I87,
    I88,
    E,
    I89);
  output [5:0]D;
  output [14:0]O1;
  output O2;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input I23;
  input I24;
  input I25;
  input I26;
  input [4:0]s_daddr_o;
  input I27;
  input I28;
  input I29;
  input I30;
  input I31;
  input I32;
  input I33;
  input I34;
  input I35;
  input I36;
  input I37;
  input I38;
  input I39;
  input I40;
  input I41;
  input I42;
  input I43;
  input I44;
  input I45;
  input I46;
  input I47;
  input I48;
  input I49;
  input I50;
  input I51;
  input I52;
  input I53;
  input I54;
  input I55;
  input I56;
  input I57;
  input I58;
  input I59;
  input I60;
  input I61;
  input I62;
  input I63;
  input I64;
  input I65;
  input I66;
  input I67;
  input I68;
  input I69;
  input I70;
  input I71;
  input I72;
  input I73;
  input I74;
  input I75;
  input I76;
  input I77;
  input I78;
  input I79;
  input I80;
  input I81;
  input I82;
  input I83;
  input I84;
  input I85;
  input I86;
  input [15:0]Q;
  input [15:0]I87;
  input I88;
  input [0:0]E;
  input I89;

  wire [5:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I28;
  wire I29;
  wire I3;
  wire I30;
  wire I31;
  wire I32;
  wire I33;
  wire I34;
  wire I35;
  wire I36;
  wire I37;
  wire I38;
  wire I39;
  wire I4;
  wire I40;
  wire I41;
  wire I42;
  wire I43;
  wire I44;
  wire I45;
  wire I46;
  wire I47;
  wire I48;
  wire I49;
  wire I5;
  wire I50;
  wire I51;
  wire I52;
  wire I53;
  wire I54;
  wire I55;
  wire I56;
  wire I57;
  wire I58;
  wire I59;
  wire I6;
  wire I60;
  wire I61;
  wire I62;
  wire I63;
  wire I64;
  wire I65;
  wire I66;
  wire I67;
  wire I68;
  wire I69;
  wire I7;
  wire I70;
  wire I71;
  wire I72;
  wire I73;
  wire I74;
  wire I75;
  wire I76;
  wire I77;
  wire I78;
  wire I79;
  wire I8;
  wire I80;
  wire I81;
  wire I82;
  wire I83;
  wire I84;
  wire I85;
  wire I86;
  wire [15:0]I87;
  wire I88;
  wire I89;
  wire I9;
  wire [14:0]O1;
  wire O2;
  wire [15:0]Q;
  wire [4:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_258 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I19(I19),
        .I2(I2),
        .I20(I20),
        .I21(I21),
        .I22(I22),
        .I23(I23),
        .I24(I24),
        .I25(I25),
        .I26(I26),
        .I27(I27),
        .I28(I28),
        .I29(I29),
        .I3(I3),
        .I30(I30),
        .I31(I31),
        .I32(I32),
        .I33(I33),
        .I34(I34),
        .I35(I35),
        .I36(I36),
        .I37(I37),
        .I38(I38),
        .I39(I39),
        .I4(I4),
        .I40(I40),
        .I41(I41),
        .I42(I42),
        .I43(I43),
        .I44(I44),
        .I45(I45),
        .I46(I46),
        .I47(I47),
        .I48(I48),
        .I49(I49),
        .I5(I5),
        .I50(I50),
        .I51(I51),
        .I52(I52),
        .I53(I53),
        .I54(I54),
        .I55(I55),
        .I56(I56),
        .I57(I57),
        .I58(I58),
        .I59(I59),
        .I6(I6),
        .I60(I60),
        .I61(I61),
        .I62(I62),
        .I63(I63),
        .I64(I64),
        .I65(I65),
        .I66(I66),
        .I67(I67),
        .I68(I68),
        .I69(I69),
        .I7(I7),
        .I70(I70),
        .I71(I71),
        .I72(I72),
        .I73(I73),
        .I74(I74),
        .I75(I75),
        .I76(I76),
        .I77(I77),
        .I78(I78),
        .I79(I79),
        .I8(I8),
        .I80(I80),
        .I81(I81),
        .I82(I82),
        .I83(I83),
        .I84(I84),
        .I85(I85),
        .I86(I86),
        .I87(I87),
        .I88(I88),
        .I89(I89),
        .I9(I9),
        .O1(O1),
        .O2(O2),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized56
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    s_daddr_o,
    Q,
    I1,
    E,
    I2);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input [1:0]s_daddr_o;
  input [15:0]Q;
  input [15:0]I1;
  input [0:0]E;
  input I2;

  wire [0:0]E;
  wire [15:0]I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire [1:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_257 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized58
   (O1,
    O2,
    O3,
    s_daddr_o,
    Q,
    E,
    I1);
  output O1;
  output O2;
  output [13:0]O3;
  input [3:0]s_daddr_o;
  input [1:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire O1;
  wire O2;
  wire [13:0]O3;
  wire [1:0]Q;
  wire [3:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_256 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .O1(O1),
        .O2(O2),
        .O3(O3),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized59
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    D,
    O16,
    O17,
    O18,
    O19,
    O20,
    O21,
    O22,
    O23,
    O24,
    O25,
    O26,
    O27,
    O28,
    O29,
    O30,
    O31,
    O32,
    s_daddr_o,
    Q,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    E,
    I24);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output [15:0]D;
  output O16;
  output O17;
  output O18;
  output O19;
  output O20;
  output O21;
  output [0:0]O22;
  output O23;
  output O24;
  output O25;
  output O26;
  output O27;
  output O28;
  output O29;
  output O30;
  output O31;
  output O32;
  input [4:0]s_daddr_o;
  input [14:0]Q;
  input I1;
  input [15:0]I2;
  input I3;
  input I4;
  input [15:0]I5;
  input [15:0]I6;
  input [15:0]I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input I23;
  input [0:0]E;
  input I24;

  wire [15:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire [15:0]I2;
  wire I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I3;
  wire I4;
  wire [15:0]I5;
  wire [15:0]I6;
  wire [15:0]I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire O20;
  wire O21;
  wire [0:0]O22;
  wire O23;
  wire O24;
  wire O25;
  wire O26;
  wire O27;
  wire O28;
  wire O29;
  wire O3;
  wire O30;
  wire O31;
  wire O32;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [14:0]Q;
  wire [4:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_225 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I19(I19),
        .I2(I2),
        .I20(I20),
        .I21(I21),
        .I22(I22),
        .I23(I23),
        .I24(I24),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O18(O18),
        .O19(O19),
        .O2(O2),
        .O20(O20),
        .O21(O21),
        .O22(O22),
        .O23(O23),
        .O24(O24),
        .O25(O25),
        .O26(O26),
        .O27(O27),
        .O28(O28),
        .O29(O29),
        .O3(O3),
        .O30(O30),
        .O31(O31),
        .O32(O32),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized6
   (O1,
    O2,
    arm_ctrl,
    O3,
    halt_ctrl,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    I1,
    I2,
    E,
    dwe,
    I3,
    s_daddr_o,
    I4,
    I5,
    Q,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    s_di_o,
    I16);
  output O1;
  output O2;
  output arm_ctrl;
  output O3;
  output halt_ctrl;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  input I1;
  input I2;
  input [0:0]E;
  input dwe;
  input I3;
  input [2:0]s_daddr_o;
  input I4;
  input I5;
  input [10:0]Q;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input [15:0]s_di_o;
  input I16;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [10:0]Q;
  wire arm_ctrl;
  wire dwe;
  wire halt_ctrl;
  wire [2:0]s_daddr_o;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl__parameterized0 \I_EN_CTL_EQ1.U_CTL 
       (.E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O17(O17),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9),
        .Q(Q),
        .arm_ctrl(arm_ctrl),
        .dwe(dwe),
        .halt_ctrl(halt_ctrl),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized60
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_259 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized65
   (Q,
    E,
    I1,
    I7);
  output [15:0]Q;
  input [0:0]E;
  input I1;
  input [1:0]I7;

  wire [0:0]E;
  wire I1;
  wire [1:0]I7;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_224 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I7(I7),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized66
   (Q,
    E,
    I8,
    I1);
  output [3:0]Q;
  input [0:0]E;
  input [3:0]I8;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [3:0]I8;
  wire [3:0]Q;

ila_0_xsdbs_v1_0_reg_stat_222 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I8(I8),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized67
   (O1,
    O2,
    O3,
    O4,
    O5,
    Q,
    s_daddr_o,
    I1,
    I2,
    E,
    I9,
    I3);
  output O1;
  output O2;
  output O3;
  output O4;
  output [11:0]O5;
  input [3:0]Q;
  input [1:0]s_daddr_o;
  input [3:0]I1;
  input [3:0]I2;
  input [0:0]E;
  input [15:0]I9;
  input I3;

  wire [0:0]E;
  wire [3:0]I1;
  wire [3:0]I2;
  wire I3;
  wire [15:0]I9;
  wire O1;
  wire O2;
  wire O3;
  wire O4;
  wire [11:0]O5;
  wire [3:0]Q;
  wire [1:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_223 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I9(I9),
        .O1(O1),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized7
   (Q,
    E,
    I5,
    I1);
  output [3:0]Q;
  input [0:0]E;
  input [3:0]I5;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [3:0]I5;
  wire [3:0]Q;

ila_0_xsdbs_v1_0_reg_stat_231 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I5(I5),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized8
   (O1,
    Q,
    s_daddr_o,
    I1,
    I2,
    E,
    I3,
    I6);
  output O1;
  output [14:0]Q;
  input [2:0]s_daddr_o;
  input I1;
  input I2;
  input [0:0]E;
  input I3;
  input [9:0]I6;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire [9:0]I6;
  wire O1;
  wire [14:0]Q;
  wire [2:0]s_daddr_o;

ila_0_xsdbs_v1_0_reg_stat_221 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I6(I6),
        .O1(O1),
        .Q(Q),
        .s_daddr_o(s_daddr_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg" *) 
module ila_0_xsdbs_v1_0_reg__parameterized9
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat_220 \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .Q(Q));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl
   (debug_data_in,
    dwe,
    I1,
    s_daddr_o,
    s_di_o,
    I2);
  output [15:0]debug_data_in;
  input dwe;
  input I1;
  input [1:0]s_daddr_o;
  input [15:0]s_di_o;
  input I2;

  wire I1;
  wire I2;
  wire [15:0]debug_data_in;
  wire dwe;
  wire \n_0_xsdb_reg[15]_i_1__7 ;
  wire [1:0]s_daddr_o;
  wire [15:0]s_di_o;

LUT4 #(
    .INIT(16'h0020)) 
     \xsdb_reg[15]_i_1__7 
       (.I0(dwe),
        .I1(I1),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .O(\n_0_xsdb_reg[15]_i_1__7 ));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[0]),
        .Q(debug_data_in[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[10]),
        .Q(debug_data_in[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[11]),
        .Q(debug_data_in[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[12]),
        .Q(debug_data_in[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[13]),
        .Q(debug_data_in[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[14]),
        .Q(debug_data_in[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[15]),
        .Q(debug_data_in[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[1]),
        .Q(debug_data_in[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[2]),
        .Q(debug_data_in[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[3]),
        .Q(debug_data_in[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[4]),
        .Q(debug_data_in[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[5]),
        .Q(debug_data_in[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[6]),
        .Q(debug_data_in[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[7]),
        .Q(debug_data_in[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[8]),
        .Q(debug_data_in[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__7 ),
        .D(s_di_o[9]),
        .Q(debug_data_in[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_226
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    I1,
    s_daddr_o,
    dwe,
    E,
    s_di_o,
    I2);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input I1;
  input [6:0]s_daddr_o;
  input dwe;
  input [0:0]E;
  input [15:0]s_di_o;
  input I2;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire dwe;
  wire \n_0_xsdb_reg[15]_i_1__0 ;
  wire \n_0_xsdb_reg[15]_i_2 ;
  wire [6:0]s_daddr_o;
  wire [15:0]s_di_o;

LUT5 #(
    .INIT(32'h00000008)) 
     \xsdb_reg[15]_i_1__0 
       (.I0(I1),
        .I1(\n_0_xsdb_reg[15]_i_2 ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[6]),
        .O(\n_0_xsdb_reg[15]_i_1__0 ));
LUT6 #(
    .INIT(64'h0400000000000000)) 
     \xsdb_reg[15]_i_2 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(dwe),
        .I5(E),
        .O(\n_0_xsdb_reg[15]_i_2 ));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[0]),
        .Q(O16),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[10]),
        .Q(O6),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[11]),
        .Q(O5),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[12]),
        .Q(O4),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[13]),
        .Q(O3),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[14]),
        .Q(O2),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[15]),
        .Q(O1),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[1]),
        .Q(O15),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[2]),
        .Q(O14),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[3]),
        .Q(O13),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[4]),
        .Q(O12),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[5]),
        .Q(O11),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[6]),
        .Q(O10),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[7]),
        .Q(O9),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[8]),
        .Q(O8),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__0 ),
        .D(s_di_o[9]),
        .Q(O7),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_227
   (slaveRegDo_84,
    s_daddr_o,
    E,
    dwe,
    s_di_o,
    I1);
  output [15:0]slaveRegDo_84;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input [15:0]s_di_o;
  input I1;

  wire [0:0]E;
  wire I1;
  wire dwe;
  wire \n_0_xsdb_reg[15]_i_1__15 ;
  wire \n_0_xsdb_reg[15]_i_2__11 ;
  wire \n_0_xsdb_reg[15]_i_3__7 ;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_84;

LUT5 #(
    .INIT(32'h04000000)) 
     \xsdb_reg[15]_i_1__15 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[0]),
        .I3(\n_0_xsdb_reg[15]_i_2__11 ),
        .I4(\n_0_xsdb_reg[15]_i_3__7 ),
        .O(\n_0_xsdb_reg[15]_i_1__15 ));
LUT6 #(
    .INIT(64'h0000000000000010)) 
     \xsdb_reg[15]_i_2__11 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_xsdb_reg[15]_i_2__11 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \xsdb_reg[15]_i_3__7 
       (.I0(s_daddr_o[10]),
        .I1(s_daddr_o[9]),
        .I2(E),
        .I3(dwe),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[12]),
        .O(\n_0_xsdb_reg[15]_i_3__7 ));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_84[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[10]),
        .Q(slaveRegDo_84[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[11]),
        .Q(slaveRegDo_84[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[12]),
        .Q(slaveRegDo_84[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[13]),
        .Q(slaveRegDo_84[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[14]),
        .Q(slaveRegDo_84[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[15]),
        .Q(slaveRegDo_84[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[1]),
        .Q(slaveRegDo_84[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_84[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[3]),
        .Q(slaveRegDo_84[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[4]),
        .Q(slaveRegDo_84[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[5]),
        .Q(slaveRegDo_84[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[6]),
        .Q(slaveRegDo_84[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[7]),
        .Q(slaveRegDo_84[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[8]),
        .Q(slaveRegDo_84[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__15 ),
        .D(s_di_o[9]),
        .Q(slaveRegDo_84[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_228
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    O18,
    O19,
    O20,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    E,
    dwe,
    Q,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    s_di_o,
    I22);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  output O18;
  output O19;
  output O20;
  input [12:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input [0:0]E;
  input dwe;
  input [11:0]Q;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input [15:0]s_di_o;
  input I22;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire I20;
  wire I21;
  wire I22;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire O20;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [11:0]Q;
  wire dwe;
  wire \n_0_slaveRegDo_mux_0[12]_i_9 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_10 ;
  wire \n_0_slaveRegDo_mux_0[1]_i_8 ;
  wire \n_0_slaveRegDo_mux_0[2]_i_8 ;
  wire \n_0_slaveRegDo_mux_0[3]_i_9 ;
  wire \n_0_slaveRegDo_mux_0[4]_i_14 ;
  wire \n_0_slaveRegDo_mux_0[6]_i_14 ;
  wire \n_0_slaveRegDo_mux_0[8]_i_14 ;
  wire \n_0_slaveRegDo_mux_0[9]_i_14 ;
  wire \n_0_xsdb_reg[15]_i_1__4 ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;

LUT6 #(
    .INIT(64'h0000000155555555)) 
     \slaveRegDo_mux_0[12]_i_3 
       (.I0(O2),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[2]),
        .I4(\n_0_slaveRegDo_mux_0[12]_i_9 ),
        .I5(I2),
        .O(O3));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[12]_i_9 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(s_daddr_o[7]),
        .I2(Q[8]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I18),
        .O(\n_0_slaveRegDo_mux_0[12]_i_9 ));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[13]_i_13 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(s_daddr_o[7]),
        .I2(Q[9]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I19),
        .O(O15));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[14]_i_13 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(s_daddr_o[7]),
        .I2(Q[10]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I20),
        .O(O16));
LUT6 #(
    .INIT(64'hFFFFFFFF000000B8)) 
     \slaveRegDo_mux_0[15]_i_10 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(s_daddr_o[7]),
        .I2(Q[11]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I21),
        .O(\n_0_slaveRegDo_mux_0[15]_i_10 ));
LUT6 #(
    .INIT(64'h0000000455555555)) 
     \slaveRegDo_mux_0[15]_i_3 
       (.I0(O2),
        .I1(\n_0_slaveRegDo_mux_0[15]_i_10 ),
        .I2(s_daddr_o[6]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[2]),
        .I5(I1),
        .O(O1));
LUT6 #(
    .INIT(64'h0000000155555555)) 
     \slaveRegDo_mux_0[1]_i_3 
       (.I0(O2),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[2]),
        .I4(\n_0_slaveRegDo_mux_0[1]_i_8 ),
        .I5(I9),
        .O(O10));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[1]_i_8 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(s_daddr_o[7]),
        .I2(Q[0]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I10),
        .O(\n_0_slaveRegDo_mux_0[1]_i_8 ));
LUT6 #(
    .INIT(64'h0000000155555555)) 
     \slaveRegDo_mux_0[2]_i_3 
       (.I0(O2),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[2]),
        .I4(\n_0_slaveRegDo_mux_0[2]_i_8 ),
        .I5(I8),
        .O(O9));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[2]_i_8 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(s_daddr_o[7]),
        .I2(Q[1]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I11),
        .O(\n_0_slaveRegDo_mux_0[2]_i_8 ));
LUT6 #(
    .INIT(64'h0000000155555555)) 
     \slaveRegDo_mux_0[3]_i_3 
       (.I0(O2),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[2]),
        .I4(\n_0_slaveRegDo_mux_0[3]_i_9 ),
        .I5(I7),
        .O(O8));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[3]_i_9 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(s_daddr_o[7]),
        .I2(Q[2]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I12),
        .O(\n_0_slaveRegDo_mux_0[3]_i_9 ));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[4]_i_14 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(s_daddr_o[7]),
        .I2(Q[3]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I13),
        .O(\n_0_slaveRegDo_mux_0[4]_i_14 ));
LUT6 #(
    .INIT(64'h0000000155555555)) 
     \slaveRegDo_mux_0[4]_i_5 
       (.I0(O2),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[2]),
        .I4(\n_0_slaveRegDo_mux_0[4]_i_14 ),
        .I5(I6),
        .O(O7));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[5]_i_13 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(s_daddr_o[7]),
        .I2(Q[4]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I14),
        .O(O14));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[6]_i_14 
       (.I0(\n_0_xsdb_reg_reg[6] ),
        .I1(s_daddr_o[7]),
        .I2(Q[5]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I15),
        .O(\n_0_slaveRegDo_mux_0[6]_i_14 ));
LUT6 #(
    .INIT(64'h0000000155555555)) 
     \slaveRegDo_mux_0[6]_i_5 
       (.I0(O2),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[2]),
        .I4(\n_0_slaveRegDo_mux_0[6]_i_14 ),
        .I5(I5),
        .O(O6));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[8]_i_14 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(s_daddr_o[7]),
        .I2(Q[6]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I16),
        .O(\n_0_slaveRegDo_mux_0[8]_i_14 ));
LUT6 #(
    .INIT(64'h0000000155555555)) 
     \slaveRegDo_mux_0[8]_i_5 
       (.I0(O2),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[2]),
        .I4(\n_0_slaveRegDo_mux_0[8]_i_14 ),
        .I5(I4),
        .O(O5));
LUT6 #(
    .INIT(64'h00000000FFFFFF47)) 
     \slaveRegDo_mux_0[9]_i_14 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(s_daddr_o[7]),
        .I2(Q[7]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I17),
        .O(\n_0_slaveRegDo_mux_0[9]_i_14 ));
LUT6 #(
    .INIT(64'h0000000155555555)) 
     \slaveRegDo_mux_0[9]_i_5 
       (.I0(O2),
        .I1(s_daddr_o[6]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[2]),
        .I4(\n_0_slaveRegDo_mux_0[9]_i_14 ),
        .I5(I3),
        .O(O4));
LUT6 #(
    .INIT(64'h0200000000000000)) 
     \xsdb_reg[15]_i_1__4 
       (.I0(O12),
        .I1(O2),
        .I2(O13),
        .I3(E),
        .I4(dwe),
        .I5(O11),
        .O(\n_0_xsdb_reg[15]_i_1__4 ));
LUT6 #(
    .INIT(64'h0000000100000000)) 
     \xsdb_reg[15]_i_2__2 
       (.I0(s_daddr_o[12]),
        .I1(s_daddr_o[11]),
        .I2(s_daddr_o[10]),
        .I3(s_daddr_o[9]),
        .I4(s_daddr_o[8]),
        .I5(s_daddr_o[7]),
        .O(O12));
LUT2 #(
    .INIT(4'h7)) 
     \xsdb_reg[15]_i_3 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .O(O2));
LUT2 #(
    .INIT(4'hE)) 
     \xsdb_reg[15]_i_3__0 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[3]),
        .O(O13));
LUT3 #(
    .INIT(8'h01)) 
     \xsdb_reg[15]_i_5 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[5]),
        .I2(s_daddr_o[6]),
        .O(O11));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[0]),
        .Q(O20),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[10]),
        .Q(O18),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[11]),
        .Q(O17),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[12]),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[13]),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[14]),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[15]),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[1]),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[2]),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[3]),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[4]),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[5]),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[6]),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[7]),
        .Q(O19),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[8]),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I22),
        .CE(\n_0_xsdb_reg[15]_i_1__4 ),
        .D(s_di_o[9]),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_229
   (slaveRegDo_81,
    s_daddr_o,
    E,
    dwe,
    s_di_o,
    I1);
  output [15:0]slaveRegDo_81;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input [15:0]s_di_o;
  input I1;

  wire [0:0]E;
  wire I1;
  wire dwe;
  wire \n_0_xsdb_reg[15]_i_1__13 ;
  wire \n_0_xsdb_reg[15]_i_2__9 ;
  wire \n_0_xsdb_reg[15]_i_3__5 ;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_81;

LUT5 #(
    .INIT(32'h04000000)) 
     \xsdb_reg[15]_i_1__13 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[2]),
        .I3(\n_0_xsdb_reg[15]_i_2__9 ),
        .I4(\n_0_xsdb_reg[15]_i_3__5 ),
        .O(\n_0_xsdb_reg[15]_i_1__13 ));
LUT6 #(
    .INIT(64'h0000000000000010)) 
     \xsdb_reg[15]_i_2__9 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_xsdb_reg[15]_i_2__9 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \xsdb_reg[15]_i_3__5 
       (.I0(s_daddr_o[10]),
        .I1(s_daddr_o[9]),
        .I2(E),
        .I3(dwe),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[12]),
        .O(\n_0_xsdb_reg[15]_i_3__5 ));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_81[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[10]),
        .Q(slaveRegDo_81[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[11]),
        .Q(slaveRegDo_81[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[12]),
        .Q(slaveRegDo_81[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[13]),
        .Q(slaveRegDo_81[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[14]),
        .Q(slaveRegDo_81[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[15]),
        .Q(slaveRegDo_81[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[1]),
        .Q(slaveRegDo_81[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_81[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[3]),
        .Q(slaveRegDo_81[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[4]),
        .Q(slaveRegDo_81[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[5]),
        .Q(slaveRegDo_81[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[6]),
        .Q(slaveRegDo_81[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[7]),
        .Q(slaveRegDo_81[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[8]),
        .Q(slaveRegDo_81[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__13 ),
        .D(s_di_o[9]),
        .Q(slaveRegDo_81[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_232
   (O1,
    O2,
    s_daddr_o,
    E,
    dwe,
    I1,
    I2,
    I3,
    I4,
    I5,
    Q,
    slaveRegDo_82,
    s_di_o,
    I6);
  output O1;
  output [14:0]O2;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input [0:0]Q;
  input [0:0]slaveRegDo_82;
  input [15:0]s_di_o;
  input I6;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire O1;
  wire [14:0]O2;
  wire [0:0]Q;
  wire dwe;
  wire \n_0_slaveRegDo_mux_0[13]_i_5 ;
  wire \n_0_xsdb_reg[15]_i_1__10 ;
  wire \n_0_xsdb_reg[15]_i_2__6 ;
  wire \n_0_xsdb_reg[15]_i_3__2 ;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [13:13]slaveRegDo_6;
  wire [0:0]slaveRegDo_82;

LUT6 #(
    .INIT(64'hFB00FB000000FB00)) 
     \slaveRegDo_mux_0[13]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[13]_i_5 ),
        .I1(s_daddr_o[1]),
        .I2(I1),
        .I3(I2),
        .I4(I3),
        .I5(I4),
        .O(O1));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[13]_i_5 
       (.I0(I5),
        .I1(slaveRegDo_6),
        .I2(s_daddr_o[7]),
        .I3(Q),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_82),
        .O(\n_0_slaveRegDo_mux_0[13]_i_5 ));
LUT5 #(
    .INIT(32'h20000000)) 
     \xsdb_reg[15]_i_1__10 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\n_0_xsdb_reg[15]_i_2__6 ),
        .I4(\n_0_xsdb_reg[15]_i_3__2 ),
        .O(\n_0_xsdb_reg[15]_i_1__10 ));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \xsdb_reg[15]_i_2__6 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_xsdb_reg[15]_i_2__6 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \xsdb_reg[15]_i_3__2 
       (.I0(s_daddr_o[10]),
        .I1(s_daddr_o[9]),
        .I2(E),
        .I3(dwe),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[12]),
        .O(\n_0_xsdb_reg[15]_i_3__2 ));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[0]),
        .Q(O2[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[10]),
        .Q(O2[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[11]),
        .Q(O2[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[12]),
        .Q(O2[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[13]),
        .Q(slaveRegDo_6),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[14]),
        .Q(O2[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[15]),
        .Q(O2[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[1]),
        .Q(O2[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[2]),
        .Q(O2[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[3]),
        .Q(O2[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[4]),
        .Q(O2[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[5]),
        .Q(O2[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[6]),
        .Q(O2[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[7]),
        .Q(O2[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[8]),
        .Q(O2[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I6),
        .CE(\n_0_xsdb_reg[15]_i_1__10 ),
        .D(s_di_o[9]),
        .Q(O2[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_236
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    O18,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    dwe,
    E,
    Q,
    s_di_o,
    I8);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  output O18;
  input [12:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input dwe;
  input [0:0]E;
  input [14:0]Q;
  input [15:0]s_di_o;
  input I8;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [14:0]Q;
  wire dwe;
  wire \n_0_slaveRegDo_mux_0[11]_i_10 ;
  wire \n_0_slaveRegDo_mux_0[7]_i_9 ;
  wire \n_0_xsdb_reg[15]_i_1__6 ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;

LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[10]_i_19 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[10] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[9]),
        .O(O13));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[11]_i_10 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[11] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[10]),
        .O(\n_0_slaveRegDo_mux_0[11]_i_10 ));
LUT6 #(
    .INIT(64'hFFFFFFFFFF0D0000)) 
     \slaveRegDo_mux_0[11]_i_4 
       (.I0(\n_0_slaveRegDo_mux_0[11]_i_10 ),
        .I1(I1),
        .I2(s_daddr_o[7]),
        .I3(I2),
        .I4(I3),
        .I5(I4),
        .O(O2));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[12]_i_12 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[12] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[11]),
        .O(O14));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[13]_i_11 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[13] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[12]),
        .O(O15));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[14]_i_6 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[14] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[13]),
        .O(O16));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[15]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[15] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[14]),
        .O(O17));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[1]_i_7 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[1] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[0]),
        .O(O5));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[2]_i_7 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[2] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[1]),
        .O(O6));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[3]_i_7 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[3] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[2]),
        .O(O7));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[4]_i_13 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[4] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[3]),
        .O(O8));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[5]_i_11 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[5] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[4]),
        .O(O9));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[6]_i_13 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[6] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[5]),
        .O(O10));
LUT6 #(
    .INIT(64'hFFFFFFFFFF0D0000)) 
     \slaveRegDo_mux_0[7]_i_4 
       (.I0(\n_0_slaveRegDo_mux_0[7]_i_9 ),
        .I1(I5),
        .I2(s_daddr_o[7]),
        .I3(I6),
        .I4(I3),
        .I5(I7),
        .O(O3));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[7]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[7] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[6]),
        .O(\n_0_slaveRegDo_mux_0[7]_i_9 ));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[8]_i_13 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[8] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[7]),
        .O(O11));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[9]_i_13 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[9] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[8]),
        .O(O12));
LUT5 #(
    .INIT(32'h00000800)) 
     \xsdb_reg[15]_i_1__6 
       (.I0(O4),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .O(\n_0_xsdb_reg[15]_i_1__6 ));
LUT6 #(
    .INIT(64'h0200000000000000)) 
     \xsdb_reg[15]_i_2__1 
       (.I0(O1),
        .I1(s_daddr_o[5]),
        .I2(s_daddr_o[6]),
        .I3(s_daddr_o[4]),
        .I4(dwe),
        .I5(E),
        .O(O4));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \xsdb_reg[15]_i_2__5 
       (.I0(s_daddr_o[7]),
        .I1(s_daddr_o[9]),
        .I2(s_daddr_o[8]),
        .I3(s_daddr_o[10]),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[12]),
        .O(O1));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[0]),
        .Q(O18),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[10]),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[11]),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[12]),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[13]),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[14]),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[15]),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[1]),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[2]),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[3]),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[4]),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[5]),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[6]),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[7]),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[8]),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I8),
        .CE(\n_0_xsdb_reg[15]_i_1__6 ),
        .D(s_di_o[9]),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_237
   (O1,
    O2,
    O3,
    O4,
    O7,
    O8,
    O9,
    O6,
    I1,
    s_daddr_o,
    I2,
    Q,
    I3,
    I4,
    O5,
    I5,
    I6,
    E,
    dwe,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    slaveRegDo_80,
    O12,
    s_di_o,
    I13);
  output O1;
  output O2;
  output O3;
  output O4;
  output O7;
  output O8;
  output O9;
  output [8:0]O6;
  input I1;
  input [12:0]s_daddr_o;
  input I2;
  input [0:0]Q;
  input I3;
  input I4;
  input [2:0]O5;
  input I5;
  input I6;
  input [0:0]E;
  input dwe;
  input I7;
  input I8;
  input I9;
  input [3:0]I10;
  input I11;
  input [1:0]I12;
  input [1:0]slaveRegDo_80;
  input [1:0]O12;
  input [15:0]s_di_o;
  input I13;

  wire [0:0]E;
  wire I1;
  wire [3:0]I10;
  wire I11;
  wire [1:0]I12;
  wire I13;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire [1:0]O12;
  wire O2;
  wire O3;
  wire O4;
  wire [2:0]O5;
  wire [8:0]O6;
  wire O7;
  wire O8;
  wire O9;
  wire [0:0]Q;
  wire dwe;
  wire \n_0_slaveRegDo_mux_0[0]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[10]_i_15 ;
  wire \n_0_slaveRegDo_mux_0[12]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[1]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[2]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[3]_i_18 ;
  wire \n_0_slaveRegDo_mux_0[6]_i_16 ;
  wire \n_0_xsdb_reg[15]_i_1__11 ;
  wire \n_0_xsdb_reg[15]_i_2__7 ;
  wire \n_0_xsdb_reg[15]_i_3__3 ;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [12:0]slaveRegDo_18;
  wire [1:0]slaveRegDo_80;

LUT6 #(
    .INIT(64'h0002020202020202)) 
     \slaveRegDo_mux_0[0]_i_11 
       (.I0(\n_0_slaveRegDo_mux_0[0]_i_17 ),
        .I1(I3),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[4]),
        .I4(I4),
        .I5(O5[0]),
        .O(O2));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[0]_i_17 
       (.I0(s_daddr_o[2]),
        .I1(slaveRegDo_18[0]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(I10[0]),
        .O(\n_0_slaveRegDo_mux_0[0]_i_17 ));
LUT5 #(
    .INIT(32'h00B00080)) 
     \slaveRegDo_mux_0[10]_i_15 
       (.I0(slaveRegDo_18[10]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[7]),
        .I4(O12[1]),
        .O(\n_0_slaveRegDo_mux_0[10]_i_15 ));
LUT6 #(
    .INIT(64'hABABABBBBBBBABBB)) 
     \slaveRegDo_mux_0[10]_i_7 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_slaveRegDo_mux_0[10]_i_15 ),
        .I2(I11),
        .I3(I12[1]),
        .I4(s_daddr_o[7]),
        .I5(slaveRegDo_80[1]),
        .O(O9));
LUT3 #(
    .INIT(8'h40)) 
     \slaveRegDo_mux_0[12]_i_17 
       (.I0(s_daddr_o[7]),
        .I1(slaveRegDo_18[12]),
        .I2(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_0[12]_i_17 ));
LUT6 #(
    .INIT(64'h0F0F0505000F0303)) 
     \slaveRegDo_mux_0[12]_i_8 
       (.I0(\n_0_slaveRegDo_mux_0[12]_i_17 ),
        .I1(I7),
        .I2(I8),
        .I3(I9),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(O7));
LUT6 #(
    .INIT(64'h0002020202020202)) 
     \slaveRegDo_mux_0[1]_i_11 
       (.I0(\n_0_slaveRegDo_mux_0[1]_i_17 ),
        .I1(I5),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[4]),
        .I4(I4),
        .I5(O5[1]),
        .O(O3));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[1]_i_17 
       (.I0(s_daddr_o[2]),
        .I1(slaveRegDo_18[1]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(I10[1]),
        .O(\n_0_slaveRegDo_mux_0[1]_i_17 ));
LUT6 #(
    .INIT(64'h0200020202020202)) 
     \slaveRegDo_mux_0[2]_i_11 
       (.I0(\n_0_slaveRegDo_mux_0[2]_i_17 ),
        .I1(I1),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[4]),
        .I4(I2),
        .I5(Q),
        .O(O1));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[2]_i_17 
       (.I0(s_daddr_o[2]),
        .I1(slaveRegDo_18[2]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(I10[2]),
        .O(\n_0_slaveRegDo_mux_0[2]_i_17 ));
LUT6 #(
    .INIT(64'h0002020202020202)) 
     \slaveRegDo_mux_0[3]_i_12 
       (.I0(\n_0_slaveRegDo_mux_0[3]_i_18 ),
        .I1(I6),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[4]),
        .I4(I4),
        .I5(O5[2]),
        .O(O4));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[3]_i_18 
       (.I0(s_daddr_o[2]),
        .I1(slaveRegDo_18[3]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(I10[3]),
        .O(\n_0_slaveRegDo_mux_0[3]_i_18 ));
LUT5 #(
    .INIT(32'h00B00080)) 
     \slaveRegDo_mux_0[6]_i_16 
       (.I0(slaveRegDo_18[6]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[7]),
        .I4(O12[0]),
        .O(\n_0_slaveRegDo_mux_0[6]_i_16 ));
LUT6 #(
    .INIT(64'hABABABBBBBBBABBB)) 
     \slaveRegDo_mux_0[6]_i_7 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_slaveRegDo_mux_0[6]_i_16 ),
        .I2(I11),
        .I3(I12[0]),
        .I4(s_daddr_o[7]),
        .I5(slaveRegDo_80[0]),
        .O(O8));
LUT5 #(
    .INIT(32'h01000000)) 
     \xsdb_reg[15]_i_1__11 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[0]),
        .I3(\n_0_xsdb_reg[15]_i_2__7 ),
        .I4(\n_0_xsdb_reg[15]_i_3__3 ),
        .O(\n_0_xsdb_reg[15]_i_1__11 ));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \xsdb_reg[15]_i_2__7 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_xsdb_reg[15]_i_2__7 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \xsdb_reg[15]_i_3__3 
       (.I0(s_daddr_o[10]),
        .I1(s_daddr_o[9]),
        .I2(E),
        .I3(dwe),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[12]),
        .O(\n_0_xsdb_reg[15]_i_3__3 ));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_18[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[10]),
        .Q(slaveRegDo_18[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[11]),
        .Q(O6[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[12]),
        .Q(slaveRegDo_18[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[13]),
        .Q(O6[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[14]),
        .Q(O6[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[15]),
        .Q(O6[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[1]),
        .Q(slaveRegDo_18[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_18[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[3]),
        .Q(slaveRegDo_18[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[4]),
        .Q(O6[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[5]),
        .Q(O6[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[6]),
        .Q(slaveRegDo_18[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[7]),
        .Q(O6[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[8]),
        .Q(O6[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I13),
        .CE(\n_0_xsdb_reg[15]_i_1__11 ),
        .D(s_di_o[9]),
        .Q(O6[4]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_238
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    I1,
    s_daddr_o,
    s_di_o,
    I2);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input I1;
  input [3:0]s_daddr_o;
  input [15:0]s_di_o;
  input I2;

  wire I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire \n_0_xsdb_reg[15]_i_1__2 ;
  wire [3:0]s_daddr_o;
  wire [15:0]s_di_o;

LUT5 #(
    .INIT(32'h20000000)) 
     \xsdb_reg[15]_i_1__2 
       (.I0(I1),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[0]),
        .O(\n_0_xsdb_reg[15]_i_1__2 ));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[0]),
        .Q(O16),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[10]),
        .Q(O6),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[11]),
        .Q(O5),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[12]),
        .Q(O4),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[13]),
        .Q(O3),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[14]),
        .Q(O2),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[15]),
        .Q(O1),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[1]),
        .Q(O15),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[2]),
        .Q(O14),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[3]),
        .Q(O13),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[4]),
        .Q(O12),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[5]),
        .Q(O11),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[6]),
        .Q(O10),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[7]),
        .Q(O9),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[8]),
        .Q(O8),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__2 ),
        .D(s_di_o[9]),
        .Q(O7),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_239
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    s_daddr_o,
    Q,
    I1,
    I2,
    I3,
    I4,
    E,
    dwe,
    s_di_o,
    I5);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  input [5:0]s_daddr_o;
  input [0:0]Q;
  input I1;
  input I2;
  input I3;
  input I4;
  input [0:0]E;
  input dwe;
  input [15:0]s_di_o;
  input I5;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [0:0]Q;
  wire dwe;
  wire \n_0_xsdb_reg[15]_i_1 ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire [5:0]s_daddr_o;
  wire [15:0]s_di_o;

LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[10]_i_16 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q),
        .O(O1));
LUT6 #(
    .INIT(64'h5555100055555555)) 
     \slaveRegDo_mux_0[5]_i_6 
       (.I0(s_daddr_o[5]),
        .I1(I1),
        .I2(s_daddr_o[4]),
        .I3(O3),
        .I4(I2),
        .I5(I3),
        .O(O2));
LUT6 #(
    .INIT(64'h0000000008000000)) 
     \xsdb_reg[15]_i_1 
       (.I0(I4),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(E),
        .I4(dwe),
        .I5(I1),
        .O(\n_0_xsdb_reg[15]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[0]),
        .Q(O17),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[10]),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[11]),
        .Q(O8),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[12]),
        .Q(O7),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[13]),
        .Q(O6),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[14]),
        .Q(O5),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[15]),
        .Q(O4),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[1]),
        .Q(O16),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[2]),
        .Q(O15),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[3]),
        .Q(O14),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[4]),
        .Q(O13),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[5]),
        .Q(O3),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[6]),
        .Q(O12),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[7]),
        .Q(O11),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[8]),
        .Q(O10),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I5),
        .CE(\n_0_xsdb_reg[15]_i_1 ),
        .D(s_di_o[9]),
        .Q(O9),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_240
   (O1,
    O2,
    O3,
    use_probe_debug_circuit,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    SR,
    O16,
    O17,
    s_daddr_o,
    I1,
    I2,
    I3,
    Q,
    I4,
    E,
    dwe,
    I5,
    I6,
    s_di_o,
    I7);
  output O1;
  output O2;
  output O3;
  output use_probe_debug_circuit;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output [0:0]SR;
  output O16;
  output O17;
  input [7:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input [12:0]Q;
  input I4;
  input [0:0]E;
  input dwe;
  input I5;
  input I6;
  input [15:0]s_di_o;
  input I7;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [12:0]Q;
  wire [0:0]SR;
  wire dwe;
  wire \n_0_slaveRegDo_mux_0[10]_i_13 ;
  wire \n_0_xsdb_reg[15]_i_1__1 ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [7:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire use_probe_debug_circuit;

LUT6 #(
    .INIT(64'h0044400000004000)) 
     \slaveRegDo_mux_0[0]_i_6 
       (.I0(s_daddr_o[7]),
        .I1(s_daddr_o[2]),
        .I2(SR),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[3]),
        .I5(Q[0]),
        .O(O15));
LUT6 #(
    .INIT(64'h5555100055555555)) 
     \slaveRegDo_mux_0[10]_i_13 
       (.I0(s_daddr_o[7]),
        .I1(I1),
        .I2(s_daddr_o[4]),
        .I3(\n_0_xsdb_reg_reg[10] ),
        .I4(I2),
        .I5(I3),
        .O(\n_0_slaveRegDo_mux_0[10]_i_13 ));
LUT6 #(
    .INIT(64'h0010000000100010)) 
     \slaveRegDo_mux_0[10]_i_5 
       (.I0(s_daddr_o[6]),
        .I1(s_daddr_o[5]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(\n_0_slaveRegDo_mux_0[10]_i_13 ),
        .I5(I4),
        .O(O12));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[11]_i_16 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[10]),
        .O(O10));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[13]_i_18 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[11]),
        .O(O11));
LUT6 #(
    .INIT(64'hFFFFFFFF2C200000)) 
     \slaveRegDo_mux_0[15]_i_8 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[4]),
        .I3(Q[12]),
        .I4(s_daddr_o[2]),
        .I5(I6),
        .O(O14));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[1]_i_14 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[1]),
        .O(O2));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[2]_i_14 
       (.I0(use_probe_debug_circuit),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[2]),
        .O(O3));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[3]_i_15 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[3]),
        .O(O1));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[4]_i_18 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[4]),
        .O(O4));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[5]_i_18 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[5]),
        .O(O5));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[6]_i_18 
       (.I0(\n_0_xsdb_reg_reg[6] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[6]),
        .O(O6));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[7]_i_16 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[7]),
        .O(O7));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[8]_i_18 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[8]),
        .O(O8));
LUT5 #(
    .INIT(32'h38000800)) 
     \slaveRegDo_mux_0[9]_i_18 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(Q[9]),
        .O(O9));
LUT6 #(
    .INIT(64'h0000080000000000)) 
     \xsdb_reg[15]_i_1__1 
       (.I0(E),
        .I1(dwe),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(O13),
        .O(\n_0_xsdb_reg[15]_i_1__1 ));
LUT4 #(
    .INIT(16'h0008)) 
     \xsdb_reg[15]_i_2__0 
       (.I0(I5),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[6]),
        .I3(s_daddr_o[5]),
        .O(O13));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[0]),
        .Q(SR),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[10]),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[11]),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[12]),
        .Q(O17),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[13]),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[14]),
        .Q(O16),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[15]),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[1]),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[2]),
        .Q(use_probe_debug_circuit),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[3]),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[4]),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[5]),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[6]),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[7]),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[8]),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I7),
        .CE(\n_0_xsdb_reg[15]_i_1__1 ),
        .D(s_di_o[9]),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl_261
   (O1,
    O3,
    O5,
    dwe,
    D,
    E,
    I5,
    s_di_o,
    I1);
  output O1;
  output O3;
  output [15:0]O5;
  input dwe;
  input [8:0]D;
  input [0:0]E;
  input I5;
  input [15:0]s_di_o;
  input I1;

  wire [8:0]D;
  wire [0:0]E;
  wire I1;
  wire I5;
  wire O1;
  wire O3;
  wire [15:0]O5;
  wire dwe;
  wire \n_0_xsdb_reg[15]_i_1__8 ;
  wire [15:0]s_di_o;

LUT5 #(
    .INIT(32'h80000000)) 
     \I_EN_CTL_EQ1.temp_en_i_3 
       (.I0(D[5]),
        .I1(D[4]),
        .I2(E),
        .I3(D[6]),
        .I4(I5),
        .O(O3));
LUT4 #(
    .INIT(16'h0002)) 
     \xsdb_reg[15]_i_1__8 
       (.I0(dwe),
        .I1(O1),
        .I2(D[1]),
        .I3(D[0]),
        .O(\n_0_xsdb_reg[15]_i_1__8 ));
LUT5 #(
    .INIT(32'hDFFFFFFF)) 
     \xsdb_reg[15]_i_2__3 
       (.I0(O3),
        .I1(D[8]),
        .I2(D[7]),
        .I3(D[2]),
        .I4(D[3]),
        .O(O1));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[0]),
        .Q(O5[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[10]),
        .Q(O5[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[11]),
        .Q(O5[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[12]),
        .Q(O5[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[13]),
        .Q(O5[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[14]),
        .Q(O5[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[15]),
        .Q(O5[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[1]),
        .Q(O5[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[2]),
        .Q(O5[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[3]),
        .Q(O5[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[4]),
        .Q(O5[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[5]),
        .Q(O5[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[6]),
        .Q(O5[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[7]),
        .Q(O5[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[8]),
        .Q(O5[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__8 ),
        .D(s_di_o[9]),
        .Q(O5[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl__parameterized0
   (O1,
    O2,
    arm_ctrl,
    O3,
    halt_ctrl,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    I1,
    I2,
    E,
    dwe,
    I3,
    s_daddr_o,
    I4,
    I5,
    Q,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    s_di_o,
    I16);
  output O1;
  output O2;
  output arm_ctrl;
  output O3;
  output halt_ctrl;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  input I1;
  input I2;
  input [0:0]E;
  input dwe;
  input I3;
  input [2:0]s_daddr_o;
  input I4;
  input I5;
  input [10:0]Q;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input [15:0]s_di_o;
  input I16;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [10:0]Q;
  wire arm_ctrl;
  wire dwe;
  wire halt_ctrl;
  wire \n_0_xsdb_reg[15]_i_1__3 ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [2:0]s_daddr_o;
  wire [15:0]s_di_o;

LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[0]_i_9 
       (.I0(I4),
        .I1(arm_ctrl),
        .I2(s_daddr_o[2]),
        .I3(I5),
        .I4(s_daddr_o[1]),
        .I5(Q[0]),
        .O(O2));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[10]_i_12 
       (.I0(I4),
        .I1(\n_0_xsdb_reg_reg[10] ),
        .I2(s_daddr_o[2]),
        .I3(I13),
        .I4(s_daddr_o[1]),
        .I5(Q[8]),
        .O(O10));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[12]_i_10 
       (.I0(I4),
        .I1(\n_0_xsdb_reg_reg[12] ),
        .I2(s_daddr_o[2]),
        .I3(I14),
        .I4(s_daddr_o[1]),
        .I5(Q[9]),
        .O(O11));
LUT6 #(
    .INIT(64'hCC1DFF1DFFFFFFFF)) 
     \slaveRegDo_mux_0[15]_i_11 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(s_daddr_o[2]),
        .I2(I15),
        .I3(s_daddr_o[1]),
        .I4(Q[10]),
        .I5(I4),
        .O(O12));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[1]_i_9 
       (.I0(I4),
        .I1(halt_ctrl),
        .I2(s_daddr_o[2]),
        .I3(I6),
        .I4(s_daddr_o[1]),
        .I5(Q[1]),
        .O(O3));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[2]_i_9 
       (.I0(I4),
        .I1(\n_0_xsdb_reg_reg[2] ),
        .I2(s_daddr_o[2]),
        .I3(I7),
        .I4(s_daddr_o[1]),
        .I5(Q[2]),
        .O(O4));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[3]_i_10 
       (.I0(I4),
        .I1(\n_0_xsdb_reg_reg[3] ),
        .I2(s_daddr_o[2]),
        .I3(I8),
        .I4(s_daddr_o[1]),
        .I5(Q[3]),
        .O(O5));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[4]_i_15 
       (.I0(I4),
        .I1(\n_0_xsdb_reg_reg[4] ),
        .I2(s_daddr_o[2]),
        .I3(I9),
        .I4(s_daddr_o[1]),
        .I5(Q[4]),
        .O(O6));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[6]_i_15 
       (.I0(I4),
        .I1(\n_0_xsdb_reg_reg[6] ),
        .I2(s_daddr_o[2]),
        .I3(I10),
        .I4(s_daddr_o[1]),
        .I5(Q[5]),
        .O(O7));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[8]_i_15 
       (.I0(I4),
        .I1(\n_0_xsdb_reg_reg[8] ),
        .I2(s_daddr_o[2]),
        .I3(I11),
        .I4(s_daddr_o[1]),
        .I5(Q[6]),
        .O(O8));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[9]_i_15 
       (.I0(I4),
        .I1(\n_0_xsdb_reg_reg[9] ),
        .I2(s_daddr_o[2]),
        .I3(I12),
        .I4(s_daddr_o[1]),
        .I5(Q[7]),
        .O(O9));
LUT6 #(
    .INIT(64'h0200000000000000)) 
     \xsdb_reg[15]_i_1__3 
       (.I0(I1),
        .I1(I2),
        .I2(O1),
        .I3(E),
        .I4(dwe),
        .I5(I3),
        .O(\n_0_xsdb_reg[15]_i_1__3 ));
LUT2 #(
    .INIT(4'hB)) 
     \xsdb_reg[15]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .O(O1));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[0] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[0]),
        .Q(arm_ctrl),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[10]),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[11]),
        .Q(O15),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[12]),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[13]),
        .Q(O14),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[14]),
        .Q(O13),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[15]),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[1]),
        .Q(halt_ctrl),
        .R(1'b0));
FDRE #(
    .INIT(1'b1)) 
     \xsdb_reg_reg[2] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[2]),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b1)) 
     \xsdb_reg_reg[3] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[3]),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[4]),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[5]),
        .Q(O17),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[6]),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[7]),
        .Q(O16),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[8]),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I16),
        .CE(\n_0_xsdb_reg[15]_i_1__3 ),
        .D(s_di_o[9]),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl__parameterized1
   (O1,
    O2,
    O3,
    O4,
    en_adv_trigger,
    A,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    s_daddr_o,
    Q,
    basic_trigger,
    trig_out_fsm_temp,
    capture_strg_qual,
    capture_fsm_temp,
    I1,
    I2,
    O20,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    s_di_o,
    I20);
  output O1;
  output O2;
  output O3;
  output O4;
  output en_adv_trigger;
  output [1:0]A;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input [5:0]s_daddr_o;
  input [14:0]Q;
  input basic_trigger;
  input trig_out_fsm_temp;
  input capture_strg_qual;
  input capture_fsm_temp;
  input I1;
  input [0:0]I2;
  input [0:0]O20;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input [15:0]s_di_o;
  input I20;

  wire [1:0]A;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire [0:0]I2;
  wire I20;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire [0:0]O20;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [14:0]Q;
  wire basic_trigger;
  wire capture_fsm_temp;
  wire [1:0]capture_qual_ctrl;
  wire capture_strg_qual;
  wire en_adv_trigger;
  wire \n_0_slaveRegDo_mux_0[10]_i_8 ;
  wire \n_0_slaveRegDo_mux_0[11]_i_7 ;
  wire \n_0_slaveRegDo_mux_0[12]_i_15 ;
  wire \n_0_slaveRegDo_mux_0[4]_i_8 ;
  wire \n_0_slaveRegDo_mux_0[6]_i_8 ;
  wire \n_0_slaveRegDo_mux_0[7]_i_14 ;
  wire \n_0_slaveRegDo_mux_0[7]_i_7 ;
  wire \n_0_slaveRegDo_mux_0[8]_i_8 ;
  wire \n_0_slaveRegDo_mux_0[9]_i_8 ;
  wire \n_0_xsdb_reg[15]_i_1__5 ;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [5:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire trig_out_fsm_temp;

LUT4 #(
    .INIT(16'hFDAD)) 
     \I_YESLUT6.U_SRL32_D_i_2 
       (.I0(capture_qual_ctrl[0]),
        .I1(capture_strg_qual),
        .I2(capture_qual_ctrl[1]),
        .I3(capture_fsm_temp),
        .O(A[1]));
LUT3 #(
    .INIT(8'hE2)) 
     \I_YESLUT6.U_SRL32_D_i_3 
       (.I0(basic_trigger),
        .I1(en_adv_trigger),
        .I2(trig_out_fsm_temp),
        .O(A[0]));
LUT5 #(
    .INIT(32'h45004000)) 
     \slaveRegDo_mux_0[0]_i_12 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[0] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[0]),
        .O(O1));
LUT5 #(
    .INIT(32'hFFFF0DFF)) 
     \slaveRegDo_mux_0[10]_i_3 
       (.I0(\n_0_slaveRegDo_mux_0[10]_i_8 ),
        .I1(I6),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[1]),
        .I4(I7),
        .O(O7));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[10]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[10] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[10]),
        .O(\n_0_slaveRegDo_mux_0[10]_i_8 ));
LUT5 #(
    .INIT(32'hFFFF0DFF)) 
     \slaveRegDo_mux_0[11]_i_3 
       (.I0(\n_0_slaveRegDo_mux_0[11]_i_7 ),
        .I1(I4),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[1]),
        .I4(I5),
        .O(O6));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[11]_i_7 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[11] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[11]),
        .O(\n_0_slaveRegDo_mux_0[11]_i_7 ));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[12]_i_15 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[12] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[12]),
        .O(\n_0_slaveRegDo_mux_0[12]_i_15 ));
LUT6 #(
    .INIT(64'h2222222200022202)) 
     \slaveRegDo_mux_0[12]_i_7 
       (.I0(\n_0_slaveRegDo_mux_0[12]_i_15 ),
        .I1(I1),
        .I2(I2),
        .I3(s_daddr_o[4]),
        .I4(O20),
        .I5(I3),
        .O(O5));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[13]_i_15 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[13] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[13]),
        .O(O14));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[14]_i_16 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[14] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[14]),
        .O(O15));
LUT5 #(
    .INIT(32'h45004000)) 
     \slaveRegDo_mux_0[1]_i_12 
       (.I0(s_daddr_o[2]),
        .I1(capture_qual_ctrl[0]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[1]),
        .O(O2));
LUT5 #(
    .INIT(32'h45004000)) 
     \slaveRegDo_mux_0[2]_i_12 
       (.I0(s_daddr_o[2]),
        .I1(capture_qual_ctrl[1]),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[2]),
        .O(O3));
LUT5 #(
    .INIT(32'h45004000)) 
     \slaveRegDo_mux_0[3]_i_13 
       (.I0(s_daddr_o[2]),
        .I1(en_adv_trigger),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[3]),
        .O(O4));
LUT5 #(
    .INIT(32'hFFFF0DFF)) 
     \slaveRegDo_mux_0[4]_i_3 
       (.I0(\n_0_slaveRegDo_mux_0[4]_i_8 ),
        .I1(I17),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[1]),
        .I4(I18),
        .O(O12));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[4]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[4] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[4]),
        .O(\n_0_slaveRegDo_mux_0[4]_i_8 ));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[5]_i_15 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[5] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[5]),
        .O(O13));
LUT5 #(
    .INIT(32'hFFFF0DFF)) 
     \slaveRegDo_mux_0[6]_i_3 
       (.I0(\n_0_slaveRegDo_mux_0[6]_i_8 ),
        .I1(I15),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[1]),
        .I4(I16),
        .O(O11));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[6]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[6] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[6]),
        .O(\n_0_slaveRegDo_mux_0[6]_i_8 ));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[7]_i_14 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[7] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[7]),
        .O(\n_0_slaveRegDo_mux_0[7]_i_14 ));
LUT6 #(
    .INIT(64'h1F1F1F1F1F1F1FFF)) 
     \slaveRegDo_mux_0[7]_i_3 
       (.I0(\n_0_slaveRegDo_mux_0[7]_i_7 ),
        .I1(s_daddr_o[5]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[3]),
        .I5(I12),
        .O(O10));
LUT6 #(
    .INIT(64'h2222022222222222)) 
     \slaveRegDo_mux_0[7]_i_7 
       (.I0(\n_0_slaveRegDo_mux_0[7]_i_14 ),
        .I1(I13),
        .I2(I14),
        .I3(s_daddr_o[4]),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[2]),
        .O(\n_0_slaveRegDo_mux_0[7]_i_7 ));
LUT5 #(
    .INIT(32'hFFFF0DFF)) 
     \slaveRegDo_mux_0[8]_i_3 
       (.I0(\n_0_slaveRegDo_mux_0[8]_i_8 ),
        .I1(I10),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[1]),
        .I4(I11),
        .O(O9));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[8]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[8] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[8]),
        .O(\n_0_slaveRegDo_mux_0[8]_i_8 ));
LUT5 #(
    .INIT(32'hFFFF0DFF)) 
     \slaveRegDo_mux_0[9]_i_3 
       (.I0(\n_0_slaveRegDo_mux_0[9]_i_8 ),
        .I1(I8),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[1]),
        .I4(I9),
        .O(O8));
LUT5 #(
    .INIT(32'hBAFFBFFF)) 
     \slaveRegDo_mux_0[9]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[9] ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[9]),
        .O(\n_0_slaveRegDo_mux_0[9]_i_8 ));
LUT5 #(
    .INIT(32'h00000800)) 
     \xsdb_reg[15]_i_1__5 
       (.I0(I19),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[0]),
        .O(\n_0_xsdb_reg[15]_i_1__5 ));
FDRE #(
    .INIT(1'b1)) 
     \xsdb_reg_reg[0] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[0]),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[10]),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[11]),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[12]),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[13]),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[14]),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[15]),
        .Q(O16),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[1]),
        .Q(capture_qual_ctrl[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[2]),
        .Q(capture_qual_ctrl[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b1)) 
     \xsdb_reg_reg[3] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[3]),
        .Q(en_adv_trigger),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[4]),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[5]),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[6]),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[7]),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[8]),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I20),
        .CE(\n_0_xsdb_reg[15]_i_1__5 ),
        .D(s_di_o[9]),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl__parameterized2
   (O1,
    O3,
    O2,
    s_daddr_o,
    E,
    dwe,
    I1,
    Q,
    s_di_o,
    I2);
  output O1;
  output O3;
  output [13:0]O2;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input [1:0]I1;
  input [1:0]Q;
  input [15:0]s_di_o;
  input I2;

  wire [0:0]E;
  wire [1:0]I1;
  wire I2;
  wire O1;
  wire [13:0]O2;
  wire O3;
  wire [1:0]Q;
  wire dwe;
  wire \n_0_xsdb_reg[15]_i_1__14 ;
  wire \n_0_xsdb_reg[15]_i_2__10 ;
  wire \n_0_xsdb_reg[15]_i_3__6 ;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:7]slaveRegDo_82;

LUT5 #(
    .INIT(32'h035FF35F)) 
     \slaveRegDo_mux_0[15]_i_13 
       (.I0(slaveRegDo_82[15]),
        .I1(I1[1]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[2]),
        .I4(Q[1]),
        .O(O3));
LUT5 #(
    .INIT(32'h035FF35F)) 
     \slaveRegDo_mux_0[7]_i_8 
       (.I0(slaveRegDo_82[7]),
        .I1(I1[0]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[2]),
        .I4(Q[0]),
        .O(O1));
LUT5 #(
    .INIT(32'h10000000)) 
     \xsdb_reg[15]_i_1__14 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[1]),
        .I3(\n_0_xsdb_reg[15]_i_2__10 ),
        .I4(\n_0_xsdb_reg[15]_i_3__6 ),
        .O(\n_0_xsdb_reg[15]_i_1__14 ));
LUT6 #(
    .INIT(64'h0000000000000010)) 
     \xsdb_reg[15]_i_2__10 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_xsdb_reg[15]_i_2__10 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \xsdb_reg[15]_i_3__6 
       (.I0(s_daddr_o[10]),
        .I1(s_daddr_o[9]),
        .I2(E),
        .I3(dwe),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[12]),
        .O(\n_0_xsdb_reg[15]_i_3__6 ));
FDRE #(
    .INIT(1'b1)) 
     \xsdb_reg_reg[0] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[0]),
        .Q(O2[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[10]),
        .Q(O2[9]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[11]),
        .Q(O2[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[12]),
        .Q(O2[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[13]),
        .Q(O2[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[14]),
        .Q(O2[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[15]),
        .Q(slaveRegDo_82[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[1]),
        .Q(O2[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[2]),
        .Q(O2[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[3]),
        .Q(O2[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[4]),
        .Q(O2[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[5]),
        .Q(O2[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[6]),
        .Q(O2[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[7]),
        .Q(slaveRegDo_82[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[8]),
        .Q(O2[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I2),
        .CE(\n_0_xsdb_reg[15]_i_1__14 ),
        .D(s_di_o[9]),
        .Q(O2[8]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_ctl" *) 
module ila_0_xsdbs_v1_0_reg_ctl__parameterized2_230
   (slaveRegDo_80,
    s_daddr_o,
    E,
    dwe,
    s_di_o,
    I1);
  output [15:0]slaveRegDo_80;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input dwe;
  input [15:0]s_di_o;
  input I1;

  wire [0:0]E;
  wire I1;
  wire dwe;
  wire \n_0_xsdb_reg[15]_i_1__12 ;
  wire \n_0_xsdb_reg[15]_i_2__8 ;
  wire \n_0_xsdb_reg[15]_i_3__4 ;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]slaveRegDo_80;

LUT5 #(
    .INIT(32'h01000000)) 
     \xsdb_reg[15]_i_1__12 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[0]),
        .I3(\n_0_xsdb_reg[15]_i_2__8 ),
        .I4(\n_0_xsdb_reg[15]_i_3__4 ),
        .O(\n_0_xsdb_reg[15]_i_1__12 ));
LUT6 #(
    .INIT(64'h0000000000000010)) 
     \xsdb_reg[15]_i_2__8 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_xsdb_reg[15]_i_2__8 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \xsdb_reg[15]_i_3__4 
       (.I0(s_daddr_o[10]),
        .I1(s_daddr_o[9]),
        .I2(E),
        .I3(dwe),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[12]),
        .O(\n_0_xsdb_reg[15]_i_3__4 ));
FDRE #(
    .INIT(1'b1)) 
     \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[0]),
        .Q(slaveRegDo_80[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[10]),
        .Q(slaveRegDo_80[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[11]),
        .Q(slaveRegDo_80[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[12]),
        .Q(slaveRegDo_80[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[13]),
        .Q(slaveRegDo_80[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[14]),
        .Q(slaveRegDo_80[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[15]),
        .Q(slaveRegDo_80[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[1]),
        .Q(slaveRegDo_80[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[2]),
        .Q(slaveRegDo_80[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[3]),
        .Q(slaveRegDo_80[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[4]),
        .Q(slaveRegDo_80[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[5]),
        .Q(slaveRegDo_80[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[6]),
        .Q(slaveRegDo_80[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[7]),
        .Q(slaveRegDo_80[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[8]),
        .Q(slaveRegDo_80[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(\n_0_xsdb_reg[15]_i_1__12 ),
        .D(s_di_o[9]),
        .Q(slaveRegDo_80[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    capture_ctrl_config_serial_output,
    dwe,
    s_daddr_o,
    E,
    Q,
    debug_data_in,
    D,
    I1,
    I10,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output capture_ctrl_config_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]Q;
  input [15:0]debug_data_in;
  input [15:0]D;
  input I1;
  input [0:0]I10;
  input [15:0]s_di_o;

  wire [15:0]D;
  wire [0:0]E;
  wire I1;
  wire [0:0]I10;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire capture_ctrl_config_serial_output;
  wire clear;
  wire [3:0]cnt_reg__0;
  wire [3:0]current_state;
  wire data_out_sel;
  wire [15:0]debug_data_in;
  wire dwe;
  wire \n_0_current_state[3]_i_2 ;
  wire \n_0_current_state[3]_i_3 ;
  wire \n_0_current_state[3]_i_5 ;
  wire \n_0_current_state[3]_i_6 ;
  wire n_0_data_out_sel_i_1;
  wire \n_0_shadow[0]_i_1 ;
  wire \n_0_shadow[10]_i_1 ;
  wire \n_0_shadow[11]_i_1 ;
  wire \n_0_shadow[12]_i_1 ;
  wire \n_0_shadow[13]_i_1 ;
  wire \n_0_shadow[14]_i_1 ;
  wire \n_0_shadow[15]_i_1 ;
  wire \n_0_shadow[1]_i_1 ;
  wire \n_0_shadow[2]_i_1 ;
  wire \n_0_shadow[3]_i_1 ;
  wire \n_0_shadow[4]_i_1 ;
  wire \n_0_shadow[5]_i_1 ;
  wire \n_0_shadow[6]_i_1 ;
  wire \n_0_shadow[7]_i_1 ;
  wire \n_0_shadow[8]_i_1 ;
  wire \n_0_shadow[9]_i_1 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]slaveRegDo_fff;

LUT3 #(
    .INIT(8'hB8)) 
     \I_YESLUT6.U_SRL32_D_i_1 
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(I10),
        .O(capture_ctrl_config_serial_output));
LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1 
       (.I0(cnt_reg__0[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair246" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair246" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1 
       (.I0(cnt_reg__0[0]),
        .I1(cnt_reg__0[1]),
        .I2(cnt_reg__0[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair244" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .I3(cnt_reg__0[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg__0[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg__0[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg__0[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg__0[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__0 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__0 
       (.I0(\n_0_current_state[3]_i_2 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__0 
       (.I0(\n_0_current_state[3]_i_2 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__0 
       (.I0(\n_0_current_state[3]_i_2 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair243" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2 ));
(* SOFT_HLUTNM = "soft_lutpair244" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3 
       (.I0(cnt_reg__0[1]),
        .I1(cnt_reg__0[0]),
        .I2(cnt_reg__0[2]),
        .I3(cnt_reg__0[3]),
        .O(\n_0_current_state[3]_i_3 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5 ),
        .I3(\n_0_current_state[3]_i_6 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h8000000000000000)) 
     \current_state[3]_i_5 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5 ));
LUT6 #(
    .INIT(64'h0080000000000000)) 
     \current_state[3]_i_6 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(E),
        .I3(s_daddr_o[12]),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair245" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[1]),
        .Q(slaveRegDo_fff[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[11]),
        .Q(slaveRegDo_fff[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[12]),
        .Q(slaveRegDo_fff[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[13]),
        .Q(slaveRegDo_fff[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[14]),
        .Q(slaveRegDo_fff[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[15]),
        .Q(slaveRegDo_fff[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(I10),
        .Q(slaveRegDo_fff[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[2]),
        .Q(slaveRegDo_fff[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[3]),
        .Q(slaveRegDo_fff[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[4]),
        .Q(slaveRegDo_fff[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[5]),
        .Q(slaveRegDo_fff[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[6]),
        .Q(slaveRegDo_fff[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[7]),
        .Q(slaveRegDo_fff[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[8]),
        .Q(slaveRegDo_fff[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[9]),
        .Q(slaveRegDo_fff[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(slaveRegDo_fff[10]),
        .Q(slaveRegDo_fff[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair243" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair245" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[0]_i_2 
       (.I0(slaveRegDo_fff[0]),
        .I1(Q[0]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[0]),
        .I4(s_daddr_o[0]),
        .I5(D[0]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[10]_i_2 
       (.I0(slaveRegDo_fff[10]),
        .I1(Q[10]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[10]),
        .I4(s_daddr_o[0]),
        .I5(D[10]),
        .O(O11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[11]_i_2 
       (.I0(slaveRegDo_fff[11]),
        .I1(Q[11]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[11]),
        .I4(s_daddr_o[0]),
        .I5(D[11]),
        .O(O12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[12]_i_2 
       (.I0(slaveRegDo_fff[12]),
        .I1(Q[12]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[12]),
        .I4(s_daddr_o[0]),
        .I5(D[12]),
        .O(O13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[13]_i_2 
       (.I0(slaveRegDo_fff[13]),
        .I1(Q[13]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[13]),
        .I4(s_daddr_o[0]),
        .I5(D[13]),
        .O(O14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[14]_i_2 
       (.I0(slaveRegDo_fff[14]),
        .I1(Q[14]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[14]),
        .I4(s_daddr_o[0]),
        .I5(D[14]),
        .O(O15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[15]_i_4 
       (.I0(slaveRegDo_fff[15]),
        .I1(Q[15]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[15]),
        .I4(s_daddr_o[0]),
        .I5(D[15]),
        .O(O16));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[1]_i_2 
       (.I0(slaveRegDo_fff[1]),
        .I1(Q[1]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[1]),
        .I4(s_daddr_o[0]),
        .I5(D[1]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[2]_i_2 
       (.I0(slaveRegDo_fff[2]),
        .I1(Q[2]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[2]),
        .I4(s_daddr_o[0]),
        .I5(D[2]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[3]_i_2 
       (.I0(slaveRegDo_fff[3]),
        .I1(Q[3]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[3]),
        .I4(s_daddr_o[0]),
        .I5(D[3]),
        .O(O4));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[4]_i_2 
       (.I0(slaveRegDo_fff[4]),
        .I1(Q[4]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[4]),
        .I4(s_daddr_o[0]),
        .I5(D[4]),
        .O(O5));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[5]_i_2 
       (.I0(slaveRegDo_fff[5]),
        .I1(Q[5]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[5]),
        .I4(s_daddr_o[0]),
        .I5(D[5]),
        .O(O6));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[6]_i_2 
       (.I0(slaveRegDo_fff[6]),
        .I1(Q[6]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[6]),
        .I4(s_daddr_o[0]),
        .I5(D[6]),
        .O(O7));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[7]_i_2 
       (.I0(slaveRegDo_fff[7]),
        .I1(Q[7]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[7]),
        .I4(s_daddr_o[0]),
        .I5(D[7]),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[8]_i_2 
       (.I0(slaveRegDo_fff[8]),
        .I1(Q[8]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[8]),
        .I4(s_daddr_o[0]),
        .I5(D[8]),
        .O(O9));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_3[9]_i_2 
       (.I0(slaveRegDo_fff[9]),
        .I1(Q[9]),
        .I2(s_daddr_o[1]),
        .I3(debug_data_in[9]),
        .I4(s_daddr_o[0]),
        .I5(D[9]),
        .O(O10));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized0
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__0 ;
  wire \n_0_current_state[3]_i_3__0 ;
  wire \n_0_current_state[3]_i_5__0 ;
  wire \n_0_current_state[3]_i_6__0 ;
  wire n_0_data_out_sel_i_1__0;
  wire \n_0_shadow[0]_i_1__0 ;
  wire \n_0_shadow[10]_i_1__0 ;
  wire \n_0_shadow[11]_i_1__0 ;
  wire \n_0_shadow[12]_i_1__0 ;
  wire \n_0_shadow[13]_i_1__0 ;
  wire \n_0_shadow[14]_i_1__0 ;
  wire \n_0_shadow[15]_i_1__0 ;
  wire \n_0_shadow[1]_i_1__0 ;
  wire \n_0_shadow[2]_i_1__0 ;
  wire \n_0_shadow[3]_i_1__0 ;
  wire \n_0_shadow[4]_i_1__0 ;
  wire \n_0_shadow[5]_i_1__0 ;
  wire \n_0_shadow[6]_i_1__0 ;
  wire \n_0_shadow[7]_i_1__0 ;
  wire \n_0_shadow[8]_i_1__0 ;
  wire \n_0_shadow[9]_i_1__0 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__0;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__0 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair66" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__0 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair66" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__0 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__0 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair64" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__0 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__1 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__0 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__0 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__1 
       (.I0(\n_0_current_state[3]_i_2__0 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__1 
       (.I0(\n_0_current_state[3]_i_2__0 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__0 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__1 
       (.I0(\n_0_current_state[3]_i_2__0 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__0 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair63" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__0 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__0 ));
(* SOFT_HLUTNM = "soft_lutpair64" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__0 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__0 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__0 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__0 ),
        .I3(\n_0_current_state[3]_i_6__0 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__0 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__0 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \current_state[3]_i_6__0 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__0 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair65" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__0
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__0));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__0),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__0 ));
(* SOFT_HLUTNM = "soft_lutpair63" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__0 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__0 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__0 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__0 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__0 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__0 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__0 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__0 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__0 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__0 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__0 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__0 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__0 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__0 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__0 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__0 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__0 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__0 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__0 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__0 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair65" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__0
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__0));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__0),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized1
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__1 ;
  wire \n_0_current_state[3]_i_3__1 ;
  wire \n_0_current_state[3]_i_5__1 ;
  wire \n_0_current_state[3]_i_6__1 ;
  wire n_0_data_out_sel_i_1__1;
  wire \n_0_shadow[0]_i_1__1 ;
  wire \n_0_shadow[10]_i_1__1 ;
  wire \n_0_shadow[11]_i_1__1 ;
  wire \n_0_shadow[12]_i_1__1 ;
  wire \n_0_shadow[13]_i_1__1 ;
  wire \n_0_shadow[14]_i_1__1 ;
  wire \n_0_shadow[15]_i_1__1 ;
  wire \n_0_shadow[1]_i_1__1 ;
  wire \n_0_shadow[2]_i_1__1 ;
  wire \n_0_shadow[3]_i_1__1 ;
  wire \n_0_shadow[4]_i_1__1 ;
  wire \n_0_shadow[5]_i_1__1 ;
  wire \n_0_shadow[6]_i_1__1 ;
  wire \n_0_shadow[7]_i_1__1 ;
  wire \n_0_shadow[8]_i_1__1 ;
  wire \n_0_shadow[9]_i_1__1 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__1;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__1 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair82" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__1 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair82" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__1 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__1 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair80" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__1 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__2 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__1 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__1 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__2 
       (.I0(\n_0_current_state[3]_i_2__1 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__2 
       (.I0(\n_0_current_state[3]_i_2__1 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__1 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__2 
       (.I0(\n_0_current_state[3]_i_2__1 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__1 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair79" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__1 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__1 ));
(* SOFT_HLUTNM = "soft_lutpair80" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__1 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__1 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__1 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__1 ),
        .I3(\n_0_current_state[3]_i_6__1 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__1 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__1 ));
LUT6 #(
    .INIT(64'h0000000000004000)) 
     \current_state[3]_i_6__1 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__1 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair81" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__1
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__1));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__1),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__1 ));
(* SOFT_HLUTNM = "soft_lutpair79" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__1 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__1 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__1 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__1 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__1 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__1 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__1 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__1 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__1 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__1 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__1 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__1 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__1 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__1 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__1 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__1 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__1 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__1 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__1 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__1 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair81" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__1
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__1));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__1),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__0
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized10
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__10 ;
  wire \n_0_current_state[3]_i_3__10 ;
  wire \n_0_current_state[3]_i_5__10 ;
  wire \n_0_current_state[3]_i_6__10 ;
  wire n_0_data_out_sel_i_1__10;
  wire \n_0_shadow[0]_i_1__10 ;
  wire \n_0_shadow[10]_i_1__10 ;
  wire \n_0_shadow[11]_i_1__10 ;
  wire \n_0_shadow[12]_i_1__10 ;
  wire \n_0_shadow[13]_i_1__10 ;
  wire \n_0_shadow[14]_i_1__10 ;
  wire \n_0_shadow[15]_i_1__10 ;
  wire \n_0_shadow[1]_i_1__10 ;
  wire \n_0_shadow[2]_i_1__10 ;
  wire \n_0_shadow[3]_i_1__10 ;
  wire \n_0_shadow[4]_i_1__10 ;
  wire \n_0_shadow[5]_i_1__10 ;
  wire \n_0_shadow[6]_i_1__10 ;
  wire \n_0_shadow[7]_i_1__10 ;
  wire \n_0_shadow[8]_i_1__10 ;
  wire \n_0_shadow[9]_i_1__10 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__10;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__10 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair70" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__10 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair70" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__10 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__10 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair68" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__10 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__11 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__10 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__10 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__11 
       (.I0(\n_0_current_state[3]_i_2__10 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__11 
       (.I0(\n_0_current_state[3]_i_2__10 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__10 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__11 
       (.I0(\n_0_current_state[3]_i_2__10 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__10 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair67" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__10 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__10 ));
(* SOFT_HLUTNM = "soft_lutpair68" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__10 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__10 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__10 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__10 ),
        .I3(\n_0_current_state[3]_i_6__10 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__10 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__10 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \current_state[3]_i_6__10 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__10 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair69" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__10
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__10));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__10),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__10 ));
(* SOFT_HLUTNM = "soft_lutpair67" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__10 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__10 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__10 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__10 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__10 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__10 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__10 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__10 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__10 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__10 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__10 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__10 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__10 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__10 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__10 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__10 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__10 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__10 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__10 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__10 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair69" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__10
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__10));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__10),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__9
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized11
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    s_do_o,
    Q,
    I1,
    I2,
    mu_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]s_do_o;
  input [15:0]Q;
  input [15:0]I1;
  input I2;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire [15:0]I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__11 ;
  wire \n_0_current_state[3]_i_3__11 ;
  wire \n_0_current_state[3]_i_5__11 ;
  wire \n_0_current_state[3]_i_6__11 ;
  wire n_0_data_out_sel_i_1__11;
  wire \n_0_shadow[0]_i_1__11 ;
  wire \n_0_shadow[10]_i_1__11 ;
  wire \n_0_shadow[11]_i_1__11 ;
  wire \n_0_shadow[12]_i_1__11 ;
  wire \n_0_shadow[13]_i_1__11 ;
  wire \n_0_shadow[14]_i_1__11 ;
  wire \n_0_shadow[15]_i_1__11 ;
  wire \n_0_shadow[1]_i_1__11 ;
  wire \n_0_shadow[2]_i_1__11 ;
  wire \n_0_shadow[3]_i_1__11 ;
  wire \n_0_shadow[4]_i_1__11 ;
  wire \n_0_shadow[5]_i_1__11 ;
  wire \n_0_shadow[6]_i_1__11 ;
  wire \n_0_shadow[7]_i_1__11 ;
  wire \n_0_shadow[8]_i_1__11 ;
  wire \n_0_shadow[9]_i_1__11 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__11;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_muConfig[4107]_12 ;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__11 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair74" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__11 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair74" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__11 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__11 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair72" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__11 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I2),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I2),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I2),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I2),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__12 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__11 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__11 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__12 
       (.I0(\n_0_current_state[3]_i_2__11 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__12 
       (.I0(\n_0_current_state[3]_i_2__11 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__11 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__12 
       (.I0(\n_0_current_state[3]_i_2__11 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__11 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair71" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__11 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__11 ));
(* SOFT_HLUTNM = "soft_lutpair72" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__11 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__11 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__11 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__11 ),
        .I3(\n_0_current_state[3]_i_6__11 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__11 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__11 ));
LUT6 #(
    .INIT(64'h0000000000004000)) 
     \current_state[3]_i_6__11 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__11 ));
FDRE \current_state_reg[0] 
       (.C(I2),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I2),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I2),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I2),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair73" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__11
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__11));
FDRE data_out_sel_reg
       (.C(I2),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__11),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [1]),
        .Q(\slaveRegDo_muConfig[4107]_12 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [11]),
        .Q(\slaveRegDo_muConfig[4107]_12 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [12]),
        .Q(\slaveRegDo_muConfig[4107]_12 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [13]),
        .Q(\slaveRegDo_muConfig[4107]_12 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [14]),
        .Q(\slaveRegDo_muConfig[4107]_12 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [15]),
        .Q(\slaveRegDo_muConfig[4107]_12 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I2),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(\slaveRegDo_muConfig[4107]_12 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [2]),
        .Q(\slaveRegDo_muConfig[4107]_12 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [3]),
        .Q(\slaveRegDo_muConfig[4107]_12 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [4]),
        .Q(\slaveRegDo_muConfig[4107]_12 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [5]),
        .Q(\slaveRegDo_muConfig[4107]_12 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [6]),
        .Q(\slaveRegDo_muConfig[4107]_12 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [7]),
        .Q(\slaveRegDo_muConfig[4107]_12 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [8]),
        .Q(\slaveRegDo_muConfig[4107]_12 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [9]),
        .Q(\slaveRegDo_muConfig[4107]_12 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I2),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4107]_12 [10]),
        .Q(\slaveRegDo_muConfig[4107]_12 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__11 ));
(* SOFT_HLUTNM = "soft_lutpair71" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__11 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__11 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__11 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__11 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__11 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__11 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__11 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__11 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__11 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__11 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__11 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__11 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__11 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__11 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__11 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__11 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__11 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__11 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__11 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I2),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__11 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair73" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__11
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__11));
FDRE shift_en_reg
       (.C(I2),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__11),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[0]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(Q[0]),
        .I4(s_daddr_o[0]),
        .I5(I1[0]),
        .O(O16));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[10]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(Q[10]),
        .I4(s_daddr_o[0]),
        .I5(I1[10]),
        .O(O6));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[11]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(Q[11]),
        .I4(s_daddr_o[0]),
        .I5(I1[11]),
        .O(O5));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[12]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(Q[12]),
        .I4(s_daddr_o[0]),
        .I5(I1[12]),
        .O(O4));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[13]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(Q[13]),
        .I4(s_daddr_o[0]),
        .I5(I1[13]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[14]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(Q[14]),
        .I4(s_daddr_o[0]),
        .I5(I1[14]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[15]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(Q[15]),
        .I4(s_daddr_o[0]),
        .I5(I1[15]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[1]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(Q[1]),
        .I4(s_daddr_o[0]),
        .I5(I1[1]),
        .O(O15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[2]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(Q[2]),
        .I4(s_daddr_o[0]),
        .I5(I1[2]),
        .O(O14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[3]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(Q[3]),
        .I4(s_daddr_o[0]),
        .I5(I1[3]),
        .O(O13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[4]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(Q[4]),
        .I4(s_daddr_o[0]),
        .I5(I1[4]),
        .O(O12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[5]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(Q[5]),
        .I4(s_daddr_o[0]),
        .I5(I1[5]),
        .O(O11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[6]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(Q[6]),
        .I4(s_daddr_o[0]),
        .I5(I1[6]),
        .O(O10));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[7]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(Q[7]),
        .I4(s_daddr_o[0]),
        .I5(I1[7]),
        .O(O9));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[8]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(Q[8]),
        .I4(s_daddr_o[0]),
        .I5(I1[8]),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[9]_i_2 
       (.I0(\slaveRegDo_muConfig[4107]_12 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(Q[9]),
        .I4(s_daddr_o[0]),
        .I5(I1[9]),
        .O(O7));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__10
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized12
   (D,
    shift_en_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    I24,
    I25,
    I26,
    I27,
    I28,
    I29,
    I30,
    I31,
    I32,
    I33,
    I34,
    I35,
    I36,
    I37,
    I38,
    I39,
    I40,
    I41,
    I42,
    I43,
    I44,
    I45,
    I46,
    I47,
    I48,
    I49,
    mu_config_cs_serial_input,
    s_di_o);
  output [15:0]D;
  output shift_en_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input I23;
  input I24;
  input I25;
  input I26;
  input I27;
  input I28;
  input I29;
  input I30;
  input I31;
  input I32;
  input I33;
  input I34;
  input I35;
  input I36;
  input I37;
  input I38;
  input I39;
  input I40;
  input I41;
  input I42;
  input I43;
  input I44;
  input I45;
  input I46;
  input I47;
  input I48;
  input I49;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [15:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I28;
  wire I29;
  wire I3;
  wire I30;
  wire I31;
  wire I32;
  wire I33;
  wire I34;
  wire I35;
  wire I36;
  wire I37;
  wire I38;
  wire I39;
  wire I4;
  wire I40;
  wire I41;
  wire I42;
  wire I43;
  wire I44;
  wire I45;
  wire I46;
  wire I47;
  wire I48;
  wire I49;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__12 ;
  wire \n_0_current_state[3]_i_3__12 ;
  wire \n_0_current_state[3]_i_5__12 ;
  wire \n_0_current_state[3]_i_6__12 ;
  wire n_0_data_out_sel_i_1__12;
  wire \n_0_shadow[0]_i_1__12 ;
  wire \n_0_shadow[10]_i_1__12 ;
  wire \n_0_shadow[11]_i_1__12 ;
  wire \n_0_shadow[12]_i_1__12 ;
  wire \n_0_shadow[13]_i_1__12 ;
  wire \n_0_shadow[14]_i_1__12 ;
  wire \n_0_shadow[15]_i_1__12 ;
  wire \n_0_shadow[1]_i_1__12 ;
  wire \n_0_shadow[2]_i_1__12 ;
  wire \n_0_shadow[3]_i_1__12 ;
  wire \n_0_shadow[4]_i_1__12 ;
  wire \n_0_shadow[5]_i_1__12 ;
  wire \n_0_shadow[6]_i_1__12 ;
  wire \n_0_shadow[7]_i_1__12 ;
  wire \n_0_shadow[8]_i_1__12 ;
  wire \n_0_shadow[9]_i_1__12 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__12;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_muConfig[4108]_13 ;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__12 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair78" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__12 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair78" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__12 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__12 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair76" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__12 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I49),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I49),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I49),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I49),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__13 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__12 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__12 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__13 
       (.I0(\n_0_current_state[3]_i_2__12 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__13 
       (.I0(\n_0_current_state[3]_i_2__12 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__12 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__13 
       (.I0(\n_0_current_state[3]_i_2__12 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__12 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair75" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__12 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__12 ));
(* SOFT_HLUTNM = "soft_lutpair76" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__12 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__12 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__12 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__12 ),
        .I3(\n_0_current_state[3]_i_6__12 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__12 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__12 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \current_state[3]_i_6__12 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__12 ));
FDRE \current_state_reg[0] 
       (.C(I49),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I49),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I49),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I49),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair77" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__12
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__12));
FDRE data_out_sel_reg
       (.C(I49),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__12),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [1]),
        .Q(\slaveRegDo_muConfig[4108]_13 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [11]),
        .Q(\slaveRegDo_muConfig[4108]_13 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [12]),
        .Q(\slaveRegDo_muConfig[4108]_13 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [13]),
        .Q(\slaveRegDo_muConfig[4108]_13 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [14]),
        .Q(\slaveRegDo_muConfig[4108]_13 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [15]),
        .Q(\slaveRegDo_muConfig[4108]_13 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I49),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(\slaveRegDo_muConfig[4108]_13 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [2]),
        .Q(\slaveRegDo_muConfig[4108]_13 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [3]),
        .Q(\slaveRegDo_muConfig[4108]_13 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [4]),
        .Q(\slaveRegDo_muConfig[4108]_13 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [5]),
        .Q(\slaveRegDo_muConfig[4108]_13 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [6]),
        .Q(\slaveRegDo_muConfig[4108]_13 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [7]),
        .Q(\slaveRegDo_muConfig[4108]_13 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [8]),
        .Q(\slaveRegDo_muConfig[4108]_13 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [9]),
        .Q(\slaveRegDo_muConfig[4108]_13 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I49),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4108]_13 [10]),
        .Q(\slaveRegDo_muConfig[4108]_13 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__12 ));
(* SOFT_HLUTNM = "soft_lutpair75" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__12 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__12 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__12 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__12 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__12 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__12 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__12 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__12 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__12 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__12 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__12 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__12 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__12 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__12 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__12 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__12 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__12 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__12 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__12 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I49),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__12 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair77" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__12
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__12));
FDRE shift_en_reg
       (.C(I49),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__12),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[0]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [0]),
        .I1(I46),
        .I2(s_daddr_o[3]),
        .I3(I47),
        .I4(s_daddr_o[2]),
        .I5(I48),
        .O(D[0]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[10]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [10]),
        .I1(I16),
        .I2(s_daddr_o[3]),
        .I3(I17),
        .I4(s_daddr_o[2]),
        .I5(I18),
        .O(D[10]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[11]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [11]),
        .I1(I13),
        .I2(s_daddr_o[3]),
        .I3(I14),
        .I4(s_daddr_o[2]),
        .I5(I15),
        .O(D[11]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[12]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [12]),
        .I1(I10),
        .I2(s_daddr_o[3]),
        .I3(I11),
        .I4(s_daddr_o[2]),
        .I5(I12),
        .O(D[12]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[13]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [13]),
        .I1(I7),
        .I2(s_daddr_o[3]),
        .I3(I8),
        .I4(s_daddr_o[2]),
        .I5(I9),
        .O(D[13]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[14]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [14]),
        .I1(I4),
        .I2(s_daddr_o[3]),
        .I3(I5),
        .I4(s_daddr_o[2]),
        .I5(I6),
        .O(D[14]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[15]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [15]),
        .I1(I1),
        .I2(s_daddr_o[3]),
        .I3(I2),
        .I4(s_daddr_o[2]),
        .I5(I3),
        .O(D[15]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[1]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [1]),
        .I1(I43),
        .I2(s_daddr_o[3]),
        .I3(I44),
        .I4(s_daddr_o[2]),
        .I5(I45),
        .O(D[1]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[2]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [2]),
        .I1(I40),
        .I2(s_daddr_o[3]),
        .I3(I41),
        .I4(s_daddr_o[2]),
        .I5(I42),
        .O(D[2]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[3]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [3]),
        .I1(I37),
        .I2(s_daddr_o[3]),
        .I3(I38),
        .I4(s_daddr_o[2]),
        .I5(I39),
        .O(D[3]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[4]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [4]),
        .I1(I34),
        .I2(s_daddr_o[3]),
        .I3(I35),
        .I4(s_daddr_o[2]),
        .I5(I36),
        .O(D[4]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[5]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [5]),
        .I1(I31),
        .I2(s_daddr_o[3]),
        .I3(I32),
        .I4(s_daddr_o[2]),
        .I5(I33),
        .O(D[5]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[6]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [6]),
        .I1(I28),
        .I2(s_daddr_o[3]),
        .I3(I29),
        .I4(s_daddr_o[2]),
        .I5(I30),
        .O(D[6]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[7]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [7]),
        .I1(I25),
        .I2(s_daddr_o[3]),
        .I3(I26),
        .I4(s_daddr_o[2]),
        .I5(I27),
        .O(D[7]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[8]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [8]),
        .I1(I22),
        .I2(s_daddr_o[3]),
        .I3(I23),
        .I4(s_daddr_o[2]),
        .I5(I24),
        .O(D[8]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[9]_i_1 
       (.I0(\slaveRegDo_muConfig[4108]_13 [9]),
        .I1(I19),
        .I2(s_daddr_o[3]),
        .I3(I20),
        .I4(s_daddr_o[2]),
        .I5(I21),
        .O(D[9]));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__11
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized13
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__13 ;
  wire \n_0_current_state[3]_i_3__13 ;
  wire \n_0_current_state[3]_i_5__13 ;
  wire \n_0_current_state[3]_i_6__13 ;
  wire n_0_data_out_sel_i_1__13;
  wire \n_0_shadow[0]_i_1__13 ;
  wire \n_0_shadow[10]_i_1__13 ;
  wire \n_0_shadow[11]_i_1__13 ;
  wire \n_0_shadow[12]_i_1__13 ;
  wire \n_0_shadow[13]_i_1__13 ;
  wire \n_0_shadow[14]_i_1__13 ;
  wire \n_0_shadow[15]_i_1__13 ;
  wire \n_0_shadow[1]_i_1__13 ;
  wire \n_0_shadow[2]_i_1__13 ;
  wire \n_0_shadow[3]_i_1__13 ;
  wire \n_0_shadow[4]_i_1__13 ;
  wire \n_0_shadow[5]_i_1__13 ;
  wire \n_0_shadow[6]_i_1__13 ;
  wire \n_0_shadow[7]_i_1__13 ;
  wire \n_0_shadow[8]_i_1__13 ;
  wire \n_0_shadow[9]_i_1__13 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__13;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__13 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair118" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__13 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair118" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__13 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__13 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair116" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__13 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__14 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__13 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__13 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__14 
       (.I0(\n_0_current_state[3]_i_2__13 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__14 
       (.I0(\n_0_current_state[3]_i_2__13 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__13 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__14 
       (.I0(\n_0_current_state[3]_i_2__13 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__13 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair115" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__13 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__13 ));
(* SOFT_HLUTNM = "soft_lutpair116" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__13 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__13 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__13 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__13 ),
        .I3(\n_0_current_state[3]_i_6__13 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__13 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__13 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__13 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__13 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair117" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__13
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__13));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__13),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__13 ));
(* SOFT_HLUTNM = "soft_lutpair115" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__13 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__13 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__13 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__13 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__13 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__13 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__13 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__13 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__13 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__13 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__13 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__13 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__13 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__13 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__13 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__13 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__13 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__13 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__13 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__13 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair117" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__13
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__13));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__13),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__12
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized14
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__14 ;
  wire \n_0_current_state[3]_i_3__14 ;
  wire \n_0_current_state[3]_i_5__14 ;
  wire \n_0_current_state[3]_i_6__14 ;
  wire n_0_data_out_sel_i_1__14;
  wire \n_0_shadow[0]_i_1__14 ;
  wire \n_0_shadow[10]_i_1__14 ;
  wire \n_0_shadow[11]_i_1__14 ;
  wire \n_0_shadow[12]_i_1__14 ;
  wire \n_0_shadow[13]_i_1__14 ;
  wire \n_0_shadow[14]_i_1__14 ;
  wire \n_0_shadow[15]_i_1__14 ;
  wire \n_0_shadow[1]_i_1__14 ;
  wire \n_0_shadow[2]_i_1__14 ;
  wire \n_0_shadow[3]_i_1__14 ;
  wire \n_0_shadow[4]_i_1__14 ;
  wire \n_0_shadow[5]_i_1__14 ;
  wire \n_0_shadow[6]_i_1__14 ;
  wire \n_0_shadow[7]_i_1__14 ;
  wire \n_0_shadow[8]_i_1__14 ;
  wire \n_0_shadow[9]_i_1__14 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__14;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__14 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair162" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__14 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair162" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__14 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__14 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair160" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__14 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__15 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__14 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__14 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__15 
       (.I0(\n_0_current_state[3]_i_2__14 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__15 
       (.I0(\n_0_current_state[3]_i_2__14 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__14 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__15 
       (.I0(\n_0_current_state[3]_i_2__14 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__14 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair159" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__14 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__14 ));
(* SOFT_HLUTNM = "soft_lutpair160" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__14 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__14 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__14 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__14 ),
        .I3(\n_0_current_state[3]_i_6__14 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__14 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__14 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__14 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__14 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair161" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__14
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__14));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__14),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__14 ));
(* SOFT_HLUTNM = "soft_lutpair159" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__14 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__14 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__14 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__14 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__14 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__14 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__14 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__14 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__14 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__14 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__14 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__14 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__14 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__14 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__14 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__14 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__14 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__14 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__14 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__14 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair161" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__14
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__14));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__14),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__13
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized15
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__15 ;
  wire \n_0_current_state[3]_i_3__15 ;
  wire \n_0_current_state[3]_i_5__15 ;
  wire \n_0_current_state[3]_i_6__15 ;
  wire n_0_data_out_sel_i_1__15;
  wire \n_0_shadow[0]_i_1__15 ;
  wire \n_0_shadow[10]_i_1__15 ;
  wire \n_0_shadow[11]_i_1__15 ;
  wire \n_0_shadow[12]_i_1__15 ;
  wire \n_0_shadow[13]_i_1__15 ;
  wire \n_0_shadow[14]_i_1__15 ;
  wire \n_0_shadow[15]_i_1__15 ;
  wire \n_0_shadow[1]_i_1__15 ;
  wire \n_0_shadow[2]_i_1__15 ;
  wire \n_0_shadow[3]_i_1__15 ;
  wire \n_0_shadow[4]_i_1__15 ;
  wire \n_0_shadow[5]_i_1__15 ;
  wire \n_0_shadow[6]_i_1__15 ;
  wire \n_0_shadow[7]_i_1__15 ;
  wire \n_0_shadow[8]_i_1__15 ;
  wire \n_0_shadow[9]_i_1__15 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__15;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__15 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair206" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__15 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair206" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__15 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__15 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair204" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__15 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__16 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__15 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__15 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__16 
       (.I0(\n_0_current_state[3]_i_2__15 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__16 
       (.I0(\n_0_current_state[3]_i_2__15 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__15 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__16 
       (.I0(\n_0_current_state[3]_i_2__15 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__15 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair203" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__15 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__15 ));
(* SOFT_HLUTNM = "soft_lutpair204" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__15 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__15 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__15 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__15 ),
        .I3(\n_0_current_state[3]_i_6__15 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__15 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__15 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__15 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__15 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair205" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__15
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__15));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__15),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__15 ));
(* SOFT_HLUTNM = "soft_lutpair203" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__15 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__15 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__15 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__15 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__15 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__15 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__15 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__15 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__15 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__15 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__15 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__15 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__15 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__15 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__15 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__15 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__15 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__15 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__15 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__15 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair205" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__15
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__15));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__15),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__14
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized16
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    s_do_o,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    tc_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [15:0]s_do_o;
  input [15:0]I2;
  input [15:0]I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire [15:0]I2;
  wire [15:0]I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__16 ;
  wire \n_0_current_state[3]_i_3__16 ;
  wire \n_0_current_state[3]_i_5__16 ;
  wire \n_0_current_state[3]_i_6__16 ;
  wire n_0_data_out_sel_i_1__16;
  wire \n_0_shadow[0]_i_1__16 ;
  wire \n_0_shadow[10]_i_1__16 ;
  wire \n_0_shadow[11]_i_1__16 ;
  wire \n_0_shadow[12]_i_1__16 ;
  wire \n_0_shadow[13]_i_1__16 ;
  wire \n_0_shadow[14]_i_1__16 ;
  wire \n_0_shadow[15]_i_1__16 ;
  wire \n_0_shadow[1]_i_1__16 ;
  wire \n_0_shadow[2]_i_1__16 ;
  wire \n_0_shadow[3]_i_1__16 ;
  wire \n_0_shadow[4]_i_1__16 ;
  wire \n_0_shadow[5]_i_1__16 ;
  wire \n_0_shadow[6]_i_1__16 ;
  wire \n_0_shadow[7]_i_1__16 ;
  wire \n_0_shadow[8]_i_1__16 ;
  wire \n_0_shadow[9]_i_1__16 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__16;
  wire \n_0_slaveRegDo_mux_5[0]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[10]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[11]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[12]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[13]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[14]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[15]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[1]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[2]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[3]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[4]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[5]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[6]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[7]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[8]_i_12 ;
  wire \n_0_slaveRegDo_mux_5[9]_i_12 ;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_tcConfig[5123]_17 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__16 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair218" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__16 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair218" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__16 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__16 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair216" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__16 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I19),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I19),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I19),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I19),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__17 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__16 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__16 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__17 
       (.I0(\n_0_current_state[3]_i_2__16 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__17 
       (.I0(\n_0_current_state[3]_i_2__16 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__16 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__17 
       (.I0(\n_0_current_state[3]_i_2__16 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__16 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair215" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__16 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__16 ));
(* SOFT_HLUTNM = "soft_lutpair216" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__16 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__16 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__16 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__16 ),
        .I3(\n_0_current_state[3]_i_6__16 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__16 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__16 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__16 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__16 ));
FDRE \current_state_reg[0] 
       (.C(I19),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I19),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I19),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I19),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair217" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__16
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__16));
FDRE data_out_sel_reg
       (.C(I19),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__16),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [1]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [11]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [12]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [13]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [14]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [15]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I19),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5123]_17 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [2]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [3]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [4]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [5]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [6]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [7]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [8]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [9]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5123]_17 [10]),
        .Q(\slaveRegDo_tcConfig[5123]_17 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__16 ));
(* SOFT_HLUTNM = "soft_lutpair215" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__16 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__16 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__16 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__16 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__16 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__16 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__16 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__16 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__16 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__16 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__16 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__16 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__16 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__16 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__16 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__16 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__16 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__16 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__16 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__16 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair217" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__16
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__16));
FDRE shift_en_reg
       (.C(I19),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__16),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I2[0]),
        .I4(s_daddr_o[0]),
        .I5(I3[0]),
        .O(\n_0_slaveRegDo_mux_5[0]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I2[10]),
        .I4(s_daddr_o[0]),
        .I5(I3[10]),
        .O(\n_0_slaveRegDo_mux_5[10]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I2[11]),
        .I4(s_daddr_o[0]),
        .I5(I3[11]),
        .O(\n_0_slaveRegDo_mux_5[11]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I2[12]),
        .I4(s_daddr_o[0]),
        .I5(I3[12]),
        .O(\n_0_slaveRegDo_mux_5[12]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I2[13]),
        .I4(s_daddr_o[0]),
        .I5(I3[13]),
        .O(\n_0_slaveRegDo_mux_5[13]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I2[14]),
        .I4(s_daddr_o[0]),
        .I5(I3[14]),
        .O(\n_0_slaveRegDo_mux_5[14]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I2[15]),
        .I4(s_daddr_o[0]),
        .I5(I3[15]),
        .O(\n_0_slaveRegDo_mux_5[15]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I2[1]),
        .I4(s_daddr_o[0]),
        .I5(I3[1]),
        .O(\n_0_slaveRegDo_mux_5[1]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I2[2]),
        .I4(s_daddr_o[0]),
        .I5(I3[2]),
        .O(\n_0_slaveRegDo_mux_5[2]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I2[3]),
        .I4(s_daddr_o[0]),
        .I5(I3[3]),
        .O(\n_0_slaveRegDo_mux_5[3]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I2[4]),
        .I4(s_daddr_o[0]),
        .I5(I3[4]),
        .O(\n_0_slaveRegDo_mux_5[4]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I2[5]),
        .I4(s_daddr_o[0]),
        .I5(I3[5]),
        .O(\n_0_slaveRegDo_mux_5[5]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I2[6]),
        .I4(s_daddr_o[0]),
        .I5(I3[6]),
        .O(\n_0_slaveRegDo_mux_5[6]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I2[7]),
        .I4(s_daddr_o[0]),
        .I5(I3[7]),
        .O(\n_0_slaveRegDo_mux_5[7]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I2[8]),
        .I4(s_daddr_o[0]),
        .I5(I3[8]),
        .O(\n_0_slaveRegDo_mux_5[8]_i_12 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_12 
       (.I0(\slaveRegDo_tcConfig[5123]_17 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I2[9]),
        .I4(s_daddr_o[0]),
        .I5(I3[9]),
        .O(\n_0_slaveRegDo_mux_5[9]_i_12 ));
MUXF7 \slaveRegDo_mux_5_reg[0]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[0]_i_12 ),
        .I1(I18),
        .O(O16),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[10]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[10]_i_12 ),
        .I1(I8),
        .O(O6),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[11]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[11]_i_12 ),
        .I1(I7),
        .O(O5),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[12]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[12]_i_12 ),
        .I1(I6),
        .O(O4),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[13]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[13]_i_12 ),
        .I1(I5),
        .O(O3),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[14]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[14]_i_12 ),
        .I1(I4),
        .O(O2),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[15]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[15]_i_12 ),
        .I1(I1),
        .O(O1),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[1]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[1]_i_12 ),
        .I1(I17),
        .O(O15),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[2]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[2]_i_12 ),
        .I1(I16),
        .O(O14),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[3]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[3]_i_12 ),
        .I1(I15),
        .O(O13),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[4]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[4]_i_12 ),
        .I1(I14),
        .O(O12),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[5]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[5]_i_12 ),
        .I1(I13),
        .O(O11),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[6]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[6]_i_12 ),
        .I1(I12),
        .O(O10),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[7]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[7]_i_12 ),
        .I1(I11),
        .O(O9),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[8]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[8]_i_12 ),
        .I1(I10),
        .O(O8),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[9]_i_5 
       (.I0(\n_0_slaveRegDo_mux_5[9]_i_12 ),
        .I1(I9),
        .O(O7),
        .S(s_daddr_o[2]));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__15
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized17
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__17 ;
  wire \n_0_current_state[3]_i_3__17 ;
  wire \n_0_current_state[3]_i_5__17 ;
  wire \n_0_current_state[3]_i_6__17 ;
  wire n_0_data_out_sel_i_1__17;
  wire \n_0_shadow[0]_i_1__17 ;
  wire \n_0_shadow[10]_i_1__17 ;
  wire \n_0_shadow[11]_i_1__17 ;
  wire \n_0_shadow[12]_i_1__17 ;
  wire \n_0_shadow[13]_i_1__17 ;
  wire \n_0_shadow[14]_i_1__17 ;
  wire \n_0_shadow[15]_i_1__17 ;
  wire \n_0_shadow[1]_i_1__17 ;
  wire \n_0_shadow[2]_i_1__17 ;
  wire \n_0_shadow[3]_i_1__17 ;
  wire \n_0_shadow[4]_i_1__17 ;
  wire \n_0_shadow[5]_i_1__17 ;
  wire \n_0_shadow[6]_i_1__17 ;
  wire \n_0_shadow[7]_i_1__17 ;
  wire \n_0_shadow[8]_i_1__17 ;
  wire \n_0_shadow[9]_i_1__17 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__17;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__17 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair222" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__17 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair222" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__17 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__17 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair220" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__17 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__18 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__17 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__17 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__18 
       (.I0(\n_0_current_state[3]_i_2__17 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__18 
       (.I0(\n_0_current_state[3]_i_2__17 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__17 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__18 
       (.I0(\n_0_current_state[3]_i_2__17 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__17 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair219" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__17 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__17 ));
(* SOFT_HLUTNM = "soft_lutpair220" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__17 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__17 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__17 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__17 ),
        .I3(\n_0_current_state[3]_i_6__17 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__17 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__17 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__17 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__17 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair221" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__17
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__17));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__17),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__17 ));
(* SOFT_HLUTNM = "soft_lutpair219" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__17 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__17 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__17 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__17 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__17 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__17 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__17 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__17 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__17 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__17 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__17 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__17 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__17 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__17 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__17 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__17 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__17 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__17 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__17 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__17 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair221" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__17
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__17));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__17),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__16
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized18
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__18 ;
  wire \n_0_current_state[3]_i_3__18 ;
  wire \n_0_current_state[3]_i_5__18 ;
  wire \n_0_current_state[3]_i_6__18 ;
  wire n_0_data_out_sel_i_1__18;
  wire \n_0_shadow[0]_i_1__18 ;
  wire \n_0_shadow[10]_i_1__18 ;
  wire \n_0_shadow[11]_i_1__18 ;
  wire \n_0_shadow[12]_i_1__18 ;
  wire \n_0_shadow[13]_i_1__18 ;
  wire \n_0_shadow[14]_i_1__18 ;
  wire \n_0_shadow[15]_i_1__18 ;
  wire \n_0_shadow[1]_i_1__18 ;
  wire \n_0_shadow[2]_i_1__18 ;
  wire \n_0_shadow[3]_i_1__18 ;
  wire \n_0_shadow[4]_i_1__18 ;
  wire \n_0_shadow[5]_i_1__18 ;
  wire \n_0_shadow[6]_i_1__18 ;
  wire \n_0_shadow[7]_i_1__18 ;
  wire \n_0_shadow[8]_i_1__18 ;
  wire \n_0_shadow[9]_i_1__18 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__18;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__18 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair226" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__18 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair226" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__18 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__18 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair224" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__18 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__19 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__18 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__18 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__19 
       (.I0(\n_0_current_state[3]_i_2__18 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__19 
       (.I0(\n_0_current_state[3]_i_2__18 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__18 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__19 
       (.I0(\n_0_current_state[3]_i_2__18 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__18 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair223" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__18 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__18 ));
(* SOFT_HLUTNM = "soft_lutpair224" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__18 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__18 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__18 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__18 ),
        .I3(\n_0_current_state[3]_i_6__18 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__18 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__18 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__18 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__18 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair225" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__18
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__18));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__18),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__18 ));
(* SOFT_HLUTNM = "soft_lutpair223" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__18 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__18 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__18 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__18 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__18 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__18 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__18 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__18 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__18 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__18 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__18 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__18 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__18 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__18 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__18 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__18 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__18 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__18 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__18 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__18 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair225" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__18
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__18));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__18),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__17
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized19
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__19 ;
  wire \n_0_current_state[3]_i_3__19 ;
  wire \n_0_current_state[3]_i_5__19 ;
  wire \n_0_current_state[3]_i_6__19 ;
  wire n_0_data_out_sel_i_1__19;
  wire \n_0_shadow[0]_i_1__19 ;
  wire \n_0_shadow[10]_i_1__19 ;
  wire \n_0_shadow[11]_i_1__19 ;
  wire \n_0_shadow[12]_i_1__19 ;
  wire \n_0_shadow[13]_i_1__19 ;
  wire \n_0_shadow[14]_i_1__19 ;
  wire \n_0_shadow[15]_i_1__19 ;
  wire \n_0_shadow[1]_i_1__19 ;
  wire \n_0_shadow[2]_i_1__19 ;
  wire \n_0_shadow[3]_i_1__19 ;
  wire \n_0_shadow[4]_i_1__19 ;
  wire \n_0_shadow[5]_i_1__19 ;
  wire \n_0_shadow[6]_i_1__19 ;
  wire \n_0_shadow[7]_i_1__19 ;
  wire \n_0_shadow[8]_i_1__19 ;
  wire \n_0_shadow[9]_i_1__19 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__19;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__19 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair230" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__19 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair230" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__19 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__19 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair228" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__19 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__20 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__19 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__19 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__20 
       (.I0(\n_0_current_state[3]_i_2__19 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__20 
       (.I0(\n_0_current_state[3]_i_2__19 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__19 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__20 
       (.I0(\n_0_current_state[3]_i_2__19 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__19 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair227" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__19 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__19 ));
(* SOFT_HLUTNM = "soft_lutpair228" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__19 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__19 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__19 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__19 ),
        .I3(\n_0_current_state[3]_i_6__19 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__19 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__19 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__19 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__19 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair229" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__19
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__19));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__19),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__19 ));
(* SOFT_HLUTNM = "soft_lutpair227" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__19 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__19 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__19 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__19 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__19 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__19 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__19 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__19 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__19 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__19 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__19 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__19 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__19 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__19 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__19 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__19 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__19 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__19 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__19 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__19 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair229" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__19
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__19));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__19),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__18
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized2
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__2 ;
  wire \n_0_current_state[3]_i_3__2 ;
  wire \n_0_current_state[3]_i_5__2 ;
  wire \n_0_current_state[3]_i_6__2 ;
  wire n_0_data_out_sel_i_1__2;
  wire \n_0_shadow[0]_i_1__2 ;
  wire \n_0_shadow[10]_i_1__2 ;
  wire \n_0_shadow[11]_i_1__2 ;
  wire \n_0_shadow[12]_i_1__2 ;
  wire \n_0_shadow[13]_i_1__2 ;
  wire \n_0_shadow[14]_i_1__2 ;
  wire \n_0_shadow[15]_i_1__2 ;
  wire \n_0_shadow[1]_i_1__2 ;
  wire \n_0_shadow[2]_i_1__2 ;
  wire \n_0_shadow[3]_i_1__2 ;
  wire \n_0_shadow[4]_i_1__2 ;
  wire \n_0_shadow[5]_i_1__2 ;
  wire \n_0_shadow[6]_i_1__2 ;
  wire \n_0_shadow[7]_i_1__2 ;
  wire \n_0_shadow[8]_i_1__2 ;
  wire \n_0_shadow[9]_i_1__2 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__2;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__2 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair86" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__2 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair86" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__2 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__2 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair84" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__2 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__3 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__2 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__2 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__3 
       (.I0(\n_0_current_state[3]_i_2__2 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__3 
       (.I0(\n_0_current_state[3]_i_2__2 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__2 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__3 
       (.I0(\n_0_current_state[3]_i_2__2 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__2 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair83" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__2 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__2 ));
(* SOFT_HLUTNM = "soft_lutpair84" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__2 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__2 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__2 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__2 ),
        .I3(\n_0_current_state[3]_i_6__2 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__2 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__2 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \current_state[3]_i_6__2 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__2 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair85" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__2
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__2));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__2),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__2 ));
(* SOFT_HLUTNM = "soft_lutpair83" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__2 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__2 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__2 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__2 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__2 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__2 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__2 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__2 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__2 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__2 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__2 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__2 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__2 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__2 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__2 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__2 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__2 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__2 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__2 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__2 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair85" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__2
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__2));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__2),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__1
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized20
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    s_do_o,
    I1,
    I2,
    I3,
    tc_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]s_do_o;
  input [15:0]I1;
  input [15:0]I2;
  input I3;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire [15:0]I1;
  wire [15:0]I2;
  wire I3;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__20 ;
  wire \n_0_current_state[3]_i_3__20 ;
  wire \n_0_current_state[3]_i_5__20 ;
  wire \n_0_current_state[3]_i_6__20 ;
  wire n_0_data_out_sel_i_1__20;
  wire \n_0_shadow[0]_i_1__20 ;
  wire \n_0_shadow[10]_i_1__20 ;
  wire \n_0_shadow[11]_i_1__20 ;
  wire \n_0_shadow[12]_i_1__20 ;
  wire \n_0_shadow[13]_i_1__20 ;
  wire \n_0_shadow[14]_i_1__20 ;
  wire \n_0_shadow[15]_i_1__20 ;
  wire \n_0_shadow[1]_i_1__20 ;
  wire \n_0_shadow[2]_i_1__20 ;
  wire \n_0_shadow[3]_i_1__20 ;
  wire \n_0_shadow[4]_i_1__20 ;
  wire \n_0_shadow[5]_i_1__20 ;
  wire \n_0_shadow[6]_i_1__20 ;
  wire \n_0_shadow[7]_i_1__20 ;
  wire \n_0_shadow[8]_i_1__20 ;
  wire \n_0_shadow[9]_i_1__20 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__20;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_tcConfig[5127]_21 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__20 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair234" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__20 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair234" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__20 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__20 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair232" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__20 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__21 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__20 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__20 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__21 
       (.I0(\n_0_current_state[3]_i_2__20 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__21 
       (.I0(\n_0_current_state[3]_i_2__20 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__20 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__21 
       (.I0(\n_0_current_state[3]_i_2__20 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__20 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair231" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__20 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__20 ));
(* SOFT_HLUTNM = "soft_lutpair232" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__20 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__20 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__20 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__20 ),
        .I3(\n_0_current_state[3]_i_6__20 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__20 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__20 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__20 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__20 ));
FDRE \current_state_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair233" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__20
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__20));
FDRE data_out_sel_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__20),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [1]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [11]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [12]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [13]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [14]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [15]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I3),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5127]_21 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [2]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [3]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [4]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [5]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [6]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [7]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [8]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [9]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5127]_21 [10]),
        .Q(\slaveRegDo_tcConfig[5127]_21 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__20 ));
(* SOFT_HLUTNM = "soft_lutpair231" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__20 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__20 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__20 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__20 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__20 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__20 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__20 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__20 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__20 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__20 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__20 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__20 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__20 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__20 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__20 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__20 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__20 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__20 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__20 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__20 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair233" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__20
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__20));
FDRE shift_en_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__20),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I1[0]),
        .I4(s_daddr_o[0]),
        .I5(I2[0]),
        .O(O16));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I1[10]),
        .I4(s_daddr_o[0]),
        .I5(I2[10]),
        .O(O6));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I1[11]),
        .I4(s_daddr_o[0]),
        .I5(I2[11]),
        .O(O5));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I1[12]),
        .I4(s_daddr_o[0]),
        .I5(I2[12]),
        .O(O4));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I1[13]),
        .I4(s_daddr_o[0]),
        .I5(I2[13]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I1[14]),
        .I4(s_daddr_o[0]),
        .I5(I2[14]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I1[15]),
        .I4(s_daddr_o[0]),
        .I5(I2[15]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I1[1]),
        .I4(s_daddr_o[0]),
        .I5(I2[1]),
        .O(O15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I1[2]),
        .I4(s_daddr_o[0]),
        .I5(I2[2]),
        .O(O14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I1[3]),
        .I4(s_daddr_o[0]),
        .I5(I2[3]),
        .O(O13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I1[4]),
        .I4(s_daddr_o[0]),
        .I5(I2[4]),
        .O(O12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I1[5]),
        .I4(s_daddr_o[0]),
        .I5(I2[5]),
        .O(O11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I1[6]),
        .I4(s_daddr_o[0]),
        .I5(I2[6]),
        .O(O10));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I1[7]),
        .I4(s_daddr_o[0]),
        .I5(I2[7]),
        .O(O9));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I1[8]),
        .I4(s_daddr_o[0]),
        .I5(I2[8]),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_13 
       (.I0(\slaveRegDo_tcConfig[5127]_21 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I1[9]),
        .I4(s_daddr_o[0]),
        .I5(I2[9]),
        .O(O7));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__19
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized21
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__21 ;
  wire \n_0_current_state[3]_i_3__21 ;
  wire \n_0_current_state[3]_i_5__21 ;
  wire \n_0_current_state[3]_i_6__21 ;
  wire n_0_data_out_sel_i_1__21;
  wire \n_0_shadow[0]_i_1__21 ;
  wire \n_0_shadow[10]_i_1__21 ;
  wire \n_0_shadow[11]_i_1__21 ;
  wire \n_0_shadow[12]_i_1__21 ;
  wire \n_0_shadow[13]_i_1__21 ;
  wire \n_0_shadow[14]_i_1__21 ;
  wire \n_0_shadow[15]_i_1__21 ;
  wire \n_0_shadow[1]_i_1__21 ;
  wire \n_0_shadow[2]_i_1__21 ;
  wire \n_0_shadow[3]_i_1__21 ;
  wire \n_0_shadow[4]_i_1__21 ;
  wire \n_0_shadow[5]_i_1__21 ;
  wire \n_0_shadow[6]_i_1__21 ;
  wire \n_0_shadow[7]_i_1__21 ;
  wire \n_0_shadow[8]_i_1__21 ;
  wire \n_0_shadow[9]_i_1__21 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__21;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__21 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair238" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__21 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair238" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__21 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__21 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair236" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__21 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__22 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__21 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__21 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__22 
       (.I0(\n_0_current_state[3]_i_2__21 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__22 
       (.I0(\n_0_current_state[3]_i_2__21 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__21 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__22 
       (.I0(\n_0_current_state[3]_i_2__21 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__21 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair235" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__21 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__21 ));
(* SOFT_HLUTNM = "soft_lutpair236" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__21 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__21 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__21 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__21 ),
        .I3(\n_0_current_state[3]_i_6__21 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__21 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__21 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__21 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__21 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair237" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__21
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__21));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__21),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__21 ));
(* SOFT_HLUTNM = "soft_lutpair235" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__21 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__21 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__21 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__21 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__21 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__21 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__21 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__21 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__21 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__21 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__21 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__21 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__21 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__21 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__21 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__21 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__21 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__21 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__21 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__21 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair237" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__21
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__21));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__21),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__20
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized22
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__22 ;
  wire \n_0_current_state[3]_i_3__22 ;
  wire \n_0_current_state[3]_i_5__22 ;
  wire \n_0_current_state[3]_i_6__22 ;
  wire n_0_data_out_sel_i_1__22;
  wire \n_0_shadow[0]_i_1__22 ;
  wire \n_0_shadow[10]_i_1__22 ;
  wire \n_0_shadow[11]_i_1__22 ;
  wire \n_0_shadow[12]_i_1__22 ;
  wire \n_0_shadow[13]_i_1__22 ;
  wire \n_0_shadow[14]_i_1__22 ;
  wire \n_0_shadow[15]_i_1__22 ;
  wire \n_0_shadow[1]_i_1__22 ;
  wire \n_0_shadow[2]_i_1__22 ;
  wire \n_0_shadow[3]_i_1__22 ;
  wire \n_0_shadow[4]_i_1__22 ;
  wire \n_0_shadow[5]_i_1__22 ;
  wire \n_0_shadow[6]_i_1__22 ;
  wire \n_0_shadow[7]_i_1__22 ;
  wire \n_0_shadow[8]_i_1__22 ;
  wire \n_0_shadow[9]_i_1__22 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__22;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__22 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair242" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__22 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair242" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__22 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__22 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair240" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__22 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__23 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__22 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__22 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__23 
       (.I0(\n_0_current_state[3]_i_2__22 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__23 
       (.I0(\n_0_current_state[3]_i_2__22 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__22 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__23 
       (.I0(\n_0_current_state[3]_i_2__22 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__22 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair239" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__22 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__22 ));
(* SOFT_HLUTNM = "soft_lutpair240" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__22 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__22 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__22 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__22 ),
        .I3(\n_0_current_state[3]_i_6__22 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__22 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__22 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__22 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__22 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair241" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__22
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__22));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__22),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__22 ));
(* SOFT_HLUTNM = "soft_lutpair239" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__22 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__22 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__22 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__22 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__22 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__22 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__22 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__22 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__22 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__22 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__22 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__22 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__22 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__22 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__22 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__22 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__22 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__22 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__22 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__22 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair241" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__22
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__22));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__22),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__21
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized23
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__23 ;
  wire \n_0_current_state[3]_i_3__23 ;
  wire \n_0_current_state[3]_i_5__23 ;
  wire \n_0_current_state[3]_i_6__23 ;
  wire n_0_data_out_sel_i_1__23;
  wire \n_0_shadow[0]_i_1__23 ;
  wire \n_0_shadow[10]_i_1__23 ;
  wire \n_0_shadow[11]_i_1__23 ;
  wire \n_0_shadow[12]_i_1__23 ;
  wire \n_0_shadow[13]_i_1__23 ;
  wire \n_0_shadow[14]_i_1__23 ;
  wire \n_0_shadow[15]_i_1__23 ;
  wire \n_0_shadow[1]_i_1__23 ;
  wire \n_0_shadow[2]_i_1__23 ;
  wire \n_0_shadow[3]_i_1__23 ;
  wire \n_0_shadow[4]_i_1__23 ;
  wire \n_0_shadow[5]_i_1__23 ;
  wire \n_0_shadow[6]_i_1__23 ;
  wire \n_0_shadow[7]_i_1__23 ;
  wire \n_0_shadow[8]_i_1__23 ;
  wire \n_0_shadow[9]_i_1__23 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__23;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__23 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair122" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__23 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair122" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__23 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__23 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair120" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__23 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__24 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__23 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__23 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__24 
       (.I0(\n_0_current_state[3]_i_2__23 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__24 
       (.I0(\n_0_current_state[3]_i_2__23 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__23 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__24 
       (.I0(\n_0_current_state[3]_i_2__23 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__23 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair119" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__23 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__23 ));
(* SOFT_HLUTNM = "soft_lutpair120" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__23 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__23 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__23 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__23 ),
        .I3(\n_0_current_state[3]_i_6__23 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__23 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__23 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__23 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__23 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair121" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__23
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__23));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__23),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__23 ));
(* SOFT_HLUTNM = "soft_lutpair119" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__23 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__23 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__23 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__23 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__23 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__23 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__23 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__23 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__23 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__23 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__23 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__23 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__23 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__23 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__23 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__23 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__23 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__23 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__23 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__23 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair121" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__23
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__23));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__23),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__22
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized24
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    s_do_o,
    Q,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    tc_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [15:0]s_do_o;
  input [15:0]Q;
  input [15:0]I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire [15:0]I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__24 ;
  wire \n_0_current_state[3]_i_3__24 ;
  wire \n_0_current_state[3]_i_5__24 ;
  wire \n_0_current_state[3]_i_6__24 ;
  wire n_0_data_out_sel_i_1__24;
  wire \n_0_shadow[0]_i_1__24 ;
  wire \n_0_shadow[10]_i_1__24 ;
  wire \n_0_shadow[11]_i_1__24 ;
  wire \n_0_shadow[12]_i_1__24 ;
  wire \n_0_shadow[13]_i_1__24 ;
  wire \n_0_shadow[14]_i_1__24 ;
  wire \n_0_shadow[15]_i_1__24 ;
  wire \n_0_shadow[1]_i_1__24 ;
  wire \n_0_shadow[2]_i_1__24 ;
  wire \n_0_shadow[3]_i_1__24 ;
  wire \n_0_shadow[4]_i_1__24 ;
  wire \n_0_shadow[5]_i_1__24 ;
  wire \n_0_shadow[6]_i_1__24 ;
  wire \n_0_shadow[7]_i_1__24 ;
  wire \n_0_shadow[8]_i_1__24 ;
  wire \n_0_shadow[9]_i_1__24 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__24;
  wire \n_0_slaveRegDo_mux_5[0]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[10]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[11]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[12]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[13]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[14]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[15]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[1]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[2]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[3]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[4]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[5]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[6]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[7]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[8]_i_10 ;
  wire \n_0_slaveRegDo_mux_5[9]_i_10 ;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_tcConfig[5131]_25 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__24 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair126" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__24 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair126" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__24 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__24 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair124" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__24 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I18),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I18),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I18),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I18),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__25 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__24 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__24 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__25 
       (.I0(\n_0_current_state[3]_i_2__24 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__25 
       (.I0(\n_0_current_state[3]_i_2__24 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__24 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__25 
       (.I0(\n_0_current_state[3]_i_2__24 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__24 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair123" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__24 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__24 ));
(* SOFT_HLUTNM = "soft_lutpair124" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__24 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__24 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__24 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__24 ),
        .I3(\n_0_current_state[3]_i_6__24 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__24 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__24 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__24 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__24 ));
FDRE \current_state_reg[0] 
       (.C(I18),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I18),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I18),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I18),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair125" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__24
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__24));
FDRE data_out_sel_reg
       (.C(I18),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__24),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [1]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [11]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [12]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [13]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [14]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [15]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I18),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5131]_25 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [2]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [3]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [4]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [5]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [6]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [7]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [8]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [9]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I18),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5131]_25 [10]),
        .Q(\slaveRegDo_tcConfig[5131]_25 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__24 ));
(* SOFT_HLUTNM = "soft_lutpair123" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__24 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__24 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__24 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__24 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__24 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__24 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__24 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__24 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__24 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__24 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__24 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__24 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__24 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__24 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__24 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__24 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__24 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__24 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__24 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I18),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__24 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair125" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__24
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__24));
FDRE shift_en_reg
       (.C(I18),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__24),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(Q[0]),
        .I4(s_daddr_o[0]),
        .I5(I2[0]),
        .O(\n_0_slaveRegDo_mux_5[0]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(Q[10]),
        .I4(s_daddr_o[0]),
        .I5(I2[10]),
        .O(\n_0_slaveRegDo_mux_5[10]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(Q[11]),
        .I4(s_daddr_o[0]),
        .I5(I2[11]),
        .O(\n_0_slaveRegDo_mux_5[11]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(Q[12]),
        .I4(s_daddr_o[0]),
        .I5(I2[12]),
        .O(\n_0_slaveRegDo_mux_5[12]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(Q[13]),
        .I4(s_daddr_o[0]),
        .I5(I2[13]),
        .O(\n_0_slaveRegDo_mux_5[13]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(Q[14]),
        .I4(s_daddr_o[0]),
        .I5(I2[14]),
        .O(\n_0_slaveRegDo_mux_5[14]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(Q[15]),
        .I4(s_daddr_o[0]),
        .I5(I2[15]),
        .O(\n_0_slaveRegDo_mux_5[15]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(Q[1]),
        .I4(s_daddr_o[0]),
        .I5(I2[1]),
        .O(\n_0_slaveRegDo_mux_5[1]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(Q[2]),
        .I4(s_daddr_o[0]),
        .I5(I2[2]),
        .O(\n_0_slaveRegDo_mux_5[2]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(Q[3]),
        .I4(s_daddr_o[0]),
        .I5(I2[3]),
        .O(\n_0_slaveRegDo_mux_5[3]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(Q[4]),
        .I4(s_daddr_o[0]),
        .I5(I2[4]),
        .O(\n_0_slaveRegDo_mux_5[4]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(Q[5]),
        .I4(s_daddr_o[0]),
        .I5(I2[5]),
        .O(\n_0_slaveRegDo_mux_5[5]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(Q[6]),
        .I4(s_daddr_o[0]),
        .I5(I2[6]),
        .O(\n_0_slaveRegDo_mux_5[6]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(Q[7]),
        .I4(s_daddr_o[0]),
        .I5(I2[7]),
        .O(\n_0_slaveRegDo_mux_5[7]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(Q[8]),
        .I4(s_daddr_o[0]),
        .I5(I2[8]),
        .O(\n_0_slaveRegDo_mux_5[8]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_10 
       (.I0(\slaveRegDo_tcConfig[5131]_25 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(Q[9]),
        .I4(s_daddr_o[0]),
        .I5(I2[9]),
        .O(\n_0_slaveRegDo_mux_5[9]_i_10 ));
MUXF7 \slaveRegDo_mux_5_reg[0]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[0]_i_10 ),
        .I1(I17),
        .O(O16),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[10]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[10]_i_10 ),
        .I1(I7),
        .O(O6),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[11]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[11]_i_10 ),
        .I1(I6),
        .O(O5),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[12]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[12]_i_10 ),
        .I1(I5),
        .O(O4),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[13]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[13]_i_10 ),
        .I1(I4),
        .O(O3),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[14]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[14]_i_10 ),
        .I1(I3),
        .O(O2),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[15]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[15]_i_10 ),
        .I1(I1),
        .O(O1),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[1]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[1]_i_10 ),
        .I1(I16),
        .O(O15),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[2]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[2]_i_10 ),
        .I1(I15),
        .O(O14),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[3]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[3]_i_10 ),
        .I1(I14),
        .O(O13),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[4]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[4]_i_10 ),
        .I1(I13),
        .O(O12),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[5]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[5]_i_10 ),
        .I1(I12),
        .O(O11),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[6]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[6]_i_10 ),
        .I1(I11),
        .O(O10),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[7]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[7]_i_10 ),
        .I1(I10),
        .O(O9),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[8]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[8]_i_10 ),
        .I1(I9),
        .O(O8),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[9]_i_4 
       (.I0(\n_0_slaveRegDo_mux_5[9]_i_10 ),
        .I1(I8),
        .O(O7),
        .S(s_daddr_o[2]));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__23
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized25
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__25 ;
  wire \n_0_current_state[3]_i_3__25 ;
  wire \n_0_current_state[3]_i_5__25 ;
  wire \n_0_current_state[3]_i_6__25 ;
  wire n_0_data_out_sel_i_1__25;
  wire \n_0_shadow[0]_i_1__25 ;
  wire \n_0_shadow[10]_i_1__25 ;
  wire \n_0_shadow[11]_i_1__25 ;
  wire \n_0_shadow[12]_i_1__25 ;
  wire \n_0_shadow[13]_i_1__25 ;
  wire \n_0_shadow[14]_i_1__25 ;
  wire \n_0_shadow[15]_i_1__25 ;
  wire \n_0_shadow[1]_i_1__25 ;
  wire \n_0_shadow[2]_i_1__25 ;
  wire \n_0_shadow[3]_i_1__25 ;
  wire \n_0_shadow[4]_i_1__25 ;
  wire \n_0_shadow[5]_i_1__25 ;
  wire \n_0_shadow[6]_i_1__25 ;
  wire \n_0_shadow[7]_i_1__25 ;
  wire \n_0_shadow[8]_i_1__25 ;
  wire \n_0_shadow[9]_i_1__25 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__25;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__25 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair130" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__25 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair130" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__25 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__25 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair128" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__25 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__26 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__25 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__25 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__26 
       (.I0(\n_0_current_state[3]_i_2__25 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__26 
       (.I0(\n_0_current_state[3]_i_2__25 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__25 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__26 
       (.I0(\n_0_current_state[3]_i_2__25 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__25 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair127" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__25 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__25 ));
(* SOFT_HLUTNM = "soft_lutpair128" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__25 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__25 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__25 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__25 ),
        .I3(\n_0_current_state[3]_i_6__25 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__25 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__25 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__25 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__25 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair129" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__25
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__25));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__25),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__25 ));
(* SOFT_HLUTNM = "soft_lutpair127" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__25 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__25 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__25 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__25 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__25 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__25 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__25 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__25 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__25 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__25 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__25 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__25 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__25 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__25 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__25 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__25 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__25 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__25 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__25 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__25 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair129" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__25
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__25));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__25),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__24
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized26
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__26 ;
  wire \n_0_current_state[3]_i_3__26 ;
  wire \n_0_current_state[3]_i_5__26 ;
  wire \n_0_current_state[3]_i_6__26 ;
  wire n_0_data_out_sel_i_1__26;
  wire \n_0_shadow[0]_i_1__26 ;
  wire \n_0_shadow[10]_i_1__26 ;
  wire \n_0_shadow[11]_i_1__26 ;
  wire \n_0_shadow[12]_i_1__26 ;
  wire \n_0_shadow[13]_i_1__26 ;
  wire \n_0_shadow[14]_i_1__26 ;
  wire \n_0_shadow[15]_i_1__26 ;
  wire \n_0_shadow[1]_i_1__26 ;
  wire \n_0_shadow[2]_i_1__26 ;
  wire \n_0_shadow[3]_i_1__26 ;
  wire \n_0_shadow[4]_i_1__26 ;
  wire \n_0_shadow[5]_i_1__26 ;
  wire \n_0_shadow[6]_i_1__26 ;
  wire \n_0_shadow[7]_i_1__26 ;
  wire \n_0_shadow[8]_i_1__26 ;
  wire \n_0_shadow[9]_i_1__26 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__26;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__26 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair134" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__26 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair134" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__26 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__26 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair132" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__26 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__27 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__26 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__26 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__27 
       (.I0(\n_0_current_state[3]_i_2__26 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__27 
       (.I0(\n_0_current_state[3]_i_2__26 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__26 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__27 
       (.I0(\n_0_current_state[3]_i_2__26 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__26 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair131" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__26 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__26 ));
(* SOFT_HLUTNM = "soft_lutpair132" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__26 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__26 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__26 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__26 ),
        .I3(\n_0_current_state[3]_i_6__26 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__26 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__26 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__26 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__26 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair133" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__26
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__26));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__26),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__26 ));
(* SOFT_HLUTNM = "soft_lutpair131" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__26 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__26 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__26 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__26 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__26 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__26 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__26 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__26 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__26 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__26 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__26 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__26 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__26 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__26 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__26 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__26 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__26 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__26 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__26 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__26 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair133" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__26
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__26));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__26),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__25
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized27
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__27 ;
  wire \n_0_current_state[3]_i_3__27 ;
  wire \n_0_current_state[3]_i_5__27 ;
  wire \n_0_current_state[3]_i_6__27 ;
  wire n_0_data_out_sel_i_1__27;
  wire \n_0_shadow[0]_i_1__27 ;
  wire \n_0_shadow[10]_i_1__27 ;
  wire \n_0_shadow[11]_i_1__27 ;
  wire \n_0_shadow[12]_i_1__27 ;
  wire \n_0_shadow[13]_i_1__27 ;
  wire \n_0_shadow[14]_i_1__27 ;
  wire \n_0_shadow[15]_i_1__27 ;
  wire \n_0_shadow[1]_i_1__27 ;
  wire \n_0_shadow[2]_i_1__27 ;
  wire \n_0_shadow[3]_i_1__27 ;
  wire \n_0_shadow[4]_i_1__27 ;
  wire \n_0_shadow[5]_i_1__27 ;
  wire \n_0_shadow[6]_i_1__27 ;
  wire \n_0_shadow[7]_i_1__27 ;
  wire \n_0_shadow[8]_i_1__27 ;
  wire \n_0_shadow[9]_i_1__27 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__27;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__27 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair138" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__27 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair138" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__27 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__27 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair136" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__27 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__28 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__27 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__27 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__28 
       (.I0(\n_0_current_state[3]_i_2__27 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__28 
       (.I0(\n_0_current_state[3]_i_2__27 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__27 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__28 
       (.I0(\n_0_current_state[3]_i_2__27 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__27 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair135" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__27 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__27 ));
(* SOFT_HLUTNM = "soft_lutpair136" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__27 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__27 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__27 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__27 ),
        .I3(\n_0_current_state[3]_i_6__27 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__27 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__27 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__27 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__27 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair137" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__27
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__27));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__27),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__27 ));
(* SOFT_HLUTNM = "soft_lutpair135" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__27 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__27 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__27 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__27 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__27 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__27 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__27 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__27 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__27 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__27 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__27 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__27 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__27 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__27 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__27 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__27 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__27 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__27 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__27 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__27 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair137" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__27
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__27));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__27),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__26
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized28
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    s_do_o,
    I1,
    I2,
    I3,
    tc_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]s_do_o;
  input [15:0]I1;
  input [15:0]I2;
  input I3;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire [15:0]I1;
  wire [15:0]I2;
  wire I3;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__28 ;
  wire \n_0_current_state[3]_i_3__28 ;
  wire \n_0_current_state[3]_i_5__28 ;
  wire \n_0_current_state[3]_i_6__28 ;
  wire n_0_data_out_sel_i_1__28;
  wire \n_0_shadow[0]_i_1__28 ;
  wire \n_0_shadow[10]_i_1__28 ;
  wire \n_0_shadow[11]_i_1__28 ;
  wire \n_0_shadow[12]_i_1__28 ;
  wire \n_0_shadow[13]_i_1__28 ;
  wire \n_0_shadow[14]_i_1__28 ;
  wire \n_0_shadow[15]_i_1__28 ;
  wire \n_0_shadow[1]_i_1__28 ;
  wire \n_0_shadow[2]_i_1__28 ;
  wire \n_0_shadow[3]_i_1__28 ;
  wire \n_0_shadow[4]_i_1__28 ;
  wire \n_0_shadow[5]_i_1__28 ;
  wire \n_0_shadow[6]_i_1__28 ;
  wire \n_0_shadow[7]_i_1__28 ;
  wire \n_0_shadow[8]_i_1__28 ;
  wire \n_0_shadow[9]_i_1__28 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__28;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_tcConfig[5135]_29 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__28 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair142" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__28 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair142" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__28 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__28 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair140" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__28 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__29 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__28 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__28 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__29 
       (.I0(\n_0_current_state[3]_i_2__28 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__29 
       (.I0(\n_0_current_state[3]_i_2__28 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__28 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__29 
       (.I0(\n_0_current_state[3]_i_2__28 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__28 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair139" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__28 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__28 ));
(* SOFT_HLUTNM = "soft_lutpair140" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__28 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__28 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__28 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__28 ),
        .I3(\n_0_current_state[3]_i_6__28 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__28 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__28 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__28 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__28 ));
FDRE \current_state_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair141" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__28
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__28));
FDRE data_out_sel_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__28),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [1]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [11]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [12]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [13]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [14]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [15]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I3),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5135]_29 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [2]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [3]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [4]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [5]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [6]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [7]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [8]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [9]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5135]_29 [10]),
        .Q(\slaveRegDo_tcConfig[5135]_29 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__28 ));
(* SOFT_HLUTNM = "soft_lutpair139" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__28 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__28 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__28 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__28 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__28 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__28 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__28 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__28 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__28 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__28 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__28 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__28 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__28 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__28 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__28 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__28 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__28 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__28 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__28 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__28 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair141" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__28
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__28));
FDRE shift_en_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__28),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I1[0]),
        .I4(s_daddr_o[0]),
        .I5(I2[0]),
        .O(O16));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I1[10]),
        .I4(s_daddr_o[0]),
        .I5(I2[10]),
        .O(O6));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I1[11]),
        .I4(s_daddr_o[0]),
        .I5(I2[11]),
        .O(O5));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I1[12]),
        .I4(s_daddr_o[0]),
        .I5(I2[12]),
        .O(O4));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I1[13]),
        .I4(s_daddr_o[0]),
        .I5(I2[13]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I1[14]),
        .I4(s_daddr_o[0]),
        .I5(I2[14]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I1[15]),
        .I4(s_daddr_o[0]),
        .I5(I2[15]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I1[1]),
        .I4(s_daddr_o[0]),
        .I5(I2[1]),
        .O(O15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I1[2]),
        .I4(s_daddr_o[0]),
        .I5(I2[2]),
        .O(O14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I1[3]),
        .I4(s_daddr_o[0]),
        .I5(I2[3]),
        .O(O13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I1[4]),
        .I4(s_daddr_o[0]),
        .I5(I2[4]),
        .O(O12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I1[5]),
        .I4(s_daddr_o[0]),
        .I5(I2[5]),
        .O(O11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I1[6]),
        .I4(s_daddr_o[0]),
        .I5(I2[6]),
        .O(O10));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I1[7]),
        .I4(s_daddr_o[0]),
        .I5(I2[7]),
        .O(O9));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I1[8]),
        .I4(s_daddr_o[0]),
        .I5(I2[8]),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_11 
       (.I0(\slaveRegDo_tcConfig[5135]_29 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I1[9]),
        .I4(s_daddr_o[0]),
        .I5(I2[9]),
        .O(O7));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__27
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized29
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__29 ;
  wire \n_0_current_state[3]_i_3__29 ;
  wire \n_0_current_state[3]_i_5__29 ;
  wire \n_0_current_state[3]_i_6__29 ;
  wire n_0_data_out_sel_i_1__29;
  wire \n_0_shadow[0]_i_1__29 ;
  wire \n_0_shadow[10]_i_1__29 ;
  wire \n_0_shadow[11]_i_1__29 ;
  wire \n_0_shadow[12]_i_1__29 ;
  wire \n_0_shadow[13]_i_1__29 ;
  wire \n_0_shadow[14]_i_1__29 ;
  wire \n_0_shadow[15]_i_1__29 ;
  wire \n_0_shadow[1]_i_1__29 ;
  wire \n_0_shadow[2]_i_1__29 ;
  wire \n_0_shadow[3]_i_1__29 ;
  wire \n_0_shadow[4]_i_1__29 ;
  wire \n_0_shadow[5]_i_1__29 ;
  wire \n_0_shadow[6]_i_1__29 ;
  wire \n_0_shadow[7]_i_1__29 ;
  wire \n_0_shadow[8]_i_1__29 ;
  wire \n_0_shadow[9]_i_1__29 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__29;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__29 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair146" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__29 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair146" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__29 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__29 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair144" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__29 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__30 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__29 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__29 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__30 
       (.I0(\n_0_current_state[3]_i_2__29 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__30 
       (.I0(\n_0_current_state[3]_i_2__29 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__29 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__30 
       (.I0(\n_0_current_state[3]_i_2__29 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__29 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair143" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__29 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__29 ));
(* SOFT_HLUTNM = "soft_lutpair144" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__29 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__29 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__29 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__29 ),
        .I3(\n_0_current_state[3]_i_6__29 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__29 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__29 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__29 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__29 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair145" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__29
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__29));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__29),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__29 ));
(* SOFT_HLUTNM = "soft_lutpair143" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__29 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__29 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__29 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__29 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__29 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__29 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__29 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__29 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__29 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__29 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__29 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__29 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__29 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__29 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__29 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__29 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__29 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__29 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__29 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__29 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair145" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__29
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__29));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__29),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__28
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized3
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    s_do_o,
    I1,
    I2,
    I3,
    mu_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]s_do_o;
  input [15:0]I1;
  input [15:0]I2;
  input I3;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire [15:0]I1;
  wire [15:0]I2;
  wire I3;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__3 ;
  wire \n_0_current_state[3]_i_3__3 ;
  wire \n_0_current_state[3]_i_5__3 ;
  wire \n_0_current_state[3]_i_6__3 ;
  wire n_0_data_out_sel_i_1__3;
  wire \n_0_shadow[0]_i_1__3 ;
  wire \n_0_shadow[10]_i_1__3 ;
  wire \n_0_shadow[11]_i_1__3 ;
  wire \n_0_shadow[12]_i_1__3 ;
  wire \n_0_shadow[13]_i_1__3 ;
  wire \n_0_shadow[14]_i_1__3 ;
  wire \n_0_shadow[15]_i_1__3 ;
  wire \n_0_shadow[1]_i_1__3 ;
  wire \n_0_shadow[2]_i_1__3 ;
  wire \n_0_shadow[3]_i_1__3 ;
  wire \n_0_shadow[4]_i_1__3 ;
  wire \n_0_shadow[5]_i_1__3 ;
  wire \n_0_shadow[6]_i_1__3 ;
  wire \n_0_shadow[7]_i_1__3 ;
  wire \n_0_shadow[8]_i_1__3 ;
  wire \n_0_shadow[9]_i_1__3 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__3;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_muConfig[4099]_4 ;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__3 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair90" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__3 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair90" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__3 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__3 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair88" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__3 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__4 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__3 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__3 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__4 
       (.I0(\n_0_current_state[3]_i_2__3 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__4 
       (.I0(\n_0_current_state[3]_i_2__3 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__3 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__4 
       (.I0(\n_0_current_state[3]_i_2__3 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__3 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair87" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__3 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__3 ));
(* SOFT_HLUTNM = "soft_lutpair88" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__3 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__3 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__3 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__3 ),
        .I3(\n_0_current_state[3]_i_6__3 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__3 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__3 ));
LUT6 #(
    .INIT(64'h0000000000004000)) 
     \current_state[3]_i_6__3 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__3 ));
FDRE \current_state_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair89" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__3
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__3));
FDRE data_out_sel_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__3),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [1]),
        .Q(\slaveRegDo_muConfig[4099]_4 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [11]),
        .Q(\slaveRegDo_muConfig[4099]_4 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [12]),
        .Q(\slaveRegDo_muConfig[4099]_4 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [13]),
        .Q(\slaveRegDo_muConfig[4099]_4 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [14]),
        .Q(\slaveRegDo_muConfig[4099]_4 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [15]),
        .Q(\slaveRegDo_muConfig[4099]_4 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I3),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(\slaveRegDo_muConfig[4099]_4 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [2]),
        .Q(\slaveRegDo_muConfig[4099]_4 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [3]),
        .Q(\slaveRegDo_muConfig[4099]_4 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [4]),
        .Q(\slaveRegDo_muConfig[4099]_4 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [5]),
        .Q(\slaveRegDo_muConfig[4099]_4 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [6]),
        .Q(\slaveRegDo_muConfig[4099]_4 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [7]),
        .Q(\slaveRegDo_muConfig[4099]_4 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [8]),
        .Q(\slaveRegDo_muConfig[4099]_4 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [9]),
        .Q(\slaveRegDo_muConfig[4099]_4 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4099]_4 [10]),
        .Q(\slaveRegDo_muConfig[4099]_4 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__3 ));
(* SOFT_HLUTNM = "soft_lutpair87" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__3 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__3 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__3 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__3 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__3 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__3 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__3 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__3 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__3 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__3 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__3 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__3 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__3 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__3 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__3 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__3 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__3 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__3 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__3 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__3 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair89" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__3
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__3));
FDRE shift_en_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__3),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[0]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I1[0]),
        .I4(s_daddr_o[0]),
        .I5(I2[0]),
        .O(O16));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[10]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I1[10]),
        .I4(s_daddr_o[0]),
        .I5(I2[10]),
        .O(O6));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[11]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I1[11]),
        .I4(s_daddr_o[0]),
        .I5(I2[11]),
        .O(O5));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[12]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I1[12]),
        .I4(s_daddr_o[0]),
        .I5(I2[12]),
        .O(O4));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[13]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I1[13]),
        .I4(s_daddr_o[0]),
        .I5(I2[13]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[14]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I1[14]),
        .I4(s_daddr_o[0]),
        .I5(I2[14]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[15]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I1[15]),
        .I4(s_daddr_o[0]),
        .I5(I2[15]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[1]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I1[1]),
        .I4(s_daddr_o[0]),
        .I5(I2[1]),
        .O(O15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[2]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I1[2]),
        .I4(s_daddr_o[0]),
        .I5(I2[2]),
        .O(O14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[3]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I1[3]),
        .I4(s_daddr_o[0]),
        .I5(I2[3]),
        .O(O13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[4]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I1[4]),
        .I4(s_daddr_o[0]),
        .I5(I2[4]),
        .O(O12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[5]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I1[5]),
        .I4(s_daddr_o[0]),
        .I5(I2[5]),
        .O(O11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[6]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I1[6]),
        .I4(s_daddr_o[0]),
        .I5(I2[6]),
        .O(O10));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[7]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I1[7]),
        .I4(s_daddr_o[0]),
        .I5(I2[7]),
        .O(O9));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[8]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I1[8]),
        .I4(s_daddr_o[0]),
        .I5(I2[8]),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[9]_i_4 
       (.I0(\slaveRegDo_muConfig[4099]_4 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I1[9]),
        .I4(s_daddr_o[0]),
        .I5(I2[9]),
        .O(O7));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__2
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized30
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__30 ;
  wire \n_0_current_state[3]_i_3__30 ;
  wire \n_0_current_state[3]_i_5__30 ;
  wire \n_0_current_state[3]_i_6__30 ;
  wire n_0_data_out_sel_i_1__30;
  wire \n_0_shadow[0]_i_1__30 ;
  wire \n_0_shadow[10]_i_1__30 ;
  wire \n_0_shadow[11]_i_1__30 ;
  wire \n_0_shadow[12]_i_1__30 ;
  wire \n_0_shadow[13]_i_1__30 ;
  wire \n_0_shadow[14]_i_1__30 ;
  wire \n_0_shadow[15]_i_1__30 ;
  wire \n_0_shadow[1]_i_1__30 ;
  wire \n_0_shadow[2]_i_1__30 ;
  wire \n_0_shadow[3]_i_1__30 ;
  wire \n_0_shadow[4]_i_1__30 ;
  wire \n_0_shadow[5]_i_1__30 ;
  wire \n_0_shadow[6]_i_1__30 ;
  wire \n_0_shadow[7]_i_1__30 ;
  wire \n_0_shadow[8]_i_1__30 ;
  wire \n_0_shadow[9]_i_1__30 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__30;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__30 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair150" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__30 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair150" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__30 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__30 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair148" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__30 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__31 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__30 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__30 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__31 
       (.I0(\n_0_current_state[3]_i_2__30 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__31 
       (.I0(\n_0_current_state[3]_i_2__30 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__30 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__31 
       (.I0(\n_0_current_state[3]_i_2__30 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__30 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair147" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__30 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__30 ));
(* SOFT_HLUTNM = "soft_lutpair148" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__30 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__30 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__30 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__30 ),
        .I3(\n_0_current_state[3]_i_6__30 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__30 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__30 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__30 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__30 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair149" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__30
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__30));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__30),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__30 ));
(* SOFT_HLUTNM = "soft_lutpair147" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__30 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__30 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__30 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__30 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__30 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__30 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__30 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__30 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__30 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__30 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__30 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__30 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__30 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__30 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__30 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__30 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__30 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__30 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__30 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__30 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair149" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__30
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__30));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__30),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__29
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized31
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__31 ;
  wire \n_0_current_state[3]_i_3__31 ;
  wire \n_0_current_state[3]_i_5__31 ;
  wire \n_0_current_state[3]_i_6__31 ;
  wire n_0_data_out_sel_i_1__31;
  wire \n_0_shadow[0]_i_1__31 ;
  wire \n_0_shadow[10]_i_1__31 ;
  wire \n_0_shadow[11]_i_1__31 ;
  wire \n_0_shadow[12]_i_1__31 ;
  wire \n_0_shadow[13]_i_1__31 ;
  wire \n_0_shadow[14]_i_1__31 ;
  wire \n_0_shadow[15]_i_1__31 ;
  wire \n_0_shadow[1]_i_1__31 ;
  wire \n_0_shadow[2]_i_1__31 ;
  wire \n_0_shadow[3]_i_1__31 ;
  wire \n_0_shadow[4]_i_1__31 ;
  wire \n_0_shadow[5]_i_1__31 ;
  wire \n_0_shadow[6]_i_1__31 ;
  wire \n_0_shadow[7]_i_1__31 ;
  wire \n_0_shadow[8]_i_1__31 ;
  wire \n_0_shadow[9]_i_1__31 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__31;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__31 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair154" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__31 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair154" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__31 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__31 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair152" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__31 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__32 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__31 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__31 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__32 
       (.I0(\n_0_current_state[3]_i_2__31 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__32 
       (.I0(\n_0_current_state[3]_i_2__31 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__31 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__32 
       (.I0(\n_0_current_state[3]_i_2__31 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__31 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair151" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__31 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__31 ));
(* SOFT_HLUTNM = "soft_lutpair152" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__31 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__31 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__31 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__31 ),
        .I3(\n_0_current_state[3]_i_6__31 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__31 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__31 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__31 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__31 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair153" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__31
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__31));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__31),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__31 ));
(* SOFT_HLUTNM = "soft_lutpair151" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__31 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__31 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__31 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__31 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__31 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__31 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__31 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__31 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__31 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__31 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__31 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__31 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__31 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__31 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__31 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__31 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__31 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__31 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__31 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__31 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair153" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__31
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__31));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__31),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__30
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized32
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    s_do_o,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    tc_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [15:0]s_do_o;
  input [15:0]I2;
  input [15:0]I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire [15:0]I2;
  wire [15:0]I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__32 ;
  wire \n_0_current_state[3]_i_3__32 ;
  wire \n_0_current_state[3]_i_5__32 ;
  wire \n_0_current_state[3]_i_6__32 ;
  wire n_0_data_out_sel_i_1__32;
  wire \n_0_shadow[0]_i_1__32 ;
  wire \n_0_shadow[10]_i_1__32 ;
  wire \n_0_shadow[11]_i_1__32 ;
  wire \n_0_shadow[12]_i_1__32 ;
  wire \n_0_shadow[13]_i_1__32 ;
  wire \n_0_shadow[14]_i_1__32 ;
  wire \n_0_shadow[15]_i_1__32 ;
  wire \n_0_shadow[1]_i_1__32 ;
  wire \n_0_shadow[2]_i_1__32 ;
  wire \n_0_shadow[3]_i_1__32 ;
  wire \n_0_shadow[4]_i_1__32 ;
  wire \n_0_shadow[5]_i_1__32 ;
  wire \n_0_shadow[6]_i_1__32 ;
  wire \n_0_shadow[7]_i_1__32 ;
  wire \n_0_shadow[8]_i_1__32 ;
  wire \n_0_shadow[9]_i_1__32 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__32;
  wire \n_0_slaveRegDo_mux_5[0]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[10]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[11]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[12]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[13]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[14]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[15]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[1]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[2]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[3]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[4]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[5]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[6]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[7]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[8]_i_8 ;
  wire \n_0_slaveRegDo_mux_5[9]_i_8 ;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_tcConfig[5139]_33 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__32 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair158" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__32 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair158" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__32 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__32 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair156" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__32 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I19),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I19),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I19),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I19),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__33 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__32 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__32 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__33 
       (.I0(\n_0_current_state[3]_i_2__32 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__33 
       (.I0(\n_0_current_state[3]_i_2__32 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__32 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__33 
       (.I0(\n_0_current_state[3]_i_2__32 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__32 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair155" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__32 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__32 ));
(* SOFT_HLUTNM = "soft_lutpair156" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__32 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__32 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__32 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__32 ),
        .I3(\n_0_current_state[3]_i_6__32 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__32 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__32 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__32 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__32 ));
FDRE \current_state_reg[0] 
       (.C(I19),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I19),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I19),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I19),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair157" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__32
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__32));
FDRE data_out_sel_reg
       (.C(I19),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__32),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [1]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [11]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [12]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [13]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [14]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [15]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I19),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5139]_33 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [2]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [3]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [4]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [5]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [6]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [7]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [8]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [9]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I19),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5139]_33 [10]),
        .Q(\slaveRegDo_tcConfig[5139]_33 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__32 ));
(* SOFT_HLUTNM = "soft_lutpair155" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__32 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__32 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__32 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__32 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__32 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__32 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__32 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__32 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__32 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__32 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__32 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__32 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__32 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__32 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__32 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__32 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__32 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__32 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__32 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I19),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__32 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair157" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__32
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__32));
FDRE shift_en_reg
       (.C(I19),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__32),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I2[0]),
        .I4(s_daddr_o[0]),
        .I5(I3[0]),
        .O(\n_0_slaveRegDo_mux_5[0]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I2[10]),
        .I4(s_daddr_o[0]),
        .I5(I3[10]),
        .O(\n_0_slaveRegDo_mux_5[10]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I2[11]),
        .I4(s_daddr_o[0]),
        .I5(I3[11]),
        .O(\n_0_slaveRegDo_mux_5[11]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I2[12]),
        .I4(s_daddr_o[0]),
        .I5(I3[12]),
        .O(\n_0_slaveRegDo_mux_5[12]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I2[13]),
        .I4(s_daddr_o[0]),
        .I5(I3[13]),
        .O(\n_0_slaveRegDo_mux_5[13]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I2[14]),
        .I4(s_daddr_o[0]),
        .I5(I3[14]),
        .O(\n_0_slaveRegDo_mux_5[14]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I2[15]),
        .I4(s_daddr_o[0]),
        .I5(I3[15]),
        .O(\n_0_slaveRegDo_mux_5[15]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I2[1]),
        .I4(s_daddr_o[0]),
        .I5(I3[1]),
        .O(\n_0_slaveRegDo_mux_5[1]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I2[2]),
        .I4(s_daddr_o[0]),
        .I5(I3[2]),
        .O(\n_0_slaveRegDo_mux_5[2]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I2[3]),
        .I4(s_daddr_o[0]),
        .I5(I3[3]),
        .O(\n_0_slaveRegDo_mux_5[3]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I2[4]),
        .I4(s_daddr_o[0]),
        .I5(I3[4]),
        .O(\n_0_slaveRegDo_mux_5[4]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I2[5]),
        .I4(s_daddr_o[0]),
        .I5(I3[5]),
        .O(\n_0_slaveRegDo_mux_5[5]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I2[6]),
        .I4(s_daddr_o[0]),
        .I5(I3[6]),
        .O(\n_0_slaveRegDo_mux_5[6]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I2[7]),
        .I4(s_daddr_o[0]),
        .I5(I3[7]),
        .O(\n_0_slaveRegDo_mux_5[7]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I2[8]),
        .I4(s_daddr_o[0]),
        .I5(I3[8]),
        .O(\n_0_slaveRegDo_mux_5[8]_i_8 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_8 
       (.I0(\slaveRegDo_tcConfig[5139]_33 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I2[9]),
        .I4(s_daddr_o[0]),
        .I5(I3[9]),
        .O(\n_0_slaveRegDo_mux_5[9]_i_8 ));
MUXF7 \slaveRegDo_mux_5_reg[0]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[0]_i_8 ),
        .I1(I18),
        .O(O16),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[10]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[10]_i_8 ),
        .I1(I8),
        .O(O6),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[11]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[11]_i_8 ),
        .I1(I7),
        .O(O5),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[12]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[12]_i_8 ),
        .I1(I6),
        .O(O4),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[13]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[13]_i_8 ),
        .I1(I5),
        .O(O3),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[14]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[14]_i_8 ),
        .I1(I4),
        .O(O2),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[15]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[15]_i_8 ),
        .I1(I1),
        .O(O1),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[1]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[1]_i_8 ),
        .I1(I17),
        .O(O15),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[2]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[2]_i_8 ),
        .I1(I16),
        .O(O14),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[3]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[3]_i_8 ),
        .I1(I15),
        .O(O13),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[4]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[4]_i_8 ),
        .I1(I14),
        .O(O12),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[5]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[5]_i_8 ),
        .I1(I13),
        .O(O11),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[6]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[6]_i_8 ),
        .I1(I12),
        .O(O10),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[7]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[7]_i_8 ),
        .I1(I11),
        .O(O9),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[8]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[8]_i_8 ),
        .I1(I10),
        .O(O8),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[9]_i_3 
       (.I0(\n_0_slaveRegDo_mux_5[9]_i_8 ),
        .I1(I9),
        .O(O7),
        .S(s_daddr_o[2]));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__31
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized33
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__33 ;
  wire \n_0_current_state[3]_i_3__33 ;
  wire \n_0_current_state[3]_i_5__33 ;
  wire \n_0_current_state[3]_i_6__33 ;
  wire n_0_data_out_sel_i_1__33;
  wire \n_0_shadow[0]_i_1__33 ;
  wire \n_0_shadow[10]_i_1__33 ;
  wire \n_0_shadow[11]_i_1__33 ;
  wire \n_0_shadow[12]_i_1__33 ;
  wire \n_0_shadow[13]_i_1__33 ;
  wire \n_0_shadow[14]_i_1__33 ;
  wire \n_0_shadow[15]_i_1__33 ;
  wire \n_0_shadow[1]_i_1__33 ;
  wire \n_0_shadow[2]_i_1__33 ;
  wire \n_0_shadow[3]_i_1__33 ;
  wire \n_0_shadow[4]_i_1__33 ;
  wire \n_0_shadow[5]_i_1__33 ;
  wire \n_0_shadow[6]_i_1__33 ;
  wire \n_0_shadow[7]_i_1__33 ;
  wire \n_0_shadow[8]_i_1__33 ;
  wire \n_0_shadow[9]_i_1__33 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__33;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__33 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair166" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__33 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair166" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__33 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__33 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair164" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__33 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__34 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__33 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__33 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__34 
       (.I0(\n_0_current_state[3]_i_2__33 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__34 
       (.I0(\n_0_current_state[3]_i_2__33 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__33 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__34 
       (.I0(\n_0_current_state[3]_i_2__33 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__33 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair163" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__33 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__33 ));
(* SOFT_HLUTNM = "soft_lutpair164" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__33 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__33 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__33 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__33 ),
        .I3(\n_0_current_state[3]_i_6__33 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__33 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__33 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__33 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__33 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair165" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__33
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__33));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__33),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__33 ));
(* SOFT_HLUTNM = "soft_lutpair163" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__33 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__33 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__33 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__33 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__33 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__33 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__33 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__33 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__33 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__33 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__33 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__33 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__33 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__33 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__33 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__33 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__33 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__33 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__33 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__33 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair165" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__33
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__33));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__33),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__32
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized34
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__34 ;
  wire \n_0_current_state[3]_i_3__34 ;
  wire \n_0_current_state[3]_i_5__34 ;
  wire \n_0_current_state[3]_i_6__34 ;
  wire n_0_data_out_sel_i_1__34;
  wire \n_0_shadow[0]_i_1__34 ;
  wire \n_0_shadow[10]_i_1__34 ;
  wire \n_0_shadow[11]_i_1__34 ;
  wire \n_0_shadow[12]_i_1__34 ;
  wire \n_0_shadow[13]_i_1__34 ;
  wire \n_0_shadow[14]_i_1__34 ;
  wire \n_0_shadow[15]_i_1__34 ;
  wire \n_0_shadow[1]_i_1__34 ;
  wire \n_0_shadow[2]_i_1__34 ;
  wire \n_0_shadow[3]_i_1__34 ;
  wire \n_0_shadow[4]_i_1__34 ;
  wire \n_0_shadow[5]_i_1__34 ;
  wire \n_0_shadow[6]_i_1__34 ;
  wire \n_0_shadow[7]_i_1__34 ;
  wire \n_0_shadow[8]_i_1__34 ;
  wire \n_0_shadow[9]_i_1__34 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__34;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__34 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair170" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__34 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair170" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__34 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__34 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair168" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__34 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__35 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__34 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__34 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__35 
       (.I0(\n_0_current_state[3]_i_2__34 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__35 
       (.I0(\n_0_current_state[3]_i_2__34 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__34 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__35 
       (.I0(\n_0_current_state[3]_i_2__34 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__34 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair167" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__34 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__34 ));
(* SOFT_HLUTNM = "soft_lutpair168" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__34 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__34 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__34 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__34 ),
        .I3(\n_0_current_state[3]_i_6__34 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__34 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__34 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__34 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__34 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair169" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__34
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__34));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__34),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__34 ));
(* SOFT_HLUTNM = "soft_lutpair167" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__34 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__34 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__34 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__34 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__34 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__34 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__34 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__34 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__34 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__34 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__34 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__34 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__34 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__34 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__34 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__34 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__34 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__34 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__34 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__34 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair169" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__34
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__34));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__34),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__33
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized35
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__35 ;
  wire \n_0_current_state[3]_i_3__35 ;
  wire \n_0_current_state[3]_i_5__35 ;
  wire \n_0_current_state[3]_i_6__35 ;
  wire n_0_data_out_sel_i_1__35;
  wire \n_0_shadow[0]_i_1__35 ;
  wire \n_0_shadow[10]_i_1__35 ;
  wire \n_0_shadow[11]_i_1__35 ;
  wire \n_0_shadow[12]_i_1__35 ;
  wire \n_0_shadow[13]_i_1__35 ;
  wire \n_0_shadow[14]_i_1__35 ;
  wire \n_0_shadow[15]_i_1__35 ;
  wire \n_0_shadow[1]_i_1__35 ;
  wire \n_0_shadow[2]_i_1__35 ;
  wire \n_0_shadow[3]_i_1__35 ;
  wire \n_0_shadow[4]_i_1__35 ;
  wire \n_0_shadow[5]_i_1__35 ;
  wire \n_0_shadow[6]_i_1__35 ;
  wire \n_0_shadow[7]_i_1__35 ;
  wire \n_0_shadow[8]_i_1__35 ;
  wire \n_0_shadow[9]_i_1__35 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__35;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__35 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair174" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__35 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair174" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__35 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__35 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair172" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__35 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__36 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__35 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__35 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__36 
       (.I0(\n_0_current_state[3]_i_2__35 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__36 
       (.I0(\n_0_current_state[3]_i_2__35 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__35 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__36 
       (.I0(\n_0_current_state[3]_i_2__35 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__35 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair171" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__35 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__35 ));
(* SOFT_HLUTNM = "soft_lutpair172" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__35 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__35 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__35 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__35 ),
        .I3(\n_0_current_state[3]_i_6__35 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__35 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__35 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__35 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__35 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair173" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__35
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__35));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__35),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__35 ));
(* SOFT_HLUTNM = "soft_lutpair171" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__35 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__35 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__35 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__35 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__35 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__35 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__35 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__35 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__35 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__35 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__35 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__35 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__35 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__35 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__35 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__35 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__35 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__35 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__35 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__35 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair173" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__35
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__35));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__35),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__34
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized36
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    s_do_o,
    I1,
    I2,
    I3,
    tc_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]s_do_o;
  input [15:0]I1;
  input [15:0]I2;
  input I3;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire [15:0]I1;
  wire [15:0]I2;
  wire I3;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__36 ;
  wire \n_0_current_state[3]_i_3__36 ;
  wire \n_0_current_state[3]_i_5__36 ;
  wire \n_0_current_state[3]_i_6__36 ;
  wire n_0_data_out_sel_i_1__36;
  wire \n_0_shadow[0]_i_1__36 ;
  wire \n_0_shadow[10]_i_1__36 ;
  wire \n_0_shadow[11]_i_1__36 ;
  wire \n_0_shadow[12]_i_1__36 ;
  wire \n_0_shadow[13]_i_1__36 ;
  wire \n_0_shadow[14]_i_1__36 ;
  wire \n_0_shadow[15]_i_1__36 ;
  wire \n_0_shadow[1]_i_1__36 ;
  wire \n_0_shadow[2]_i_1__36 ;
  wire \n_0_shadow[3]_i_1__36 ;
  wire \n_0_shadow[4]_i_1__36 ;
  wire \n_0_shadow[5]_i_1__36 ;
  wire \n_0_shadow[6]_i_1__36 ;
  wire \n_0_shadow[7]_i_1__36 ;
  wire \n_0_shadow[8]_i_1__36 ;
  wire \n_0_shadow[9]_i_1__36 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__36;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_tcConfig[5143]_37 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__36 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair178" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__36 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair178" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__36 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__36 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair176" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__36 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__37 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__36 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__36 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__37 
       (.I0(\n_0_current_state[3]_i_2__36 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__37 
       (.I0(\n_0_current_state[3]_i_2__36 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__36 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__37 
       (.I0(\n_0_current_state[3]_i_2__36 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__36 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair175" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__36 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__36 ));
(* SOFT_HLUTNM = "soft_lutpair176" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__36 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__36 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__36 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__36 ),
        .I3(\n_0_current_state[3]_i_6__36 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__36 
       (.I0(s_daddr_o[3]),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__36 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__36 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__36 ));
FDRE \current_state_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair177" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__36
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__36));
FDRE data_out_sel_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__36),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [1]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [11]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [12]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [13]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [14]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [15]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I3),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5143]_37 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [2]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [3]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [4]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [5]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [6]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [7]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [8]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [9]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5143]_37 [10]),
        .Q(\slaveRegDo_tcConfig[5143]_37 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__36 ));
(* SOFT_HLUTNM = "soft_lutpair175" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__36 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__36 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__36 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__36 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__36 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__36 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__36 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__36 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__36 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__36 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__36 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__36 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__36 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__36 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__36 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__36 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__36 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__36 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__36 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__36 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair177" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__36
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__36));
FDRE shift_en_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__36),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I1[0]),
        .I4(s_daddr_o[0]),
        .I5(I2[0]),
        .O(O16));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I1[10]),
        .I4(s_daddr_o[0]),
        .I5(I2[10]),
        .O(O6));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I1[11]),
        .I4(s_daddr_o[0]),
        .I5(I2[11]),
        .O(O5));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I1[12]),
        .I4(s_daddr_o[0]),
        .I5(I2[12]),
        .O(O4));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I1[13]),
        .I4(s_daddr_o[0]),
        .I5(I2[13]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I1[14]),
        .I4(s_daddr_o[0]),
        .I5(I2[14]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I1[15]),
        .I4(s_daddr_o[0]),
        .I5(I2[15]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I1[1]),
        .I4(s_daddr_o[0]),
        .I5(I2[1]),
        .O(O15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I1[2]),
        .I4(s_daddr_o[0]),
        .I5(I2[2]),
        .O(O14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I1[3]),
        .I4(s_daddr_o[0]),
        .I5(I2[3]),
        .O(O13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I1[4]),
        .I4(s_daddr_o[0]),
        .I5(I2[4]),
        .O(O12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I1[5]),
        .I4(s_daddr_o[0]),
        .I5(I2[5]),
        .O(O11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I1[6]),
        .I4(s_daddr_o[0]),
        .I5(I2[6]),
        .O(O10));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I1[7]),
        .I4(s_daddr_o[0]),
        .I5(I2[7]),
        .O(O9));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I1[8]),
        .I4(s_daddr_o[0]),
        .I5(I2[8]),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_9 
       (.I0(\slaveRegDo_tcConfig[5143]_37 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I1[9]),
        .I4(s_daddr_o[0]),
        .I5(I2[9]),
        .O(O7));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__35
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized37
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__37 ;
  wire \n_0_current_state[3]_i_3__37 ;
  wire \n_0_current_state[3]_i_5__37 ;
  wire \n_0_current_state[3]_i_6__37 ;
  wire n_0_data_out_sel_i_1__37;
  wire \n_0_shadow[0]_i_1__37 ;
  wire \n_0_shadow[10]_i_1__37 ;
  wire \n_0_shadow[11]_i_1__37 ;
  wire \n_0_shadow[12]_i_1__37 ;
  wire \n_0_shadow[13]_i_1__37 ;
  wire \n_0_shadow[14]_i_1__37 ;
  wire \n_0_shadow[15]_i_1__37 ;
  wire \n_0_shadow[1]_i_1__37 ;
  wire \n_0_shadow[2]_i_1__37 ;
  wire \n_0_shadow[3]_i_1__37 ;
  wire \n_0_shadow[4]_i_1__37 ;
  wire \n_0_shadow[5]_i_1__37 ;
  wire \n_0_shadow[6]_i_1__37 ;
  wire \n_0_shadow[7]_i_1__37 ;
  wire \n_0_shadow[8]_i_1__37 ;
  wire \n_0_shadow[9]_i_1__37 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__37;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__37 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair182" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__37 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair182" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__37 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__37 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair180" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__37 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__38 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__37 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__37 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__38 
       (.I0(\n_0_current_state[3]_i_2__37 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__38 
       (.I0(\n_0_current_state[3]_i_2__37 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__37 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__38 
       (.I0(\n_0_current_state[3]_i_2__37 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__37 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair179" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__37 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__37 ));
(* SOFT_HLUTNM = "soft_lutpair180" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__37 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__37 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__37 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__37 ),
        .I3(\n_0_current_state[3]_i_6__37 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \current_state[3]_i_5__37 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__37 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__37 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__37 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair181" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__37
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__37));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__37),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__37 ));
(* SOFT_HLUTNM = "soft_lutpair179" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__37 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__37 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__37 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__37 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__37 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__37 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__37 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__37 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__37 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__37 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__37 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__37 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__37 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__37 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__37 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__37 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__37 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__37 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__37 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__37 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair181" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__37
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__37));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__37),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__36
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized38
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__38 ;
  wire \n_0_current_state[3]_i_3__38 ;
  wire \n_0_current_state[3]_i_5__38 ;
  wire \n_0_current_state[3]_i_6__38 ;
  wire n_0_data_out_sel_i_1__38;
  wire \n_0_shadow[0]_i_1__38 ;
  wire \n_0_shadow[10]_i_1__38 ;
  wire \n_0_shadow[11]_i_1__38 ;
  wire \n_0_shadow[12]_i_1__38 ;
  wire \n_0_shadow[13]_i_1__38 ;
  wire \n_0_shadow[14]_i_1__38 ;
  wire \n_0_shadow[15]_i_1__38 ;
  wire \n_0_shadow[1]_i_1__38 ;
  wire \n_0_shadow[2]_i_1__38 ;
  wire \n_0_shadow[3]_i_1__38 ;
  wire \n_0_shadow[4]_i_1__38 ;
  wire \n_0_shadow[5]_i_1__38 ;
  wire \n_0_shadow[6]_i_1__38 ;
  wire \n_0_shadow[7]_i_1__38 ;
  wire \n_0_shadow[8]_i_1__38 ;
  wire \n_0_shadow[9]_i_1__38 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__38;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__38 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair186" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__38 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair186" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__38 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__38 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair184" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__38 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__39 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__38 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__38 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__39 
       (.I0(\n_0_current_state[3]_i_2__38 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__39 
       (.I0(\n_0_current_state[3]_i_2__38 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__38 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__39 
       (.I0(\n_0_current_state[3]_i_2__38 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__38 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair183" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__38 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__38 ));
(* SOFT_HLUTNM = "soft_lutpair184" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__38 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__38 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__38 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__38 ),
        .I3(\n_0_current_state[3]_i_6__38 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \current_state[3]_i_5__38 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__38 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__38 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__38 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair185" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__38
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__38));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__38),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__38 ));
(* SOFT_HLUTNM = "soft_lutpair183" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__38 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__38 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__38 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__38 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__38 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__38 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__38 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__38 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__38 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__38 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__38 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__38 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__38 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__38 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__38 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__38 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__38 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__38 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__38 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__38 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair185" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__38
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__38));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__38),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__37
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized39
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__39 ;
  wire \n_0_current_state[3]_i_3__39 ;
  wire \n_0_current_state[3]_i_5__39 ;
  wire \n_0_current_state[3]_i_6__39 ;
  wire n_0_data_out_sel_i_1__39;
  wire \n_0_shadow[0]_i_1__39 ;
  wire \n_0_shadow[10]_i_1__39 ;
  wire \n_0_shadow[11]_i_1__39 ;
  wire \n_0_shadow[12]_i_1__39 ;
  wire \n_0_shadow[13]_i_1__39 ;
  wire \n_0_shadow[14]_i_1__39 ;
  wire \n_0_shadow[15]_i_1__39 ;
  wire \n_0_shadow[1]_i_1__39 ;
  wire \n_0_shadow[2]_i_1__39 ;
  wire \n_0_shadow[3]_i_1__39 ;
  wire \n_0_shadow[4]_i_1__39 ;
  wire \n_0_shadow[5]_i_1__39 ;
  wire \n_0_shadow[6]_i_1__39 ;
  wire \n_0_shadow[7]_i_1__39 ;
  wire \n_0_shadow[8]_i_1__39 ;
  wire \n_0_shadow[9]_i_1__39 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__39;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__39 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair190" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__39 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair190" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__39 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__39 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair188" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__39 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__40 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__39 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__39 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__40 
       (.I0(\n_0_current_state[3]_i_2__39 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__40 
       (.I0(\n_0_current_state[3]_i_2__39 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__39 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__40 
       (.I0(\n_0_current_state[3]_i_2__39 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__39 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair187" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__39 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__39 ));
(* SOFT_HLUTNM = "soft_lutpair188" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__39 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__39 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__39 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__39 ),
        .I3(\n_0_current_state[3]_i_6__39 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \current_state[3]_i_5__39 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__39 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__39 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__39 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair189" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__39
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__39));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__39),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__39 ));
(* SOFT_HLUTNM = "soft_lutpair187" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__39 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__39 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__39 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__39 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__39 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__39 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__39 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__39 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__39 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__39 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__39 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__39 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__39 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__39 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__39 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__39 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__39 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__39 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__39 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__39 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair189" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__39
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__39));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__39),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__38
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized4
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__4 ;
  wire \n_0_current_state[3]_i_3__4 ;
  wire \n_0_current_state[3]_i_5__4 ;
  wire \n_0_current_state[3]_i_6__4 ;
  wire n_0_data_out_sel_i_1__4;
  wire \n_0_shadow[0]_i_1__4 ;
  wire \n_0_shadow[10]_i_1__4 ;
  wire \n_0_shadow[11]_i_1__4 ;
  wire \n_0_shadow[12]_i_1__4 ;
  wire \n_0_shadow[13]_i_1__4 ;
  wire \n_0_shadow[14]_i_1__4 ;
  wire \n_0_shadow[15]_i_1__4 ;
  wire \n_0_shadow[1]_i_1__4 ;
  wire \n_0_shadow[2]_i_1__4 ;
  wire \n_0_shadow[3]_i_1__4 ;
  wire \n_0_shadow[4]_i_1__4 ;
  wire \n_0_shadow[5]_i_1__4 ;
  wire \n_0_shadow[6]_i_1__4 ;
  wire \n_0_shadow[7]_i_1__4 ;
  wire \n_0_shadow[8]_i_1__4 ;
  wire \n_0_shadow[9]_i_1__4 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__4;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__4 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair94" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__4 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair94" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__4 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__4 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair92" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__4 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__5 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__4 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__4 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__5 
       (.I0(\n_0_current_state[3]_i_2__4 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__5 
       (.I0(\n_0_current_state[3]_i_2__4 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__4 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__5 
       (.I0(\n_0_current_state[3]_i_2__4 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__4 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair91" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__4 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__4 ));
(* SOFT_HLUTNM = "soft_lutpair92" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__4 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__4 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__4 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__4 ),
        .I3(\n_0_current_state[3]_i_6__4 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__4 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__4 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \current_state[3]_i_6__4 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__4 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair93" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__4
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__4));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__4),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__4 ));
(* SOFT_HLUTNM = "soft_lutpair91" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__4 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__4 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__4 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__4 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__4 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__4 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__4 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__4 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__4 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__4 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__4 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__4 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__4 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__4 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__4 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__4 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__4 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__4 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__4 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__4 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair93" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__4
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__4));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__4),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__3
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized40
   (D,
    shift_en_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    I2,
    I3,
    I4,
    s_do_o,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    I24,
    I25,
    I26,
    I27,
    I28,
    I29,
    I30,
    I31,
    I32,
    I33,
    I34,
    I35,
    I36,
    I37,
    I38,
    I39,
    I40,
    I41,
    I42,
    I43,
    I44,
    I45,
    I46,
    I47,
    I48,
    I49,
    I50,
    I51,
    I52,
    I53,
    I54,
    I55,
    I56,
    I57,
    I58,
    I59,
    I60,
    I61,
    I62,
    I63,
    I64,
    I65,
    I66,
    I67,
    tc_config_cs_serial_input,
    s_di_o);
  output [15:0]D;
  output shift_en_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input I2;
  input I3;
  input I4;
  input [15:0]s_do_o;
  input [15:0]I5;
  input [15:0]I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input I23;
  input I24;
  input I25;
  input I26;
  input I27;
  input I28;
  input I29;
  input I30;
  input I31;
  input I32;
  input I33;
  input I34;
  input I35;
  input I36;
  input I37;
  input I38;
  input I39;
  input I40;
  input I41;
  input I42;
  input I43;
  input I44;
  input I45;
  input I46;
  input I47;
  input I48;
  input I49;
  input I50;
  input I51;
  input I52;
  input I53;
  input I54;
  input I55;
  input I56;
  input I57;
  input I58;
  input I59;
  input I60;
  input I61;
  input I62;
  input I63;
  input I64;
  input I65;
  input I66;
  input I67;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [15:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I28;
  wire I29;
  wire I3;
  wire I30;
  wire I31;
  wire I32;
  wire I33;
  wire I34;
  wire I35;
  wire I36;
  wire I37;
  wire I38;
  wire I39;
  wire I4;
  wire I40;
  wire I41;
  wire I42;
  wire I43;
  wire I44;
  wire I45;
  wire I46;
  wire I47;
  wire I48;
  wire I49;
  wire [15:0]I5;
  wire I50;
  wire I51;
  wire I52;
  wire I53;
  wire I54;
  wire I55;
  wire I56;
  wire I57;
  wire I58;
  wire I59;
  wire [15:0]I6;
  wire I60;
  wire I61;
  wire I62;
  wire I63;
  wire I64;
  wire I65;
  wire I66;
  wire I67;
  wire I7;
  wire I8;
  wire I9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__40 ;
  wire \n_0_current_state[3]_i_3__40 ;
  wire \n_0_current_state[3]_i_5__40 ;
  wire \n_0_current_state[3]_i_6__40 ;
  wire n_0_data_out_sel_i_1__40;
  wire \n_0_shadow[0]_i_1__40 ;
  wire \n_0_shadow[10]_i_1__40 ;
  wire \n_0_shadow[11]_i_1__40 ;
  wire \n_0_shadow[12]_i_1__40 ;
  wire \n_0_shadow[13]_i_1__40 ;
  wire \n_0_shadow[14]_i_1__40 ;
  wire \n_0_shadow[15]_i_1__40 ;
  wire \n_0_shadow[1]_i_1__40 ;
  wire \n_0_shadow[2]_i_1__40 ;
  wire \n_0_shadow[3]_i_1__40 ;
  wire \n_0_shadow[4]_i_1__40 ;
  wire \n_0_shadow[5]_i_1__40 ;
  wire \n_0_shadow[6]_i_1__40 ;
  wire \n_0_shadow[7]_i_1__40 ;
  wire \n_0_shadow[8]_i_1__40 ;
  wire \n_0_shadow[9]_i_1__40 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__40;
  wire \n_0_slaveRegDo_mux_5[0]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[10]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[11]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[12]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[13]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[14]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[15]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[1]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[2]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[3]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[4]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[5]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[6]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[7]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[8]_i_6 ;
  wire \n_0_slaveRegDo_mux_5[9]_i_6 ;
  wire \n_0_slaveRegDo_mux_5_reg[0]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[10]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[11]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[12]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[13]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[14]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[15]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[1]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[2]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[3]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[4]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[5]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[6]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[7]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[8]_i_2 ;
  wire \n_0_slaveRegDo_mux_5_reg[9]_i_2 ;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_tcConfig[5147]_41 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__40 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair194" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__40 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair194" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__40 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__40 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair192" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__40 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I67),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I67),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I67),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I67),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__41 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__40 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__40 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__41 
       (.I0(\n_0_current_state[3]_i_2__40 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__41 
       (.I0(\n_0_current_state[3]_i_2__40 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__40 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__41 
       (.I0(\n_0_current_state[3]_i_2__40 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__40 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair191" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__40 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__40 ));
(* SOFT_HLUTNM = "soft_lutpair192" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__40 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__40 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__40 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__40 ),
        .I3(\n_0_current_state[3]_i_6__40 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \current_state[3]_i_5__40 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__40 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__40 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__40 ));
FDRE \current_state_reg[0] 
       (.C(I67),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I67),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I67),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I67),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair193" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__40
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__40));
FDRE data_out_sel_reg
       (.C(I67),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__40),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [1]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [11]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [12]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [13]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [14]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [15]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I67),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5147]_41 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [2]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [3]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [4]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [5]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [6]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [7]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [8]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [9]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I67),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5147]_41 [10]),
        .Q(\slaveRegDo_tcConfig[5147]_41 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__40 ));
(* SOFT_HLUTNM = "soft_lutpair191" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__40 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__40 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__40 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__40 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__40 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__40 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__40 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__40 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__40 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__40 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__40 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__40 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__40 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__40 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__40 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__40 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__40 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__40 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__40 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I67),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__40 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair193" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__40
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__40));
FDRE shift_en_reg
       (.C(I67),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__40),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[0]_i_2 ),
        .I1(I63),
        .I2(s_daddr_o[4]),
        .I3(I64),
        .I4(s_daddr_o[3]),
        .I5(I65),
        .O(D[0]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I5[0]),
        .I4(s_daddr_o[0]),
        .I5(I6[0]),
        .O(\n_0_slaveRegDo_mux_5[0]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[10]_i_2 ),
        .I1(I23),
        .I2(s_daddr_o[4]),
        .I3(I24),
        .I4(s_daddr_o[3]),
        .I5(I25),
        .O(D[10]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I5[10]),
        .I4(s_daddr_o[0]),
        .I5(I6[10]),
        .O(\n_0_slaveRegDo_mux_5[10]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[11]_i_2 ),
        .I1(I19),
        .I2(s_daddr_o[4]),
        .I3(I20),
        .I4(s_daddr_o[3]),
        .I5(I21),
        .O(D[11]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I5[11]),
        .I4(s_daddr_o[0]),
        .I5(I6[11]),
        .O(\n_0_slaveRegDo_mux_5[11]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[12]_i_2 ),
        .I1(I15),
        .I2(s_daddr_o[4]),
        .I3(I16),
        .I4(s_daddr_o[3]),
        .I5(I17),
        .O(D[12]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I5[12]),
        .I4(s_daddr_o[0]),
        .I5(I6[12]),
        .O(\n_0_slaveRegDo_mux_5[12]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[13]_i_2 ),
        .I1(I11),
        .I2(s_daddr_o[4]),
        .I3(I12),
        .I4(s_daddr_o[3]),
        .I5(I13),
        .O(D[13]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I5[13]),
        .I4(s_daddr_o[0]),
        .I5(I6[13]),
        .O(\n_0_slaveRegDo_mux_5[13]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[14]_i_2 ),
        .I1(I7),
        .I2(s_daddr_o[4]),
        .I3(I8),
        .I4(s_daddr_o[3]),
        .I5(I9),
        .O(D[14]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I5[14]),
        .I4(s_daddr_o[0]),
        .I5(I6[14]),
        .O(\n_0_slaveRegDo_mux_5[14]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[15]_i_2 ),
        .I1(I1),
        .I2(s_daddr_o[4]),
        .I3(I2),
        .I4(s_daddr_o[3]),
        .I5(I3),
        .O(D[15]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I5[15]),
        .I4(s_daddr_o[0]),
        .I5(I6[15]),
        .O(\n_0_slaveRegDo_mux_5[15]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[1]_i_2 ),
        .I1(I59),
        .I2(s_daddr_o[4]),
        .I3(I60),
        .I4(s_daddr_o[3]),
        .I5(I61),
        .O(D[1]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I5[1]),
        .I4(s_daddr_o[0]),
        .I5(I6[1]),
        .O(\n_0_slaveRegDo_mux_5[1]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[2]_i_2 ),
        .I1(I55),
        .I2(s_daddr_o[4]),
        .I3(I56),
        .I4(s_daddr_o[3]),
        .I5(I57),
        .O(D[2]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I5[2]),
        .I4(s_daddr_o[0]),
        .I5(I6[2]),
        .O(\n_0_slaveRegDo_mux_5[2]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[3]_i_2 ),
        .I1(I51),
        .I2(s_daddr_o[4]),
        .I3(I52),
        .I4(s_daddr_o[3]),
        .I5(I53),
        .O(D[3]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I5[3]),
        .I4(s_daddr_o[0]),
        .I5(I6[3]),
        .O(\n_0_slaveRegDo_mux_5[3]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[4]_i_2 ),
        .I1(I47),
        .I2(s_daddr_o[4]),
        .I3(I48),
        .I4(s_daddr_o[3]),
        .I5(I49),
        .O(D[4]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I5[4]),
        .I4(s_daddr_o[0]),
        .I5(I6[4]),
        .O(\n_0_slaveRegDo_mux_5[4]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[5]_i_2 ),
        .I1(I43),
        .I2(s_daddr_o[4]),
        .I3(I44),
        .I4(s_daddr_o[3]),
        .I5(I45),
        .O(D[5]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I5[5]),
        .I4(s_daddr_o[0]),
        .I5(I6[5]),
        .O(\n_0_slaveRegDo_mux_5[5]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[6]_i_2 ),
        .I1(I39),
        .I2(s_daddr_o[4]),
        .I3(I40),
        .I4(s_daddr_o[3]),
        .I5(I41),
        .O(D[6]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I5[6]),
        .I4(s_daddr_o[0]),
        .I5(I6[6]),
        .O(\n_0_slaveRegDo_mux_5[6]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[7]_i_2 ),
        .I1(I35),
        .I2(s_daddr_o[4]),
        .I3(I36),
        .I4(s_daddr_o[3]),
        .I5(I37),
        .O(D[7]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I5[7]),
        .I4(s_daddr_o[0]),
        .I5(I6[7]),
        .O(\n_0_slaveRegDo_mux_5[7]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[8]_i_2 ),
        .I1(I31),
        .I2(s_daddr_o[4]),
        .I3(I32),
        .I4(s_daddr_o[3]),
        .I5(I33),
        .O(D[8]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I5[8]),
        .I4(s_daddr_o[0]),
        .I5(I6[8]),
        .O(\n_0_slaveRegDo_mux_5[8]_i_6 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_1 
       (.I0(\n_0_slaveRegDo_mux_5_reg[9]_i_2 ),
        .I1(I27),
        .I2(s_daddr_o[4]),
        .I3(I28),
        .I4(s_daddr_o[3]),
        .I5(I29),
        .O(D[9]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_6 
       (.I0(\slaveRegDo_tcConfig[5147]_41 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I5[9]),
        .I4(s_daddr_o[0]),
        .I5(I6[9]),
        .O(\n_0_slaveRegDo_mux_5[9]_i_6 ));
MUXF7 \slaveRegDo_mux_5_reg[0]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[0]_i_6 ),
        .I1(I66),
        .O(\n_0_slaveRegDo_mux_5_reg[0]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[10]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[10]_i_6 ),
        .I1(I26),
        .O(\n_0_slaveRegDo_mux_5_reg[10]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[11]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[11]_i_6 ),
        .I1(I22),
        .O(\n_0_slaveRegDo_mux_5_reg[11]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[12]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[12]_i_6 ),
        .I1(I18),
        .O(\n_0_slaveRegDo_mux_5_reg[12]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[13]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[13]_i_6 ),
        .I1(I14),
        .O(\n_0_slaveRegDo_mux_5_reg[13]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[14]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[14]_i_6 ),
        .I1(I10),
        .O(\n_0_slaveRegDo_mux_5_reg[14]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[15]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[15]_i_6 ),
        .I1(I4),
        .O(\n_0_slaveRegDo_mux_5_reg[15]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[1]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[1]_i_6 ),
        .I1(I62),
        .O(\n_0_slaveRegDo_mux_5_reg[1]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[2]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[2]_i_6 ),
        .I1(I58),
        .O(\n_0_slaveRegDo_mux_5_reg[2]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[3]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[3]_i_6 ),
        .I1(I54),
        .O(\n_0_slaveRegDo_mux_5_reg[3]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[4]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[4]_i_6 ),
        .I1(I50),
        .O(\n_0_slaveRegDo_mux_5_reg[4]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[5]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[5]_i_6 ),
        .I1(I46),
        .O(\n_0_slaveRegDo_mux_5_reg[5]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[6]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[6]_i_6 ),
        .I1(I42),
        .O(\n_0_slaveRegDo_mux_5_reg[6]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[7]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[7]_i_6 ),
        .I1(I38),
        .O(\n_0_slaveRegDo_mux_5_reg[7]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[8]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[8]_i_6 ),
        .I1(I34),
        .O(\n_0_slaveRegDo_mux_5_reg[8]_i_2 ),
        .S(s_daddr_o[2]));
MUXF7 \slaveRegDo_mux_5_reg[9]_i_2 
       (.I0(\n_0_slaveRegDo_mux_5[9]_i_6 ),
        .I1(I30),
        .O(\n_0_slaveRegDo_mux_5_reg[9]_i_2 ),
        .S(s_daddr_o[2]));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__39
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized41
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__41 ;
  wire \n_0_current_state[3]_i_3__41 ;
  wire \n_0_current_state[3]_i_5__41 ;
  wire \n_0_current_state[3]_i_6__41 ;
  wire n_0_data_out_sel_i_1__41;
  wire \n_0_shadow[0]_i_1__41 ;
  wire \n_0_shadow[10]_i_1__41 ;
  wire \n_0_shadow[11]_i_1__41 ;
  wire \n_0_shadow[12]_i_1__41 ;
  wire \n_0_shadow[13]_i_1__41 ;
  wire \n_0_shadow[14]_i_1__41 ;
  wire \n_0_shadow[15]_i_1__41 ;
  wire \n_0_shadow[1]_i_1__41 ;
  wire \n_0_shadow[2]_i_1__41 ;
  wire \n_0_shadow[3]_i_1__41 ;
  wire \n_0_shadow[4]_i_1__41 ;
  wire \n_0_shadow[5]_i_1__41 ;
  wire \n_0_shadow[6]_i_1__41 ;
  wire \n_0_shadow[7]_i_1__41 ;
  wire \n_0_shadow[8]_i_1__41 ;
  wire \n_0_shadow[9]_i_1__41 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__41;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__41 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair198" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__41 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair198" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__41 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__41 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair196" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__41 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__42 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__41 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__41 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__42 
       (.I0(\n_0_current_state[3]_i_2__41 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__42 
       (.I0(\n_0_current_state[3]_i_2__41 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__41 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__42 
       (.I0(\n_0_current_state[3]_i_2__41 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__41 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair195" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__41 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__41 ));
(* SOFT_HLUTNM = "soft_lutpair196" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__41 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__41 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__41 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__41 ),
        .I3(\n_0_current_state[3]_i_6__41 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \current_state[3]_i_5__41 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__41 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__41 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__41 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair197" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__41
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__41));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__41),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__41 ));
(* SOFT_HLUTNM = "soft_lutpair195" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__41 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__41 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__41 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__41 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__41 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__41 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__41 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__41 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__41 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__41 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__41 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__41 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__41 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__41 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__41 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__41 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__41 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__41 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__41 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__41 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair197" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__41
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__41));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__41),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__40
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized42
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__42 ;
  wire \n_0_current_state[3]_i_3__42 ;
  wire \n_0_current_state[3]_i_5__42 ;
  wire \n_0_current_state[3]_i_6__42 ;
  wire n_0_data_out_sel_i_1__42;
  wire \n_0_shadow[0]_i_1__42 ;
  wire \n_0_shadow[10]_i_1__42 ;
  wire \n_0_shadow[11]_i_1__42 ;
  wire \n_0_shadow[12]_i_1__42 ;
  wire \n_0_shadow[13]_i_1__42 ;
  wire \n_0_shadow[14]_i_1__42 ;
  wire \n_0_shadow[15]_i_1__42 ;
  wire \n_0_shadow[1]_i_1__42 ;
  wire \n_0_shadow[2]_i_1__42 ;
  wire \n_0_shadow[3]_i_1__42 ;
  wire \n_0_shadow[4]_i_1__42 ;
  wire \n_0_shadow[5]_i_1__42 ;
  wire \n_0_shadow[6]_i_1__42 ;
  wire \n_0_shadow[7]_i_1__42 ;
  wire \n_0_shadow[8]_i_1__42 ;
  wire \n_0_shadow[9]_i_1__42 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__42;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__42 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair202" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__42 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair202" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__42 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__42 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair200" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__42 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__43 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__42 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__42 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__43 
       (.I0(\n_0_current_state[3]_i_2__42 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__43 
       (.I0(\n_0_current_state[3]_i_2__42 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__42 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__43 
       (.I0(\n_0_current_state[3]_i_2__42 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__42 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair199" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__42 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__42 ));
(* SOFT_HLUTNM = "soft_lutpair200" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__42 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__42 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__42 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__42 ),
        .I3(\n_0_current_state[3]_i_6__42 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \current_state[3]_i_5__42 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__42 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__42 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__42 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair201" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__42
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__42));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__42),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__42 ));
(* SOFT_HLUTNM = "soft_lutpair199" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__42 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__42 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__42 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__42 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__42 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__42 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__42 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__42 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__42 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__42 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__42 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__42 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__42 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__42 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__42 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__42 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__42 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__42 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__42 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__42 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair201" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__42
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__42));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__42),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__41
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized43
   (shift_en_o,
    s_do_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    tc_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__43 ;
  wire \n_0_current_state[3]_i_3__43 ;
  wire \n_0_current_state[3]_i_5__43 ;
  wire \n_0_current_state[3]_i_6__43 ;
  wire n_0_data_out_sel_i_1__43;
  wire \n_0_shadow[0]_i_1__43 ;
  wire \n_0_shadow[10]_i_1__43 ;
  wire \n_0_shadow[11]_i_1__43 ;
  wire \n_0_shadow[12]_i_1__43 ;
  wire \n_0_shadow[13]_i_1__43 ;
  wire \n_0_shadow[14]_i_1__43 ;
  wire \n_0_shadow[15]_i_1__43 ;
  wire \n_0_shadow[1]_i_1__43 ;
  wire \n_0_shadow[2]_i_1__43 ;
  wire \n_0_shadow[3]_i_1__43 ;
  wire \n_0_shadow[4]_i_1__43 ;
  wire \n_0_shadow[5]_i_1__43 ;
  wire \n_0_shadow[6]_i_1__43 ;
  wire \n_0_shadow[7]_i_1__43 ;
  wire \n_0_shadow[8]_i_1__43 ;
  wire \n_0_shadow[9]_i_1__43 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__43;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__43 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair210" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__43 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair210" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__43 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__43 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair208" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__43 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__44 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__43 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__43 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__44 
       (.I0(\n_0_current_state[3]_i_2__43 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__44 
       (.I0(\n_0_current_state[3]_i_2__43 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__43 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__44 
       (.I0(\n_0_current_state[3]_i_2__43 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__43 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair207" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__43 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__43 ));
(* SOFT_HLUTNM = "soft_lutpair208" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__43 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__43 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__43 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__43 ),
        .I3(\n_0_current_state[3]_i_6__43 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \current_state[3]_i_5__43 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__43 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__43 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__43 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair209" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__43
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__43));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__43),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__43 ));
(* SOFT_HLUTNM = "soft_lutpair207" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__43 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__43 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__43 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__43 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__43 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__43 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__43 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__43 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__43 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__43 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__43 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__43 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__43 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__43 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__43 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__43 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__43 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__43 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__43 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__43 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair209" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__43
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__43));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__43),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__42
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized44
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    tc_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    s_do_o,
    I1,
    I2,
    I3,
    tc_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]tc_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]s_do_o;
  input [15:0]I1;
  input [15:0]I2;
  input I3;
  input [0:0]tc_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire [15:0]I1;
  wire [15:0]I2;
  wire I3;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__44 ;
  wire \n_0_current_state[3]_i_3__44 ;
  wire \n_0_current_state[3]_i_5__44 ;
  wire \n_0_current_state[3]_i_6__44 ;
  wire n_0_data_out_sel_i_1__44;
  wire \n_0_shadow[0]_i_1__44 ;
  wire \n_0_shadow[10]_i_1__44 ;
  wire \n_0_shadow[11]_i_1__44 ;
  wire \n_0_shadow[12]_i_1__44 ;
  wire \n_0_shadow[13]_i_1__44 ;
  wire \n_0_shadow[14]_i_1__44 ;
  wire \n_0_shadow[15]_i_1__44 ;
  wire \n_0_shadow[1]_i_1__44 ;
  wire \n_0_shadow[2]_i_1__44 ;
  wire \n_0_shadow[3]_i_1__44 ;
  wire \n_0_shadow[4]_i_1__44 ;
  wire \n_0_shadow[5]_i_1__44 ;
  wire \n_0_shadow[6]_i_1__44 ;
  wire \n_0_shadow[7]_i_1__44 ;
  wire \n_0_shadow[8]_i_1__44 ;
  wire \n_0_shadow[9]_i_1__44 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__44;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_tcConfig[5151]_45 ;
  wire [0:0]tc_config_cs_serial_input;
  wire [0:0]tc_config_cs_serial_output;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__44 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair214" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__44 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair214" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__44 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__44 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair212" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__44 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__45 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__44 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__44 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__45 
       (.I0(\n_0_current_state[3]_i_2__44 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__45 
       (.I0(\n_0_current_state[3]_i_2__44 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__44 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__45 
       (.I0(\n_0_current_state[3]_i_2__44 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__44 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair211" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__44 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__44 ));
(* SOFT_HLUTNM = "soft_lutpair212" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__44 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__44 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__44 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__44 ),
        .I3(\n_0_current_state[3]_i_6__44 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000008)) 
     \current_state[3]_i_5__44 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__44 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__44 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__44 ));
FDRE \current_state_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair213" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__44
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__44));
FDRE data_out_sel_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__44),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [1]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [11]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [12]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [13]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [14]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [15]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I3),
        .CE(shift_en_o),
        .D(tc_config_cs_serial_input),
        .Q(\slaveRegDo_tcConfig[5151]_45 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [2]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [3]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [4]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [5]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [6]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [7]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [8]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [9]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_tcConfig[5151]_45 [10]),
        .Q(\slaveRegDo_tcConfig[5151]_45 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__44 ));
(* SOFT_HLUTNM = "soft_lutpair211" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__44 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__44 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__44 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__44 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__44 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__44 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__44 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__44 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__44 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__44 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__44 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__44 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__44 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__44 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__44 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__44 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__44 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__44 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__44 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__44 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair213" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__44
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__44));
FDRE shift_en_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__44),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[0]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I1[0]),
        .I4(s_daddr_o[0]),
        .I5(I2[0]),
        .O(O16));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[10]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I1[10]),
        .I4(s_daddr_o[0]),
        .I5(I2[10]),
        .O(O6));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[11]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I1[11]),
        .I4(s_daddr_o[0]),
        .I5(I2[11]),
        .O(O5));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[12]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I1[12]),
        .I4(s_daddr_o[0]),
        .I5(I2[12]),
        .O(O4));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[13]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I1[13]),
        .I4(s_daddr_o[0]),
        .I5(I2[13]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[14]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I1[14]),
        .I4(s_daddr_o[0]),
        .I5(I2[14]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[15]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I1[15]),
        .I4(s_daddr_o[0]),
        .I5(I2[15]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[1]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I1[1]),
        .I4(s_daddr_o[0]),
        .I5(I2[1]),
        .O(O15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[2]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I1[2]),
        .I4(s_daddr_o[0]),
        .I5(I2[2]),
        .O(O14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[3]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I1[3]),
        .I4(s_daddr_o[0]),
        .I5(I2[3]),
        .O(O13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[4]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I1[4]),
        .I4(s_daddr_o[0]),
        .I5(I2[4]),
        .O(O12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[5]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I1[5]),
        .I4(s_daddr_o[0]),
        .I5(I2[5]),
        .O(O11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[6]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I1[6]),
        .I4(s_daddr_o[0]),
        .I5(I2[6]),
        .O(O10));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[7]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I1[7]),
        .I4(s_daddr_o[0]),
        .I5(I2[7]),
        .O(O9));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[8]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I1[8]),
        .I4(s_daddr_o[0]),
        .I5(I2[8]),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_5[9]_i_7 
       (.I0(\slaveRegDo_tcConfig[5151]_45 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I1[9]),
        .I4(s_daddr_o[0]),
        .I5(I2[9]),
        .O(O7));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__43
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(tc_config_cs_serial_input),
        .O(tc_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized45
   (shift_en_o,
    s_do_o,
    CFG_CNT_DIN,
    dwe,
    D,
    E,
    I1,
    CFG_CNT_DOUT,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]CFG_CNT_DIN;
  input dwe;
  input [12:0]D;
  input [0:0]E;
  input I1;
  input [0:0]CFG_CNT_DOUT;
  input [15:0]s_di_o;

  wire [0:0]CFG_CNT_DIN;
  wire [0:0]CFG_CNT_DOUT;
  wire [12:0]D;
  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__45 ;
  wire \n_0_current_state[3]_i_3__45 ;
  wire \n_0_current_state[3]_i_5__45 ;
  wire \n_0_current_state[3]_i_6__45 ;
  wire n_0_data_out_sel_i_1__45;
  wire \n_0_shadow[0]_i_1__45 ;
  wire \n_0_shadow[10]_i_1__45 ;
  wire \n_0_shadow[11]_i_1__45 ;
  wire \n_0_shadow[12]_i_1__45 ;
  wire \n_0_shadow[13]_i_1__45 ;
  wire \n_0_shadow[14]_i_1__45 ;
  wire \n_0_shadow[15]_i_1__45 ;
  wire \n_0_shadow[1]_i_1__45 ;
  wire \n_0_shadow[2]_i_1__45 ;
  wire \n_0_shadow[3]_i_1__45 ;
  wire \n_0_shadow[4]_i_1__45 ;
  wire \n_0_shadow[5]_i_1__45 ;
  wire \n_0_shadow[6]_i_1__45 ;
  wire \n_0_shadow[7]_i_1__45 ;
  wire \n_0_shadow[8]_i_1__45 ;
  wire \n_0_shadow[9]_i_1__45 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__45;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT3 #(
    .INIT(8'hB8)) 
     \G_COUNTER[0].U_COUNTER_i_4 
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(CFG_CNT_DOUT),
        .O(CFG_CNT_DIN));
LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__45 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair50" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__45 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair50" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__45 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__45 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair48" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__45 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__46 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__45 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__45 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__46 
       (.I0(\n_0_current_state[3]_i_2__45 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__46 
       (.I0(\n_0_current_state[3]_i_2__45 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__45 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__46 
       (.I0(\n_0_current_state[3]_i_2__45 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__45 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair47" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__45 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__45 ));
(* SOFT_HLUTNM = "soft_lutpair48" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__45 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__45 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__45 
       (.I0(D[2]),
        .I1(D[1]),
        .I2(\n_0_current_state[3]_i_5__45 ),
        .I3(\n_0_current_state[3]_i_6__45 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__45 
       (.I0(D[4]),
        .I1(D[3]),
        .I2(D[7]),
        .I3(D[8]),
        .I4(D[5]),
        .I5(D[6]),
        .O(\n_0_current_state[3]_i_5__45 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__45 
       (.I0(D[9]),
        .I1(D[0]),
        .I2(D[12]),
        .I3(E),
        .I4(D[11]),
        .I5(D[10]),
        .O(\n_0_current_state[3]_i_6__45 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair49" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__45
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__45));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__45),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(CFG_CNT_DOUT),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__45 ));
(* SOFT_HLUTNM = "soft_lutpair47" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__45 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__45 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__45 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__45 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__45 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__45 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__45 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__45 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__45 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__45 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__45 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__45 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__45 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__45 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__45 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__45 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__45 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__45 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__45 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__45 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair49" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__45
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__45));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__45),
        .Q(shift_en_o),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized46
   (shift_en_o,
    s_do_o,
    CFG_CNT_DIN,
    dwe,
    s_daddr_o,
    E,
    I1,
    CFG_CNT_DOUT,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]CFG_CNT_DIN;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]CFG_CNT_DOUT;
  input [15:0]s_di_o;

  wire [0:0]CFG_CNT_DIN;
  wire [0:0]CFG_CNT_DOUT;
  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__46 ;
  wire \n_0_current_state[3]_i_3__46 ;
  wire \n_0_current_state[3]_i_5__46 ;
  wire \n_0_current_state[3]_i_6__46 ;
  wire n_0_data_out_sel_i_1__46;
  wire \n_0_shadow[0]_i_1__46 ;
  wire \n_0_shadow[10]_i_1__46 ;
  wire \n_0_shadow[11]_i_1__46 ;
  wire \n_0_shadow[12]_i_1__46 ;
  wire \n_0_shadow[13]_i_1__46 ;
  wire \n_0_shadow[14]_i_1__46 ;
  wire \n_0_shadow[15]_i_1__46 ;
  wire \n_0_shadow[1]_i_1__46 ;
  wire \n_0_shadow[2]_i_1__46 ;
  wire \n_0_shadow[3]_i_1__46 ;
  wire \n_0_shadow[4]_i_1__46 ;
  wire \n_0_shadow[5]_i_1__46 ;
  wire \n_0_shadow[6]_i_1__46 ;
  wire \n_0_shadow[7]_i_1__46 ;
  wire \n_0_shadow[8]_i_1__46 ;
  wire \n_0_shadow[9]_i_1__46 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__46;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT3 #(
    .INIT(8'hB8)) 
     \G_COUNTER[1].U_COUNTER_i_3 
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(CFG_CNT_DOUT),
        .O(CFG_CNT_DIN));
LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__46 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair54" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__46 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair54" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__46 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__46 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair52" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__46 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__47 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__46 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__46 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__47 
       (.I0(\n_0_current_state[3]_i_2__46 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__47 
       (.I0(\n_0_current_state[3]_i_2__46 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__46 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__47 
       (.I0(\n_0_current_state[3]_i_2__46 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__46 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair51" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__46 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__46 ));
(* SOFT_HLUTNM = "soft_lutpair52" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__46 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__46 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__46 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__46 ),
        .I3(\n_0_current_state[3]_i_6__46 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__46 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__46 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__46 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[10]),
        .O(\n_0_current_state[3]_i_6__46 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair53" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__46
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__46));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__46),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(CFG_CNT_DOUT),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__46 ));
(* SOFT_HLUTNM = "soft_lutpair51" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__46 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__46 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__46 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__46 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__46 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__46 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__46 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__46 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__46 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__46 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__46 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__46 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__46 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__46 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__46 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__46 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__46 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__46 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__46 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__46 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair53" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__46
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__46));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__46),
        .Q(shift_en_o),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized47
   (shift_en_o,
    s_do_o,
    CFG_CNT_DIN,
    dwe,
    s_daddr_o,
    E,
    I1,
    CFG_CNT_DOUT,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]CFG_CNT_DIN;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]CFG_CNT_DOUT;
  input [15:0]s_di_o;

  wire [0:0]CFG_CNT_DIN;
  wire [0:0]CFG_CNT_DOUT;
  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__47 ;
  wire \n_0_current_state[3]_i_3__47 ;
  wire \n_0_current_state[3]_i_5__47 ;
  wire \n_0_current_state[3]_i_6__47 ;
  wire n_0_data_out_sel_i_1__47;
  wire \n_0_shadow[0]_i_1__47 ;
  wire \n_0_shadow[10]_i_1__47 ;
  wire \n_0_shadow[11]_i_1__47 ;
  wire \n_0_shadow[12]_i_1__47 ;
  wire \n_0_shadow[13]_i_1__47 ;
  wire \n_0_shadow[14]_i_1__47 ;
  wire \n_0_shadow[15]_i_1__47 ;
  wire \n_0_shadow[1]_i_1__47 ;
  wire \n_0_shadow[2]_i_1__47 ;
  wire \n_0_shadow[3]_i_1__47 ;
  wire \n_0_shadow[4]_i_1__47 ;
  wire \n_0_shadow[5]_i_1__47 ;
  wire \n_0_shadow[6]_i_1__47 ;
  wire \n_0_shadow[7]_i_1__47 ;
  wire \n_0_shadow[8]_i_1__47 ;
  wire \n_0_shadow[9]_i_1__47 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__47;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT3 #(
    .INIT(8'hB8)) 
     \G_COUNTER[2].U_COUNTER_i_3 
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(CFG_CNT_DOUT),
        .O(CFG_CNT_DIN));
LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__47 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair58" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__47 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair58" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__47 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__47 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair56" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__47 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__48 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__47 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__47 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__48 
       (.I0(\n_0_current_state[3]_i_2__47 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__48 
       (.I0(\n_0_current_state[3]_i_2__47 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__47 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__48 
       (.I0(\n_0_current_state[3]_i_2__47 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__47 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair55" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__47 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__47 ));
(* SOFT_HLUTNM = "soft_lutpair56" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__47 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__47 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__47 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__47 ),
        .I3(\n_0_current_state[3]_i_6__47 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__47 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__47 ));
LUT6 #(
    .INIT(64'h0000000010000000)) 
     \current_state[3]_i_6__47 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[10]),
        .O(\n_0_current_state[3]_i_6__47 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair57" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__47
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__47));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__47),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(CFG_CNT_DOUT),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__47 ));
(* SOFT_HLUTNM = "soft_lutpair55" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__47 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__47 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__47 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__47 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__47 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__47 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__47 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__47 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__47 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__47 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__47 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__47 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__47 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__47 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__47 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__47 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__47 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__47 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__47 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__47 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair57" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__47
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__47));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__47),
        .Q(shift_en_o),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized48
   (D,
    shift_en_o,
    CFG_CNT_DIN,
    dwe,
    s_daddr_o,
    E,
    s_do_o,
    I1,
    I2,
    I3,
    CFG_CNT_DOUT,
    s_di_o);
  output [15:0]D;
  output shift_en_o;
  output [0:0]CFG_CNT_DIN;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]s_do_o;
  input [15:0]I1;
  input [15:0]I2;
  input I3;
  input [0:0]CFG_CNT_DOUT;
  input [15:0]s_di_o;

  wire [0:0]CFG_CNT_DIN;
  wire [0:0]CFG_CNT_DOUT;
  wire [15:0]D;
  wire [0:0]E;
  wire [15:0]I1;
  wire [15:0]I2;
  wire I3;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire \n_0_current_state[3]_i_2__48 ;
  wire \n_0_current_state[3]_i_3__48 ;
  wire \n_0_current_state[3]_i_5__48 ;
  wire \n_0_current_state[3]_i_6__48 ;
  wire n_0_data_out_sel_i_1__48;
  wire \n_0_shadow[0]_i_1__48 ;
  wire \n_0_shadow[10]_i_1__48 ;
  wire \n_0_shadow[11]_i_1__48 ;
  wire \n_0_shadow[12]_i_1__48 ;
  wire \n_0_shadow[13]_i_1__48 ;
  wire \n_0_shadow[14]_i_1__48 ;
  wire \n_0_shadow[15]_i_1__48 ;
  wire \n_0_shadow[1]_i_1__48 ;
  wire \n_0_shadow[2]_i_1__48 ;
  wire \n_0_shadow[3]_i_1__48 ;
  wire \n_0_shadow[4]_i_1__48 ;
  wire \n_0_shadow[5]_i_1__48 ;
  wire \n_0_shadow[6]_i_1__48 ;
  wire \n_0_shadow[7]_i_1__48 ;
  wire \n_0_shadow[8]_i_1__48 ;
  wire \n_0_shadow[9]_i_1__48 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__48;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_cntConfig[6147]_49 ;

LUT3 #(
    .INIT(8'hB8)) 
     \G_COUNTER[3].U_COUNTER_i_3 
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(CFG_CNT_DOUT),
        .O(CFG_CNT_DIN));
LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__48 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__48 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair62" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__48 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__48 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair60" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__48 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__49 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__48 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__48 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__49 
       (.I0(\n_0_current_state[3]_i_2__48 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__49 
       (.I0(\n_0_current_state[3]_i_2__48 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__48 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__49 
       (.I0(\n_0_current_state[3]_i_2__48 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__48 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair59" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__48 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__48 ));
(* SOFT_HLUTNM = "soft_lutpair60" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__48 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__48 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__48 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__48 ),
        .I3(\n_0_current_state[3]_i_6__48 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__48 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__48 ));
LUT6 #(
    .INIT(64'h0000000040000000)) 
     \current_state[3]_i_6__48 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[11]),
        .I5(s_daddr_o[10]),
        .O(\n_0_current_state[3]_i_6__48 ));
FDRE \current_state_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair61" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__48
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__48));
FDRE data_out_sel_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__48),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [1]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [11]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [12]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [13]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [14]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [15]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I3),
        .CE(shift_en_o),
        .D(CFG_CNT_DOUT),
        .Q(\slaveRegDo_cntConfig[6147]_49 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [2]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [3]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [4]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [5]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [6]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [7]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [8]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [9]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_cntConfig[6147]_49 [10]),
        .Q(\slaveRegDo_cntConfig[6147]_49 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__48 ));
(* SOFT_HLUTNM = "soft_lutpair59" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__48 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__48 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__48 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__48 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__48 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__48 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__48 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__48 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__48 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__48 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__48 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__48 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__48 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__48 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__48 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__48 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__48 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__48 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__48 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__48 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair61" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__48
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__48));
FDRE shift_en_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__48),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[0]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[0]),
        .I3(I1[0]),
        .I4(s_daddr_o[1]),
        .I5(I2[0]),
        .O(D[0]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[10]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[0]),
        .I3(I1[10]),
        .I4(s_daddr_o[1]),
        .I5(I2[10]),
        .O(D[10]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[11]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[0]),
        .I3(I1[11]),
        .I4(s_daddr_o[1]),
        .I5(I2[11]),
        .O(D[11]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[12]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[0]),
        .I3(I1[12]),
        .I4(s_daddr_o[1]),
        .I5(I2[12]),
        .O(D[12]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[13]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[0]),
        .I3(I1[13]),
        .I4(s_daddr_o[1]),
        .I5(I2[13]),
        .O(D[13]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[14]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[0]),
        .I3(I1[14]),
        .I4(s_daddr_o[1]),
        .I5(I2[14]),
        .O(D[14]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[15]_i_2 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[0]),
        .I3(I1[15]),
        .I4(s_daddr_o[1]),
        .I5(I2[15]),
        .O(D[15]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[1]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[0]),
        .I3(I1[1]),
        .I4(s_daddr_o[1]),
        .I5(I2[1]),
        .O(D[1]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[2]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[0]),
        .I3(I1[2]),
        .I4(s_daddr_o[1]),
        .I5(I2[2]),
        .O(D[2]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[3]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[0]),
        .I3(I1[3]),
        .I4(s_daddr_o[1]),
        .I5(I2[3]),
        .O(D[3]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[4]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[0]),
        .I3(I1[4]),
        .I4(s_daddr_o[1]),
        .I5(I2[4]),
        .O(D[4]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[5]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[0]),
        .I3(I1[5]),
        .I4(s_daddr_o[1]),
        .I5(I2[5]),
        .O(D[5]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[6]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[0]),
        .I3(I1[6]),
        .I4(s_daddr_o[1]),
        .I5(I2[6]),
        .O(D[6]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[7]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[0]),
        .I3(I1[7]),
        .I4(s_daddr_o[1]),
        .I5(I2[7]),
        .O(D[7]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[8]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[0]),
        .I3(I1[8]),
        .I4(s_daddr_o[1]),
        .I5(I2[8]),
        .O(D[8]));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_6[9]_i_1 
       (.I0(\slaveRegDo_cntConfig[6147]_49 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[0]),
        .I3(I1[9]),
        .I4(s_daddr_o[1]),
        .I5(I2[9]),
        .O(D[9]));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized5
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__5 ;
  wire \n_0_current_state[3]_i_3__5 ;
  wire \n_0_current_state[3]_i_5__5 ;
  wire \n_0_current_state[3]_i_6__5 ;
  wire n_0_data_out_sel_i_1__5;
  wire \n_0_shadow[0]_i_1__5 ;
  wire \n_0_shadow[10]_i_1__5 ;
  wire \n_0_shadow[11]_i_1__5 ;
  wire \n_0_shadow[12]_i_1__5 ;
  wire \n_0_shadow[13]_i_1__5 ;
  wire \n_0_shadow[14]_i_1__5 ;
  wire \n_0_shadow[15]_i_1__5 ;
  wire \n_0_shadow[1]_i_1__5 ;
  wire \n_0_shadow[2]_i_1__5 ;
  wire \n_0_shadow[3]_i_1__5 ;
  wire \n_0_shadow[4]_i_1__5 ;
  wire \n_0_shadow[5]_i_1__5 ;
  wire \n_0_shadow[6]_i_1__5 ;
  wire \n_0_shadow[7]_i_1__5 ;
  wire \n_0_shadow[8]_i_1__5 ;
  wire \n_0_shadow[9]_i_1__5 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__5;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__5 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair98" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__5 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair98" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__5 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__5 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair96" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__5 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__6 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__5 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__5 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__6 
       (.I0(\n_0_current_state[3]_i_2__5 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__6 
       (.I0(\n_0_current_state[3]_i_2__5 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__5 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__6 
       (.I0(\n_0_current_state[3]_i_2__5 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__5 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair95" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__5 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__5 ));
(* SOFT_HLUTNM = "soft_lutpair96" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__5 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__5 ));
LUT4 #(
    .INIT(16'h4000)) 
     \current_state[3]_i_4__5 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_current_state[3]_i_5__5 ),
        .I3(\n_0_current_state[3]_i_6__5 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__5 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__5 ));
LUT6 #(
    .INIT(64'h0000000000004000)) 
     \current_state[3]_i_6__5 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__5 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair97" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__5
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__5));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__5),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__5 ));
(* SOFT_HLUTNM = "soft_lutpair95" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__5 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__5 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__5 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__5 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__5 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__5 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__5 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__5 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__5 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__5 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__5 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__5 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__5 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__5 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__5 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__5 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__5 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__5 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__5 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__5 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair97" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__5
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__5));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__5),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__4
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized6
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__6 ;
  wire \n_0_current_state[3]_i_3__6 ;
  wire \n_0_current_state[3]_i_5__6 ;
  wire \n_0_current_state[3]_i_6__6 ;
  wire n_0_data_out_sel_i_1__6;
  wire \n_0_shadow[0]_i_1__6 ;
  wire \n_0_shadow[10]_i_1__6 ;
  wire \n_0_shadow[11]_i_1__6 ;
  wire \n_0_shadow[12]_i_1__6 ;
  wire \n_0_shadow[13]_i_1__6 ;
  wire \n_0_shadow[14]_i_1__6 ;
  wire \n_0_shadow[15]_i_1__6 ;
  wire \n_0_shadow[1]_i_1__6 ;
  wire \n_0_shadow[2]_i_1__6 ;
  wire \n_0_shadow[3]_i_1__6 ;
  wire \n_0_shadow[4]_i_1__6 ;
  wire \n_0_shadow[5]_i_1__6 ;
  wire \n_0_shadow[6]_i_1__6 ;
  wire \n_0_shadow[7]_i_1__6 ;
  wire \n_0_shadow[8]_i_1__6 ;
  wire \n_0_shadow[9]_i_1__6 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__6;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__6 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair102" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__6 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair102" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__6 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__6 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair100" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__6 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__7 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__6 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__6 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__7 
       (.I0(\n_0_current_state[3]_i_2__6 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__7 
       (.I0(\n_0_current_state[3]_i_2__6 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__6 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__7 
       (.I0(\n_0_current_state[3]_i_2__6 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__6 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair99" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__6 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__6 ));
(* SOFT_HLUTNM = "soft_lutpair100" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__6 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__6 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__6 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__6 ),
        .I3(\n_0_current_state[3]_i_6__6 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__6 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__6 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \current_state[3]_i_6__6 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__6 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair101" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__6
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__6));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__6),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__6 ));
(* SOFT_HLUTNM = "soft_lutpair99" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__6 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__6 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__6 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__6 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__6 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__6 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__6 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__6 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__6 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__6 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__6 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__6 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__6 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__6 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__6 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__6 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__6 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__6 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__6 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__6 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair101" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__6
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__6));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__6),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__5
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized7
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    shift_en_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    s_do_o,
    I1,
    I2,
    I3,
    mu_config_cs_serial_input,
    s_di_o);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output shift_en_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input [15:0]s_do_o;
  input [15:0]I1;
  input [15:0]I2;
  input I3;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire [15:0]I1;
  wire [15:0]I2;
  wire I3;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__7 ;
  wire \n_0_current_state[3]_i_3__7 ;
  wire \n_0_current_state[3]_i_5__7 ;
  wire \n_0_current_state[3]_i_6__7 ;
  wire n_0_data_out_sel_i_1__7;
  wire \n_0_shadow[0]_i_1__7 ;
  wire \n_0_shadow[10]_i_1__7 ;
  wire \n_0_shadow[11]_i_1__7 ;
  wire \n_0_shadow[12]_i_1__7 ;
  wire \n_0_shadow[13]_i_1__7 ;
  wire \n_0_shadow[14]_i_1__7 ;
  wire \n_0_shadow[15]_i_1__7 ;
  wire \n_0_shadow[1]_i_1__7 ;
  wire \n_0_shadow[2]_i_1__7 ;
  wire \n_0_shadow[3]_i_1__7 ;
  wire \n_0_shadow[4]_i_1__7 ;
  wire \n_0_shadow[5]_i_1__7 ;
  wire \n_0_shadow[6]_i_1__7 ;
  wire \n_0_shadow[7]_i_1__7 ;
  wire \n_0_shadow[8]_i_1__7 ;
  wire \n_0_shadow[9]_i_1__7 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__7;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;
  wire [15:0]\slaveRegDo_muConfig[4103]_8 ;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__7 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair106" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__7 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair106" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__7 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__7 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair104" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__7 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__8 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__7 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__7 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__8 
       (.I0(\n_0_current_state[3]_i_2__7 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__8 
       (.I0(\n_0_current_state[3]_i_2__7 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__7 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__8 
       (.I0(\n_0_current_state[3]_i_2__7 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__7 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair103" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__7 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__7 ));
(* SOFT_HLUTNM = "soft_lutpair104" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__7 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__7 ));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[3]_i_4__7 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__7 ),
        .I3(\n_0_current_state[3]_i_6__7 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000001)) 
     \current_state[3]_i_5__7 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__7 ));
LUT6 #(
    .INIT(64'h0000000000004000)) 
     \current_state[3]_i_6__7 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__7 ));
FDRE \current_state_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair105" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__7
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__7));
FDRE data_out_sel_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__7),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [1]),
        .Q(\slaveRegDo_muConfig[4103]_8 [0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [11]),
        .Q(\slaveRegDo_muConfig[4103]_8 [10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [12]),
        .Q(\slaveRegDo_muConfig[4103]_8 [11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [13]),
        .Q(\slaveRegDo_muConfig[4103]_8 [12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [14]),
        .Q(\slaveRegDo_muConfig[4103]_8 [13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [15]),
        .Q(\slaveRegDo_muConfig[4103]_8 [14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I3),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(\slaveRegDo_muConfig[4103]_8 [15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [2]),
        .Q(\slaveRegDo_muConfig[4103]_8 [1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [3]),
        .Q(\slaveRegDo_muConfig[4103]_8 [2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [4]),
        .Q(\slaveRegDo_muConfig[4103]_8 [3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [5]),
        .Q(\slaveRegDo_muConfig[4103]_8 [4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [6]),
        .Q(\slaveRegDo_muConfig[4103]_8 [5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [7]),
        .Q(\slaveRegDo_muConfig[4103]_8 [6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [8]),
        .Q(\slaveRegDo_muConfig[4103]_8 [7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [9]),
        .Q(\slaveRegDo_muConfig[4103]_8 [8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I3),
        .CE(shift_en_o),
        .D(\slaveRegDo_muConfig[4103]_8 [10]),
        .Q(\slaveRegDo_muConfig[4103]_8 [9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__7 ));
(* SOFT_HLUTNM = "soft_lutpair103" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__7 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__7 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__7 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__7 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__7 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__7 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__7 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__7 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__7 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__7 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__7 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__7 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__7 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__7 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__7 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__7 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__7 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__7 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__7 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I3),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__7 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair105" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__7
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__7));
FDRE shift_en_reg
       (.C(I3),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__7),
        .Q(shift_en_o),
        .R(1'b0));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[0]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [0]),
        .I1(s_do_o[0]),
        .I2(s_daddr_o[1]),
        .I3(I1[0]),
        .I4(s_daddr_o[0]),
        .I5(I2[0]),
        .O(O16));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[10]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [10]),
        .I1(s_do_o[10]),
        .I2(s_daddr_o[1]),
        .I3(I1[10]),
        .I4(s_daddr_o[0]),
        .I5(I2[10]),
        .O(O6));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[11]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [11]),
        .I1(s_do_o[11]),
        .I2(s_daddr_o[1]),
        .I3(I1[11]),
        .I4(s_daddr_o[0]),
        .I5(I2[11]),
        .O(O5));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[12]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [12]),
        .I1(s_do_o[12]),
        .I2(s_daddr_o[1]),
        .I3(I1[12]),
        .I4(s_daddr_o[0]),
        .I5(I2[12]),
        .O(O4));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[13]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [13]),
        .I1(s_do_o[13]),
        .I2(s_daddr_o[1]),
        .I3(I1[13]),
        .I4(s_daddr_o[0]),
        .I5(I2[13]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[14]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [14]),
        .I1(s_do_o[14]),
        .I2(s_daddr_o[1]),
        .I3(I1[14]),
        .I4(s_daddr_o[0]),
        .I5(I2[14]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[15]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [15]),
        .I1(s_do_o[15]),
        .I2(s_daddr_o[1]),
        .I3(I1[15]),
        .I4(s_daddr_o[0]),
        .I5(I2[15]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[1]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [1]),
        .I1(s_do_o[1]),
        .I2(s_daddr_o[1]),
        .I3(I1[1]),
        .I4(s_daddr_o[0]),
        .I5(I2[1]),
        .O(O15));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[2]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [2]),
        .I1(s_do_o[2]),
        .I2(s_daddr_o[1]),
        .I3(I1[2]),
        .I4(s_daddr_o[0]),
        .I5(I2[2]),
        .O(O14));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[3]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [3]),
        .I1(s_do_o[3]),
        .I2(s_daddr_o[1]),
        .I3(I1[3]),
        .I4(s_daddr_o[0]),
        .I5(I2[3]),
        .O(O13));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[4]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [4]),
        .I1(s_do_o[4]),
        .I2(s_daddr_o[1]),
        .I3(I1[4]),
        .I4(s_daddr_o[0]),
        .I5(I2[4]),
        .O(O12));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[5]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [5]),
        .I1(s_do_o[5]),
        .I2(s_daddr_o[1]),
        .I3(I1[5]),
        .I4(s_daddr_o[0]),
        .I5(I2[5]),
        .O(O11));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[6]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [6]),
        .I1(s_do_o[6]),
        .I2(s_daddr_o[1]),
        .I3(I1[6]),
        .I4(s_daddr_o[0]),
        .I5(I2[6]),
        .O(O10));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[7]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [7]),
        .I1(s_do_o[7]),
        .I2(s_daddr_o[1]),
        .I3(I1[7]),
        .I4(s_daddr_o[0]),
        .I5(I2[7]),
        .O(O9));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[8]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [8]),
        .I1(s_do_o[8]),
        .I2(s_daddr_o[1]),
        .I3(I1[8]),
        .I4(s_daddr_o[0]),
        .I5(I2[8]),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_4[9]_i_3 
       (.I0(\slaveRegDo_muConfig[4103]_8 [9]),
        .I1(s_do_o[9]),
        .I2(s_daddr_o[1]),
        .I3(I1[9]),
        .I4(s_daddr_o[0]),
        .I5(I2[9]),
        .O(O7));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__6
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized8
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__8 ;
  wire \n_0_current_state[3]_i_3__8 ;
  wire \n_0_current_state[3]_i_5__8 ;
  wire \n_0_current_state[3]_i_6__8 ;
  wire n_0_data_out_sel_i_1__8;
  wire \n_0_shadow[0]_i_1__8 ;
  wire \n_0_shadow[10]_i_1__8 ;
  wire \n_0_shadow[11]_i_1__8 ;
  wire \n_0_shadow[12]_i_1__8 ;
  wire \n_0_shadow[13]_i_1__8 ;
  wire \n_0_shadow[14]_i_1__8 ;
  wire \n_0_shadow[15]_i_1__8 ;
  wire \n_0_shadow[1]_i_1__8 ;
  wire \n_0_shadow[2]_i_1__8 ;
  wire \n_0_shadow[3]_i_1__8 ;
  wire \n_0_shadow[4]_i_1__8 ;
  wire \n_0_shadow[5]_i_1__8 ;
  wire \n_0_shadow[6]_i_1__8 ;
  wire \n_0_shadow[7]_i_1__8 ;
  wire \n_0_shadow[8]_i_1__8 ;
  wire \n_0_shadow[9]_i_1__8 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__8;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__8 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair110" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__8 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair110" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__8 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__8 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair108" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__8 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__9 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__8 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__8 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__9 
       (.I0(\n_0_current_state[3]_i_2__8 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__9 
       (.I0(\n_0_current_state[3]_i_2__8 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__8 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__9 
       (.I0(\n_0_current_state[3]_i_2__8 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__8 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair107" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__8 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__8 ));
(* SOFT_HLUTNM = "soft_lutpair108" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__8 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__8 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__8 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__8 ),
        .I3(\n_0_current_state[3]_i_6__8 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__8 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__8 ));
LUT6 #(
    .INIT(64'h0000000000001000)) 
     \current_state[3]_i_6__8 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__8 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair109" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__8
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__8));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__8),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__8 ));
(* SOFT_HLUTNM = "soft_lutpair107" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__8 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__8 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__8 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__8 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__8 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__8 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__8 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__8 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__8 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__8 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__8 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__8 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__8 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__8 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__8 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__8 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__8 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__8 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__8 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__8 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair109" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__8
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__8));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__8),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__7
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_p2s" *) 
module ila_0_xsdbs_v1_0_reg_p2s__parameterized9
   (shift_en_o,
    s_do_o,
    mu_config_cs_serial_output,
    dwe,
    s_daddr_o,
    E,
    I1,
    mu_config_cs_serial_input,
    s_di_o);
  output shift_en_o;
  output [15:0]s_do_o;
  output [0:0]mu_config_cs_serial_output;
  input dwe;
  input [12:0]s_daddr_o;
  input [0:0]E;
  input I1;
  input [0:0]mu_config_cs_serial_input;
  input [15:0]s_di_o;

  wire [0:0]E;
  wire I1;
  wire clear;
  wire [3:0]cnt_reg;
  wire [3:0]current_state;
  wire data_out_sel;
  wire dwe;
  wire [0:0]mu_config_cs_serial_input;
  wire [0:0]mu_config_cs_serial_output;
  wire \n_0_current_state[3]_i_2__9 ;
  wire \n_0_current_state[3]_i_3__9 ;
  wire \n_0_current_state[3]_i_5__9 ;
  wire \n_0_current_state[3]_i_6__9 ;
  wire n_0_data_out_sel_i_1__9;
  wire \n_0_shadow[0]_i_1__9 ;
  wire \n_0_shadow[10]_i_1__9 ;
  wire \n_0_shadow[11]_i_1__9 ;
  wire \n_0_shadow[12]_i_1__9 ;
  wire \n_0_shadow[13]_i_1__9 ;
  wire \n_0_shadow[14]_i_1__9 ;
  wire \n_0_shadow[15]_i_1__9 ;
  wire \n_0_shadow[1]_i_1__9 ;
  wire \n_0_shadow[2]_i_1__9 ;
  wire \n_0_shadow[3]_i_1__9 ;
  wire \n_0_shadow[4]_i_1__9 ;
  wire \n_0_shadow[5]_i_1__9 ;
  wire \n_0_shadow[6]_i_1__9 ;
  wire \n_0_shadow[7]_i_1__9 ;
  wire \n_0_shadow[8]_i_1__9 ;
  wire \n_0_shadow[9]_i_1__9 ;
  wire \n_0_shadow_reg[0] ;
  wire \n_0_shadow_reg[10] ;
  wire \n_0_shadow_reg[11] ;
  wire \n_0_shadow_reg[12] ;
  wire \n_0_shadow_reg[13] ;
  wire \n_0_shadow_reg[14] ;
  wire \n_0_shadow_reg[15] ;
  wire \n_0_shadow_reg[1] ;
  wire \n_0_shadow_reg[2] ;
  wire \n_0_shadow_reg[3] ;
  wire \n_0_shadow_reg[4] ;
  wire \n_0_shadow_reg[5] ;
  wire \n_0_shadow_reg[6] ;
  wire \n_0_shadow_reg[7] ;
  wire \n_0_shadow_reg[8] ;
  wire \n_0_shadow_reg[9] ;
  wire n_0_shift_en_i_1__9;
  wire [3:0]next_state;
  wire [3:0]p_0_in;
  wire reg_ce;
  wire [12:0]s_daddr_o;
  wire [15:0]s_di_o;
  wire [15:0]s_do_o;
  wire serial_dout;
  wire shift_en_o;

LUT1 #(
    .INIT(2'h1)) 
     \cnt[0]_i_1__9 
       (.I0(cnt_reg[0]),
        .O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair114" *) 
   LUT2 #(
    .INIT(4'h6)) 
     \cnt[1]_i_1__9 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair114" *) 
   LUT3 #(
    .INIT(8'h78)) 
     \cnt[2]_i_1__9 
       (.I0(cnt_reg[0]),
        .I1(cnt_reg[1]),
        .I2(cnt_reg[2]),
        .O(p_0_in[2]));
LUT4 #(
    .INIT(16'hFEEF)) 
     \cnt[3]_i_1__9 
       (.I0(current_state[1]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(clear));
(* SOFT_HLUTNM = "soft_lutpair112" *) 
   LUT4 #(
    .INIT(16'h7F80)) 
     \cnt[3]_i_2__9 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(p_0_in[3]));
FDRE \cnt_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(cnt_reg[0]),
        .R(clear));
FDRE \cnt_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(cnt_reg[1]),
        .R(clear));
FDRE \cnt_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(cnt_reg[2]),
        .R(clear));
FDRE \cnt_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(cnt_reg[3]),
        .R(clear));
LUT6 #(
    .INIT(64'h3F332F22FFFFFFFF)) 
     \current_state[0]_i_1__10 
       (.I0(current_state[3]),
        .I1(\n_0_current_state[3]_i_3__9 ),
        .I2(reg_ce),
        .I3(current_state[0]),
        .I4(current_state[2]),
        .I5(\n_0_current_state[3]_i_2__9 ),
        .O(next_state[0]));
LUT4 #(
    .INIT(16'h8000)) 
     \current_state[1]_i_1__10 
       (.I0(\n_0_current_state[3]_i_2__9 ),
        .I1(reg_ce),
        .I2(dwe),
        .I3(current_state[0]),
        .O(next_state[1]));
LUT4 #(
    .INIT(16'hAA80)) 
     \current_state[2]_i_1__10 
       (.I0(\n_0_current_state[3]_i_2__9 ),
        .I1(current_state[2]),
        .I2(\n_0_current_state[3]_i_3__9 ),
        .I3(current_state[1]),
        .O(next_state[2]));
LUT6 #(
    .INIT(64'h8080AA8080808080)) 
     \current_state[3]_i_1__10 
       (.I0(\n_0_current_state[3]_i_2__9 ),
        .I1(current_state[3]),
        .I2(\n_0_current_state[3]_i_3__9 ),
        .I3(current_state[0]),
        .I4(dwe),
        .I5(reg_ce),
        .O(next_state[3]));
(* SOFT_HLUTNM = "soft_lutpair111" *) 
   LUT4 #(
    .INIT(16'h0116)) 
     \current_state[3]_i_2__9 
       (.I0(current_state[0]),
        .I1(current_state[1]),
        .I2(current_state[2]),
        .I3(current_state[3]),
        .O(\n_0_current_state[3]_i_2__9 ));
(* SOFT_HLUTNM = "soft_lutpair112" *) 
   LUT4 #(
    .INIT(16'h7FFF)) 
     \current_state[3]_i_3__9 
       (.I0(cnt_reg[1]),
        .I1(cnt_reg[0]),
        .I2(cnt_reg[2]),
        .I3(cnt_reg[3]),
        .O(\n_0_current_state[3]_i_3__9 ));
LUT4 #(
    .INIT(16'h1000)) 
     \current_state[3]_i_4__9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_current_state[3]_i_5__9 ),
        .I3(\n_0_current_state[3]_i_6__9 ),
        .O(reg_ce));
LUT6 #(
    .INIT(64'h0000000000000004)) 
     \current_state[3]_i_5__9 
       (.I0(s_daddr_o[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[7]),
        .I3(s_daddr_o[8]),
        .I4(s_daddr_o[5]),
        .I5(s_daddr_o[6]),
        .O(\n_0_current_state[3]_i_5__9 ));
LUT6 #(
    .INIT(64'h0000000000004000)) 
     \current_state[3]_i_6__9 
       (.I0(s_daddr_o[9]),
        .I1(s_daddr_o[0]),
        .I2(s_daddr_o[12]),
        .I3(E),
        .I4(s_daddr_o[10]),
        .I5(s_daddr_o[11]),
        .O(\n_0_current_state[3]_i_6__9 ));
FDRE \current_state_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[0]),
        .Q(current_state[0]),
        .R(1'b0));
FDRE \current_state_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[1]),
        .Q(current_state[1]),
        .R(1'b0));
FDRE \current_state_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[2]),
        .Q(current_state[2]),
        .R(1'b0));
FDRE \current_state_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(next_state[3]),
        .Q(current_state[3]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair113" *) 
   LUT4 #(
    .INIT(16'h0010)) 
     data_out_sel_i_1__9
       (.I0(current_state[3]),
        .I1(current_state[0]),
        .I2(current_state[2]),
        .I3(current_state[1]),
        .O(n_0_data_out_sel_i_1__9));
FDRE data_out_sel_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_data_out_sel_i_1__9),
        .Q(data_out_sel),
        .R(1'b0));
FDRE \parallel_dout_reg[0] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[1]),
        .Q(s_do_o[0]),
        .R(1'b0));
FDRE \parallel_dout_reg[10] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[11]),
        .Q(s_do_o[10]),
        .R(1'b0));
FDRE \parallel_dout_reg[11] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[12]),
        .Q(s_do_o[11]),
        .R(1'b0));
FDRE \parallel_dout_reg[12] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[13]),
        .Q(s_do_o[12]),
        .R(1'b0));
FDRE \parallel_dout_reg[13] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[14]),
        .Q(s_do_o[13]),
        .R(1'b0));
FDRE \parallel_dout_reg[14] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[15]),
        .Q(s_do_o[14]),
        .R(1'b0));
FDRE \parallel_dout_reg[15] 
       (.C(I1),
        .CE(shift_en_o),
        .D(mu_config_cs_serial_input),
        .Q(s_do_o[15]),
        .R(1'b0));
FDRE \parallel_dout_reg[1] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[2]),
        .Q(s_do_o[1]),
        .R(1'b0));
FDRE \parallel_dout_reg[2] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[3]),
        .Q(s_do_o[2]),
        .R(1'b0));
FDRE \parallel_dout_reg[3] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[4]),
        .Q(s_do_o[3]),
        .R(1'b0));
FDRE \parallel_dout_reg[4] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[5]),
        .Q(s_do_o[4]),
        .R(1'b0));
FDRE \parallel_dout_reg[5] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[6]),
        .Q(s_do_o[5]),
        .R(1'b0));
FDRE \parallel_dout_reg[6] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[7]),
        .Q(s_do_o[6]),
        .R(1'b0));
FDRE \parallel_dout_reg[7] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[8]),
        .Q(s_do_o[7]),
        .R(1'b0));
FDRE \parallel_dout_reg[8] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[9]),
        .Q(s_do_o[8]),
        .R(1'b0));
FDRE \parallel_dout_reg[9] 
       (.C(I1),
        .CE(shift_en_o),
        .D(s_do_o[10]),
        .Q(s_do_o[9]),
        .R(1'b0));
FDRE serial_dout_reg
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow_reg[0] ),
        .Q(serial_dout),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[0]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[1] ),
        .I4(current_state[1]),
        .I5(s_di_o[0]),
        .O(\n_0_shadow[0]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[10]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[11] ),
        .I4(current_state[1]),
        .I5(s_di_o[10]),
        .O(\n_0_shadow[10]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[11]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[12] ),
        .I4(current_state[1]),
        .I5(s_di_o[11]),
        .O(\n_0_shadow[11]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[12]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[13] ),
        .I4(current_state[1]),
        .I5(s_di_o[12]),
        .O(\n_0_shadow[12]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[13]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[14] ),
        .I4(current_state[1]),
        .I5(s_di_o[13]),
        .O(\n_0_shadow[13]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[14]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[15] ),
        .I4(current_state[1]),
        .I5(s_di_o[14]),
        .O(\n_0_shadow[14]_i_1__9 ));
(* SOFT_HLUTNM = "soft_lutpair111" *) 
   LUT5 #(
    .INIT(32'h01000000)) 
     \shadow[15]_i_1__9 
       (.I0(current_state[2]),
        .I1(current_state[0]),
        .I2(current_state[3]),
        .I3(current_state[1]),
        .I4(s_di_o[15]),
        .O(\n_0_shadow[15]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[1]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[2] ),
        .I4(current_state[1]),
        .I5(s_di_o[1]),
        .O(\n_0_shadow[1]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[2]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[3] ),
        .I4(current_state[1]),
        .I5(s_di_o[2]),
        .O(\n_0_shadow[2]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[3]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[4] ),
        .I4(current_state[1]),
        .I5(s_di_o[3]),
        .O(\n_0_shadow[3]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[4]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[5] ),
        .I4(current_state[1]),
        .I5(s_di_o[4]),
        .O(\n_0_shadow[4]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[5]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[6] ),
        .I4(current_state[1]),
        .I5(s_di_o[5]),
        .O(\n_0_shadow[5]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[6]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[7] ),
        .I4(current_state[1]),
        .I5(s_di_o[6]),
        .O(\n_0_shadow[6]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[7]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[8] ),
        .I4(current_state[1]),
        .I5(s_di_o[7]),
        .O(\n_0_shadow[7]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[8]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[9] ),
        .I4(current_state[1]),
        .I5(s_di_o[8]),
        .O(\n_0_shadow[8]_i_1__9 ));
LUT6 #(
    .INIT(64'h0101100000001000)) 
     \shadow[9]_i_1__9 
       (.I0(current_state[0]),
        .I1(current_state[3]),
        .I2(current_state[2]),
        .I3(\n_0_shadow_reg[10] ),
        .I4(current_state[1]),
        .I5(s_di_o[9]),
        .O(\n_0_shadow[9]_i_1__9 ));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[0] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[0]_i_1__9 ),
        .Q(\n_0_shadow_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[10] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[10]_i_1__9 ),
        .Q(\n_0_shadow_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[11] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[11]_i_1__9 ),
        .Q(\n_0_shadow_reg[11] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[12] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[12]_i_1__9 ),
        .Q(\n_0_shadow_reg[12] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[13] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[13]_i_1__9 ),
        .Q(\n_0_shadow_reg[13] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[14] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[14]_i_1__9 ),
        .Q(\n_0_shadow_reg[14] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[15] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[15]_i_1__9 ),
        .Q(\n_0_shadow_reg[15] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[1] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[1]_i_1__9 ),
        .Q(\n_0_shadow_reg[1] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[2] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[2]_i_1__9 ),
        .Q(\n_0_shadow_reg[2] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[3] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[3]_i_1__9 ),
        .Q(\n_0_shadow_reg[3] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[4] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[4]_i_1__9 ),
        .Q(\n_0_shadow_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[5] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[5]_i_1__9 ),
        .Q(\n_0_shadow_reg[5] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[6] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[6]_i_1__9 ),
        .Q(\n_0_shadow_reg[6] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[7] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[7]_i_1__9 ),
        .Q(\n_0_shadow_reg[7] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[8] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[8]_i_1__9 ),
        .Q(\n_0_shadow_reg[8] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \shadow_reg[9] 
       (.C(I1),
        .CE(1'b1),
        .D(\n_0_shadow[9]_i_1__9 ),
        .Q(\n_0_shadow_reg[9] ),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair113" *) 
   LUT4 #(
    .INIT(16'h0006)) 
     shift_en_i_1__9
       (.I0(current_state[3]),
        .I1(current_state[2]),
        .I2(current_state[0]),
        .I3(current_state[1]),
        .O(n_0_shift_en_i_1__9));
FDRE shift_en_reg
       (.C(I1),
        .CE(1'b1),
        .D(n_0_shift_en_i_1__9),
        .Q(shift_en_o),
        .R(1'b0));
LUT3 #(
    .INIT(8'hB8)) 
     u_srlD_i_1__8
       (.I0(serial_dout),
        .I1(data_out_sel),
        .I2(mu_config_cs_serial_input),
        .O(mu_config_cs_serial_output));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat
   (Q,
    E,
    I4,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input [15:0]I4;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]I4;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(I4[0]),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(I4[10]),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(I4[11]),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(I4[12]),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(I4[13]),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(I4[14]),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(I4[15]),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(I4[1]),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(I4[2]),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(I4[3]),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(I4[4]),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(I4[5]),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(I4[6]),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(I4[7]),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(I4[8]),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(I4[9]),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_215
   (O1,
    O2,
    O3,
    O4,
    O5,
    Q,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    E,
    I14);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output [10:0]Q;
  input [5:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input [0:0]E;
  input I14;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire [10:0]Q;
  wire \n_0_slaveRegDo_mux_0[13]_i_12 ;
  wire \n_0_slaveRegDo_mux_0[14]_i_12 ;
  wire \n_0_slaveRegDo_mux_0[5]_i_12 ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire [5:0]s_daddr_o;

LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[11]_i_20 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(s_daddr_o[1]),
        .I2(I8),
        .I3(s_daddr_o[2]),
        .I4(I9),
        .O(O4));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[13]_i_12 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(s_daddr_o[1]),
        .I2(I6),
        .I3(s_daddr_o[2]),
        .I4(I7),
        .O(\n_0_slaveRegDo_mux_0[13]_i_12 ));
LUT6 #(
    .INIT(64'hFFFFFFFFFFFFDDF0)) 
     \slaveRegDo_mux_0[13]_i_4 
       (.I0(\n_0_slaveRegDo_mux_0[13]_i_12 ),
        .I1(s_daddr_o[5]),
        .I2(I2),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[4]),
        .O(O2));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[14]_i_12 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(s_daddr_o[1]),
        .I2(I4),
        .I3(s_daddr_o[2]),
        .I4(I5),
        .O(\n_0_slaveRegDo_mux_0[14]_i_12 ));
LUT6 #(
    .INIT(64'hFFFFFFFFFFFFDDF0)) 
     \slaveRegDo_mux_0[14]_i_4 
       (.I0(\n_0_slaveRegDo_mux_0[14]_i_12 ),
        .I1(s_daddr_o[5]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[4]),
        .O(O1));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[5]_i_12 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(s_daddr_o[1]),
        .I2(I12),
        .I3(s_daddr_o[2]),
        .I4(I13),
        .O(\n_0_slaveRegDo_mux_0[5]_i_12 ));
LUT6 #(
    .INIT(64'hFFFFFFFFFFFFDDF0)) 
     \slaveRegDo_mux_0[5]_i_4 
       (.I0(\n_0_slaveRegDo_mux_0[5]_i_12 ),
        .I1(s_daddr_o[5]),
        .I2(I3),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[3]),
        .I5(s_daddr_o[4]),
        .O(O3));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[7]_i_19 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(s_daddr_o[1]),
        .I2(I10),
        .I3(s_daddr_o[2]),
        .I4(I11),
        .O(O5));
FDRE \xsdb_reg_reg[0] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_216
   (O1,
    O2,
    O3,
    O4,
    O5,
    O7,
    O8,
    O10,
    O11,
    O12,
    O13,
    O14,
    Q,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    O6,
    I8,
    O9,
    I9,
    I10,
    I11,
    I12,
    I13,
    E,
    I14);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O7;
  output O8;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output [3:0]Q;
  input [4:0]s_daddr_o;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input O6;
  input I8;
  input O9;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input [0:0]E;
  input I14;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [3:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [4:0]s_daddr_o;

LUT6 #(
    .INIT(64'hFFFFFFFF5555D555)) 
     \slaveRegDo_mux_0[0]_i_13 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[0] ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(I13),
        .O(O14));
LUT5 #(
    .INIT(32'h0C800080)) 
     \slaveRegDo_mux_0[11]_i_15 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(I7),
        .O(O4));
LUT5 #(
    .INIT(32'h0C800080)) 
     \slaveRegDo_mux_0[12]_i_16 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(I6),
        .O(O3));
LUT5 #(
    .INIT(32'h55105555)) 
     \slaveRegDo_mux_0[13]_i_6 
       (.I0(s_daddr_o[4]),
        .I1(I1),
        .I2(\n_0_xsdb_reg_reg[13] ),
        .I3(I2),
        .I4(I3),
        .O(O1));
LUT5 #(
    .INIT(32'h55105555)) 
     \slaveRegDo_mux_0[14]_i_9 
       (.I0(s_daddr_o[4]),
        .I1(I1),
        .I2(\n_0_xsdb_reg_reg[14] ),
        .I3(I4),
        .I4(I5),
        .O(O2));
LUT6 #(
    .INIT(64'hFFFFFFFF5555D555)) 
     \slaveRegDo_mux_0[1]_i_13 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[1] ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(I12),
        .O(O13));
LUT6 #(
    .INIT(64'hFFFFFFFF5555D555)) 
     \slaveRegDo_mux_0[2]_i_13 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[2] ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(I11),
        .O(O12));
LUT6 #(
    .INIT(64'hFFFFFFFF5555D555)) 
     \slaveRegDo_mux_0[3]_i_14 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[3] ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(I10),
        .O(O11));
LUT5 #(
    .INIT(32'h0C800080)) 
     \slaveRegDo_mux_0[4]_i_17 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(I9),
        .O(O10));
LUT5 #(
    .INIT(32'h0C800080)) 
     \slaveRegDo_mux_0[6]_i_17 
       (.I0(\n_0_xsdb_reg_reg[6] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(O9),
        .O(O8));
LUT5 #(
    .INIT(32'h0C800080)) 
     \slaveRegDo_mux_0[8]_i_17 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(I8),
        .O(O7));
LUT5 #(
    .INIT(32'h0C800080)) 
     \slaveRegDo_mux_0[9]_i_17 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[3]),
        .I4(O6),
        .O(O5));
FDRE \xsdb_reg_reg[0] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_217
   (O1,
    Q,
    s_daddr_o,
    I1,
    E,
    I2);
  output O1;
  output [14:0]Q;
  input [2:0]s_daddr_o;
  input I1;
  input [0:0]E;
  input I2;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire O1;
  wire [14:0]Q;
  wire \n_0_xsdb_reg_reg[14] ;
  wire [2:0]s_daddr_o;

LUT5 #(
    .INIT(32'h2200C000)) 
     \slaveRegDo_mux_0[14]_i_14 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(s_daddr_o[2]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .O(O1));
FDRE \xsdb_reg_reg[0] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_218
   (O1,
    O2,
    O3,
    O4,
    O5,
    s_daddr_o,
    O12,
    Q,
    E,
    I1);
  output O1;
  output O2;
  output O3;
  output O4;
  output [11:0]O5;
  input [4:0]s_daddr_o;
  input [2:0]O12;
  input [2:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire O1;
  wire [2:0]O12;
  wire O2;
  wire O3;
  wire O4;
  wire [11:0]O5;
  wire [2:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire [4:0]s_daddr_o;

LUT6 #(
    .INIT(64'h0300838303008080)) 
     \slaveRegDo_mux_0[0]_i_18 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(O12[0]),
        .I4(s_daddr_o[3]),
        .I5(Q[0]),
        .O(O1));
LUT6 #(
    .INIT(64'hAAAAAAEAAAAAAAAA)) 
     \slaveRegDo_mux_0[12]_i_19 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(\n_0_xsdb_reg_reg[12] ),
        .O(O4));
LUT6 #(
    .INIT(64'h0300838303008080)) 
     \slaveRegDo_mux_0[1]_i_18 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(O12[1]),
        .I4(s_daddr_o[3]),
        .I5(Q[1]),
        .O(O2));
LUT6 #(
    .INIT(64'h0300838303008080)) 
     \slaveRegDo_mux_0[3]_i_19 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(O12[2]),
        .I4(s_daddr_o[3]),
        .I5(Q[2]),
        .O(O3));
FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O5[6]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_219
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    I1,
    I2,
    I3,
    I4,
    I5,
    s_daddr_o,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    E,
    I13);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input [5:0]s_daddr_o;
  input I6;
  input I7;
  input I8;
  input I9;
  input [13:0]I10;
  input I11;
  input I12;
  input [0:0]E;
  input I13;

  wire [0:0]E;
  wire I1;
  wire [13:0]I10;
  wire I11;
  wire I12;
  wire I13;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire \n_0_slaveRegDo_mux_0[0]_i_8 ;
  wire \n_0_slaveRegDo_mux_0[10]_i_11 ;
  wire \n_0_slaveRegDo_mux_0[11]_i_18 ;
  wire \n_0_slaveRegDo_mux_0[7]_i_17 ;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [5:0]s_daddr_o;

LUT6 #(
    .INIT(64'h0000000455555555)) 
     \slaveRegDo_mux_0[0]_i_3 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_0[0]_i_8 ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[0]),
        .I5(I9),
        .O(O4));
LUT5 #(
    .INIT(32'h02FF0200)) 
     \slaveRegDo_mux_0[0]_i_8 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[1]),
        .I4(I11),
        .O(\n_0_slaveRegDo_mux_0[0]_i_8 ));
LUT5 #(
    .INIT(32'h02FF0200)) 
     \slaveRegDo_mux_0[10]_i_11 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[5]),
        .I3(s_daddr_o[1]),
        .I4(I12),
        .O(\n_0_slaveRegDo_mux_0[10]_i_11 ));
LUT6 #(
    .INIT(64'h0000000455555555)) 
     \slaveRegDo_mux_0[10]_i_4 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_0[10]_i_11 ),
        .I2(s_daddr_o[4]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[0]),
        .I5(I6),
        .O(O2));
LUT6 #(
    .INIT(64'h5555404440444044)) 
     \slaveRegDo_mux_0[11]_i_13 
       (.I0(I1),
        .I1(I2),
        .I2(\n_0_slaveRegDo_mux_0[11]_i_18 ),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .O(O1));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[11]_i_18 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[9]),
        .O(\n_0_slaveRegDo_mux_0[11]_i_18 ));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[12]_i_21 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[10]),
        .O(O13));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[13]_i_19 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[11]),
        .O(O14));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[14]_i_19 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[12]),
        .O(O15));
LUT5 #(
    .INIT(32'h00003088)) 
     \slaveRegDo_mux_0[15]_i_19 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(s_daddr_o[1]),
        .I2(I10[13]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[5]),
        .O(O16));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[1]_i_15 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[0]),
        .O(O5));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[2]_i_15 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[1]),
        .O(O6));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[3]_i_16 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[2]),
        .O(O7));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[4]_i_19 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[3]),
        .O(O8));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[5]_i_19 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[4]),
        .O(O9));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[6]_i_19 
       (.I0(\n_0_xsdb_reg_reg[6] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[5]),
        .O(O10));
LUT6 #(
    .INIT(64'h5555404440444044)) 
     \slaveRegDo_mux_0[7]_i_12 
       (.I0(I1),
        .I1(I2),
        .I2(\n_0_slaveRegDo_mux_0[7]_i_17 ),
        .I3(I7),
        .I4(I4),
        .I5(I8),
        .O(O3));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[7]_i_17 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[6]),
        .O(\n_0_slaveRegDo_mux_0[7]_i_17 ));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[8]_i_19 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[7]),
        .O(O11));
LUT5 #(
    .INIT(32'h00380008)) 
     \slaveRegDo_mux_0[9]_i_19 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(I10[8]),
        .O(O12));
FDRE \xsdb_reg_reg[0] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I13),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_220
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_221
   (O1,
    Q,
    s_daddr_o,
    I1,
    I2,
    E,
    I3,
    I6);
  output O1;
  output [14:0]Q;
  input [2:0]s_daddr_o;
  input I1;
  input I2;
  input [0:0]E;
  input I3;
  input [9:0]I6;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire [9:0]I6;
  wire O1;
  wire [14:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire [2:0]s_daddr_o;

LUT6 #(
    .INIT(64'h00000000FFFF37F7)) 
     \slaveRegDo_mux_0[0]_i_7 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[2]),
        .I3(I1),
        .I4(s_daddr_o[0]),
        .I5(I2),
        .O(O1));
FDRE \xsdb_reg_reg[0] 
       (.C(I3),
        .CE(E),
        .D(I6[0]),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I3),
        .CE(E),
        .D(I6[1]),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I3),
        .CE(E),
        .D(I6[2]),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I3),
        .CE(E),
        .D(I6[3]),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I3),
        .CE(E),
        .D(I6[4]),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I3),
        .CE(E),
        .D(I6[5]),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I3),
        .CE(E),
        .D(I6[6]),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I3),
        .CE(E),
        .D(I6[7]),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I3),
        .CE(E),
        .D(I6[8]),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I3),
        .CE(E),
        .D(I6[9]),
        .Q(Q[8]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_222
   (Q,
    E,
    I8,
    I1);
  output [3:0]Q;
  input [0:0]E;
  input [3:0]I8;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [3:0]I8;
  wire [3:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(I8[0]),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(I8[1]),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(I8[2]),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(I8[3]),
        .Q(Q[3]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_223
   (O1,
    O2,
    O3,
    O4,
    O5,
    Q,
    s_daddr_o,
    I1,
    I2,
    E,
    I9,
    I3);
  output O1;
  output O2;
  output O3;
  output O4;
  output [11:0]O5;
  input [3:0]Q;
  input [1:0]s_daddr_o;
  input [3:0]I1;
  input [3:0]I2;
  input [0:0]E;
  input [15:0]I9;
  input I3;

  wire [0:0]E;
  wire [3:0]I1;
  wire [3:0]I2;
  wire I3;
  wire [15:0]I9;
  wire O1;
  wire O2;
  wire O3;
  wire O4;
  wire [11:0]O5;
  wire [3:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire [1:0]s_daddr_o;

LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_2[0]_i_3 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(Q[0]),
        .I2(s_daddr_o[1]),
        .I3(I1[0]),
        .I4(s_daddr_o[0]),
        .I5(I2[0]),
        .O(O1));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_2[1]_i_3 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(Q[1]),
        .I2(s_daddr_o[1]),
        .I3(I1[1]),
        .I4(s_daddr_o[0]),
        .I5(I2[1]),
        .O(O2));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_2[2]_i_3 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(Q[2]),
        .I2(s_daddr_o[1]),
        .I3(I1[2]),
        .I4(s_daddr_o[0]),
        .I5(I2[2]),
        .O(O3));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_2[3]_i_3 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(Q[3]),
        .I2(s_daddr_o[1]),
        .I3(I1[3]),
        .I4(s_daddr_o[0]),
        .I5(I2[3]),
        .O(O4));
FDRE \xsdb_reg_reg[0] 
       (.C(I3),
        .CE(E),
        .D(I9[0]),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I3),
        .CE(E),
        .D(I9[10]),
        .Q(O5[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I3),
        .CE(E),
        .D(I9[11]),
        .Q(O5[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I3),
        .CE(E),
        .D(I9[12]),
        .Q(O5[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I3),
        .CE(E),
        .D(I9[13]),
        .Q(O5[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I3),
        .CE(E),
        .D(I9[14]),
        .Q(O5[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I3),
        .CE(E),
        .D(I9[15]),
        .Q(O5[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I3),
        .CE(E),
        .D(I9[1]),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I3),
        .CE(E),
        .D(I9[2]),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I3),
        .CE(E),
        .D(I9[3]),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I3),
        .CE(E),
        .D(I9[4]),
        .Q(O5[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I3),
        .CE(E),
        .D(I9[5]),
        .Q(O5[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I3),
        .CE(E),
        .D(I9[6]),
        .Q(O5[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I3),
        .CE(E),
        .D(I9[7]),
        .Q(O5[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I3),
        .CE(E),
        .D(I9[8]),
        .Q(O5[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I3),
        .CE(E),
        .D(I9[9]),
        .Q(O5[5]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_224
   (Q,
    E,
    I1,
    I7);
  output [15:0]Q;
  input [0:0]E;
  input I1;
  input [1:0]I7;

  wire [0:0]E;
  wire I1;
  wire [1:0]I7;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(I7[0]),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(I7[1]),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_225
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    D,
    O16,
    O17,
    O18,
    O19,
    O20,
    O21,
    O22,
    O23,
    O24,
    O25,
    O26,
    O27,
    O28,
    O29,
    O30,
    O31,
    O32,
    s_daddr_o,
    Q,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    E,
    I24);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output [15:0]D;
  output O16;
  output O17;
  output O18;
  output O19;
  output O20;
  output O21;
  output [0:0]O22;
  output O23;
  output O24;
  output O25;
  output O26;
  output O27;
  output O28;
  output O29;
  output O30;
  output O31;
  output O32;
  input [4:0]s_daddr_o;
  input [14:0]Q;
  input I1;
  input [15:0]I2;
  input I3;
  input I4;
  input [15:0]I5;
  input [15:0]I6;
  input [15:0]I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input I23;
  input [0:0]E;
  input I24;

  wire [15:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire [15:0]I2;
  wire I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I3;
  wire I4;
  wire [15:0]I5;
  wire [15:0]I6;
  wire [15:0]I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire O20;
  wire O21;
  wire [0:0]O22;
  wire O23;
  wire O24;
  wire O25;
  wire O26;
  wire O27;
  wire O28;
  wire O29;
  wire O3;
  wire O30;
  wire O31;
  wire O32;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [14:0]Q;
  wire \n_0_slaveRegDo_mux_2[0]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[10]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[11]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[12]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[13]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[14]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[15]_i_3 ;
  wire \n_0_slaveRegDo_mux_2[1]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[2]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[3]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[4]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[5]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[6]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[7]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[8]_i_2 ;
  wire \n_0_slaveRegDo_mux_2[9]_i_2 ;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [4:0]s_daddr_o;

LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[0]_i_10 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[2]),
        .I2(I6[0]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[0]),
        .O(O16));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[0]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[0] ),
        .I2(s_daddr_o[1]),
        .I3(Q[0]),
        .O(O15));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[10]_i_10 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(s_daddr_o[2]),
        .I2(I6[10]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[10]),
        .O(O24));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[10]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[10] ),
        .I2(s_daddr_o[1]),
        .I3(Q[9]),
        .O(O6));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[11]_i_10 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(s_daddr_o[2]),
        .I2(I6[11]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[11]),
        .O(O29));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[11]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[11] ),
        .I2(s_daddr_o[1]),
        .I3(Q[10]),
        .O(O5));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[12]_i_10 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(s_daddr_o[2]),
        .I2(I6[12]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[12]),
        .O(O25));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[12]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[12] ),
        .I2(s_daddr_o[1]),
        .I3(Q[11]),
        .O(O4));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[13]_i_10 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(s_daddr_o[2]),
        .I2(I6[13]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[13]),
        .O(O26));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[13]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[13] ),
        .I2(s_daddr_o[1]),
        .I3(Q[12]),
        .O(O3));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[14]_i_10 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(s_daddr_o[2]),
        .I2(I6[14]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[14]),
        .O(O27));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[14]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[14] ),
        .I2(s_daddr_o[1]),
        .I3(Q[13]),
        .O(O2));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[15]_i_12 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(s_daddr_o[2]),
        .I2(I6[15]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[15]),
        .O(O28));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[15]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[15] ),
        .I2(s_daddr_o[1]),
        .I3(Q[14]),
        .O(O1));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[1]_i_10 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(s_daddr_o[2]),
        .I2(I6[1]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[1]),
        .O(O30));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[1]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[1] ),
        .I2(s_daddr_o[1]),
        .I3(Q[1]),
        .O(O14));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[2]_i_10 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(s_daddr_o[2]),
        .I2(I6[2]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[2]),
        .O(O17));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[2]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[2] ),
        .I2(s_daddr_o[1]),
        .I3(Q[2]),
        .O(O13));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[3]_i_10 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(s_daddr_o[2]),
        .I2(I6[3]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[3]),
        .O(O31));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[3]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[3] ),
        .I2(s_daddr_o[1]),
        .I3(Q[3]),
        .O(O12));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[4]_i_10 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(s_daddr_o[2]),
        .I2(I6[4]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[4]),
        .O(O18));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[4]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[4] ),
        .I2(s_daddr_o[1]),
        .I3(Q[4]),
        .O(O11));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[5]_i_10 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(s_daddr_o[2]),
        .I2(I6[5]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[5]),
        .O(O19));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[5]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[5] ),
        .I2(s_daddr_o[1]),
        .I3(Q[5]),
        .O(O10));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[6]_i_10 
       (.I0(\n_0_xsdb_reg_reg[6] ),
        .I1(s_daddr_o[2]),
        .I2(I6[6]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[6]),
        .O(O20));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[6]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[6] ),
        .I2(s_daddr_o[1]),
        .I3(Q[6]),
        .O(O9));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[7]_i_10 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(s_daddr_o[2]),
        .I2(I6[7]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[7]),
        .O(O32));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[7]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[7] ),
        .I2(s_daddr_o[1]),
        .I3(Q[7]),
        .O(O8));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[8]_i_5 
       (.I0(O22),
        .I1(s_daddr_o[2]),
        .I2(I6[8]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[8]),
        .O(O21));
LUT6 #(
    .INIT(64'h470C0F33473F0FFF)) 
     \slaveRegDo_mux_1[9]_i_10 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(s_daddr_o[2]),
        .I2(I6[9]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[4]),
        .I5(I7[9]),
        .O(O23));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[9]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(\n_0_xsdb_reg_reg[9] ),
        .I2(s_daddr_o[1]),
        .I3(Q[8]),
        .O(O7));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[0]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[0]_i_2 ),
        .I2(I2[0]),
        .I3(I3),
        .I4(I4),
        .I5(I5[0]),
        .O(D[0]));
LUT6 #(
    .INIT(64'hFF00FFFF80800000)) 
     \slaveRegDo_mux_2[0]_i_2 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(I23),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[0]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[10]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[10]_i_2 ),
        .I2(I2[10]),
        .I3(I3),
        .I4(I4),
        .I5(I5[10]),
        .O(D[10]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[10]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[10] ),
        .I2(s_daddr_o[1]),
        .I3(I13),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[10]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[11]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[11]_i_2 ),
        .I2(I2[11]),
        .I3(I3),
        .I4(I4),
        .I5(I5[11]),
        .O(D[11]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[11]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[11] ),
        .I2(s_daddr_o[1]),
        .I3(I12),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[11]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[12]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[12]_i_2 ),
        .I2(I2[12]),
        .I3(I3),
        .I4(I4),
        .I5(I5[12]),
        .O(D[12]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[12]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[12] ),
        .I2(s_daddr_o[1]),
        .I3(I11),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[12]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[13]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[13]_i_2 ),
        .I2(I2[13]),
        .I3(I3),
        .I4(I4),
        .I5(I5[13]),
        .O(D[13]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[13]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[13] ),
        .I2(s_daddr_o[1]),
        .I3(I10),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[13]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[14]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[14]_i_2 ),
        .I2(I2[14]),
        .I3(I3),
        .I4(I4),
        .I5(I5[14]),
        .O(D[14]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[14]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[14] ),
        .I2(s_daddr_o[1]),
        .I3(I9),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[14]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[15]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[15]_i_3 ),
        .I2(I2[15]),
        .I3(I3),
        .I4(I4),
        .I5(I5[15]),
        .O(D[15]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[15]_i_3 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[15] ),
        .I2(s_daddr_o[1]),
        .I3(I8),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[15]_i_3 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[1]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[1]_i_2 ),
        .I2(I2[1]),
        .I3(I3),
        .I4(I4),
        .I5(I5[1]),
        .O(D[1]));
LUT6 #(
    .INIT(64'hFF00FFFF80800000)) 
     \slaveRegDo_mux_2[1]_i_2 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(I22),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[1]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[2]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[2]_i_2 ),
        .I2(I2[2]),
        .I3(I3),
        .I4(I4),
        .I5(I5[2]),
        .O(D[2]));
LUT6 #(
    .INIT(64'hFF00FFFF80800000)) 
     \slaveRegDo_mux_2[2]_i_2 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(I21),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[2]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[3]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[3]_i_2 ),
        .I2(I2[3]),
        .I3(I3),
        .I4(I4),
        .I5(I5[3]),
        .O(D[3]));
LUT6 #(
    .INIT(64'hFF00FFFF80800000)) 
     \slaveRegDo_mux_2[3]_i_2 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[0]),
        .I3(I20),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[3]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[4]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[4]_i_2 ),
        .I2(I2[4]),
        .I3(I3),
        .I4(I4),
        .I5(I5[4]),
        .O(D[4]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[4]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[4] ),
        .I2(s_daddr_o[1]),
        .I3(I19),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[4]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[5]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[5]_i_2 ),
        .I2(I2[5]),
        .I3(I3),
        .I4(I4),
        .I5(I5[5]),
        .O(D[5]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[5]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[5] ),
        .I2(s_daddr_o[1]),
        .I3(I18),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[5]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[6]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[6]_i_2 ),
        .I2(I2[6]),
        .I3(I3),
        .I4(I4),
        .I5(I5[6]),
        .O(D[6]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[6]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[6] ),
        .I2(s_daddr_o[1]),
        .I3(I17),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[6]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[7]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[7]_i_2 ),
        .I2(I2[7]),
        .I3(I3),
        .I4(I4),
        .I5(I5[7]),
        .O(D[7]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[7]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[7] ),
        .I2(s_daddr_o[1]),
        .I3(I16),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[7]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[8]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[8]_i_2 ),
        .I2(I2[8]),
        .I3(I3),
        .I4(I4),
        .I5(I5[8]),
        .O(D[8]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[8]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(O22),
        .I2(s_daddr_o[1]),
        .I3(I15),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[8]_i_2 ));
LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
     \slaveRegDo_mux_2[9]_i_1 
       (.I0(I1),
        .I1(\n_0_slaveRegDo_mux_2[9]_i_2 ),
        .I2(I2[9]),
        .I3(I3),
        .I4(I4),
        .I5(I5[9]),
        .O(D[9]));
LUT6 #(
    .INIT(64'hFF00FFFF8F800000)) 
     \slaveRegDo_mux_2[9]_i_2 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_xsdb_reg_reg[9] ),
        .I2(s_daddr_o[1]),
        .I3(I14),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_2[9]_i_2 ));
FDRE \xsdb_reg_reg[0] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I24),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(O22),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I24),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_231
   (Q,
    E,
    I5,
    I1);
  output [3:0]Q;
  input [0:0]E;
  input [3:0]I5;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [3:0]I5;
  wire [3:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(I5[0]),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(I5[1]),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(I5[2]),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(I5[3]),
        .Q(Q[3]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_233
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    D,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    O17,
    O18,
    O19,
    O20,
    Q,
    I1,
    s_daddr_o,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    slaveRegDo_84,
    I20,
    I21,
    I22,
    I23,
    I24,
    I25,
    I26,
    I27,
    I28,
    I29,
    I30,
    I31,
    I32,
    I33,
    I34,
    I35,
    I36,
    I37,
    E,
    I38);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output [1:0]D;
  output [0:0]O7;
  output [15:0]O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  output O17;
  output O18;
  output O19;
  output O20;
  input [7:0]Q;
  input I1;
  input [5:0]s_daddr_o;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input [0:0]I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input [7:0]slaveRegDo_84;
  input [7:0]I20;
  input I21;
  input I22;
  input I23;
  input I24;
  input I25;
  input I26;
  input I27;
  input I28;
  input I29;
  input I30;
  input I31;
  input I32;
  input [12:0]I33;
  input I34;
  input I35;
  input I36;
  input I37;
  input [0:0]E;
  input I38;

  wire [1:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire [0:0]I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire [7:0]I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I28;
  wire I29;
  wire I3;
  wire I30;
  wire I31;
  wire I32;
  wire [12:0]I33;
  wire I34;
  wire I35;
  wire I36;
  wire I37;
  wire I38;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire O20;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire [0:0]O7;
  wire [15:0]O8;
  wire O9;
  wire [7:0]Q;
  wire \n_0_slaveRegDo_mux_0[10]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[10]_i_6 ;
  wire \n_0_slaveRegDo_mux_0[11]_i_5 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_14 ;
  wire \n_0_slaveRegDo_mux_0[4]_i_6 ;
  wire \n_0_slaveRegDo_mux_0[6]_i_6 ;
  wire \n_0_slaveRegDo_mux_0[7]_i_5 ;
  wire \n_0_slaveRegDo_mux_0[8]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[8]_i_6 ;
  wire \n_0_slaveRegDo_mux_0[9]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[0]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[10]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[12]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[14]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[15]_i_11 ;
  wire \n_0_slaveRegDo_mux_1[1]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[2]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[3]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[4]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[6]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[7]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[8]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[8]_i_4 ;
  wire \n_0_slaveRegDo_mux_1[9]_i_9 ;
  wire [5:0]s_daddr_o;
  wire [7:0]slaveRegDo_84;

LUT6 #(
    .INIT(64'hFFFF0000FFF4FFF4)) 
     \slaveRegDo_mux_0[10]_i_1 
       (.I0(\n_0_slaveRegDo_mux_0[10]_i_2 ),
        .I1(I12),
        .I2(I13),
        .I3(I14),
        .I4(I15),
        .I5(I16),
        .O(D[1]));
LUT6 #(
    .INIT(64'h00510000FFFFFFFF)) 
     \slaveRegDo_mux_0[10]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[10]_i_6 ),
        .I1(Q[5]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(I8),
        .I5(I3),
        .O(\n_0_slaveRegDo_mux_0[10]_i_2 ));
LUT6 #(
    .INIT(64'h0000000033E200E2)) 
     \slaveRegDo_mux_0[10]_i_6 
       (.I0(O8[10]),
        .I1(s_daddr_o[5]),
        .I2(slaveRegDo_84[5]),
        .I3(s_daddr_o[3]),
        .I4(I20[5]),
        .I5(I21),
        .O(\n_0_slaveRegDo_mux_0[10]_i_6 ));
LUT6 #(
    .INIT(64'h00510000FFFFFFFF)) 
     \slaveRegDo_mux_0[11]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[11]_i_5 ),
        .I1(Q[6]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(I9),
        .I5(I3),
        .O(O5));
LUT6 #(
    .INIT(64'h0000000033E200E2)) 
     \slaveRegDo_mux_0[11]_i_5 
       (.I0(O8[11]),
        .I1(s_daddr_o[5]),
        .I2(slaveRegDo_84[6]),
        .I3(s_daddr_o[3]),
        .I4(I20[6]),
        .I5(I21),
        .O(\n_0_slaveRegDo_mux_0[11]_i_5 ));
LUT6 #(
    .INIT(64'hF5F557F7FFFF57F7)) 
     \slaveRegDo_mux_0[15]_i_14 
       (.I0(I37),
        .I1(O8[15]),
        .I2(s_daddr_o[5]),
        .I3(slaveRegDo_84[7]),
        .I4(s_daddr_o[3]),
        .I5(I20[7]),
        .O(\n_0_slaveRegDo_mux_0[15]_i_14 ));
LUT6 #(
    .INIT(64'h00A20000FFFFFFFF)) 
     \slaveRegDo_mux_0[15]_i_5 
       (.I0(\n_0_slaveRegDo_mux_0[15]_i_14 ),
        .I1(Q[7]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(I11),
        .I5(I3),
        .O(O6));
LUT6 #(
    .INIT(64'h00510000FFFFFFFF)) 
     \slaveRegDo_mux_0[4]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[4]_i_6 ),
        .I1(Q[0]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(I2),
        .I5(I3),
        .O(O1));
LUT6 #(
    .INIT(64'h0000000033E200E2)) 
     \slaveRegDo_mux_0[4]_i_6 
       (.I0(O8[4]),
        .I1(s_daddr_o[5]),
        .I2(slaveRegDo_84[0]),
        .I3(s_daddr_o[3]),
        .I4(I20[0]),
        .I5(I21),
        .O(\n_0_slaveRegDo_mux_0[4]_i_6 ));
LUT6 #(
    .INIT(64'h00510000FFFFFFFF)) 
     \slaveRegDo_mux_0[6]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[6]_i_6 ),
        .I1(Q[1]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(I4),
        .I5(I3),
        .O(O2));
LUT6 #(
    .INIT(64'h0000000033E200E2)) 
     \slaveRegDo_mux_0[6]_i_6 
       (.I0(O8[6]),
        .I1(s_daddr_o[5]),
        .I2(slaveRegDo_84[1]),
        .I3(s_daddr_o[3]),
        .I4(I20[1]),
        .I5(I21),
        .O(\n_0_slaveRegDo_mux_0[6]_i_6 ));
LUT6 #(
    .INIT(64'h00510000FFFFFFFF)) 
     \slaveRegDo_mux_0[7]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[7]_i_5 ),
        .I1(Q[2]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(I5),
        .I5(I3),
        .O(O3));
LUT6 #(
    .INIT(64'h0000000033E200E2)) 
     \slaveRegDo_mux_0[7]_i_5 
       (.I0(O8[7]),
        .I1(s_daddr_o[5]),
        .I2(slaveRegDo_84[2]),
        .I3(s_daddr_o[3]),
        .I4(I20[2]),
        .I5(I21),
        .O(\n_0_slaveRegDo_mux_0[7]_i_5 ));
LUT6 #(
    .INIT(64'hBBBBBBBBBBBB8B88)) 
     \slaveRegDo_mux_0[8]_i_1 
       (.I0(O7),
        .I1(I16),
        .I2(\n_0_slaveRegDo_mux_0[8]_i_2 ),
        .I3(I17),
        .I4(I18),
        .I5(I19),
        .O(D[0]));
LUT6 #(
    .INIT(64'h00510000FFFFFFFF)) 
     \slaveRegDo_mux_0[8]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[8]_i_6 ),
        .I1(Q[3]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(I6),
        .I5(I3),
        .O(\n_0_slaveRegDo_mux_0[8]_i_2 ));
LUT6 #(
    .INIT(64'h0000000033E200E2)) 
     \slaveRegDo_mux_0[8]_i_6 
       (.I0(O8[8]),
        .I1(s_daddr_o[5]),
        .I2(slaveRegDo_84[3]),
        .I3(s_daddr_o[3]),
        .I4(I20[3]),
        .I5(I21),
        .O(\n_0_slaveRegDo_mux_0[8]_i_6 ));
LUT6 #(
    .INIT(64'h00510000FFFFFFFF)) 
     \slaveRegDo_mux_0[9]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[9]_i_6 ),
        .I1(Q[4]),
        .I2(I1),
        .I3(s_daddr_o[0]),
        .I4(I7),
        .I5(I3),
        .O(O4));
LUT6 #(
    .INIT(64'h0000000033E200E2)) 
     \slaveRegDo_mux_0[9]_i_6 
       (.I0(O8[9]),
        .I1(s_daddr_o[5]),
        .I2(slaveRegDo_84[4]),
        .I3(s_daddr_o[3]),
        .I4(I20[4]),
        .I5(I21),
        .O(\n_0_slaveRegDo_mux_0[9]_i_6 ));
LUT5 #(
    .INIT(32'h02DF5D7F)) 
     \slaveRegDo_mux_1[0]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(O8[0]),
        .I3(I33[0]),
        .I4(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_1[0]_i_9 ));
LUT5 #(
    .INIT(32'h1D3F473F)) 
     \slaveRegDo_mux_1[10]_i_9 
       (.I0(O8[10]),
        .I1(s_daddr_o[3]),
        .I2(I33[9]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .O(\n_0_slaveRegDo_mux_1[10]_i_9 ));
LUT5 #(
    .INIT(32'h1D3F473F)) 
     \slaveRegDo_mux_1[12]_i_9 
       (.I0(O8[12]),
        .I1(s_daddr_o[3]),
        .I2(I33[10]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .O(\n_0_slaveRegDo_mux_1[12]_i_9 ));
LUT5 #(
    .INIT(32'h1D3F473F)) 
     \slaveRegDo_mux_1[14]_i_9 
       (.I0(O8[14]),
        .I1(s_daddr_o[3]),
        .I2(I33[11]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .O(\n_0_slaveRegDo_mux_1[14]_i_9 ));
LUT5 #(
    .INIT(32'h1D3F473F)) 
     \slaveRegDo_mux_1[15]_i_11 
       (.I0(O8[15]),
        .I1(s_daddr_o[3]),
        .I2(I33[12]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .O(\n_0_slaveRegDo_mux_1[15]_i_11 ));
LUT5 #(
    .INIT(32'h02DF5D7F)) 
     \slaveRegDo_mux_1[1]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(O8[1]),
        .I3(I33[1]),
        .I4(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_1[1]_i_9 ));
LUT5 #(
    .INIT(32'h02DF5D7F)) 
     \slaveRegDo_mux_1[2]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(O8[2]),
        .I3(I33[2]),
        .I4(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_1[2]_i_9 ));
LUT5 #(
    .INIT(32'h02DF5D7F)) 
     \slaveRegDo_mux_1[3]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(O8[3]),
        .I3(I33[3]),
        .I4(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_1[3]_i_9 ));
LUT5 #(
    .INIT(32'h02DF5D7F)) 
     \slaveRegDo_mux_1[4]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(O8[4]),
        .I3(I33[4]),
        .I4(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_1[4]_i_9 ));
LUT5 #(
    .INIT(32'h1D3F473F)) 
     \slaveRegDo_mux_1[6]_i_9 
       (.I0(O8[6]),
        .I1(s_daddr_o[3]),
        .I2(I33[5]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .O(\n_0_slaveRegDo_mux_1[6]_i_9 ));
LUT5 #(
    .INIT(32'h02DF5D7F)) 
     \slaveRegDo_mux_1[7]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(O8[7]),
        .I3(I33[6]),
        .I4(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_1[7]_i_9 ));
LUT4 #(
    .INIT(16'h0151)) 
     \slaveRegDo_mux_1[8]_i_2 
       (.I0(s_daddr_o[4]),
        .I1(\n_0_slaveRegDo_mux_1[8]_i_4 ),
        .I2(s_daddr_o[0]),
        .I3(I10),
        .O(\n_0_slaveRegDo_mux_1[8]_i_2 ));
LUT5 #(
    .INIT(32'h02DF5D7F)) 
     \slaveRegDo_mux_1[8]_i_4 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(O8[8]),
        .I3(I33[7]),
        .I4(s_daddr_o[3]),
        .O(\n_0_slaveRegDo_mux_1[8]_i_4 ));
LUT5 #(
    .INIT(32'h1D3F473F)) 
     \slaveRegDo_mux_1[9]_i_9 
       (.I0(O8[9]),
        .I1(s_daddr_o[3]),
        .I2(I33[8]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .O(\n_0_slaveRegDo_mux_1[9]_i_9 ));
MUXF7 \slaveRegDo_mux_1_reg[0]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[0]_i_9 ),
        .I1(I22),
        .O(O9),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[10]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[10]_i_9 ),
        .I1(I29),
        .O(O14),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[12]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[12]_i_9 ),
        .I1(I30),
        .O(O15),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[14]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[14]_i_9 ),
        .I1(I31),
        .O(O16),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[15]_i_6 
       (.I0(\n_0_slaveRegDo_mux_1[15]_i_11 ),
        .I1(I32),
        .O(O17),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[1]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[1]_i_9 ),
        .I1(I36),
        .O(O20),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[2]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[2]_i_9 ),
        .I1(I23),
        .O(O10),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[3]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[3]_i_9 ),
        .I1(I35),
        .O(O19),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[4]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[4]_i_9 ),
        .I1(I24),
        .O(O11),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[6]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[6]_i_9 ),
        .I1(I25),
        .O(O12),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[7]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[7]_i_9 ),
        .I1(I34),
        .O(O18),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[8]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[8]_i_2 ),
        .I1(I27),
        .O(O7),
        .S(I26));
MUXF7 \slaveRegDo_mux_1_reg[9]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[9]_i_9 ),
        .I1(I28),
        .O(O13),
        .S(s_daddr_o[0]));
FDRE \xsdb_reg_reg[0] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I38),
        .CE(E),
        .D(1'b1),
        .Q(O8[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I38),
        .CE(E),
        .D(1'b0),
        .Q(O8[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_234
   (O1,
    O2,
    Q,
    s_daddr_o,
    I1,
    I2,
    E,
    I3);
  output O1;
  output O2;
  output [13:0]Q;
  input [2:0]s_daddr_o;
  input I1;
  input I2;
  input [0:0]E;
  input I3;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire O1;
  wire O2;
  wire [13:0]Q;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire [2:0]s_daddr_o;

LUT5 #(
    .INIT(32'hEEEFFFEF)) 
     \slaveRegDo_mux_0[11]_i_19 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .I2(\n_0_xsdb_reg_reg[11] ),
        .I3(s_daddr_o[2]),
        .I4(I2),
        .O(O2));
LUT5 #(
    .INIT(32'hEEEFFFEF)) 
     \slaveRegDo_mux_0[7]_i_18 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[0]),
        .I2(\n_0_xsdb_reg_reg[7] ),
        .I3(s_daddr_o[2]),
        .I4(I1),
        .O(O1));
FDRE \xsdb_reg_reg[0] 
       (.C(I3),
        .CE(E),
        .D(1'b1),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I3),
        .CE(E),
        .D(1'b1),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I3),
        .CE(E),
        .D(1'b1),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_235
   (O1,
    Q,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    D,
    O16,
    O17,
    O18,
    O19,
    O20,
    O21,
    O22,
    O23,
    O24,
    O25,
    O26,
    O27,
    O28,
    O29,
    O30,
    O31,
    O32,
    O33,
    O34,
    O35,
    O36,
    O37,
    O38,
    O39,
    O40,
    O41,
    O42,
    O43,
    O44,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    slaveRegDo_81,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    I24,
    I25,
    I26,
    I27,
    I28,
    I29,
    I30,
    I31,
    I32,
    I33,
    I34,
    I35,
    I36,
    I37,
    I38,
    I39,
    I40,
    I41,
    I42,
    I43,
    I44,
    I45,
    I46,
    I47,
    I48,
    I49,
    I50,
    I51,
    I52,
    I53,
    I54,
    I55,
    I56,
    I57,
    I58,
    I59,
    I60,
    I61,
    I62,
    I63,
    I64,
    I65,
    I66,
    I67,
    I68,
    slaveRegDo_6,
    slaveRegDo_82,
    I69,
    I70,
    I71,
    I72,
    I73,
    I74,
    I75,
    I76,
    I77,
    slaveRegDo_80,
    slaveRegDo_84,
    I78,
    E,
    I79);
  output O1;
  output [15:0]Q;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output [5:0]D;
  output O16;
  output O17;
  output O18;
  output O19;
  output O20;
  output O21;
  output O22;
  output O23;
  output O24;
  output O25;
  output O26;
  output O27;
  output O28;
  output O29;
  output O30;
  output O31;
  output O32;
  output O33;
  output O34;
  output O35;
  output O36;
  output O37;
  output O38;
  output O39;
  output O40;
  output O41;
  output O42;
  output O43;
  output O44;
  input [6:0]s_daddr_o;
  input [11:0]I1;
  input [11:0]I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input [15:0]slaveRegDo_81;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input [5:0]I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input [0:0]I23;
  input I24;
  input I25;
  input I26;
  input I27;
  input I28;
  input I29;
  input I30;
  input I31;
  input I32;
  input I33;
  input I34;
  input I35;
  input I36;
  input I37;
  input I38;
  input I39;
  input I40;
  input I41;
  input I42;
  input I43;
  input I44;
  input I45;
  input I46;
  input I47;
  input I48;
  input I49;
  input I50;
  input I51;
  input I52;
  input I53;
  input I54;
  input I55;
  input I56;
  input I57;
  input I58;
  input I59;
  input I60;
  input I61;
  input I62;
  input I63;
  input I64;
  input [13:0]I65;
  input I66;
  input I67;
  input I68;
  input [12:0]slaveRegDo_6;
  input [12:0]slaveRegDo_82;
  input I69;
  input I70;
  input I71;
  input I72;
  input I73;
  input I74;
  input I75;
  input I76;
  input I77;
  input [3:0]slaveRegDo_80;
  input [3:0]slaveRegDo_84;
  input [3:0]I78;
  input [0:0]E;
  input I79;

  wire [5:0]D;
  wire [0:0]E;
  wire [11:0]I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire [5:0]I16;
  wire I17;
  wire I18;
  wire I19;
  wire [11:0]I2;
  wire I20;
  wire I21;
  wire I22;
  wire [0:0]I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I28;
  wire I29;
  wire I3;
  wire I30;
  wire I31;
  wire I32;
  wire I33;
  wire I34;
  wire I35;
  wire I36;
  wire I37;
  wire I38;
  wire I39;
  wire I4;
  wire I40;
  wire I41;
  wire I42;
  wire I43;
  wire I44;
  wire I45;
  wire I46;
  wire I47;
  wire I48;
  wire I49;
  wire I5;
  wire I50;
  wire I51;
  wire I52;
  wire I53;
  wire I54;
  wire I55;
  wire I56;
  wire I57;
  wire I58;
  wire I59;
  wire I6;
  wire I60;
  wire I61;
  wire I62;
  wire I63;
  wire I64;
  wire [13:0]I65;
  wire I66;
  wire I67;
  wire I68;
  wire I69;
  wire I7;
  wire I70;
  wire I71;
  wire I72;
  wire I73;
  wire I74;
  wire I75;
  wire I76;
  wire I77;
  wire [3:0]I78;
  wire I79;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire O20;
  wire O21;
  wire O22;
  wire O23;
  wire O24;
  wire O25;
  wire O26;
  wire O27;
  wire O28;
  wire O29;
  wire O3;
  wire O30;
  wire O31;
  wire O32;
  wire O33;
  wire O34;
  wire O35;
  wire O36;
  wire O37;
  wire O38;
  wire O39;
  wire O4;
  wire O40;
  wire O41;
  wire O42;
  wire O43;
  wire O44;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire \n_0_slaveRegDo_mux_0[0]_i_10 ;
  wire \n_0_slaveRegDo_mux_0[0]_i_16 ;
  wire \n_0_slaveRegDo_mux_0[0]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[0]_i_4 ;
  wire \n_0_slaveRegDo_mux_0[0]_i_5 ;
  wire \n_0_slaveRegDo_mux_0[12]_i_11 ;
  wire \n_0_slaveRegDo_mux_0[12]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[12]_i_5 ;
  wire \n_0_slaveRegDo_mux_0[12]_i_6 ;
  wire \n_0_slaveRegDo_mux_0[13]_i_9 ;
  wire \n_0_slaveRegDo_mux_0[14]_i_8 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_7 ;
  wire \n_0_slaveRegDo_mux_0[1]_i_10 ;
  wire \n_0_slaveRegDo_mux_0[1]_i_16 ;
  wire \n_0_slaveRegDo_mux_0[1]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[1]_i_4 ;
  wire \n_0_slaveRegDo_mux_0[1]_i_5 ;
  wire \n_0_slaveRegDo_mux_0[2]_i_10 ;
  wire \n_0_slaveRegDo_mux_0[2]_i_16 ;
  wire \n_0_slaveRegDo_mux_0[2]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[2]_i_4 ;
  wire \n_0_slaveRegDo_mux_0[2]_i_5 ;
  wire \n_0_slaveRegDo_mux_0[3]_i_11 ;
  wire \n_0_slaveRegDo_mux_0[3]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[4]_i_11 ;
  wire \n_0_slaveRegDo_mux_0[5]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[5]_i_3 ;
  wire \n_0_slaveRegDo_mux_0[5]_i_5 ;
  wire \n_0_slaveRegDo_mux_0[5]_i_9 ;
  wire \n_0_slaveRegDo_mux_0[6]_i_11 ;
  wire \n_0_slaveRegDo_mux_0[8]_i_11 ;
  wire \n_0_slaveRegDo_mux_0[9]_i_11 ;
  wire [6:0]s_daddr_o;
  wire [12:0]slaveRegDo_6;
  wire [3:0]slaveRegDo_80;
  wire [15:0]slaveRegDo_81;
  wire [12:0]slaveRegDo_82;
  wire [3:0]slaveRegDo_84;

LUT6 #(
    .INIT(64'hFFFF0000EEFEEEFE)) 
     \slaveRegDo_mux_0[0]_i_1 
       (.I0(\n_0_slaveRegDo_mux_0[0]_i_2 ),
        .I1(I41),
        .I2(I19),
        .I3(\n_0_slaveRegDo_mux_0[0]_i_4 ),
        .I4(I16[0]),
        .I5(I17),
        .O(D[0]));
LUT6 #(
    .INIT(64'h4777474747777777)) 
     \slaveRegDo_mux_0[0]_i_10 
       (.I0(\n_0_slaveRegDo_mux_0[0]_i_16 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[6]),
        .I3(slaveRegDo_82[0]),
        .I4(s_daddr_o[1]),
        .I5(slaveRegDo_80[0]),
        .O(\n_0_slaveRegDo_mux_0[0]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_0[0]_i_16 
       (.I0(Q[0]),
        .I1(slaveRegDo_84[0]),
        .I2(s_daddr_o[6]),
        .I3(slaveRegDo_6[0]),
        .I4(s_daddr_o[1]),
        .I5(I78[0]),
        .O(\n_0_slaveRegDo_mux_0[0]_i_16 ));
LUT5 #(
    .INIT(32'hA8A8A8AA)) 
     \slaveRegDo_mux_0[0]_i_2 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[0]_i_5 ),
        .I2(I51),
        .I3(s_daddr_o[6]),
        .I4(I52),
        .O(\n_0_slaveRegDo_mux_0[0]_i_2 ));
LUT6 #(
    .INIT(64'hDDD0DDD0DDD0DDDD)) 
     \slaveRegDo_mux_0[0]_i_4 
       (.I0(I11),
        .I1(\n_0_slaveRegDo_mux_0[0]_i_10 ),
        .I2(s_daddr_o[6]),
        .I3(I42),
        .I4(I43),
        .I5(I44),
        .O(\n_0_slaveRegDo_mux_0[0]_i_4 ));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[0]_i_5 
       (.I0(I11),
        .I1(Q[0]),
        .I2(s_daddr_o[6]),
        .I3(I66),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[0]),
        .O(\n_0_slaveRegDo_mux_0[0]_i_5 ));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[10]_i_10 
       (.I0(I11),
        .I1(Q[10]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[9]),
        .I5(slaveRegDo_82[9]),
        .O(O42));
LUT6 #(
    .INIT(64'h1D331DFFFFFFFFFF)) 
     \slaveRegDo_mux_0[10]_i_14 
       (.I0(Q[10]),
        .I1(s_daddr_o[6]),
        .I2(I13),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_81[10]),
        .I5(I11),
        .O(O14));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[11]_i_12 
       (.I0(I11),
        .I1(Q[11]),
        .I2(s_daddr_o[6]),
        .I3(I75),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[11]),
        .O(O44));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[11]_i_9 
       (.I0(I11),
        .I1(Q[11]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[10]),
        .I5(slaveRegDo_82[10]),
        .O(O43));
LUT6 #(
    .INIT(64'hFFFF0000EEFEEEFE)) 
     \slaveRegDo_mux_0[12]_i_1 
       (.I0(\n_0_slaveRegDo_mux_0[12]_i_2 ),
        .I1(I15),
        .I2(I3),
        .I3(\n_0_slaveRegDo_mux_0[12]_i_5 ),
        .I4(I16[4]),
        .I5(I17),
        .O(D[4]));
LUT6 #(
    .INIT(64'h1D331DFFFFFFFFFF)) 
     \slaveRegDo_mux_0[12]_i_11 
       (.I0(Q[12]),
        .I1(s_daddr_o[6]),
        .I2(I12),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_81[12]),
        .I5(I11),
        .O(\n_0_slaveRegDo_mux_0[12]_i_11 ));
LUT6 #(
    .INIT(64'h00000000BBBF0000)) 
     \slaveRegDo_mux_0[12]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[12]_i_6 ),
        .I1(s_daddr_o[1]),
        .I2(s_daddr_o[6]),
        .I3(I18),
        .I4(I19),
        .I5(I20),
        .O(\n_0_slaveRegDo_mux_0[12]_i_2 ));
LUT6 #(
    .INIT(64'hAAAAAAAA08080008)) 
     \slaveRegDo_mux_0[12]_i_5 
       (.I0(\n_0_slaveRegDo_mux_0[12]_i_11 ),
        .I1(I21),
        .I2(I22),
        .I3(I23),
        .I4(I24),
        .I5(s_daddr_o[6]),
        .O(\n_0_slaveRegDo_mux_0[12]_i_5 ));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[12]_i_6 
       (.I0(I11),
        .I1(Q[12]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[11]),
        .I5(slaveRegDo_82[11]),
        .O(\n_0_slaveRegDo_mux_0[12]_i_6 ));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[13]_i_3 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[13]_i_9 ),
        .I2(s_daddr_o[6]),
        .I3(I63),
        .I4(I64),
        .O(O22));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[13]_i_9 
       (.I0(I11),
        .I1(Q[13]),
        .I2(s_daddr_o[6]),
        .I3(I76),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[13]),
        .O(\n_0_slaveRegDo_mux_0[13]_i_9 ));
LUT6 #(
    .INIT(64'hFB00FB000000FB00)) 
     \slaveRegDo_mux_0[14]_i_3 
       (.I0(\n_0_slaveRegDo_mux_0[14]_i_8 ),
        .I1(s_daddr_o[1]),
        .I2(I45),
        .I3(I19),
        .I4(I46),
        .I5(I47),
        .O(O17));
LUT6 #(
    .INIT(64'h1D331DFFFFFFFFFF)) 
     \slaveRegDo_mux_0[14]_i_7 
       (.I0(Q[14]),
        .I1(s_daddr_o[6]),
        .I2(I10),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_81[14]),
        .I5(I11),
        .O(O13));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[14]_i_8 
       (.I0(I11),
        .I1(Q[14]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[12]),
        .I5(slaveRegDo_82[12]),
        .O(\n_0_slaveRegDo_mux_0[14]_i_8 ));
LUT6 #(
    .INIT(64'hFFFF0000EEFEEEFE)) 
     \slaveRegDo_mux_0[15]_i_1 
       (.I0(\n_0_slaveRegDo_mux_0[15]_i_2 ),
        .I1(I48),
        .I2(I49),
        .I3(I50),
        .I4(I16[5]),
        .I5(I17),
        .O(D[5]));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[15]_i_2 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[15]_i_7 ),
        .I2(s_daddr_o[6]),
        .I3(I8),
        .I4(I9),
        .O(\n_0_slaveRegDo_mux_0[15]_i_2 ));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[15]_i_7 
       (.I0(I11),
        .I1(Q[15]),
        .I2(s_daddr_o[6]),
        .I3(I77),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[15]),
        .O(\n_0_slaveRegDo_mux_0[15]_i_7 ));
LUT6 #(
    .INIT(64'hFFFF0000EEFEEEFE)) 
     \slaveRegDo_mux_0[1]_i_1 
       (.I0(\n_0_slaveRegDo_mux_0[1]_i_2 ),
        .I1(I37),
        .I2(I19),
        .I3(\n_0_slaveRegDo_mux_0[1]_i_4 ),
        .I4(I16[1]),
        .I5(I17),
        .O(D[1]));
LUT6 #(
    .INIT(64'h4777474747777777)) 
     \slaveRegDo_mux_0[1]_i_10 
       (.I0(\n_0_slaveRegDo_mux_0[1]_i_16 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[6]),
        .I3(slaveRegDo_82[1]),
        .I4(s_daddr_o[1]),
        .I5(slaveRegDo_80[1]),
        .O(\n_0_slaveRegDo_mux_0[1]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_0[1]_i_16 
       (.I0(Q[1]),
        .I1(slaveRegDo_84[1]),
        .I2(s_daddr_o[6]),
        .I3(slaveRegDo_6[1]),
        .I4(s_daddr_o[1]),
        .I5(I78[1]),
        .O(\n_0_slaveRegDo_mux_0[1]_i_16 ));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[1]_i_2 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[1]_i_5 ),
        .I2(s_daddr_o[6]),
        .I3(I4),
        .I4(I5),
        .O(\n_0_slaveRegDo_mux_0[1]_i_2 ));
LUT6 #(
    .INIT(64'hDDD0DDD0DDD0DDDD)) 
     \slaveRegDo_mux_0[1]_i_4 
       (.I0(I11),
        .I1(\n_0_slaveRegDo_mux_0[1]_i_10 ),
        .I2(s_daddr_o[6]),
        .I3(I38),
        .I4(I39),
        .I5(I40),
        .O(\n_0_slaveRegDo_mux_0[1]_i_4 ));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[1]_i_5 
       (.I0(I11),
        .I1(Q[1]),
        .I2(s_daddr_o[6]),
        .I3(I67),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[1]),
        .O(\n_0_slaveRegDo_mux_0[1]_i_5 ));
LUT6 #(
    .INIT(64'hFFFF0000EEFEEEFE)) 
     \slaveRegDo_mux_0[2]_i_1 
       (.I0(\n_0_slaveRegDo_mux_0[2]_i_2 ),
        .I1(I33),
        .I2(I19),
        .I3(\n_0_slaveRegDo_mux_0[2]_i_4 ),
        .I4(I16[2]),
        .I5(I17),
        .O(D[2]));
LUT6 #(
    .INIT(64'h4777474747777777)) 
     \slaveRegDo_mux_0[2]_i_10 
       (.I0(\n_0_slaveRegDo_mux_0[2]_i_16 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[6]),
        .I3(slaveRegDo_82[2]),
        .I4(s_daddr_o[1]),
        .I5(slaveRegDo_80[2]),
        .O(\n_0_slaveRegDo_mux_0[2]_i_10 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_0[2]_i_16 
       (.I0(Q[2]),
        .I1(slaveRegDo_84[2]),
        .I2(s_daddr_o[6]),
        .I3(slaveRegDo_6[2]),
        .I4(s_daddr_o[1]),
        .I5(I78[2]),
        .O(\n_0_slaveRegDo_mux_0[2]_i_16 ));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[2]_i_2 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[2]_i_5 ),
        .I2(s_daddr_o[6]),
        .I3(I6),
        .I4(I7),
        .O(\n_0_slaveRegDo_mux_0[2]_i_2 ));
LUT6 #(
    .INIT(64'hDDD0DDD0DDD0DDDD)) 
     \slaveRegDo_mux_0[2]_i_4 
       (.I0(I11),
        .I1(\n_0_slaveRegDo_mux_0[2]_i_10 ),
        .I2(s_daddr_o[6]),
        .I3(I34),
        .I4(I35),
        .I5(I36),
        .O(\n_0_slaveRegDo_mux_0[2]_i_4 ));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[2]_i_5 
       (.I0(I11),
        .I1(Q[2]),
        .I2(s_daddr_o[6]),
        .I3(I68),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[2]),
        .O(\n_0_slaveRegDo_mux_0[2]_i_5 ));
LUT6 #(
    .INIT(64'h4777474747777777)) 
     \slaveRegDo_mux_0[3]_i_11 
       (.I0(\n_0_slaveRegDo_mux_0[3]_i_17 ),
        .I1(s_daddr_o[2]),
        .I2(s_daddr_o[6]),
        .I3(slaveRegDo_82[3]),
        .I4(s_daddr_o[1]),
        .I5(slaveRegDo_80[3]),
        .O(\n_0_slaveRegDo_mux_0[3]_i_11 ));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_0[3]_i_17 
       (.I0(Q[3]),
        .I1(slaveRegDo_84[3]),
        .I2(s_daddr_o[6]),
        .I3(slaveRegDo_6[3]),
        .I4(s_daddr_o[1]),
        .I5(I78[3]),
        .O(\n_0_slaveRegDo_mux_0[3]_i_17 ));
LUT6 #(
    .INIT(64'hDDD0DDD0DDD0DDDD)) 
     \slaveRegDo_mux_0[3]_i_5 
       (.I0(I11),
        .I1(\n_0_slaveRegDo_mux_0[3]_i_11 ),
        .I2(s_daddr_o[6]),
        .I3(I30),
        .I4(I31),
        .I5(I32),
        .O(O16));
LUT6 #(
    .INIT(64'h1D331DFFFFFFFFFF)) 
     \slaveRegDo_mux_0[3]_i_8 
       (.I0(Q[3]),
        .I1(s_daddr_o[6]),
        .I2(I14),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_81[3]),
        .I5(I11),
        .O(O15));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[4]_i_10 
       (.I0(I11),
        .I1(Q[4]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[4]),
        .I5(slaveRegDo_82[4]),
        .O(O37));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[4]_i_11 
       (.I0(I11),
        .I1(Q[4]),
        .I2(s_daddr_o[6]),
        .I3(I69),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[4]),
        .O(\n_0_slaveRegDo_mux_0[4]_i_11 ));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[4]_i_4 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[4]_i_11 ),
        .I2(s_daddr_o[6]),
        .I3(I53),
        .I4(I54),
        .O(O18));
LUT6 #(
    .INIT(64'hBBB8BBB8BBB8BBBB)) 
     \slaveRegDo_mux_0[5]_i_1 
       (.I0(I16[3]),
        .I1(I17),
        .I2(\n_0_slaveRegDo_mux_0[5]_i_2 ),
        .I3(\n_0_slaveRegDo_mux_0[5]_i_3 ),
        .I4(I25),
        .I5(I26),
        .O(D[3]));
LUT6 #(
    .INIT(64'hFB00FB000000FB00)) 
     \slaveRegDo_mux_0[5]_i_2 
       (.I0(\n_0_slaveRegDo_mux_0[5]_i_5 ),
        .I1(s_daddr_o[1]),
        .I2(I27),
        .I3(I19),
        .I4(I28),
        .I5(I29),
        .O(\n_0_slaveRegDo_mux_0[5]_i_2 ));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[5]_i_3 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[5]_i_9 ),
        .I2(s_daddr_o[6]),
        .I3(I55),
        .I4(I56),
        .O(\n_0_slaveRegDo_mux_0[5]_i_3 ));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[5]_i_5 
       (.I0(I11),
        .I1(Q[5]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[5]),
        .I5(slaveRegDo_82[5]),
        .O(\n_0_slaveRegDo_mux_0[5]_i_5 ));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[5]_i_9 
       (.I0(I11),
        .I1(Q[5]),
        .I2(s_daddr_o[6]),
        .I3(I70),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[5]),
        .O(\n_0_slaveRegDo_mux_0[5]_i_9 ));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[6]_i_10 
       (.I0(I11),
        .I1(Q[6]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[6]),
        .I5(slaveRegDo_82[6]),
        .O(O38));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[6]_i_11 
       (.I0(I11),
        .I1(Q[6]),
        .I2(s_daddr_o[6]),
        .I3(I71),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[6]),
        .O(\n_0_slaveRegDo_mux_0[6]_i_11 ));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[6]_i_4 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[6]_i_11 ),
        .I2(s_daddr_o[6]),
        .I3(I57),
        .I4(I58),
        .O(O19));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[7]_i_11 
       (.I0(I11),
        .I1(Q[7]),
        .I2(s_daddr_o[6]),
        .I3(I72),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[7]),
        .O(O39));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[8]_i_10 
       (.I0(I11),
        .I1(Q[8]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[7]),
        .I5(slaveRegDo_82[7]),
        .O(O40));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[8]_i_11 
       (.I0(I11),
        .I1(Q[8]),
        .I2(s_daddr_o[6]),
        .I3(I73),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[8]),
        .O(\n_0_slaveRegDo_mux_0[8]_i_11 ));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[8]_i_4 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[8]_i_11 ),
        .I2(s_daddr_o[6]),
        .I3(I59),
        .I4(I60),
        .O(O20));
LUT6 #(
    .INIT(64'h8AA08A0080A08000)) 
     \slaveRegDo_mux_0[9]_i_10 
       (.I0(I11),
        .I1(Q[9]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[6]),
        .I4(slaveRegDo_6[8]),
        .I5(slaveRegDo_82[8]),
        .O(O41));
LUT6 #(
    .INIT(64'hA808A0A0A8080000)) 
     \slaveRegDo_mux_0[9]_i_11 
       (.I0(I11),
        .I1(Q[9]),
        .I2(s_daddr_o[6]),
        .I3(I74),
        .I4(s_daddr_o[2]),
        .I5(slaveRegDo_81[9]),
        .O(\n_0_slaveRegDo_mux_0[9]_i_11 ));
LUT5 #(
    .INIT(32'h8A888A8A)) 
     \slaveRegDo_mux_0[9]_i_4 
       (.I0(I3),
        .I1(\n_0_slaveRegDo_mux_0[9]_i_11 ),
        .I2(s_daddr_o[6]),
        .I3(I61),
        .I4(I62),
        .O(O21));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[11]_i_3 
       (.I0(Q[11]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[9]),
        .O(O32));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[12]_i_3 
       (.I0(Q[12]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[10]),
        .O(O33));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[13]_i_3 
       (.I0(Q[13]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[11]),
        .O(O34));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[14]_i_3 
       (.I0(Q[14]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[12]),
        .O(O35));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[15]_i_3 
       (.I0(Q[15]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[13]),
        .O(O36));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[1]_i_3 
       (.I0(Q[1]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[0]),
        .O(O23));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[2]_i_3 
       (.I0(Q[2]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[1]),
        .O(O24));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[3]_i_3 
       (.I0(Q[3]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[2]),
        .O(O25));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[4]_i_3 
       (.I0(Q[4]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[3]),
        .O(O26));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[5]_i_3 
       (.I0(Q[5]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[4]),
        .O(O27));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[6]_i_3 
       (.I0(Q[6]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[5]),
        .O(O28));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[7]_i_3 
       (.I0(Q[7]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[6]),
        .O(O29));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[8]_i_7 
       (.I0(Q[8]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[7]),
        .O(O30));
LUT6 #(
    .INIT(64'h0000030800000008)) 
     \slaveRegDo_mux_1[9]_i_3 
       (.I0(Q[9]),
        .I1(s_daddr_o[3]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[5]),
        .I4(s_daddr_o[4]),
        .I5(I65[8]),
        .O(O31));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[10]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[10]),
        .I2(s_daddr_o[0]),
        .I3(I1[6]),
        .I4(s_daddr_o[1]),
        .I5(I2[6]),
        .O(O6));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[11]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[11]),
        .I2(s_daddr_o[0]),
        .I3(I1[7]),
        .I4(s_daddr_o[1]),
        .I5(I2[7]),
        .O(O5));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[12]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[12]),
        .I2(s_daddr_o[0]),
        .I3(I1[8]),
        .I4(s_daddr_o[1]),
        .I5(I2[8]),
        .O(O4));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[13]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[13]),
        .I2(s_daddr_o[0]),
        .I3(I1[9]),
        .I4(s_daddr_o[1]),
        .I5(I2[9]),
        .O(O3));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[14]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[14]),
        .I2(s_daddr_o[0]),
        .I3(I1[10]),
        .I4(s_daddr_o[1]),
        .I5(I2[10]),
        .O(O2));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[15]_i_4 
       (.I0(s_daddr_o[3]),
        .I1(Q[15]),
        .I2(s_daddr_o[0]),
        .I3(I1[11]),
        .I4(s_daddr_o[1]),
        .I5(I2[11]),
        .O(O1));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[4]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[4]),
        .I2(s_daddr_o[0]),
        .I3(I1[0]),
        .I4(s_daddr_o[1]),
        .I5(I2[0]),
        .O(O12));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[5]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[5]),
        .I2(s_daddr_o[0]),
        .I3(I1[1]),
        .I4(s_daddr_o[1]),
        .I5(I2[1]),
        .O(O11));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[6]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[6]),
        .I2(s_daddr_o[0]),
        .I3(I1[2]),
        .I4(s_daddr_o[1]),
        .I5(I2[2]),
        .O(O10));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[7]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[7]),
        .I2(s_daddr_o[0]),
        .I3(I1[3]),
        .I4(s_daddr_o[1]),
        .I5(I2[3]),
        .O(O9));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[8]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[8]),
        .I2(s_daddr_o[0]),
        .I3(I1[4]),
        .I4(s_daddr_o[1]),
        .I5(I2[4]),
        .O(O8));
LUT6 #(
    .INIT(64'hF0F0A8080000A808)) 
     \slaveRegDo_mux_2[9]_i_3 
       (.I0(s_daddr_o[3]),
        .I1(Q[9]),
        .I2(s_daddr_o[0]),
        .I3(I1[5]),
        .I4(s_daddr_o[1]),
        .I5(I2[5]),
        .O(O7));
FDRE \xsdb_reg_reg[0] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I79),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_241
   (O1,
    O2,
    O3,
    O4,
    O5,
    s_daddr_o,
    Q,
    I1,
    slaveRegDo_84,
    I2,
    E,
    I3);
  output O1;
  output O2;
  output O3;
  output O4;
  output [11:0]O5;
  input [4:0]s_daddr_o;
  input [2:0]Q;
  input I1;
  input [3:0]slaveRegDo_84;
  input [3:0]I2;
  input [0:0]E;
  input I3;

  wire [0:0]E;
  wire I1;
  wire [3:0]I2;
  wire I3;
  wire O1;
  wire O2;
  wire O3;
  wire O4;
  wire [11:0]O5;
  wire [2:0]Q;
  wire \n_0_slaveRegDo_mux_0[13]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[14]_i_18 ;
  wire \n_0_slaveRegDo_mux_0[5]_i_17 ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire [4:0]s_daddr_o;
  wire [3:0]slaveRegDo_84;

LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[12]_i_20 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(s_daddr_o[3]),
        .I2(slaveRegDo_84[1]),
        .I3(s_daddr_o[4]),
        .I4(I2[1]),
        .O(O4));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[13]_i_17 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(s_daddr_o[3]),
        .I2(slaveRegDo_84[2]),
        .I3(s_daddr_o[4]),
        .I4(I2[2]),
        .O(\n_0_slaveRegDo_mux_0[13]_i_17 ));
LUT6 #(
    .INIT(64'hFFFFFFFF4040FF40)) 
     \slaveRegDo_mux_0[13]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_slaveRegDo_mux_0[13]_i_17 ),
        .I3(Q[1]),
        .I4(I1),
        .I5(s_daddr_o[0]),
        .O(O2));
LUT6 #(
    .INIT(64'hFFFFFFFF4040FF40)) 
     \slaveRegDo_mux_0[14]_i_11 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_slaveRegDo_mux_0[14]_i_18 ),
        .I3(Q[2]),
        .I4(I1),
        .I5(s_daddr_o[0]),
        .O(O3));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[14]_i_18 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(s_daddr_o[3]),
        .I2(slaveRegDo_84[3]),
        .I3(s_daddr_o[4]),
        .I4(I2[3]),
        .O(\n_0_slaveRegDo_mux_0[14]_i_18 ));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[5]_i_17 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(s_daddr_o[3]),
        .I2(slaveRegDo_84[0]),
        .I3(s_daddr_o[4]),
        .I4(I2[0]),
        .O(\n_0_slaveRegDo_mux_0[5]_i_17 ));
LUT6 #(
    .INIT(64'hFFFFFFFF4040FF40)) 
     \slaveRegDo_mux_0[5]_i_8 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_slaveRegDo_mux_0[5]_i_17 ),
        .I3(Q[0]),
        .I4(I1),
        .I5(s_daddr_o[0]),
        .O(O1));
FDRE \xsdb_reg_reg[0] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O5[8]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_242
   (O1,
    O2,
    O3,
    s_daddr_o,
    I1,
    Q,
    I2,
    E,
    I3);
  output O1;
  output O2;
  output [13:0]O3;
  input [1:0]s_daddr_o;
  input I1;
  input [1:0]Q;
  input I2;
  input [0:0]E;
  input I3;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire O1;
  wire O2;
  wire [13:0]O3;
  wire [1:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire [1:0]s_daddr_o;

LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[0]_i_15 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[0]),
        .I2(I2),
        .I3(s_daddr_o[1]),
        .I4(Q[0]),
        .O(O2));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[10]_i_17 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(s_daddr_o[0]),
        .I2(I1),
        .I3(s_daddr_o[1]),
        .I4(Q[1]),
        .O(O1));
FDRE \xsdb_reg_reg[0] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(O3[8]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_243
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O15,
    O16,
    O17,
    O18,
    O19,
    O20,
    s_daddr_o,
    Q,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    O11,
    O12,
    O13,
    O14,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    E,
    I14);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O15;
  output O16;
  output O17;
  output O18;
  output O19;
  output [0:0]O20;
  input [4:0]s_daddr_o;
  input [14:0]Q;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input O11;
  input O12;
  input O13;
  input O14;
  input [2:0]I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input [0:0]I13;
  input [0:0]E;
  input I14;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire [0:0]I13;
  wire I14;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire [2:0]I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O17;
  wire O18;
  wire O19;
  wire O2;
  wire [0:0]O20;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [14:0]Q;
  wire \n_0_slaveRegDo_mux_0[15]_i_12 ;
  wire \n_0_slaveRegDo_mux_0[15]_i_21 ;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [4:0]s_daddr_o;

LUT6 #(
    .INIT(64'h00FA000C000A000C)) 
     \slaveRegDo_mux_0[0]_i_19 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(Q[0]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(O14),
        .O(O10));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[10]_i_9 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_xsdb_reg_reg[10] ),
        .I3(s_daddr_o[3]),
        .I4(Q[10]),
        .I5(I1),
        .O(O1));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[11]_i_8 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_xsdb_reg_reg[11] ),
        .I3(s_daddr_o[3]),
        .I4(Q[11]),
        .I5(I2),
        .O(O2));
LUT6 #(
    .INIT(64'h00000000F000ACAC)) 
     \slaveRegDo_mux_0[13]_i_14 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(Q[12]),
        .I2(s_daddr_o[3]),
        .I3(I8),
        .I4(s_daddr_o[1]),
        .I5(s_daddr_o[2]),
        .O(O17));
LUT6 #(
    .INIT(64'h00000000F000ACAC)) 
     \slaveRegDo_mux_0[14]_i_15 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(Q[13]),
        .I2(s_daddr_o[3]),
        .I3(I9),
        .I4(s_daddr_o[1]),
        .I5(s_daddr_o[2]),
        .O(O18));
LUT6 #(
    .INIT(64'hCF33CFFFAAAAAAAA)) 
     \slaveRegDo_mux_0[15]_i_12 
       (.I0(\n_0_slaveRegDo_mux_0[15]_i_21 ),
        .I1(s_daddr_o[2]),
        .I2(I11),
        .I3(s_daddr_o[3]),
        .I4(I7[2]),
        .I5(s_daddr_o[1]),
        .O(\n_0_slaveRegDo_mux_0[15]_i_12 ));
LUT6 #(
    .INIT(64'h0F0055330FFF5533)) 
     \slaveRegDo_mux_0[15]_i_21 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(Q[14]),
        .I2(I12),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[2]),
        .I5(I13),
        .O(\n_0_slaveRegDo_mux_0[15]_i_21 ));
LUT6 #(
    .INIT(64'h1F1F1F1F1F1F1FFF)) 
     \slaveRegDo_mux_0[15]_i_4 
       (.I0(\n_0_slaveRegDo_mux_0[15]_i_12 ),
        .I1(s_daddr_o[4]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[2]),
        .I5(I10),
        .O(O19));
LUT6 #(
    .INIT(64'h00FA000C000A000C)) 
     \slaveRegDo_mux_0[1]_i_19 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(Q[1]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(O13),
        .O(O9));
LUT6 #(
    .INIT(64'h00FA000C000A000C)) 
     \slaveRegDo_mux_0[2]_i_19 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(Q[2]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(O12),
        .O(O8));
LUT6 #(
    .INIT(64'h00FA000C000A000C)) 
     \slaveRegDo_mux_0[3]_i_20 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(Q[3]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[3]),
        .I5(O11),
        .O(O7));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[4]_i_9 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_xsdb_reg_reg[4] ),
        .I3(s_daddr_o[3]),
        .I4(Q[4]),
        .I5(I6),
        .O(O6));
LUT6 #(
    .INIT(64'h0F0000AC000000AC)) 
     \slaveRegDo_mux_0[5]_i_14 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(Q[5]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .I5(I7[0]),
        .O(O15));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[6]_i_9 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_xsdb_reg_reg[6] ),
        .I3(s_daddr_o[3]),
        .I4(Q[6]),
        .I5(I5),
        .O(O5));
LUT6 #(
    .INIT(64'h0F0000AC000000AC)) 
     \slaveRegDo_mux_0[7]_i_15 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(Q[7]),
        .I2(s_daddr_o[3]),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[1]),
        .I5(I7[1]),
        .O(O16));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[8]_i_9 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_xsdb_reg_reg[8] ),
        .I3(s_daddr_o[3]),
        .I4(Q[8]),
        .I5(I4),
        .O(O4));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[9]_i_9 
       (.I0(s_daddr_o[1]),
        .I1(s_daddr_o[2]),
        .I2(\n_0_xsdb_reg_reg[9] ),
        .I3(s_daddr_o[3]),
        .I4(Q[9]),
        .I5(I3),
        .O(O3));
FDRE \xsdb_reg_reg[0] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(O20),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I14),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_244
   (O1,
    D,
    O2,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    s_daddr_o,
    O3,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    Q,
    I24,
    I25,
    I26,
    E,
    I27);
  output O1;
  output [1:0]D;
  output O2;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output [1:0]O14;
  input [3:0]s_daddr_o;
  input [13:0]O3;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input [1:0]I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input I23;
  input [0:0]Q;
  input I24;
  input I25;
  input I26;
  input [0:0]E;
  input I27;

  wire [1:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I3;
  wire I4;
  wire I5;
  wire [1:0]I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire [1:0]O14;
  wire O2;
  wire [13:0]O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [0:0]Q;
  wire \n_0_slaveRegDo_mux_0[14]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[14]_i_5 ;
  wire \n_0_slaveRegDo_mux_0[3]_i_2 ;
  wire \n_0_slaveRegDo_mux_0[3]_i_6 ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [3:0]s_daddr_o;

LUT6 #(
    .INIT(64'h0F0000AC000000AC)) 
     \slaveRegDo_mux_0[10]_i_18 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(O3[9]),
        .I2(s_daddr_o[2]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[0]),
        .I5(Q),
        .O(O11));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[11]_i_11 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[11] ),
        .I3(s_daddr_o[2]),
        .I4(O3[10]),
        .I5(I24),
        .O(O12));
LUT6 #(
    .INIT(64'h00FA000C000A000C)) 
     \slaveRegDo_mux_0[12]_i_13 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(O3[11]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[2]),
        .I5(I2),
        .O(O1));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[13]_i_10 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[13] ),
        .I3(s_daddr_o[2]),
        .I4(O3[12]),
        .I5(I25),
        .O(O13));
LUT6 #(
    .INIT(64'hFFFF0000EEEFEEEF)) 
     \slaveRegDo_mux_0[14]_i_1 
       (.I0(\n_0_slaveRegDo_mux_0[14]_i_2 ),
        .I1(I11),
        .I2(I12),
        .I3(I13),
        .I4(I6[1]),
        .I5(I7),
        .O(D[1]));
LUT5 #(
    .INIT(32'h2022AAAA)) 
     \slaveRegDo_mux_0[14]_i_2 
       (.I0(I8),
        .I1(s_daddr_o[3]),
        .I2(\n_0_slaveRegDo_mux_0[14]_i_5 ),
        .I3(I14),
        .I4(I15),
        .O(\n_0_slaveRegDo_mux_0[14]_i_2 ));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[14]_i_5 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[14] ),
        .I3(s_daddr_o[2]),
        .I4(O3[13]),
        .I5(I26),
        .O(\n_0_slaveRegDo_mux_0[14]_i_5 ));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[1]_i_6 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[1] ),
        .I3(s_daddr_o[2]),
        .I4(O3[0]),
        .I5(I16),
        .O(O2));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[2]_i_6 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[2] ),
        .I3(s_daddr_o[2]),
        .I4(O3[1]),
        .I5(I17),
        .O(O4));
LUT6 #(
    .INIT(64'hFFFF0000EEFEEEFE)) 
     \slaveRegDo_mux_0[3]_i_1 
       (.I0(\n_0_slaveRegDo_mux_0[3]_i_2 ),
        .I1(I3),
        .I2(I4),
        .I3(I5),
        .I4(I6[0]),
        .I5(I7),
        .O(D[0]));
LUT5 #(
    .INIT(32'h2022AAAA)) 
     \slaveRegDo_mux_0[3]_i_2 
       (.I0(I8),
        .I1(s_daddr_o[3]),
        .I2(\n_0_slaveRegDo_mux_0[3]_i_6 ),
        .I3(I9),
        .I4(I10),
        .O(\n_0_slaveRegDo_mux_0[3]_i_2 ));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[3]_i_6 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[3] ),
        .I3(s_daddr_o[2]),
        .I4(O3[2]),
        .I5(I1),
        .O(\n_0_slaveRegDo_mux_0[3]_i_6 ));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[4]_i_12 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[4] ),
        .I3(s_daddr_o[2]),
        .I4(O3[3]),
        .I5(I18),
        .O(O5));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[5]_i_10 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[5] ),
        .I3(s_daddr_o[2]),
        .I4(O3[4]),
        .I5(I19),
        .O(O6));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[6]_i_12 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[6] ),
        .I3(s_daddr_o[2]),
        .I4(O3[5]),
        .I5(I20),
        .O(O7));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[7]_i_10 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[7] ),
        .I3(s_daddr_o[2]),
        .I4(O3[6]),
        .I5(I21),
        .O(O8));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[8]_i_12 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[8] ),
        .I3(s_daddr_o[2]),
        .I4(O3[7]),
        .I5(I22),
        .O(O9));
LUT6 #(
    .INIT(64'hFFFFFFFF10111000)) 
     \slaveRegDo_mux_0[9]_i_12 
       (.I0(s_daddr_o[0]),
        .I1(s_daddr_o[1]),
        .I2(\n_0_xsdb_reg_reg[9] ),
        .I3(s_daddr_o[2]),
        .I4(O3[8]),
        .I5(I23),
        .O(O10));
FDRE \xsdb_reg_reg[0] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(O14[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(O14[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I27),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_245
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    Q,
    s_daddr_o,
    I1,
    slaveRegDo_18,
    slaveRegDo_80,
    E,
    I2);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output [4:0]O12;
  input [9:0]Q;
  input [3:0]s_daddr_o;
  input [0:0]I1;
  input [8:0]slaveRegDo_18;
  input [8:0]slaveRegDo_80;
  input [0:0]E;
  input I2;

  wire [0:0]E;
  wire [0:0]I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire [4:0]O12;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [9:0]Q;
  wire \n_0_slaveRegDo_mux_0[11]_i_14 ;
  wire \n_0_slaveRegDo_mux_0[13]_i_16 ;
  wire \n_0_slaveRegDo_mux_0[14]_i_17 ;
  wire \n_0_slaveRegDo_mux_0[4]_i_16 ;
  wire \n_0_slaveRegDo_mux_0[5]_i_16 ;
  wire \n_0_slaveRegDo_mux_0[7]_i_13 ;
  wire \n_0_slaveRegDo_mux_0[8]_i_16 ;
  wire \n_0_slaveRegDo_mux_0[9]_i_16 ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [3:0]s_daddr_o;
  wire [8:0]slaveRegDo_18;
  wire [8:0]slaveRegDo_80;

LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[11]_i_14 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[5]),
        .I3(s_daddr_o[3]),
        .I4(Q[6]),
        .O(\n_0_slaveRegDo_mux_0[11]_i_14 ));
LUT6 #(
    .INIT(64'hFBFBFBFBABFBFBFB)) 
     \slaveRegDo_mux_0[11]_i_6 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_slaveRegDo_mux_0[11]_i_14 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_18[5]),
        .I5(s_daddr_o[3]),
        .O(O4));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[12]_i_18 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[6]),
        .I3(s_daddr_o[3]),
        .I4(Q[7]),
        .O(O11));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[13]_i_16 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[7]),
        .I3(s_daddr_o[3]),
        .I4(Q[8]),
        .O(\n_0_slaveRegDo_mux_0[13]_i_16 ));
LUT6 #(
    .INIT(64'hFBFBFBFBABFBFBFB)) 
     \slaveRegDo_mux_0[13]_i_7 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_slaveRegDo_mux_0[13]_i_16 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_18[6]),
        .I5(s_daddr_o[3]),
        .O(O3));
LUT6 #(
    .INIT(64'hFBFBFBFBABFBFBFB)) 
     \slaveRegDo_mux_0[14]_i_10 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_slaveRegDo_mux_0[14]_i_17 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_18[7]),
        .I5(s_daddr_o[3]),
        .O(O2));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[14]_i_17 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[8]),
        .I3(s_daddr_o[3]),
        .I4(Q[9]),
        .O(\n_0_slaveRegDo_mux_0[14]_i_17 ));
LUT5 #(
    .INIT(32'hDDDFFFDF)) 
     \slaveRegDo_mux_0[15]_i_23 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[3]),
        .I2(\n_0_xsdb_reg_reg[15] ),
        .I3(s_daddr_o[1]),
        .I4(slaveRegDo_18[8]),
        .O(O10));
LUT6 #(
    .INIT(64'h00FA000C000A000C)) 
     \slaveRegDo_mux_0[2]_i_18 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(Q[0]),
        .I2(s_daddr_o[0]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[2]),
        .I5(I1),
        .O(O1));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[4]_i_16 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[0]),
        .I3(s_daddr_o[3]),
        .I4(Q[1]),
        .O(\n_0_slaveRegDo_mux_0[4]_i_16 ));
LUT6 #(
    .INIT(64'hFBFBFBFBABFBFBFB)) 
     \slaveRegDo_mux_0[4]_i_7 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_slaveRegDo_mux_0[4]_i_16 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_18[0]),
        .I5(s_daddr_o[3]),
        .O(O9));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[5]_i_16 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[1]),
        .I3(s_daddr_o[3]),
        .I4(Q[2]),
        .O(\n_0_slaveRegDo_mux_0[5]_i_16 ));
LUT6 #(
    .INIT(64'hFBFBFBFBABFBFBFB)) 
     \slaveRegDo_mux_0[5]_i_7 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_slaveRegDo_mux_0[5]_i_16 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_18[1]),
        .I5(s_daddr_o[3]),
        .O(O8));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[7]_i_13 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[2]),
        .I3(s_daddr_o[3]),
        .I4(Q[3]),
        .O(\n_0_slaveRegDo_mux_0[7]_i_13 ));
LUT6 #(
    .INIT(64'hFBFBFBFBABFBFBFB)) 
     \slaveRegDo_mux_0[7]_i_6 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_slaveRegDo_mux_0[7]_i_13 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_18[2]),
        .I5(s_daddr_o[3]),
        .O(O7));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[8]_i_16 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[3]),
        .I3(s_daddr_o[3]),
        .I4(Q[4]),
        .O(\n_0_slaveRegDo_mux_0[8]_i_16 ));
LUT6 #(
    .INIT(64'hFBFBFBFBABFBFBFB)) 
     \slaveRegDo_mux_0[8]_i_7 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_slaveRegDo_mux_0[8]_i_16 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_18[3]),
        .I5(s_daddr_o[3]),
        .O(O6));
LUT5 #(
    .INIT(32'h30BB3088)) 
     \slaveRegDo_mux_0[9]_i_16 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(s_daddr_o[2]),
        .I2(slaveRegDo_80[4]),
        .I3(s_daddr_o[3]),
        .I4(Q[5]),
        .O(\n_0_slaveRegDo_mux_0[9]_i_16 ));
LUT6 #(
    .INIT(64'hFBFBFBFBABFBFBFB)) 
     \slaveRegDo_mux_0[9]_i_7 
       (.I0(s_daddr_o[0]),
        .I1(\n_0_slaveRegDo_mux_0[9]_i_16 ),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[2]),
        .I4(slaveRegDo_18[4]),
        .I5(s_daddr_o[3]),
        .O(O5));
FDRE \xsdb_reg_reg[0] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(O12[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(O12[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(O12[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(O12[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(O12[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_246
   (O1,
    O2,
    O3,
    s_daddr_o,
    Q,
    E,
    I1);
  output O1;
  output O2;
  output [13:0]O3;
  input [2:0]s_daddr_o;
  input [1:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire O1;
  wire O2;
  wire [13:0]O3;
  wire [1:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire [2:0]s_daddr_o;

LUT5 #(
    .INIT(32'h000000E2)) 
     \slaveRegDo_mux_0[0]_i_14 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[2]),
        .I2(Q[0]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[0]),
        .O(O1));
LUT5 #(
    .INIT(32'h000000E2)) 
     \slaveRegDo_mux_0[15]_i_18 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(s_daddr_o[2]),
        .I2(Q[1]),
        .I3(s_daddr_o[1]),
        .I4(s_daddr_o[0]),
        .O(O2));
FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(O3[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[8]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_247
   (O1,
    Q,
    s_daddr_o,
    I1,
    slaveRegDo_80,
    I2,
    E,
    I3);
  output O1;
  output [14:0]Q;
  input [1:0]s_daddr_o;
  input I1;
  input [0:0]slaveRegDo_80;
  input I2;
  input [0:0]E;
  input I3;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire O1;
  wire [14:0]Q;
  wire \n_0_xsdb_reg_reg[15] ;
  wire [1:0]s_daddr_o;
  wire [0:0]slaveRegDo_80;

LUT6 #(
    .INIT(64'hBBBFFFBFAAAAAAAA)) 
     \slaveRegDo_mux_0[15]_i_16 
       (.I0(s_daddr_o[0]),
        .I1(I1),
        .I2(\n_0_xsdb_reg_reg[15] ),
        .I3(s_daddr_o[1]),
        .I4(slaveRegDo_80),
        .I5(I2),
        .O(O1));
FDRE \xsdb_reg_reg[0] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I3),
        .CE(E),
        .D(1'b1),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I3),
        .CE(E),
        .D(1'b1),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I3),
        .CE(E),
        .D(1'b1),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I3),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_248
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_249
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_250
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    s_daddr_o,
    Q,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    E,
    I19);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input [1:0]s_daddr_o;
  input [15:0]Q;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input [0:0]I17;
  input [0:0]I18;
  input [0:0]E;
  input I19;

  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire [0:0]I17;
  wire [0:0]I18;
  wire I19;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [1:0]s_daddr_o;

LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[0]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[0] ),
        .I2(s_daddr_o[0]),
        .I3(Q[0]),
        .I4(I16),
        .I5(I2),
        .O(O15));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[10]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[10] ),
        .I2(s_daddr_o[0]),
        .I3(Q[10]),
        .I4(I7),
        .I5(I2),
        .O(O6));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[11]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[11] ),
        .I2(s_daddr_o[0]),
        .I3(Q[11]),
        .I4(I6),
        .I5(I2),
        .O(O5));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[12]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[12] ),
        .I2(s_daddr_o[0]),
        .I3(Q[12]),
        .I4(I5),
        .I5(I2),
        .O(O4));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[13]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[13] ),
        .I2(s_daddr_o[0]),
        .I3(Q[13]),
        .I4(I4),
        .I5(I2),
        .O(O3));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[14]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[14] ),
        .I2(s_daddr_o[0]),
        .I3(Q[14]),
        .I4(I3),
        .I5(I2),
        .O(O2));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[15]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[15] ),
        .I2(s_daddr_o[0]),
        .I3(Q[15]),
        .I4(I1),
        .I5(I2),
        .O(O1));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[1]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[1] ),
        .I2(s_daddr_o[0]),
        .I3(Q[1]),
        .I4(I15),
        .I5(I2),
        .O(O14));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[2]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[2] ),
        .I2(s_daddr_o[0]),
        .I3(Q[2]),
        .I4(I14),
        .I5(I2),
        .O(O13));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[3]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[3] ),
        .I2(s_daddr_o[0]),
        .I3(Q[3]),
        .I4(I13),
        .I5(I2),
        .O(O12));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[4]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[4] ),
        .I2(s_daddr_o[0]),
        .I3(Q[4]),
        .I4(I12),
        .I5(I2),
        .O(O11));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[5]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[5] ),
        .I2(s_daddr_o[0]),
        .I3(Q[5]),
        .I4(I11),
        .I5(I2),
        .O(O10));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[6]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[6] ),
        .I2(s_daddr_o[0]),
        .I3(Q[6]),
        .I4(I10),
        .I5(I2),
        .O(O9));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[7]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[7] ),
        .I2(s_daddr_o[0]),
        .I3(Q[7]),
        .I4(I9),
        .I5(I2),
        .O(O8));
LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
     \slaveRegDo_mux_1[8]_i_8 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(Q[8]),
        .I2(s_daddr_o[1]),
        .I3(I17),
        .I4(s_daddr_o[0]),
        .I5(I18),
        .O(O16));
LUT6 #(
    .INIT(64'h000000000000DFD5)) 
     \slaveRegDo_mux_1[9]_i_4 
       (.I0(s_daddr_o[1]),
        .I1(\n_0_xsdb_reg_reg[9] ),
        .I2(s_daddr_o[0]),
        .I3(Q[9]),
        .I4(I8),
        .I5(I2),
        .O(O7));
FDRE \xsdb_reg_reg[0] 
       (.C(I19),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I19),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I19),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I19),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_251
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_252
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_253
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_254
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_255
   (O1,
    O2,
    Q,
    O3,
    s_daddr_o,
    I1,
    I2,
    I3,
    I4,
    E,
    I5);
  output O1;
  output O2;
  output [15:0]Q;
  output O3;
  input [3:0]s_daddr_o;
  input I1;
  input I2;
  input [2:0]I3;
  input I4;
  input [0:0]E;
  input I5;

  wire [0:0]E;
  wire I1;
  wire I2;
  wire [2:0]I3;
  wire I4;
  wire I5;
  wire O1;
  wire O2;
  wire O3;
  wire [15:0]Q;
  wire \n_0_slaveRegDo_mux_1[11]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[13]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[5]_i_9 ;
  wire [3:0]s_daddr_o;

LUT5 #(
    .INIT(32'h0D572FDF)) 
     \slaveRegDo_mux_1[11]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(Q[11]),
        .I3(s_daddr_o[3]),
        .I4(I3[1]),
        .O(\n_0_slaveRegDo_mux_1[11]_i_9 ));
LUT5 #(
    .INIT(32'h0D572FDF)) 
     \slaveRegDo_mux_1[13]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(Q[13]),
        .I3(s_daddr_o[3]),
        .I4(I3[2]),
        .O(\n_0_slaveRegDo_mux_1[13]_i_9 ));
LUT5 #(
    .INIT(32'h0D572FDF)) 
     \slaveRegDo_mux_1[5]_i_9 
       (.I0(s_daddr_o[2]),
        .I1(s_daddr_o[1]),
        .I2(Q[5]),
        .I3(s_daddr_o[3]),
        .I4(I3[0]),
        .O(\n_0_slaveRegDo_mux_1[5]_i_9 ));
MUXF7 \slaveRegDo_mux_1_reg[11]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[11]_i_9 ),
        .I1(I4),
        .O(O3),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[13]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[13]_i_9 ),
        .I1(I2),
        .O(O2),
        .S(s_daddr_o[0]));
MUXF7 \slaveRegDo_mux_1_reg[5]_i_5 
       (.I0(\n_0_slaveRegDo_mux_1[5]_i_9 ),
        .I1(I1),
        .O(O1),
        .S(s_daddr_o[0]));
FDRE \xsdb_reg_reg[0] 
       (.C(I5),
        .CE(E),
        .D(1'b1),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I5),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_256
   (O1,
    O2,
    O3,
    s_daddr_o,
    Q,
    E,
    I1);
  output O1;
  output O2;
  output [13:0]O3;
  input [3:0]s_daddr_o;
  input [1:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire O1;
  wire O2;
  wire [13:0]O3;
  wire [1:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire [3:0]s_daddr_o;

LUT6 #(
    .INIT(64'h0000002200300000)) 
     \slaveRegDo_mux_1[0]_i_3 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[2]),
        .I2(Q[0]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_daddr_o[3]),
        .O(O1));
LUT6 #(
    .INIT(64'h0000002200300000)) 
     \slaveRegDo_mux_1[10]_i_3 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(s_daddr_o[2]),
        .I2(Q[1]),
        .I3(s_daddr_o[0]),
        .I4(s_daddr_o[1]),
        .I5(s_daddr_o[3]),
        .O(O2));
FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[9]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(O3[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(O3[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(O3[8]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_257
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    s_daddr_o,
    Q,
    I1,
    E,
    I2);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input [1:0]s_daddr_o;
  input [15:0]Q;
  input [15:0]I1;
  input [0:0]E;
  input I2;

  wire [0:0]E;
  wire [15:0]I1;
  wire I2;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire [15:0]Q;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [1:0]s_daddr_o;

LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[0]_i_7 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(s_daddr_o[0]),
        .I2(Q[0]),
        .I3(s_daddr_o[1]),
        .I4(I1[0]),
        .O(O16));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[10]_i_7 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(s_daddr_o[0]),
        .I2(Q[10]),
        .I3(s_daddr_o[1]),
        .I4(I1[10]),
        .O(O6));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[11]_i_7 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(s_daddr_o[0]),
        .I2(Q[11]),
        .I3(s_daddr_o[1]),
        .I4(I1[11]),
        .O(O5));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[12]_i_7 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(s_daddr_o[0]),
        .I2(Q[12]),
        .I3(s_daddr_o[1]),
        .I4(I1[12]),
        .O(O4));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[13]_i_7 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(s_daddr_o[0]),
        .I2(Q[13]),
        .I3(s_daddr_o[1]),
        .I4(I1[13]),
        .O(O3));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[14]_i_7 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(s_daddr_o[0]),
        .I2(Q[14]),
        .I3(s_daddr_o[1]),
        .I4(I1[14]),
        .O(O2));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[15]_i_8 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(s_daddr_o[0]),
        .I2(Q[15]),
        .I3(s_daddr_o[1]),
        .I4(I1[15]),
        .O(O1));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[1]_i_7 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(s_daddr_o[0]),
        .I2(Q[1]),
        .I3(s_daddr_o[1]),
        .I4(I1[1]),
        .O(O15));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[2]_i_7 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(s_daddr_o[0]),
        .I2(Q[2]),
        .I3(s_daddr_o[1]),
        .I4(I1[2]),
        .O(O14));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[3]_i_7 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(s_daddr_o[0]),
        .I2(Q[3]),
        .I3(s_daddr_o[1]),
        .I4(I1[3]),
        .O(O13));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[4]_i_7 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(s_daddr_o[0]),
        .I2(Q[4]),
        .I3(s_daddr_o[1]),
        .I4(I1[4]),
        .O(O12));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[5]_i_7 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(s_daddr_o[0]),
        .I2(Q[5]),
        .I3(s_daddr_o[1]),
        .I4(I1[5]),
        .O(O11));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[6]_i_7 
       (.I0(\n_0_xsdb_reg_reg[6] ),
        .I1(s_daddr_o[0]),
        .I2(Q[6]),
        .I3(s_daddr_o[1]),
        .I4(I1[6]),
        .O(O10));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[7]_i_7 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(s_daddr_o[0]),
        .I2(Q[7]),
        .I3(s_daddr_o[1]),
        .I4(I1[7]),
        .O(O9));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[8]_i_10 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(s_daddr_o[0]),
        .I2(Q[8]),
        .I3(s_daddr_o[1]),
        .I4(I1[8]),
        .O(O8));
LUT5 #(
    .INIT(32'hB8FFB800)) 
     \slaveRegDo_mux_1[9]_i_7 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(s_daddr_o[0]),
        .I2(Q[9]),
        .I3(s_daddr_o[1]),
        .I4(I1[9]),
        .O(O7));
FDRE \xsdb_reg_reg[0] 
       (.C(I2),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I2),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I2),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I2),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_258
   (D,
    O1,
    O2,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    I17,
    I18,
    I19,
    I20,
    I21,
    I22,
    I23,
    I24,
    I25,
    I26,
    s_daddr_o,
    I27,
    I28,
    I29,
    I30,
    I31,
    I32,
    I33,
    I34,
    I35,
    I36,
    I37,
    I38,
    I39,
    I40,
    I41,
    I42,
    I43,
    I44,
    I45,
    I46,
    I47,
    I48,
    I49,
    I50,
    I51,
    I52,
    I53,
    I54,
    I55,
    I56,
    I57,
    I58,
    I59,
    I60,
    I61,
    I62,
    I63,
    I64,
    I65,
    I66,
    I67,
    I68,
    I69,
    I70,
    I71,
    I72,
    I73,
    I74,
    I75,
    I76,
    I77,
    I78,
    I79,
    I80,
    I81,
    I82,
    I83,
    I84,
    I85,
    I86,
    Q,
    I87,
    I88,
    E,
    I89);
  output [5:0]D;
  output [14:0]O1;
  output O2;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input I17;
  input I18;
  input I19;
  input I20;
  input I21;
  input I22;
  input I23;
  input I24;
  input I25;
  input I26;
  input [4:0]s_daddr_o;
  input I27;
  input I28;
  input I29;
  input I30;
  input I31;
  input I32;
  input I33;
  input I34;
  input I35;
  input I36;
  input I37;
  input I38;
  input I39;
  input I40;
  input I41;
  input I42;
  input I43;
  input I44;
  input I45;
  input I46;
  input I47;
  input I48;
  input I49;
  input I50;
  input I51;
  input I52;
  input I53;
  input I54;
  input I55;
  input I56;
  input I57;
  input I58;
  input I59;
  input I60;
  input I61;
  input I62;
  input I63;
  input I64;
  input I65;
  input I66;
  input I67;
  input I68;
  input I69;
  input I70;
  input I71;
  input I72;
  input I73;
  input I74;
  input I75;
  input I76;
  input I77;
  input I78;
  input I79;
  input I80;
  input I81;
  input I82;
  input I83;
  input I84;
  input I85;
  input I86;
  input [15:0]Q;
  input [15:0]I87;
  input I88;
  input [0:0]E;
  input I89;

  wire [5:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire I17;
  wire I18;
  wire I19;
  wire I2;
  wire I20;
  wire I21;
  wire I22;
  wire I23;
  wire I24;
  wire I25;
  wire I26;
  wire I27;
  wire I28;
  wire I29;
  wire I3;
  wire I30;
  wire I31;
  wire I32;
  wire I33;
  wire I34;
  wire I35;
  wire I36;
  wire I37;
  wire I38;
  wire I39;
  wire I4;
  wire I40;
  wire I41;
  wire I42;
  wire I43;
  wire I44;
  wire I45;
  wire I46;
  wire I47;
  wire I48;
  wire I49;
  wire I5;
  wire I50;
  wire I51;
  wire I52;
  wire I53;
  wire I54;
  wire I55;
  wire I56;
  wire I57;
  wire I58;
  wire I59;
  wire I6;
  wire I60;
  wire I61;
  wire I62;
  wire I63;
  wire I64;
  wire I65;
  wire I66;
  wire I67;
  wire I68;
  wire I69;
  wire I7;
  wire I70;
  wire I71;
  wire I72;
  wire I73;
  wire I74;
  wire I75;
  wire I76;
  wire I77;
  wire I78;
  wire I79;
  wire I8;
  wire I80;
  wire I81;
  wire I82;
  wire I83;
  wire I84;
  wire I85;
  wire I86;
  wire [15:0]I87;
  wire I88;
  wire I89;
  wire I9;
  wire [14:0]O1;
  wire O2;
  wire [15:0]Q;
  wire \n_0_slaveRegDo_mux_1[0]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[0]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[10]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[10]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[11]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[11]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[12]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[12]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[13]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[13]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[14]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[14]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[15]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[15]_i_7 ;
  wire \n_0_slaveRegDo_mux_1[1]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[1]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[2]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[2]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[3]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[3]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[4]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[4]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[5]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[5]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[6]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[6]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[7]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[7]_i_6 ;
  wire \n_0_slaveRegDo_mux_1[8]_i_9 ;
  wire \n_0_slaveRegDo_mux_1[9]_i_2 ;
  wire \n_0_slaveRegDo_mux_1[9]_i_6 ;
  wire \n_0_slaveRegDo_mux_1_reg[8]_i_6 ;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;
  wire [4:0]s_daddr_o;

LUT5 #(
    .INIT(32'hBBBB8B88)) 
     \slaveRegDo_mux_0[11]_i_1 
       (.I0(O1[10]),
        .I1(I1),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .O(D[4]));
LUT6 #(
    .INIT(64'hBBB8BBB8BBB8BBBB)) 
     \slaveRegDo_mux_0[13]_i_1 
       (.I0(O1[12]),
        .I1(I1),
        .I2(I20),
        .I3(I21),
        .I4(I22),
        .I5(I23),
        .O(D[5]));
LUT6 #(
    .INIT(64'hBBBBBBBBBBBB8B88)) 
     \slaveRegDo_mux_0[4]_i_1 
       (.I0(O1[4]),
        .I1(I1),
        .I2(I16),
        .I3(I17),
        .I4(I18),
        .I5(I19),
        .O(D[0]));
LUT6 #(
    .INIT(64'hBBBBBBBBBBBB8B88)) 
     \slaveRegDo_mux_0[6]_i_1 
       (.I0(O1[6]),
        .I1(I1),
        .I2(I12),
        .I3(I13),
        .I4(I14),
        .I5(I15),
        .O(D[1]));
LUT5 #(
    .INIT(32'hBBBB8B88)) 
     \slaveRegDo_mux_0[7]_i_1 
       (.I0(O1[7]),
        .I1(I1),
        .I2(I9),
        .I3(I10),
        .I4(I11),
        .O(D[2]));
LUT6 #(
    .INIT(64'hBBBBBBBBBBBB8B88)) 
     \slaveRegDo_mux_0[9]_i_1 
       (.I0(O1[8]),
        .I1(I1),
        .I2(I5),
        .I3(I6),
        .I4(I7),
        .I5(I8),
        .O(D[3]));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[0]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[0]_i_2 ),
        .I1(I24),
        .I2(I25),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I27),
        .O(O1[0]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[0]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[0]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I72),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[0]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[0]_i_6 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(Q[0]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[0]),
        .O(\n_0_slaveRegDo_mux_1[0]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[10]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[10]_i_2 ),
        .I1(I43),
        .I2(I44),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I45),
        .O(O1[9]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[10]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[10]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I81),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[10]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[10]_i_6 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(Q[10]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[10]),
        .O(\n_0_slaveRegDo_mux_1[10]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[11]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[11]_i_2 ),
        .I1(I58),
        .I2(I59),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I60),
        .O(O1[10]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[11]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[11]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I82),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[11]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[11]_i_6 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(Q[11]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[11]),
        .O(\n_0_slaveRegDo_mux_1[11]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[12]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[12]_i_2 ),
        .I1(I46),
        .I2(I47),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I48),
        .O(O1[11]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[12]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[12]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I83),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[12]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[12]_i_6 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(Q[12]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[12]),
        .O(\n_0_slaveRegDo_mux_1[12]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[13]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[13]_i_2 ),
        .I1(I49),
        .I2(I50),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I51),
        .O(O1[12]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[13]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[13]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I84),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[13]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[13]_i_6 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(Q[13]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[13]),
        .O(\n_0_slaveRegDo_mux_1[13]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[14]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[14]_i_2 ),
        .I1(I52),
        .I2(I53),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I54),
        .O(O1[13]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[14]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[14]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I85),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[14]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[14]_i_6 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(Q[14]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[14]),
        .O(\n_0_slaveRegDo_mux_1[14]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[15]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[15]_i_2 ),
        .I1(I55),
        .I2(I56),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I57),
        .O(O1[14]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[15]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[15]_i_7 ),
        .I1(s_daddr_o[0]),
        .I2(I86),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[15]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[15]_i_7 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(Q[15]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[15]),
        .O(\n_0_slaveRegDo_mux_1[15]_i_7 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[1]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[1]_i_2 ),
        .I1(I67),
        .I2(I68),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I69),
        .O(O1[1]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[1]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[1]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I73),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[1]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[1]_i_6 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(Q[1]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[1]),
        .O(\n_0_slaveRegDo_mux_1[1]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[2]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[2]_i_2 ),
        .I1(I28),
        .I2(I29),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I30),
        .O(O1[2]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[2]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[2]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I74),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[2]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[2]_i_6 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(Q[2]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[2]),
        .O(\n_0_slaveRegDo_mux_1[2]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[3]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[3]_i_2 ),
        .I1(I64),
        .I2(I65),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I66),
        .O(O1[3]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[3]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[3]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I75),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[3]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[3]_i_6 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(Q[3]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[3]),
        .O(\n_0_slaveRegDo_mux_1[3]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[4]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[4]_i_2 ),
        .I1(I31),
        .I2(I32),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I33),
        .O(O1[4]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[4]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[4]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I76),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[4]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[4]_i_6 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(Q[4]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[4]),
        .O(\n_0_slaveRegDo_mux_1[4]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[5]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[5]_i_2 ),
        .I1(I34),
        .I2(I35),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I36),
        .O(O1[5]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[5]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[5]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I77),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[5]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[5]_i_6 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(Q[5]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[5]),
        .O(\n_0_slaveRegDo_mux_1[5]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[6]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[6]_i_2 ),
        .I1(I37),
        .I2(I38),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I39),
        .O(O1[6]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[6]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[6]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I78),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[6]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[6]_i_6 
       (.I0(\n_0_xsdb_reg_reg[6] ),
        .I1(Q[6]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[6]),
        .O(\n_0_slaveRegDo_mux_1[6]_i_6 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[7]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[7]_i_2 ),
        .I1(I61),
        .I2(I62),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I63),
        .O(O1[7]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[7]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[7]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I79),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[7]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[7]_i_6 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(Q[7]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[7]),
        .O(\n_0_slaveRegDo_mux_1[7]_i_6 ));
LUT6 #(
    .INIT(64'hCCCCCCCCEEEEFCCC)) 
     \slaveRegDo_mux_1[8]_i_3 
       (.I0(\n_0_slaveRegDo_mux_1_reg[8]_i_6 ),
        .I1(I70),
        .I2(I71),
        .I3(s_daddr_o[3]),
        .I4(s_daddr_o[2]),
        .I5(s_daddr_o[4]),
        .O(O2));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[8]_i_9 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(Q[8]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[8]),
        .O(\n_0_slaveRegDo_mux_1[8]_i_9 ));
LUT6 #(
    .INIT(64'hFE00FE00FE00FEFF)) 
     \slaveRegDo_mux_1[9]_i_1 
       (.I0(\n_0_slaveRegDo_mux_1[9]_i_2 ),
        .I1(I40),
        .I2(I41),
        .I3(I26),
        .I4(s_daddr_o[4]),
        .I5(I42),
        .O(O1[8]));
LUT5 #(
    .INIT(32'h0000E200)) 
     \slaveRegDo_mux_1[9]_i_2 
       (.I0(\n_0_slaveRegDo_mux_1[9]_i_6 ),
        .I1(s_daddr_o[0]),
        .I2(I80),
        .I3(s_daddr_o[2]),
        .I4(s_daddr_o[4]),
        .O(\n_0_slaveRegDo_mux_1[9]_i_2 ));
LUT5 #(
    .INIT(32'hAFC0A0C0)) 
     \slaveRegDo_mux_1[9]_i_6 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(Q[9]),
        .I2(s_daddr_o[1]),
        .I3(s_daddr_o[3]),
        .I4(I87[9]),
        .O(\n_0_slaveRegDo_mux_1[9]_i_6 ));
MUXF7 \slaveRegDo_mux_1_reg[8]_i_6 
       (.I0(\n_0_slaveRegDo_mux_1[8]_i_9 ),
        .I1(I88),
        .O(\n_0_slaveRegDo_mux_1_reg[8]_i_6 ),
        .S(s_daddr_o[0]));
FDRE \xsdb_reg_reg[0] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I89),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I89),
        .CE(E),
        .D(1'b1),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I89),
        .CE(E),
        .D(1'b0),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_259
   (Q,
    E,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]Q;

FDRE \xsdb_reg_reg[0] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[0]),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[10]),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[11]),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[12]),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[13]),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[14]),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[15]),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[1]),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[2]),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[3]),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I1),
        .CE(E),
        .D(1'b1),
        .Q(Q[4]),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[5]),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[6]),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[7]),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[8]),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I1),
        .CE(E),
        .D(1'b0),
        .Q(Q[9]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stat" *) 
module ila_0_xsdbs_v1_0_reg_stat_260
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    D,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    E,
    I17,
    I18);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input [2:0]D;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input [0:0]E;
  input [15:0]I17;
  input I18;

  wire [2:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire [15:0]I17;
  wire I18;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;
  wire \n_0_xsdb_reg_reg[0] ;
  wire \n_0_xsdb_reg_reg[10] ;
  wire \n_0_xsdb_reg_reg[11] ;
  wire \n_0_xsdb_reg_reg[12] ;
  wire \n_0_xsdb_reg_reg[13] ;
  wire \n_0_xsdb_reg_reg[14] ;
  wire \n_0_xsdb_reg_reg[15] ;
  wire \n_0_xsdb_reg_reg[1] ;
  wire \n_0_xsdb_reg_reg[2] ;
  wire \n_0_xsdb_reg_reg[3] ;
  wire \n_0_xsdb_reg_reg[4] ;
  wire \n_0_xsdb_reg_reg[5] ;
  wire \n_0_xsdb_reg_reg[6] ;
  wire \n_0_xsdb_reg_reg[7] ;
  wire \n_0_xsdb_reg_reg[8] ;
  wire \n_0_xsdb_reg_reg[9] ;

LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[0]_i_1 
       (.I0(\n_0_xsdb_reg_reg[0] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I16),
        .O(O16));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[10]_i_1 
       (.I0(\n_0_xsdb_reg_reg[10] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I6),
        .O(O6));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[11]_i_1 
       (.I0(\n_0_xsdb_reg_reg[11] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I5),
        .O(O5));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[12]_i_1 
       (.I0(\n_0_xsdb_reg_reg[12] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I4),
        .O(O4));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[13]_i_1 
       (.I0(\n_0_xsdb_reg_reg[13] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I3),
        .O(O3));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[14]_i_1 
       (.I0(\n_0_xsdb_reg_reg[14] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I2),
        .O(O2));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[15]_i_2 
       (.I0(\n_0_xsdb_reg_reg[15] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I1),
        .O(O1));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[1]_i_1 
       (.I0(\n_0_xsdb_reg_reg[1] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I15),
        .O(O15));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[2]_i_1 
       (.I0(\n_0_xsdb_reg_reg[2] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I14),
        .O(O14));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[3]_i_1 
       (.I0(\n_0_xsdb_reg_reg[3] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I13),
        .O(O13));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[4]_i_1 
       (.I0(\n_0_xsdb_reg_reg[4] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I12),
        .O(O12));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[5]_i_1 
       (.I0(\n_0_xsdb_reg_reg[5] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I11),
        .O(O11));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[6]_i_1 
       (.I0(\n_0_xsdb_reg_reg[6] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I10),
        .O(O10));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[7]_i_1 
       (.I0(\n_0_xsdb_reg_reg[7] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I9),
        .O(O9));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[8]_i_1 
       (.I0(\n_0_xsdb_reg_reg[8] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I8),
        .O(O8));
LUT5 #(
    .INIT(32'hF8F00800)) 
     \slaveRegDo_mux_3[9]_i_1 
       (.I0(\n_0_xsdb_reg_reg[9] ),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[0]),
        .I4(I7),
        .O(O7));
FDRE \xsdb_reg_reg[0] 
       (.C(I18),
        .CE(E),
        .D(I17[0]),
        .Q(\n_0_xsdb_reg_reg[0] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[10] 
       (.C(I18),
        .CE(E),
        .D(I17[10]),
        .Q(\n_0_xsdb_reg_reg[10] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[11] 
       (.C(I18),
        .CE(E),
        .D(I17[11]),
        .Q(\n_0_xsdb_reg_reg[11] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[12] 
       (.C(I18),
        .CE(E),
        .D(I17[12]),
        .Q(\n_0_xsdb_reg_reg[12] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[13] 
       (.C(I18),
        .CE(E),
        .D(I17[13]),
        .Q(\n_0_xsdb_reg_reg[13] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[14] 
       (.C(I18),
        .CE(E),
        .D(I17[14]),
        .Q(\n_0_xsdb_reg_reg[14] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[15] 
       (.C(I18),
        .CE(E),
        .D(I17[15]),
        .Q(\n_0_xsdb_reg_reg[15] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[1] 
       (.C(I18),
        .CE(E),
        .D(I17[1]),
        .Q(\n_0_xsdb_reg_reg[1] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[2] 
       (.C(I18),
        .CE(E),
        .D(I17[2]),
        .Q(\n_0_xsdb_reg_reg[2] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[3] 
       (.C(I18),
        .CE(E),
        .D(I17[3]),
        .Q(\n_0_xsdb_reg_reg[3] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[4] 
       (.C(I18),
        .CE(E),
        .D(I17[4]),
        .Q(\n_0_xsdb_reg_reg[4] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[5] 
       (.C(I18),
        .CE(E),
        .D(I17[5]),
        .Q(\n_0_xsdb_reg_reg[5] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[6] 
       (.C(I18),
        .CE(E),
        .D(I17[6]),
        .Q(\n_0_xsdb_reg_reg[6] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[7] 
       (.C(I18),
        .CE(E),
        .D(I17[7]),
        .Q(\n_0_xsdb_reg_reg[7] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[8] 
       (.C(I18),
        .CE(E),
        .D(I17[8]),
        .Q(\n_0_xsdb_reg_reg[8] ),
        .R(1'b0));
FDRE \xsdb_reg_reg[9] 
       (.C(I18),
        .CE(E),
        .D(I17[9]),
        .Q(\n_0_xsdb_reg_reg[9] ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stream" *) 
module ila_0_xsdbs_v1_0_reg_stream
   (O1,
    O2,
    O3,
    O4,
    O5,
    O6,
    O7,
    O8,
    O9,
    O10,
    O11,
    O12,
    O13,
    O14,
    O15,
    O16,
    D,
    I1,
    I2,
    I3,
    I4,
    I5,
    I6,
    I7,
    I8,
    I9,
    I10,
    I11,
    I12,
    I13,
    I14,
    I15,
    I16,
    E,
    I17,
    I18);
  output O1;
  output O2;
  output O3;
  output O4;
  output O5;
  output O6;
  output O7;
  output O8;
  output O9;
  output O10;
  output O11;
  output O12;
  output O13;
  output O14;
  output O15;
  output O16;
  input [2:0]D;
  input I1;
  input I2;
  input I3;
  input I4;
  input I5;
  input I6;
  input I7;
  input I8;
  input I9;
  input I10;
  input I11;
  input I12;
  input I13;
  input I14;
  input I15;
  input I16;
  input [0:0]E;
  input [15:0]I17;
  input I18;

  wire [2:0]D;
  wire [0:0]E;
  wire I1;
  wire I10;
  wire I11;
  wire I12;
  wire I13;
  wire I14;
  wire I15;
  wire I16;
  wire [15:0]I17;
  wire I18;
  wire I2;
  wire I3;
  wire I4;
  wire I5;
  wire I6;
  wire I7;
  wire I8;
  wire I9;
  wire O1;
  wire O10;
  wire O11;
  wire O12;
  wire O13;
  wire O14;
  wire O15;
  wire O16;
  wire O2;
  wire O3;
  wire O4;
  wire O5;
  wire O6;
  wire O7;
  wire O8;
  wire O9;

ila_0_xsdbs_v1_0_reg_stat_260 \I_EN_STAT_EQ1.U_STAT 
       (.D(D),
        .E(E),
        .I1(I1),
        .I10(I10),
        .I11(I11),
        .I12(I12),
        .I13(I13),
        .I14(I14),
        .I15(I15),
        .I16(I16),
        .I17(I17),
        .I18(I18),
        .I2(I2),
        .I3(I3),
        .I4(I4),
        .I5(I5),
        .I6(I6),
        .I7(I7),
        .I8(I8),
        .I9(I9),
        .O1(O1),
        .O10(O10),
        .O11(O11),
        .O12(O12),
        .O13(O13),
        .O14(O14),
        .O15(O15),
        .O16(O16),
        .O2(O2),
        .O3(O3),
        .O4(O4),
        .O5(O5),
        .O6(O6),
        .O7(O7),
        .O8(O8),
        .O9(O9));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stream" *) 
module ila_0_xsdbs_v1_0_reg_stream__parameterized0
   (bram_en,
    O4,
    O1,
    O2,
    O3,
    O5,
    I1,
    I2,
    Q,
    I3,
    I4,
    dwe,
    D,
    E,
    I5,
    s_di_o);
  output bram_en;
  output O4;
  output O1;
  output O2;
  output O3;
  output [15:0]O5;
  input I1;
  input I2;
  input [7:0]Q;
  input I3;
  input [0:0]I4;
  input dwe;
  input [8:0]D;
  input [0:0]E;
  input I5;
  input [15:0]s_di_o;

  wire [8:0]D;
  wire [0:0]E;
  wire I1;
  wire I2;
  wire I3;
  wire [0:0]I4;
  wire I5;
  wire O1;
  wire O2;
  wire O3;
  wire O4;
  wire [15:0]O5;
  wire [7:0]Q;
  wire bram_en;
  wire config_fsm_en;
  wire dwe;
  wire n_0_bram_en_i_3;
  wire reg_ce;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl_261 \I_EN_CTL_EQ1.U_CTL 
       (.D(D),
        .E(E),
        .I1(I1),
        .I5(I5),
        .O1(O1),
        .O3(O3),
        .O5(O5),
        .dwe(dwe),
        .s_di_o(s_di_o));
LUT6 #(
    .INIT(64'h0000100000000000)) 
     \I_EN_CTL_EQ1.temp_en_i_1 
       (.I0(D[0]),
        .I1(D[1]),
        .I2(O2),
        .I3(D[7]),
        .I4(D[8]),
        .I5(O3),
        .O(reg_ce));
LUT2 #(
    .INIT(4'h8)) 
     \I_EN_CTL_EQ1.temp_en_i_2 
       (.I0(D[2]),
        .I1(D[3]),
        .O(O2));
FDRE \I_EN_CTL_EQ1.temp_en_reg 
       (.C(I1),
        .CE(1'b1),
        .D(reg_ce),
        .Q(config_fsm_en),
        .R(1'b0));
LUT6 #(
    .INIT(64'h0004000000000000)) 
     bram_en_i_1
       (.I0(I2),
        .I1(Q[1]),
        .I2(Q[6]),
        .I3(Q[7]),
        .I4(I3),
        .I5(n_0_bram_en_i_3),
        .O(bram_en));
LUT6 #(
    .INIT(64'h0000000080000000)) 
     bram_en_i_3
       (.I0(Q[5]),
        .I1(config_fsm_en),
        .I2(Q[3]),
        .I3(Q[2]),
        .I4(Q[4]),
        .I5(Q[0]),
        .O(n_0_bram_en_i_3));
LUT2 #(
    .INIT(4'h6)) 
     toggle_i_1
       (.I0(bram_en),
        .I1(I4),
        .O(O4));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stream" *) 
module ila_0_xsdbs_v1_0_reg_stream__parameterized1
   (debug_data_in,
    dwe,
    I1,
    s_daddr_o,
    s_di_o,
    I2);
  output [15:0]debug_data_in;
  input dwe;
  input I1;
  input [1:0]s_daddr_o;
  input [15:0]s_di_o;
  input I2;

  wire I1;
  wire I2;
  wire [15:0]debug_data_in;
  wire dwe;
  wire [1:0]s_daddr_o;
  wire [15:0]s_di_o;

ila_0_xsdbs_v1_0_reg_ctl \I_EN_CTL_EQ1.U_CTL 
       (.I1(I1),
        .I2(I2),
        .debug_data_in(debug_data_in),
        .dwe(dwe),
        .s_daddr_o(s_daddr_o),
        .s_di_o(s_di_o));
endmodule

(* ORIG_REF_NAME = "xsdbs_v1_0_reg_stream" *) 
module ila_0_xsdbs_v1_0_reg_stream__parameterized2
   (Q,
    E,
    I4,
    I1);
  output [15:0]Q;
  input [0:0]E;
  input [15:0]I4;
  input I1;

  wire [0:0]E;
  wire I1;
  wire [15:0]I4;
  wire [15:0]Q;

ila_0_xsdbs_v1_0_reg_stat \I_EN_STAT_EQ1.U_STAT 
       (.E(E),
        .I1(I1),
        .I4(I4),
        .Q(Q));
endmodule

(* DONT_TOUCH = "true" *) (* C_XDEVICEFAMILY = "artix7" *) (* C_MAJOR_VERSION = "2013" *) 
(* C_MINOR_VERSION = "3" *) (* C_BUILD_REVISION = "0" *) (* C_CORE_TYPE = "1" *) 
(* C_CORE_MAJOR_VER = "4" *) (* C_CORE_MINOR_VER = "0" *) (* C_XSDB_SLAVE_TYPE = "17" *) 
(* C_NEXT_SLAVE = "0" *) (* C_CSE_DRV_VER = "1" *) (* C_USE_TEST_REG = "1" *) 
(* C_PIPE_IFACE = "1" *) (* C_CORE_INFO1 = "0" *) (* C_CORE_INFO2 = "0" *) 
(* ORIG_REF_NAME = "xsdbs_v1_0_xsdbs" *) 
module ila_0_xsdbs_v1_0_xsdbs
   (s_rst_o,
    s_dclk_o,
    s_den_o,
    s_dwe_o,
    s_daddr_o,
    s_di_o,
    sl_oport_o,
    s_do_i,
    sl_iport_i,
    s_drdy_i);
  output s_rst_o;
  output s_dclk_o;
  output s_den_o;
  output s_dwe_o;
  output [16:0]s_daddr_o;
  output [15:0]s_di_o;
  output [16:0]sl_oport_o;
  input [15:0]s_do_i;
  input [36:0]sl_iport_i;
  input s_drdy_i;

  wire \n_0_G_1PIPE_IFACE.s_den_r_i_2 ;
  wire \n_0_G_1PIPE_IFACE.s_den_r_i_3 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[0]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[10]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[11]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[12]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[13]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[14]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[15]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[1]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[2]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[3]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[4]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[5]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[6]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[7]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[8]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_do_r[9]_i_1 ;
  wire \n_0_G_1PIPE_IFACE.s_drdy_r_i_1 ;
  wire \n_0_reg_do[10]_i_2 ;
  wire \n_0_reg_do[10]_i_3 ;
  wire \n_0_reg_do[10]_i_4 ;
  wire \n_0_reg_do[10]_i_5 ;
  wire \n_0_reg_do[10]_i_6 ;
  wire \n_0_reg_do[10]_i_7 ;
  wire \n_0_reg_do[15]_i_1 ;
  wire \n_0_reg_do[1]_i_2 ;
  wire \n_0_reg_do[2]_i_1 ;
  wire \n_0_reg_do[3]_i_1 ;
  wire \n_0_reg_do[4]_i_2 ;
  wire \n_0_reg_do[6]_i_1 ;
  wire \n_0_reg_do[7]_i_1 ;
  wire \n_0_reg_do[8]_i_2 ;
  wire \n_0_reg_do[9]_i_1 ;
  wire \n_0_reg_do[9]_i_2 ;
  wire \n_0_reg_do_reg[0] ;
  wire \n_0_reg_do_reg[10] ;
  wire \n_0_reg_do_reg[11] ;
  wire \n_0_reg_do_reg[12] ;
  wire \n_0_reg_do_reg[13] ;
  wire \n_0_reg_do_reg[14] ;
  wire \n_0_reg_do_reg[15] ;
  wire \n_0_reg_do_reg[1] ;
  wire \n_0_reg_do_reg[2] ;
  wire \n_0_reg_do_reg[3] ;
  wire \n_0_reg_do_reg[4] ;
  wire \n_0_reg_do_reg[5] ;
  wire \n_0_reg_do_reg[6] ;
  wire \n_0_reg_do_reg[7] ;
  wire \n_0_reg_do_reg[8] ;
  wire \n_0_reg_do_reg[9] ;
  wire [10:0]reg_do;
  wire reg_drdy;
  wire reg_drdy0;
  wire [15:0]reg_test;
  wire reg_test0;
  wire [16:0]s_daddr_o;
  wire s_den_o;
  wire s_den_r0;
  wire [15:0]s_di_o;
  wire [15:0]s_do_i;
  wire s_drdy_i;
  wire s_dwe_o;
  wire [36:0]sl_iport_i;
  wire [16:0]sl_oport_o;

  assign s_dclk_o = sl_iport_i[1];
  assign s_rst_o = sl_iport_i[0];
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[4]),
        .Q(s_daddr_o[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[14]),
        .Q(s_daddr_o[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[15]),
        .Q(s_daddr_o[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[16]),
        .Q(s_daddr_o[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[17]),
        .Q(s_daddr_o[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[18]),
        .Q(s_daddr_o[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[19]),
        .Q(s_daddr_o[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[16] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[20]),
        .Q(s_daddr_o[16]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[5]),
        .Q(s_daddr_o[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[6]),
        .Q(s_daddr_o[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[7]),
        .Q(s_daddr_o[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[8]),
        .Q(s_daddr_o[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[9]),
        .Q(s_daddr_o[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[10]),
        .Q(s_daddr_o[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[11]),
        .Q(s_daddr_o[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[12]),
        .Q(s_daddr_o[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_daddr_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[13]),
        .Q(s_daddr_o[9]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair35" *) 
   LUT5 #(
    .INIT(32'hEFFF0000)) 
     \G_1PIPE_IFACE.s_den_r_i_1 
       (.I0(\n_0_G_1PIPE_IFACE.s_den_r_i_2 ),
        .I1(\n_0_G_1PIPE_IFACE.s_den_r_i_3 ),
        .I2(sl_iport_i[14]),
        .I3(sl_iport_i[13]),
        .I4(sl_iport_i[2]),
        .O(s_den_r0));
LUT4 #(
    .INIT(16'h7FFF)) 
     \G_1PIPE_IFACE.s_den_r_i_2 
       (.I0(sl_iport_i[16]),
        .I1(sl_iport_i[15]),
        .I2(sl_iport_i[18]),
        .I3(sl_iport_i[17]),
        .O(\n_0_G_1PIPE_IFACE.s_den_r_i_2 ));
LUT3 #(
    .INIT(8'h7F)) 
     \G_1PIPE_IFACE.s_den_r_i_3 
       (.I0(sl_iport_i[20]),
        .I1(sl_iport_i[19]),
        .I2(sl_iport_i[12]),
        .O(\n_0_G_1PIPE_IFACE.s_den_r_i_3 ));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_den_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(s_den_r0),
        .Q(s_den_o),
        .R(sl_iport_i[0]));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[21]),
        .Q(s_di_o[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[31]),
        .Q(s_di_o[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[32]),
        .Q(s_di_o[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[33]),
        .Q(s_di_o[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[34]),
        .Q(s_di_o[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[35]),
        .Q(s_di_o[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[36]),
        .Q(s_di_o[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[22]),
        .Q(s_di_o[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[23]),
        .Q(s_di_o[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[24]),
        .Q(s_di_o[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[25]),
        .Q(s_di_o[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[26]),
        .Q(s_di_o[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[27]),
        .Q(s_di_o[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[28]),
        .Q(s_di_o[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[29]),
        .Q(s_di_o[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_di_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[30]),
        .Q(s_di_o[9]),
        .R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair38" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[0]_i_1 
       (.I0(\n_0_reg_do_reg[0] ),
        .I1(s_do_i[0]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[0]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair42" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[10]_i_1 
       (.I0(\n_0_reg_do_reg[10] ),
        .I1(s_do_i[10]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[10]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair41" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[11]_i_1 
       (.I0(\n_0_reg_do_reg[11] ),
        .I1(s_do_i[11]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[11]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair40" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[12]_i_1 
       (.I0(\n_0_reg_do_reg[12] ),
        .I1(s_do_i[12]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[12]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair46" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[13]_i_1 
       (.I0(\n_0_reg_do_reg[13] ),
        .I1(s_do_i[13]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[13]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair45" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[14]_i_1 
       (.I0(\n_0_reg_do_reg[14] ),
        .I1(s_do_i[14]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[14]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair38" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[15]_i_1 
       (.I0(\n_0_reg_do_reg[15] ),
        .I1(s_do_i[15]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[15]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair40" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[1]_i_1 
       (.I0(\n_0_reg_do_reg[1] ),
        .I1(s_do_i[1]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[1]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair41" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[2]_i_1 
       (.I0(\n_0_reg_do_reg[2] ),
        .I1(s_do_i[2]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[2]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair42" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[3]_i_1 
       (.I0(\n_0_reg_do_reg[3] ),
        .I1(s_do_i[3]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[3]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair43" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[4]_i_1 
       (.I0(\n_0_reg_do_reg[4] ),
        .I1(s_do_i[4]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[4]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair44" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[5]_i_1 
       (.I0(\n_0_reg_do_reg[5] ),
        .I1(s_do_i[5]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[5]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair45" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[6]_i_1 
       (.I0(\n_0_reg_do_reg[6] ),
        .I1(s_do_i[6]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[6]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair46" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[7]_i_1 
       (.I0(\n_0_reg_do_reg[7] ),
        .I1(s_do_i[7]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[7]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair44" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[8]_i_1 
       (.I0(\n_0_reg_do_reg[8] ),
        .I1(s_do_i[8]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[8]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair43" *) 
   LUT3 #(
    .INIT(8'hAC)) 
     \G_1PIPE_IFACE.s_do_r[9]_i_1 
       (.I0(\n_0_reg_do_reg[9] ),
        .I1(s_do_i[9]),
        .I2(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_do_r[9]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[0]_i_1 ),
        .Q(sl_oport_o[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[10]_i_1 ),
        .Q(sl_oport_o[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[11]_i_1 ),
        .Q(sl_oport_o[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[12]_i_1 ),
        .Q(sl_oport_o[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[13]_i_1 ),
        .Q(sl_oport_o[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[14]_i_1 ),
        .Q(sl_oport_o[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[15]_i_1 ),
        .Q(sl_oport_o[16]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[1]_i_1 ),
        .Q(sl_oport_o[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[2]_i_1 ),
        .Q(sl_oport_o[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[3]_i_1 ),
        .Q(sl_oport_o[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[4]_i_1 ),
        .Q(sl_oport_o[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[5]_i_1 ),
        .Q(sl_oport_o[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[6]_i_1 ),
        .Q(sl_oport_o[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[7]_i_1 ),
        .Q(sl_oport_o[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[8]_i_1 ),
        .Q(sl_oport_o[9]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_do_r_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_do_r[9]_i_1 ),
        .Q(sl_oport_o[10]),
        .R(1'b0));
LUT2 #(
    .INIT(4'hE)) 
     \G_1PIPE_IFACE.s_drdy_r_i_1 
       (.I0(s_drdy_i),
        .I1(reg_drdy),
        .O(\n_0_G_1PIPE_IFACE.s_drdy_r_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_drdy_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_G_1PIPE_IFACE.s_drdy_r_i_1 ),
        .Q(sl_oport_o[0]),
        .R(sl_iport_i[0]));
FDRE #(
    .INIT(1'b0)) 
     \G_1PIPE_IFACE.s_dwe_r_reg 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(sl_iport_i[3]),
        .Q(s_dwe_o),
        .R(sl_iport_i[0]));
LUT6 #(
    .INIT(64'hBBABFFFFAAAAAAAA)) 
     \reg_do[0]_i_1 
       (.I0(\n_0_reg_do[4]_i_2 ),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[6]),
        .I3(reg_test[0]),
        .I4(sl_iport_i[5]),
        .I5(sl_iport_i[11]),
        .O(reg_do[0]));
LUT6 #(
    .INIT(64'h000F000E000E000E)) 
     \reg_do[10]_i_1 
       (.I0(\n_0_reg_do[10]_i_2 ),
        .I1(\n_0_reg_do[10]_i_3 ),
        .I2(\n_0_reg_do[10]_i_4 ),
        .I3(\n_0_reg_do[10]_i_5 ),
        .I4(\n_0_reg_do[10]_i_6 ),
        .I5(\n_0_reg_do[10]_i_7 ),
        .O(reg_do[10]));
(* SOFT_HLUTNM = "soft_lutpair37" *) 
   LUT4 #(
    .INIT(16'h0800)) 
     \reg_do[10]_i_2 
       (.I0(sl_iport_i[11]),
        .I1(sl_iport_i[6]),
        .I2(sl_iport_i[5]),
        .I3(sl_iport_i[4]),
        .O(\n_0_reg_do[10]_i_2 ));
(* SOFT_HLUTNM = "soft_lutpair37" *) 
   LUT4 #(
    .INIT(16'h0800)) 
     \reg_do[10]_i_3 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[6]),
        .I3(sl_iport_i[11]),
        .O(\n_0_reg_do[10]_i_3 ));
LUT2 #(
    .INIT(4'hB)) 
     \reg_do[10]_i_4 
       (.I0(sl_iport_i[7]),
        .I1(sl_iport_i[8]),
        .O(\n_0_reg_do[10]_i_4 ));
LUT2 #(
    .INIT(4'h7)) 
     \reg_do[10]_i_5 
       (.I0(sl_iport_i[9]),
        .I1(sl_iport_i[10]),
        .O(\n_0_reg_do[10]_i_5 ));
(* SOFT_HLUTNM = "soft_lutpair39" *) 
   LUT3 #(
    .INIT(8'h08)) 
     \reg_do[10]_i_6 
       (.I0(sl_iport_i[11]),
        .I1(sl_iport_i[6]),
        .I2(sl_iport_i[4]),
        .O(\n_0_reg_do[10]_i_6 ));
LUT2 #(
    .INIT(4'h8)) 
     \reg_do[10]_i_7 
       (.I0(sl_iport_i[5]),
        .I1(reg_test[10]),
        .O(\n_0_reg_do[10]_i_7 ));
LUT5 #(
    .INIT(32'hFFFFDFFF)) 
     \reg_do[15]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(sl_iport_i[4]),
        .I2(sl_iport_i[6]),
        .I3(sl_iport_i[11]),
        .I4(\n_0_reg_do[1]_i_2 ),
        .O(\n_0_reg_do[15]_i_1 ));
LUT6 #(
    .INIT(64'h000000000000B000)) 
     \reg_do[1]_i_1 
       (.I0(reg_test[1]),
        .I1(sl_iport_i[5]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[4]),
        .I5(\n_0_reg_do[1]_i_2 ),
        .O(reg_do[1]));
(* SOFT_HLUTNM = "soft_lutpair36" *) 
   LUT4 #(
    .INIT(16'hFF7F)) 
     \reg_do[1]_i_2 
       (.I0(sl_iport_i[10]),
        .I1(sl_iport_i[9]),
        .I2(sl_iport_i[8]),
        .I3(sl_iport_i[7]),
        .O(\n_0_reg_do[1]_i_2 ));
LUT6 #(
    .INIT(64'h0000000000008000)) 
     \reg_do[2]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(reg_test[2]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[4]),
        .I5(\n_0_reg_do[1]_i_2 ),
        .O(\n_0_reg_do[2]_i_1 ));
LUT6 #(
    .INIT(64'h0000000000008000)) 
     \reg_do[3]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(reg_test[3]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[4]),
        .I5(\n_0_reg_do[1]_i_2 ),
        .O(\n_0_reg_do[3]_i_1 ));
LUT6 #(
    .INIT(64'hBEABAAAABAABAAAA)) 
     \reg_do[4]_i_1 
       (.I0(\n_0_reg_do[4]_i_2 ),
        .I1(sl_iport_i[5]),
        .I2(sl_iport_i[4]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[11]),
        .I5(reg_test[4]),
        .O(reg_do[4]));
(* SOFT_HLUTNM = "soft_lutpair36" *) 
   LUT5 #(
    .INIT(32'hBFFFFFFC)) 
     \reg_do[4]_i_2 
       (.I0(sl_iport_i[7]),
        .I1(sl_iport_i[11]),
        .I2(sl_iport_i[10]),
        .I3(sl_iport_i[9]),
        .I4(sl_iport_i[8]),
        .O(\n_0_reg_do[4]_i_2 ));
LUT6 #(
    .INIT(64'h0000000000008000)) 
     \reg_do[6]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(reg_test[6]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[4]),
        .I5(\n_0_reg_do[1]_i_2 ),
        .O(\n_0_reg_do[6]_i_1 ));
LUT6 #(
    .INIT(64'h0000000000008000)) 
     \reg_do[7]_i_1 
       (.I0(sl_iport_i[5]),
        .I1(reg_test[7]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[4]),
        .I5(\n_0_reg_do[1]_i_2 ),
        .O(\n_0_reg_do[7]_i_1 ));
LUT6 #(
    .INIT(64'h00020000000F0000)) 
     \reg_do[8]_i_1 
       (.I0(reg_test[8]),
        .I1(sl_iport_i[4]),
        .I2(\n_0_reg_do[10]_i_5 ),
        .I3(\n_0_reg_do[10]_i_4 ),
        .I4(\n_0_reg_do[8]_i_2 ),
        .I5(sl_iport_i[5]),
        .O(reg_do[8]));
(* SOFT_HLUTNM = "soft_lutpair39" *) 
   LUT2 #(
    .INIT(4'h8)) 
     \reg_do[8]_i_2 
       (.I0(sl_iport_i[6]),
        .I1(sl_iport_i[11]),
        .O(\n_0_reg_do[8]_i_2 ));
LUT6 #(
    .INIT(64'h0020000000000000)) 
     \reg_do[9]_i_1 
       (.I0(sl_iport_i[4]),
        .I1(sl_iport_i[5]),
        .I2(\n_0_reg_do[8]_i_2 ),
        .I3(\n_0_reg_do[10]_i_4 ),
        .I4(sl_iport_i[9]),
        .I5(sl_iport_i[10]),
        .O(\n_0_reg_do[9]_i_1 ));
LUT6 #(
    .INIT(64'h0000000000008000)) 
     \reg_do[9]_i_2 
       (.I0(sl_iport_i[5]),
        .I1(reg_test[9]),
        .I2(sl_iport_i[11]),
        .I3(sl_iport_i[6]),
        .I4(sl_iport_i[4]),
        .I5(\n_0_reg_do[1]_i_2 ),
        .O(\n_0_reg_do[9]_i_2 ));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[0]),
        .Q(\n_0_reg_do_reg[0] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[10]),
        .Q(\n_0_reg_do_reg[10] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[11]),
        .Q(\n_0_reg_do_reg[11] ),
        .R(\n_0_reg_do[15]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[12]),
        .Q(\n_0_reg_do_reg[12] ),
        .R(\n_0_reg_do[15]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[13]),
        .Q(\n_0_reg_do_reg[13] ),
        .R(\n_0_reg_do[15]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[14]),
        .Q(\n_0_reg_do_reg[14] ),
        .R(\n_0_reg_do[15]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[15]),
        .Q(\n_0_reg_do_reg[15] ),
        .R(\n_0_reg_do[15]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[1]),
        .Q(\n_0_reg_do_reg[1] ),
        .R(1'b0));
FDSE #(
    .INIT(1'b0)) 
     \reg_do_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_reg_do[2]_i_1 ),
        .Q(\n_0_reg_do_reg[2] ),
        .S(\n_0_reg_do[9]_i_1 ));
FDSE #(
    .INIT(1'b0)) 
     \reg_do_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_reg_do[3]_i_1 ),
        .Q(\n_0_reg_do_reg[3] ),
        .S(\n_0_reg_do[9]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[4]),
        .Q(\n_0_reg_do_reg[4] ),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_test[5]),
        .Q(\n_0_reg_do_reg[5] ),
        .R(\n_0_reg_do[15]_i_1 ));
FDSE #(
    .INIT(1'b0)) 
     \reg_do_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_reg_do[6]_i_1 ),
        .Q(\n_0_reg_do_reg[6] ),
        .S(\n_0_reg_do[9]_i_1 ));
FDSE #(
    .INIT(1'b0)) 
     \reg_do_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_reg_do[7]_i_1 ),
        .Q(\n_0_reg_do_reg[7] ),
        .S(\n_0_reg_do[9]_i_1 ));
FDRE #(
    .INIT(1'b0)) 
     \reg_do_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_do[8]),
        .Q(\n_0_reg_do_reg[8] ),
        .R(1'b0));
FDSE #(
    .INIT(1'b0)) 
     \reg_do_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(\n_0_reg_do[9]_i_2 ),
        .Q(\n_0_reg_do_reg[9] ),
        .S(\n_0_reg_do[9]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair35" *) 
   LUT5 #(
    .INIT(32'h00000080)) 
     reg_drdy_i_1
       (.I0(sl_iport_i[14]),
        .I1(sl_iport_i[13]),
        .I2(sl_iport_i[2]),
        .I3(\n_0_G_1PIPE_IFACE.s_den_r_i_2 ),
        .I4(\n_0_G_1PIPE_IFACE.s_den_r_i_3 ),
        .O(reg_drdy0));
FDRE #(
    .INIT(1'b0)) 
     reg_drdy_reg
       (.C(sl_iport_i[1]),
        .CE(1'b1),
        .D(reg_drdy0),
        .Q(reg_drdy),
        .R(sl_iport_i[0]));
LUT6 #(
    .INIT(64'h0000000000008000)) 
     \reg_test[15]_i_1 
       (.I0(sl_iport_i[14]),
        .I1(sl_iport_i[13]),
        .I2(sl_iport_i[3]),
        .I3(sl_iport_i[2]),
        .I4(\n_0_G_1PIPE_IFACE.s_den_r_i_2 ),
        .I5(\n_0_G_1PIPE_IFACE.s_den_r_i_3 ),
        .O(reg_test0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[0] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[21]),
        .Q(reg_test[0]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[10] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[31]),
        .Q(reg_test[10]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[11] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[32]),
        .Q(reg_test[11]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[12] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[33]),
        .Q(reg_test[12]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[13] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[34]),
        .Q(reg_test[13]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[14] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[35]),
        .Q(reg_test[14]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[15] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[36]),
        .Q(reg_test[15]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[1] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[22]),
        .Q(reg_test[1]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[2] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[23]),
        .Q(reg_test[2]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[3] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[24]),
        .Q(reg_test[3]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[4] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[25]),
        .Q(reg_test[4]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[5] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[26]),
        .Q(reg_test[5]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[6] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[27]),
        .Q(reg_test[6]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[7] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[28]),
        .Q(reg_test[7]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[8] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[29]),
        .Q(reg_test[8]),
        .R(1'b0));
FDRE #(
    .INIT(1'b0)) 
     \reg_test_reg[9] 
       (.C(sl_iport_i[1]),
        .CE(reg_test0),
        .D(sl_iport_i[30]),
        .Q(reg_test[9]),
        .R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (weak1, weak0) GSR = GSR_int;
    assign (weak1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif