-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:20:35 MST 2015 -- Date : Wed Apr 22 09:08:53 2015 -- Host : phys-pc458-4 running 64-bit Service Pack 1 (build 7601) -- Command : write_vhdl -force -mode funcsim -- C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.vhdl -- Design : clk_wiz_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a200tfbg484-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_wiz_0_clk_wiz_0_clk_wiz is port ( clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; clk_out2 : out STD_LOGIC; clk_out3 : out STD_LOGIC; clk_out4 : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz"; end clk_wiz_0_clk_wiz_0_clk_wiz; architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is signal clk_in1_clk_wiz_0 : STD_LOGIC; signal clk_out1_clk_wiz_0 : STD_LOGIC; signal clk_out2_clk_wiz_0 : STD_LOGIC; signal clk_out3_clk_wiz_0 : STD_LOGIC; signal clk_out4_clk_wiz_0 : STD_LOGIC; signal clkfbout_buf_clk_wiz_0 : STD_LOGIC; signal clkfbout_clk_wiz_0 : STD_LOGIC; signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_plle2_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC; signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute box_type : string; attribute box_type of clkf_buf : label is "PRIMITIVE"; attribute CAPACITANCE : string; attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE"; attribute IBUF_DELAY_VALUE : string; attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0"; attribute IFD_DELAY_VALUE : string; attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO"; attribute box_type of clkin1_ibufg : label is "PRIMITIVE"; attribute box_type of clkout1_buf : label is "PRIMITIVE"; attribute box_type of clkout2_buf : label is "PRIMITIVE"; attribute box_type of clkout3_buf : label is "PRIMITIVE"; attribute box_type of clkout4_buf : label is "PRIMITIVE"; attribute box_type of plle2_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG port map ( I => clkfbout_clk_wiz_0, O => clkfbout_buf_clk_wiz_0 ); clkin1_ibufg: unisim.vcomponents.IBUF generic map( IOSTANDARD => "DEFAULT" ) port map ( I => clk_in1, O => clk_in1_clk_wiz_0 ); clkout1_buf: unisim.vcomponents.BUFG port map ( I => clk_out1_clk_wiz_0, O => clk_out1 ); clkout2_buf: unisim.vcomponents.BUFG port map ( I => clk_out2_clk_wiz_0, O => clk_out2 ); clkout3_buf: unisim.vcomponents.BUFG port map ( I => clk_out3_clk_wiz_0, O => clk_out3 ); clkout4_buf: unisim.vcomponents.BUFG port map ( I => clk_out4_clk_wiz_0, O => clk_out4 ); plle2_adv_inst: unisim.vcomponents.PLLE2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT => 8, CLKFBOUT_PHASE => 0.000000, CLKIN1_PERIOD => 5.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE => 51, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT1_DIVIDE => 10, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT2_DIVIDE => 40, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT3_DIVIDE => 8, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, COMPENSATION => "ZHOLD", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.000000, REF_JITTER2 => 0.000000, STARTUP_WAIT => "FALSE" ) port map ( CLKFBIN => clkfbout_buf_clk_wiz_0, CLKFBOUT => clkfbout_clk_wiz_0, CLKIN1 => clk_in1_clk_wiz_0, CLKIN2 => '0', CLKINSEL => '1', CLKOUT0 => clk_out1_clk_wiz_0, CLKOUT1 => clk_out2_clk_wiz_0, CLKOUT2 => clk_out3_clk_wiz_0, CLKOUT3 => clk_out4_clk_wiz_0, CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED, DADDR(6) => '0', DADDR(5) => '0', DADDR(4) => '0', DADDR(3) => '0', DADDR(2) => '0', DADDR(1) => '0', DADDR(0) => '0', DCLK => '0', DEN => '0', DI(15) => '0', DI(14) => '0', DI(13) => '0', DI(12) => '0', DI(11) => '0', DI(10) => '0', DI(9) => '0', DI(8) => '0', DI(7) => '0', DI(6) => '0', DI(5) => '0', DI(4) => '0', DI(3) => '0', DI(2) => '0', DI(1) => '0', DI(0) => '0', DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => NLW_plle2_adv_inst_LOCKED_UNCONNECTED, PWRDWN => '0', RST => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity clk_wiz_0 is port ( clk_in1 : in STD_LOGIC; clk_out1 : out STD_LOGIC; clk_out2 : out STD_LOGIC; clk_out3 : out STD_LOGIC; clk_out4 : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of clk_wiz_0 : entity is true; attribute core_generation_info : string; attribute core_generation_info of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=4,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end clk_wiz_0; architecture STRUCTURE of clk_wiz_0 is begin U0: entity work.clk_wiz_0_clk_wiz_0_clk_wiz port map ( clk_in1 => clk_in1, clk_out1 => clk_out1, clk_out2 => clk_out2, clk_out3 => clk_out3, clk_out4 => clk_out4 ); end STRUCTURE;