// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:20:35 MST 2015 // Date : Wed Apr 22 09:08:53 2015 // Host : phys-pc458-4 running 64-bit Service Pack 1 (build 7601) // Command : write_verilog -force -mode funcsim // C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.v // Design : clk_wiz_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7a200tfbg484-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* core_generation_info = "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=4,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) (* NotValidForBitStream *) module clk_wiz_0 (clk_in1, clk_out1, clk_out2, clk_out3, clk_out4); input clk_in1; output clk_out1; output clk_out2; output clk_out3; output clk_out4; (* IBUF_LOW_PWR *) wire clk_in1; wire clk_out1; wire clk_out2; wire clk_out3; wire clk_out4; clk_wiz_0_clk_wiz_0_clk_wiz U0 (.clk_in1(clk_in1), .clk_out1(clk_out1), .clk_out2(clk_out2), .clk_out3(clk_out3), .clk_out4(clk_out4)); endmodule (* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *) module clk_wiz_0_clk_wiz_0_clk_wiz (clk_in1, clk_out1, clk_out2, clk_out3, clk_out4); input clk_in1; output clk_out1; output clk_out2; output clk_out3; output clk_out4; (* IBUF_LOW_PWR *) wire clk_in1; wire clk_in1_clk_wiz_0; wire clk_out1; wire clk_out1_clk_wiz_0; wire clk_out2; wire clk_out2_clk_wiz_0; wire clk_out3; wire clk_out3_clk_wiz_0; wire clk_out4; wire clk_out4_clk_wiz_0; wire clkfbout_buf_clk_wiz_0; wire clkfbout_clk_wiz_0; wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED; wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED; wire NLW_plle2_adv_inst_DRDY_UNCONNECTED; wire NLW_plle2_adv_inst_LOCKED_UNCONNECTED; wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED; (* box_type = "PRIMITIVE" *) BUFG clkf_buf (.I(clkfbout_clk_wiz_0), .O(clkfbout_buf_clk_wiz_0)); (* CAPACITANCE = "DONT_CARE" *) (* IBUF_DELAY_VALUE = "0" *) (* IFD_DELAY_VALUE = "AUTO" *) (* box_type = "PRIMITIVE" *) IBUF #( .IOSTANDARD("DEFAULT")) clkin1_ibufg (.I(clk_in1), .O(clk_in1_clk_wiz_0)); (* box_type = "PRIMITIVE" *) BUFG clkout1_buf (.I(clk_out1_clk_wiz_0), .O(clk_out1)); (* box_type = "PRIMITIVE" *) BUFG clkout2_buf (.I(clk_out2_clk_wiz_0), .O(clk_out2)); (* box_type = "PRIMITIVE" *) BUFG clkout3_buf (.I(clk_out3_clk_wiz_0), .O(clk_out3)); (* box_type = "PRIMITIVE" *) BUFG clkout4_buf (.I(clk_out4_clk_wiz_0), .O(clk_out4)); (* box_type = "PRIMITIVE" *) PLLE2_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKFBOUT_MULT(8), .CLKFBOUT_PHASE(0.000000), .CLKIN1_PERIOD(5.000000), .CLKIN2_PERIOD(0.000000), .CLKOUT0_DIVIDE(51), .CLKOUT0_DUTY_CYCLE(0.500000), .CLKOUT0_PHASE(0.000000), .CLKOUT1_DIVIDE(10), .CLKOUT1_DUTY_CYCLE(0.500000), .CLKOUT1_PHASE(0.000000), .CLKOUT2_DIVIDE(40), .CLKOUT2_DUTY_CYCLE(0.500000), .CLKOUT2_PHASE(0.000000), .CLKOUT3_DIVIDE(8), .CLKOUT3_DUTY_CYCLE(0.500000), .CLKOUT3_PHASE(0.000000), .CLKOUT4_DIVIDE(1), .CLKOUT4_DUTY_CYCLE(0.500000), .CLKOUT4_PHASE(0.000000), .CLKOUT5_DIVIDE(1), .CLKOUT5_DUTY_CYCLE(0.500000), .CLKOUT5_PHASE(0.000000), .COMPENSATION("ZHOLD"), .DIVCLK_DIVIDE(1), .IS_CLKINSEL_INVERTED(1'b0), .IS_PWRDWN_INVERTED(1'b0), .IS_RST_INVERTED(1'b0), .REF_JITTER1(0.000000), .REF_JITTER2(0.000000), .STARTUP_WAIT("FALSE")) plle2_adv_inst (.CLKFBIN(clkfbout_buf_clk_wiz_0), .CLKFBOUT(clkfbout_clk_wiz_0), .CLKIN1(clk_in1_clk_wiz_0), .CLKIN2(1'b0), .CLKINSEL(1'b1), .CLKOUT0(clk_out1_clk_wiz_0), .CLKOUT1(clk_out2_clk_wiz_0), .CLKOUT2(clk_out3_clk_wiz_0), .CLKOUT3(clk_out4_clk_wiz_0), .CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED), .CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED), .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DCLK(1'b0), .DEN(1'b0), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]), .DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED), .DWE(1'b0), .LOCKED(NLW_plle2_adv_inst_LOCKED_UNCONNECTED), .PWRDWN(1'b0), .RST(1'b0)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif