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-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT mbsys_rst_clk_wiz_1_100M_0
  PORT (
    slowest_sync_clk : IN STD_LOGIC;
    ext_reset_in : IN STD_LOGIC;
    aux_reset_in : IN STD_LOGIC;
    mb_debug_sys_rst : IN STD_LOGIC;
    dcm_locked : IN STD_LOGIC;
    mb_reset : OUT STD_LOGIC;
    bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : mbsys_rst_clk_wiz_1_100M_0
  PORT MAP (
    slowest_sync_clk => slowest_sync_clk,
    ext_reset_in => ext_reset_in,
    aux_reset_in => aux_reset_in,
    mb_debug_sys_rst => mb_debug_sys_rst,
    dcm_locked => dcm_locked,
    mb_reset => mb_reset,
    bus_struct_reset => bus_struct_reset,
    peripheral_reset => peripheral_reset,
    interconnect_aresetn => interconnect_aresetn,
    peripheral_aresetn => peripheral_aresetn
  );
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file mbsys_rst_clk_wiz_1_100M_0.vhd when simulating
-- the core, mbsys_rst_clk_wiz_1_100M_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.