2014.4.1:
 * Version 4.1 (Rev. 2)
 * No changes

2014.4:
 * Version 4.1 (Rev. 2)
 * No changes

2014.3:
 * Version 4.1 (Rev. 2)
 * Updated subcore references, no functional changes

2014.2:
 * Version 4.1 (Rev. 1)
 * No changes

2014.1:
 * Version 4.1 (Rev. 1)
 * Allow changing C_IVAR_RESET_VALUE from the default value, to use C_BASE_VECTORS of the processor to initialize IVAR
 * Corrected OOC constraints
 * Modified block design propagation to support Concat v2.0
 * Internal device family name change, no functional changes
 * Removed unused WebTalk core generation information, no functional changes

2013.4:
 * Version 4.1
 * Added Interrupt Level Register to support nested interrupts.
 * Added validation of hexadecimal parameter syntax and length.

2013.3:
 * Version 4.0
 * Hide processor_clk and processor_rst pins when Fast Interrupt is not enabled.
 * Corrected setting parameters Interrupts Type, Level Type and Edge Type from propagated values.
 * Fixed XDC critical warning
 * Support for Automotive Artix-7, Artix-7 Lower Power, Automotive Zynq, Defense Grade Artix-7, Defense Grade Kintex-7, Defense Grade Kintex-7 Lower Power, and Defense Grade Zynq devices at Production status
 * Added synchronization flip-flops on asynchronous interrupt inputs, which adds a two clock cycle latency by default
 * Changed edge triggered interrupt detection to avoid using the input as clock, which requires that it is active at least one clock cycle

2013.2:
 * Version 3.1
 * Support for Software Interrupts added.
 * Constraints processing order changed.

2013.1:
 * Version 3.0
 * Core up reved for 2013.1
 * Fixed issue - Intermediate updates in the IVAR register were resetting the IPIER bits when the core was configured in Fast Interrupt mode.

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