2014.4.1: * Version 4.1 (Rev. 1) * No changes 2014.4: * Version 4.1 (Rev. 1) * Internal device family change, no functional changes 2014.3: * Version 4.1 * Increased the FIFO depth support up to 128K * Increased the AXI4 Data Width support up to 512 * OFFSET address of TDFD and RDFD registers are changed to 0x0000 and 0x1000 respectively for AXI4 Data Interface to support wider data width 2014.2: * Version 4.0 (Rev. 5) * Repackaged to improve internal automation, no functional changes. 2014.1: * Version 4.0 (Rev. 4) * Internal device family name change, no functional changes 2013.4: * Version 4.0 (Rev. 3) * Added support for Ultrascale devices 2013.3: * Version 4.0 (Rev. 2) * Selectable transmit and receive path * Enhanced support for IP Integrator * Reduced warnings in synthesis and simulation * Added example design * Added support for Cadence IES and Synopsys VCS simulators 2013.2: * Version 4.0 (Rev. 1) * Repackaged to enable internal version management, no functional changes. 2013.1: * Version 4.0 * Native Vivado Release * TID and TUSER ports added to the AXI4 Stream interface * TID, TUSER, TDEST, TKEEP and TSTRB are made as selectable option in IP Customization GUI (c) Copyright 2002 - 2015 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.