Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:20:35 MST 2015
| Date              : Wed Apr 22 12:15:37 2015
| Host              : phys-pc458-4 running 64-bit Service Pack 1  (build 7601)
| Command           : report_timing_summary -warn_on_violation -max_paths 10 -file toplevel_timing_summary_routed.rpt -rpx toplevel_timing_summary_routed.rpx
| Design            : toplevel
| Device            : 7a200t-fbg484
| Speed File        : -2  PRODUCTION 1.14 2014-09-11
| Temperature Grade : C
--------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking unexpandable_clocks
13. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 3 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There is 1 port with no output delay but with a timing clock defined on it or propagating through it (LOW)


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 3 generated clocks that are not connected to a clock source. (HIGH)


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking unexpandable_clocks
--------------------------------
 There are 0 unexpandable clock pairs.


13. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.545        0.000                      0                45832        0.037        0.000                      0                45786        1.100        0.000                       0                 18002  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                                                              Waveform(ns)         Period(ns)      Frequency(MHz)
-----                                                                                                                              ------------         ----------      --------------
MGTREFCLK1P                                                                                                                        {0.000 2.500}        5.000           200.000         
  clk_out1_mbsys_clk_wiz_1_0                                                                                                       {0.000 5.000}        10.000          100.000         
  clk_out2_mbsys_clk_wiz_1_0                                                                                                       {0.000 2.500}        5.000           200.000         
  clkfbout_mbsys_clk_wiz_1_0                                                                                                       {0.000 2.500}        5.000           200.000         
clk_user_inst/U0/clk_in1                                                                                                           {0.000 2.500}        5.000           200.000         
  clk_out1_clk_wiz_0                                                                                                               {0.000 15.938}       31.875          31.373          
  clk_out2_clk_wiz_0                                                                                                               {0.000 3.125}        6.250           160.000         
  clk_out3_clk_wiz_0                                                                                                               {0.000 12.500}       25.000          40.000          
  clk_out4_clk_wiz_0                                                                                                               {0.000 2.500}        5.000           200.000         
  clkfbout_clk_wiz_0                                                                                                               {0.000 2.500}        5.000           200.000         
dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK                                                                              {0.000 15.000}       30.000          33.333          
  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE                                                                          {0.000 30.000}       60.000          16.667          
mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {0.000 8.000}        16.000          62.500          
mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK  {0.000 8.000}        16.000          62.500          
  U0/core_clocking_i/clkfbout                                                                                                      {0.000 8.000}        16.000          62.500          
  U0/core_clocking_i/clkout0                                                                                                       {0.000 4.000}        8.000           125.000         
  U0/core_clocking_i/clkout1                                                                                                       {0.000 8.000}        16.000          62.500          
mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK                                                                                             {0.000 16.666}       33.333          30.000          
mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE                                                                                           {0.000 16.666}       33.333          30.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                                                                  WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                                                                  -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
MGTREFCLK1P                                                                                                                                                                                                                                                                          1.100        0.000                       0                     2  
  clk_out1_mbsys_clk_wiz_1_0                                                                                                             0.554        0.000                      0                33855        0.055        0.000                      0                33855        3.870        0.000                       0                 12603  
  clk_out2_mbsys_clk_wiz_1_0                                                                                                             1.185        0.000                      0                  461        0.112        0.000                      0                  461        2.000        0.000                       0                   261  
  clkfbout_mbsys_clk_wiz_1_0                                                                                                                                                                                                                                                         3.408        0.000                       0                     3  
clk_user_inst/U0/clk_in1                                                                                                                                                                                                                                                             1.100        0.000                       0                     1  
  clk_out1_clk_wiz_0                                                                                                                                                                                                                                                                30.626        0.000                       0                     1  
  clk_out2_clk_wiz_0                                                                                                                                                                                                                                                                 5.001        0.000                       0                     1  
  clk_out3_clk_wiz_0                                                                                                                                                                                                                                                                23.408        0.000                       0                     2  
  clk_out4_clk_wiz_0                                                                                                                                                                                                                                                                 3.751        0.000                       0                     1  
  clkfbout_clk_wiz_0                                                                                                                                                                                                                                                                 3.408        0.000                       0                     3  
dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK                                                                                   23.884        0.000                      0                  913        0.037        0.000                      0                  913       13.870        0.000                       0                   458  
  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE                                                                               58.727        0.000                      0                    1        0.408        0.000                      0                    1       29.500        0.000                       0                     2  
mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK       12.623        0.000                      0                  561        0.076        0.000                      0                  561        6.870        0.000                       0                   212  
mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK                                                                                                                                                    5.000        0.000                       0                     3  
  U0/core_clocking_i/clkfbout                                                                                                                                                                                                                                                       14.751        0.000                       0                     2  
  U0/core_clocking_i/clkout0                                                                                                             0.545        0.000                      0                 9089        0.069        0.000                      0                 9088        2.286        0.000                       0                  4065  
  U0/core_clocking_i/clkout1                                                                                                            12.781        0.000                      0                   85        0.139        0.000                      0                   85        7.500        0.000                       0                    66  
mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK                                                                                                  14.080        0.000                      0                  238        0.103        0.000                      0                  238       15.812        0.000                       0                   274  
mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE                                                                                                11.724        0.000                      0                   49        0.320        0.000                      0                   49       16.167        0.000                       0                    42  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                                                         To Clock                                                                                                                               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                                                         --------                                                                                                                               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
U0/core_clocking_i/clkout0                                                                                                         clk_out1_mbsys_clk_wiz_1_0                                                                                                               3.759        0.000                      0                   34                                                                        
dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE                                                                            dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK                                                                                   57.744        0.000                      0                   18       30.047        0.000                      0                   18  
U0/core_clocking_i/clkout0                                                                                                         mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK        7.086        0.000                      0                    6                                                                        
clk_out1_mbsys_clk_wiz_1_0                                                                                                         U0/core_clocking_i/clkout0                                                                                                               1.572        0.000                      0                  106                                                                        
mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  U0/core_clocking_i/clkout0                                                                                                              14.937        0.000                      0                    6                                                                        
U0/core_clocking_i/clkout1                                                                                                         U0/core_clocking_i/clkout0                                                                                                               5.867        0.000                      0                    1        0.153        0.000                      0                    1  
U0/core_clocking_i/clkout0                                                                                                         U0/core_clocking_i/clkout1                                                                                                               5.594        0.000                      0                   23        0.154        0.000                      0                   23  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                             From Clock                                             To Clock                                                   WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                             ----------                                             --------                                                   -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                      U0/core_clocking_i/clkout0                             U0/core_clocking_i/clkout0                                   5.748        0.000                      0                   47        0.376        0.000                      0                   47  
**async_default**                                      clk_out1_mbsys_clk_wiz_1_0                             clk_out1_mbsys_clk_wiz_1_0                                   4.111        0.000                      0                  330        0.337        0.000                      0                  330  
**async_default**                                      clk_out2_mbsys_clk_wiz_1_0                             clk_out2_mbsys_clk_wiz_1_0                                   2.597        0.000                      0                   16        0.557        0.000                      0                   16  
**async_default**                                      dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK       24.667        0.000                      0                   98        0.116        0.000                      0                   98  
**async_default**                                      mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE               mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE                    14.147        0.000                      0                    2        0.622        0.000                      0                    2  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  MGTREFCLK1P
  To Clock:  MGTREFCLK1P

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.100ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         MGTREFCLK1P
Waveform:           { 0 2.5 }
Period:             5.000
Sources:            { MGTREFCLK1P }

Check Type        Corner  Lib Pin            Reference Pin  Required  Actual  Slack   Location          Pin                                        
Min Period        n/a     IBUFDS_GTE2/I      n/a            1.408     5.000   3.592   IBUFDS_GTE2_X0Y3  IBUFDS_GTE2_inst_1/I                       
Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249     5.000   3.751   MMCME2_ADV_X0Y4   mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKIN1  
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000   5.000   95.000  MMCME2_ADV_X0Y4   mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKIN1  
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            1.400     2.500   1.100   MMCME2_ADV_X0Y4   mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKIN1  
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            1.400     2.500   1.100   MMCME2_ADV_X0Y4   mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKIN1  
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            1.400     2.500   1.100   MMCME2_ADV_X0Y4   mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKIN1  
High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            1.400     2.500   1.100   MMCME2_ADV_X0Y4   mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKIN1  



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_mbsys_clk_wiz_1_0
  To Clock:  clk_out1_mbsys_clk_wiz_1_0

Setup :            0  Failing Endpoints,  Worst Slack        0.554ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        3.870ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.554ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        9.188ns  (logic 0.379ns (4.125%)  route 8.809ns (95.875%))
  Logic Levels:           0  
  Clock Path Skew:        -0.132ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.324ns = ( 12.324 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X17Y147                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X17Y147        FDRE (Prop_fdre_C_Q)         0.379     3.906 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/Q
                         net (fo=66, routed)          8.809    12.715    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/s_di_o[3]
    SLICE_X49Y144        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.304    12.324    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/I2
    SLICE_X49Y144                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/C
                         clock pessimism              1.071    13.395    
                         clock uncertainty           -0.066    13.329    
    SLICE_X49Y144        FDRE (Setup_fdre_C_D)       -0.059    13.270    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         13.270    
                         arrival time                         -12.715    
  -------------------------------------------------------------------
                         slack                                  0.554    

Slack (MET) :             0.586ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        9.188ns  (logic 0.379ns (4.125%)  route 8.809ns (95.875%))
  Logic Levels:           0  
  Clock Path Skew:        -0.132ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.324ns = ( 12.324 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X17Y147                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X17Y147        FDRE (Prop_fdre_C_Q)         0.379     3.906 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/Q
                         net (fo=66, routed)          8.809    12.715    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/s_di_o[3]
    SLICE_X48Y144        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.304    12.324    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/I16
    SLICE_X48Y144                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/C
                         clock pessimism              1.071    13.395    
                         clock uncertainty           -0.066    13.329    
    SLICE_X48Y144        FDRE (Setup_fdre_C_D)       -0.027    13.302    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         13.302    
                         arrival time                         -12.715    
  -------------------------------------------------------------------
                         slack                                  0.586    

Slack (MET) :             0.596ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        9.147ns  (logic 0.379ns (4.143%)  route 8.768ns (95.857%))
  Logic Levels:           0  
  Clock Path Skew:        -0.132ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.324ns = ( 12.324 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X17Y147                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X17Y147        FDRE (Prop_fdre_C_Q)         0.379     3.906 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/Q
                         net (fo=66, routed)          8.768    12.674    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/s_di_o[3]
    SLICE_X50Y146        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.304    12.324    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/I2
    SLICE_X50Y146                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/C
                         clock pessimism              1.071    13.395    
                         clock uncertainty           -0.066    13.329    
    SLICE_X50Y146        FDRE (Setup_fdre_C_D)       -0.059    13.270    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         13.270    
                         arrival time                         -12.674    
  -------------------------------------------------------------------
                         slack                                  0.596    

Slack (MET) :             0.616ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        9.144ns  (logic 0.379ns (4.145%)  route 8.765ns (95.855%))
  Logic Levels:           0  
  Clock Path Skew:        -0.132ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.324ns = ( 12.324 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X17Y147                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X17Y147        FDRE (Prop_fdre_C_Q)         0.379     3.906 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/Q
                         net (fo=66, routed)          8.765    12.671    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/s_di_o[3]
    SLICE_X49Y145        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.304    12.324    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/I22
    SLICE_X49Y145                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]/C
                         clock pessimism              1.071    13.395    
                         clock uncertainty           -0.066    13.329    
    SLICE_X49Y145        FDRE (Setup_fdre_C_D)       -0.042    13.287    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         13.287    
                         arrival time                         -12.671    
  -------------------------------------------------------------------
                         slack                                  0.616    

Slack (MET) :             0.740ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/shadow_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        9.208ns  (logic 0.538ns (5.842%)  route 8.670ns (94.158%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.059ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.397ns = ( 12.397 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X16Y146                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X16Y146        FDRE (Prop_fdre_C_Q)         0.433     3.960 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/Q
                         net (fo=66, routed)          8.670    12.630    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/s_di_o[6]
    SLICE_X36Y137        LUT6 (Prop_lut6_I5_O)        0.105    12.735 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/shadow[6]_i_1__46/O
                         net (fo=1, routed)           0.000    12.735    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/n_0_shadow[6]_i_1__46
    SLICE_X36Y137        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/shadow_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.377    12.397    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/I1
    SLICE_X36Y137                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/shadow_reg[6]/C
                         clock pessimism              1.071    13.468    
                         clock uncertainty           -0.066    13.402    
    SLICE_X36Y137        FDRE (Setup_fdre_C_D)        0.074    13.476    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/shadow_reg[6]
  -------------------------------------------------------------------
                         required time                         13.476    
                         arrival time                         -12.735    
  -------------------------------------------------------------------
                         slack                                  0.740    

Slack (MET) :             0.838ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/shadow_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        9.069ns  (logic 0.538ns (5.932%)  route 8.531ns (94.068%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.059ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.397ns = ( 12.397 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X16Y146                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X16Y146        FDRE (Prop_fdre_C_Q)         0.433     3.960 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/Q
                         net (fo=66, routed)          8.531    12.491    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/s_di_o[6]
    SLICE_X39Y142        LUT6 (Prop_lut6_I5_O)        0.105    12.596 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/shadow[6]_i_1__48/O
                         net (fo=1, routed)           0.000    12.596    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/n_0_shadow[6]_i_1__48
    SLICE_X39Y142        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/shadow_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.377    12.397    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/I3
    SLICE_X39Y142                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/shadow_reg[6]/C
                         clock pessimism              1.071    13.468    
                         clock uncertainty           -0.066    13.402    
    SLICE_X39Y142        FDRE (Setup_fdre_C_D)        0.032    13.434    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/shadow_reg[6]
  -------------------------------------------------------------------
                         required time                         13.434    
                         arrival time                         -12.596    
  -------------------------------------------------------------------
                         slack                                  0.838    

Slack (MET) :             0.858ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        8.767ns  (logic 0.398ns (4.539%)  route 8.369ns (95.461%))
  Logic Levels:           0  
  Clock Path Skew:        -0.134ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.322ns = ( 12.322 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X16Y146                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X16Y146        FDRE (Prop_fdre_C_Q)         0.398     3.925 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/Q
                         net (fo=66, routed)          8.369    12.294    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/s_di_o[10]
    SLICE_X49Y139        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.302    12.322    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/I2
    SLICE_X49Y139                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[10]/C
                         clock pessimism              1.071    13.393    
                         clock uncertainty           -0.066    13.327    
    SLICE_X49Y139        FDRE (Setup_fdre_C_D)       -0.174    13.153    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[10]
  -------------------------------------------------------------------
                         required time                         13.153    
                         arrival time                         -12.294    
  -------------------------------------------------------------------
                         slack                                  0.858    

Slack (MET) :             0.933ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        8.807ns  (logic 0.433ns (4.916%)  route 8.374ns (95.084%))
  Logic Levels:           0  
  Clock Path Skew:        -0.135ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.321ns = ( 12.321 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X18Y147                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X18Y147        FDRE (Prop_fdre_C_Q)         0.433     3.960 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/Q
                         net (fo=66, routed)          8.374    12.334    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/s_di_o[14]
    SLICE_X50Y138        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.301    12.321    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/I7
    SLICE_X50Y138                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]/C
                         clock pessimism              1.071    13.392    
                         clock uncertainty           -0.066    13.326    
    SLICE_X50Y138        FDRE (Setup_fdre_C_D)       -0.059    13.267    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]
  -------------------------------------------------------------------
                         required time                         13.267    
                         arrival time                         -12.334    
  -------------------------------------------------------------------
                         slack                                  0.933    

Slack (MET) :             0.935ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        8.938ns  (logic 0.538ns (6.020%)  route 8.400ns (93.980%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.135ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.321ns = ( 12.321 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X18Y147                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X18Y147        FDRE (Prop_fdre_C_Q)         0.433     3.960 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/Q
                         net (fo=66, routed)          8.400    12.359    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/s_di_o[14]
    SLICE_X46Y137        LUT6 (Prop_lut6_I5_O)        0.105    12.464 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow[14]_i_1__7/O
                         net (fo=1, routed)           0.000    12.464    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/n_0_shadow[14]_i_1__7
    SLICE_X46Y137        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.301    12.321    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/I3
    SLICE_X46Y137                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[14]/C
                         clock pessimism              1.071    13.392    
                         clock uncertainty           -0.066    13.326    
    SLICE_X46Y137        FDRE (Setup_fdre_C_D)        0.074    13.400    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[14]
  -------------------------------------------------------------------
                         required time                         13.400    
                         arrival time                         -12.464    
  -------------------------------------------------------------------
                         slack                                  0.935    

Slack (MET) :             0.936ns  (required time - arrival time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        8.805ns  (logic 0.433ns (4.918%)  route 8.372ns (95.082%))
  Logic Levels:           0  
  Clock Path Skew:        -0.134ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.322ns = ( 12.322 - 10.000 ) 
    Source Clock Delay      (SCD):    3.527ns
    Clock Pessimism Removal (CPR):    1.071ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.503     3.527    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X18Y147                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X18Y147        FDRE (Prop_fdre_C_Q)         0.433     3.960 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/Q
                         net (fo=66, routed)          8.372    12.332    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/s_di_o[14]
    SLICE_X54Y140        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.302    12.322    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/I5
    SLICE_X54Y140                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]/C
                         clock pessimism              1.071    13.393    
                         clock uncertainty           -0.066    13.327    
    SLICE_X54Y140        FDRE (Setup_fdre_C_D)       -0.059    13.268    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg[14]
  -------------------------------------------------------------------
                         required time                         13.268    
                         arrival time                         -12.332    
  -------------------------------------------------------------------
                         slack                                  0.936    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[2].cnt_srl_reg/parallel_dout_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.441ns  (logic 0.209ns (47.364%)  route 0.232ns (52.636%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.371ns
    Source Clock Delay      (SCD):    0.827ns
    Clock Pessimism Removal (CPR):    0.279ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.589     0.827    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[2].cnt_srl_reg/I1
    SLICE_X42Y148                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[2].cnt_srl_reg/parallel_dout_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y148        FDRE (Prop_fdre_C_Q)         0.164     0.991 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[2].cnt_srl_reg/parallel_dout_reg[3]/Q
                         net (fo=2, routed)           0.232     1.223    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/I1[3]
    SLICE_X42Y150        LUT6 (Prop_lut6_I3_O)        0.045     1.268 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/slaveRegDo_mux_6[3]_i_1/O
                         net (fo=1, routed)           0.000     1.268    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/p_1_in[3]
    SLICE_X42Y150        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.854     1.371    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/s_dclk
    SLICE_X42Y150                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[3]/C
                         clock pessimism             -0.279     1.092    
    SLICE_X42Y150        FDRE (Hold_fdre_C_D)         0.121     1.213    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.213    
                         arrival time                           1.268    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.056ns  (arrival time - required time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][33]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[30]
                            (rising edge-triggered cell RAMB36E1 clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.267ns  (logic 0.164ns (61.506%)  route 0.103ns (38.494%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.402ns
    Source Clock Delay      (SCD):    0.813ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.575     0.813    U_CS_EAXI/U0/ila_core_inst/clk
    SLICE_X76Y146                                                     r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][33]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y146        FDRE (Prop_fdre_C_Q)         0.164     0.977 r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][33]/Q
                         net (fo=1, routed)           0.103     1.079    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DINA[33]
    RAMB36_X4Y29         RAMB36E1                                     r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[30]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.885     1.402    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/clk
    RAMB36_X4Y29                                                      r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
                         clock pessimism             -0.534     0.868    
    RAMB36_X4Y29         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[30])
                                                      0.155     1.023    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
  -------------------------------------------------------------------
                         required time                         -1.023    
                         arrival time                           1.079    
  -------------------------------------------------------------------
                         slack                                  0.056    

Slack (MET) :             0.058ns  (arrival time - required time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][66]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[27]
                            (rising edge-triggered cell RAMB36E1 clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.267ns  (logic 0.164ns (61.345%)  route 0.103ns (38.655%))
  Logic Levels:           0  
  Clock Path Skew:        0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.409ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.583     0.821    U_CS_EAXI/U0/ila_core_inst/clk
    SLICE_X62Y144                                                     r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][66]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y144        FDRE (Prop_fdre_C_Q)         0.164     0.985 r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][66]/Q
                         net (fo=1, routed)           0.103     1.088    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DINA[30]
    RAMB36_X3Y28         RAMB36E1                                     r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[27]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.892     1.409    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/clk
    RAMB36_X3Y28                                                      r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
                         clock pessimism             -0.534     0.875    
    RAMB36_X3Y28         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[27])
                                                      0.155     1.030    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
  -------------------------------------------------------------------
                         required time                         -1.030    
                         arrival time                           1.088    
  -------------------------------------------------------------------
                         slack                                  0.058    

Slack (MET) :             0.058ns  (arrival time - required time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][130]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[21]
                            (rising edge-triggered cell RAMB36E1 clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.267ns  (logic 0.164ns (61.345%)  route 0.103ns (38.655%))
  Logic Levels:           0  
  Clock Path Skew:        0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.407ns
    Source Clock Delay      (SCD):    0.819ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.581     0.819    U_CS_EAXI/U0/ila_core_inst/clk
    SLICE_X62Y138                                                     r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][130]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y138        FDRE (Prop_fdre_C_Q)         0.164     0.983 r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][130]/Q
                         net (fo=1, routed)           0.103     1.086    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DINA[22]
    RAMB36_X3Y27         RAMB36E1                                     r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[21]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.890     1.407    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/clk
    RAMB36_X3Y27                                                      r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
                         clock pessimism             -0.534     0.873    
    RAMB36_X3Y27         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[21])
                                                      0.155     1.028    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
  -------------------------------------------------------------------
                         required time                         -1.028    
                         arrival time                           1.086    
  -------------------------------------------------------------------
                         slack                                  0.058    

Slack (MET) :             0.058ns  (arrival time - required time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][91]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[17]
                            (rising edge-triggered cell RAMB36E1 clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.268ns  (logic 0.164ns (61.276%)  route 0.104ns (38.724%))
  Logic Levels:           0  
  Clock Path Skew:        0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.399ns
    Source Clock Delay      (SCD):    0.811ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.573     0.811    U_CS_EAXI/U0/ila_core_inst/clk
    SLICE_X76Y138                                                     r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][91]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y138        FDRE (Prop_fdre_C_Q)         0.164     0.975 r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][91]/Q
                         net (fo=1, routed)           0.104     1.078    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DINA[19]
    RAMB36_X4Y27         RAMB36E1                                     r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[17]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.882     1.399    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/clk
    RAMB36_X4Y27                                                      r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
                         clock pessimism             -0.534     0.865    
    RAMB36_X4Y27         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[17])
                                                      0.155     1.020    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
  -------------------------------------------------------------------
                         required time                         -1.020    
                         arrival time                           1.078    
  -------------------------------------------------------------------
                         slack                                  0.058    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][128]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[19]
                            (rising edge-triggered cell RAMB36E1 clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.268ns  (logic 0.164ns (61.116%)  route 0.104ns (38.884%))
  Logic Levels:           0  
  Clock Path Skew:        0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.407ns
    Source Clock Delay      (SCD):    0.819ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.581     0.819    U_CS_EAXI/U0/ila_core_inst/clk
    SLICE_X62Y138                                                     r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][128]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y138        FDRE (Prop_fdre_C_Q)         0.164     0.983 r  U_CS_EAXI/U0/ila_core_inst/shifted_data_in_reg[8][128]/Q
                         net (fo=1, routed)           0.104     1.087    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DINA[20]
    RAMB36_X3Y27         RAMB36E1                                     r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[19]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.890     1.407    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/clk
    RAMB36_X3Y27                                                      r  U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
                         clock pessimism             -0.534     0.873    
    RAMB36_X3Y27         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[19])
                                                      0.155     1.028    U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
  -------------------------------------------------------------------
                         required time                         -1.028    
                         arrival time                           1.087    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.061ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[33]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[6]
                            (rising edge-triggered cell RAMB36E1 clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.428ns  (logic 0.141ns (32.916%)  route 0.287ns (67.084%))
  Logic Levels:           0  
  Clock Path Skew:        0.072ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.392ns
    Source Clock Delay      (SCD):    0.808ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.570     0.808    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AXI_STR_RXD_ACLK
    SLICE_X103Y176                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[33]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y176       FDRE (Prop_fdre_C_Q)         0.141     0.949 r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/goreg_dm.dout_i_reg[33]/Q
                         net (fo=5, routed)           0.287     1.236    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DINA[2]
    RAMB36_X6Y34         RAMB36E1                                     r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[6]
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.875     1.392    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/s_axi_aclk
    RAMB36_X6Y34                                                      r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
                         clock pessimism             -0.513     0.879    
    RAMB36_X6Y34         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[6])
                                                      0.296     1.175    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
  -------------------------------------------------------------------
                         required time                         -1.175    
                         arrival time                           1.236    
  -------------------------------------------------------------------
                         slack                                  0.061    

Slack (MET) :             0.064ns  (arrival time - required time)
  Source:                 U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[0].cnt_srl_reg/parallel_dout_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            U_CS_EAXI/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.433ns  (logic 0.226ns (52.219%)  route 0.207ns (47.781%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.277ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.377ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.279ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.583     0.821    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[0].cnt_srl_reg/I1
    SLICE_X43Y150                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[0].cnt_srl_reg/parallel_dout_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y150        FDRE (Prop_fdre_C_Q)         0.128     0.949 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[0].cnt_srl_reg/parallel_dout_reg[6]/Q
                         net (fo=2, routed)           0.207     1.156    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/I2[6]
    SLICE_X43Y149        LUT6 (Prop_lut6_I5_O)        0.098     1.254 r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/slaveRegDo_mux_6[6]_i_1/O
                         net (fo=1, routed)           0.000     1.254    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/p_1_in[6]
    SLICE_X43Y149        FDRE                                         r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.860     1.377    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/s_dclk
    SLICE_X43Y149                                                     r  U_CS_EAXI/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[6]/C
                         clock pessimism             -0.279     1.098    
    SLICE_X43Y149        FDRE (Hold_fdre_C_D)         0.092     1.190    U_CS_EAXI/U0/ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[6]
  -------------------------------------------------------------------
                         required time                         -1.190    
                         arrival time                           1.254    
  -------------------------------------------------------------------
                         slack                                  0.064    

Slack (MET) :             0.073ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/DP/WADR4
                            (rising edge-triggered cell RAMD64E clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.141ns (45.359%)  route 0.170ns (54.641%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.349ns
    Source Clock Delay      (SCD):    0.798ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.560     0.798    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_axi_aclk
    SLICE_X89Y171                                                     r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y171        FDRE (Prop_fdre_C_Q)         0.141     0.939 r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/Q
                         net (fo=611, routed)         0.170     1.109    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/A4
    SLICE_X90Y170        RAMD64E                                      r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/DP/WADR4
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.831     1.349    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/WCLK
    SLICE_X90Y170                                                     r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/DP/CLK
                         clock pessimism             -0.513     0.836    
    SLICE_X90Y170        RAMD64E (Hold_ramd64e_CLK_WADR4)
                                                      0.200     1.036    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/DP
  -------------------------------------------------------------------
                         required time                         -1.036    
                         arrival time                           1.109    
  -------------------------------------------------------------------
                         slack                                  0.073    

Slack (MET) :             0.073ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/SP/WADR4
                            (rising edge-triggered cell RAMD64E clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.141ns (45.359%)  route 0.170ns (54.641%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.349ns
    Source Clock Delay      (SCD):    0.798ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.560     0.798    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/s_axi_aclk
    SLICE_X89Y171                                                     r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y171        FDRE (Prop_fdre_C_Q)         0.141     0.939 r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[4]/Q
                         net (fo=611, routed)         0.170     1.109    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/A4
    SLICE_X90Y170        RAMD64E                                      r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/SP/WADR4
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.831     1.349    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/WCLK
    SLICE_X90Y170                                                     r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/SP/CLK
                         clock pessimism             -0.513     0.836    
    SLICE_X90Y170        RAMD64E (Hold_ramd64e_CLK_WADR4)
                                                      0.200     1.036    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_320_383_21_21/SP
  -------------------------------------------------------------------
                         required time                         -1.036    
                         arrival time                           1.109    
  -------------------------------------------------------------------
                         slack                                  0.073    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_mbsys_clk_wiz_1_0
Waveform:           { 0 5 }
Period:             10.000
Sources:            { mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required  Actual  Slack    Location         Pin                                                                                                                                                                                                                                              
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472     10.000  7.528    RAMB36_X4Y29     U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK  
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.472     10.000  7.528    RAMB36_X4Y29     U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK  
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472     10.000  7.528    RAMB36_X3Y28     U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK  
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.472     10.000  7.528    RAMB36_X3Y28     U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK  
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472     10.000  7.528    RAMB36_X4Y27     U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK  
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.472     10.000  7.528    RAMB36_X4Y27     U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK  
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472     10.000  7.528    RAMB36_X3Y27     U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK  
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.472     10.000  7.528    RAMB36_X3Y27     U_CS_EAXI/U0/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK  
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.389     10.000  7.611    RAMB36_X5Y24     mbsys_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B/CLKARDCLK                   
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.389     10.000  7.611    RAMB36_X5Y24     mbsys_i/microblaze_0_local_memory/lmb_bram/U0/inst_blk_mem_gen/gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.CASCADED_PRIM36.ram_B/CLKBWRCLK                   
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360   10.000  203.360  MMCME2_ADV_X0Y4  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0                                                                                                                                                                                                       
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.130     5.000   3.870    SLICE_X102Y178   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_18_23/RAMA/CLK                                                        
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.130     5.000   3.870    SLICE_X102Y178   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_18_23/RAMA_D1/CLK                                                     
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.130     5.000   3.870    SLICE_X102Y178   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_18_23/RAMB/CLK                                                        
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.130     5.000   3.870    SLICE_X102Y178   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_18_23/RAMB_D1/CLK                                                     
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.130     5.000   3.870    SLICE_X102Y178   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_18_23/RAMC/CLK                                                        
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.130     5.000   3.870    SLICE_X102Y178   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_18_23/RAMC_D1/CLK                                                     
Low Pulse Width   Slow    RAMS32/CLK          n/a            1.130     5.000   3.870    SLICE_X102Y178   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_18_23/RAMD/CLK                                                        
Low Pulse Width   Slow    RAMS32/CLK          n/a            1.130     5.000   3.870    SLICE_X102Y178   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_18_23/RAMD_D1/CLK                                                     
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.130     5.000   3.870    SLICE_X104Y175   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_6_11/RAMA/CLK                                                         
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.130     5.000   3.870    SLICE_X104Y175   mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_31_6_11/RAMA_D1/CLK                                                      
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X42Y153    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_0_2/RAMA/CLK                                                                                                                                                             
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X42Y153    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_0_2/RAMB/CLK                                                                                                                                                             
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X42Y153    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_0_2/RAMC/CLK                                                                                                                                                             
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X42Y153    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_0_2/RAMD/CLK                                                                                                                                                             
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X42Y151    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_12_14/RAMA/CLK                                                                                                                                                           
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X42Y151    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_12_14/RAMB/CLK                                                                                                                                                           
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X42Y151    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_12_14/RAMC/CLK                                                                                                                                                           
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X42Y151    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_12_14/RAMD/CLK                                                                                                                                                           
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X44Y156    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_15_17/RAMA/CLK                                                                                                                                                           
High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130     5.000   3.870    SLICE_X44Y156    U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/fsm_mem_data_reg_r1_0_63_15_17/RAMB/CLK                                                                                                                                                           



---------------------------------------------------------------------------------------------------
From Clock:  clk_out2_mbsys_clk_wiz_1_0
  To Clock:  clk_out2_mbsys_clk_wiz_1_0

Setup :            0  Failing Endpoints,  Worst Slack        1.185ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.112ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.185ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.303ns  (logic 0.748ns (22.643%)  route 2.555ns (77.357%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.641     6.713    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X66Y196        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y196                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[0]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X66Y196        FDRE (Setup_fdre_C_R)       -0.423     7.898    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[0]
  -------------------------------------------------------------------
                         required time                          7.898    
                         arrival time                          -6.713    
  -------------------------------------------------------------------
                         slack                                  1.185    

Slack (MET) :             1.185ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.303ns  (logic 0.748ns (22.643%)  route 2.555ns (77.357%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.641     6.713    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X66Y196        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y196                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[1]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X66Y196        FDRE (Setup_fdre_C_R)       -0.423     7.898    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[1]
  -------------------------------------------------------------------
                         required time                          7.898    
                         arrival time                          -6.713    
  -------------------------------------------------------------------
                         slack                                  1.185    

Slack (MET) :             1.185ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.303ns  (logic 0.748ns (22.643%)  route 2.555ns (77.357%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.641     6.713    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X66Y196        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y196                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[2]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X66Y196        FDRE (Setup_fdre_C_R)       -0.423     7.898    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[2]
  -------------------------------------------------------------------
                         required time                          7.898    
                         arrival time                          -6.713    
  -------------------------------------------------------------------
                         slack                                  1.185    

Slack (MET) :             1.185ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.303ns  (logic 0.748ns (22.643%)  route 2.555ns (77.357%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.641     6.713    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X66Y196        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y196                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[3]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X66Y196        FDRE (Setup_fdre_C_R)       -0.423     7.898    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[3]
  -------------------------------------------------------------------
                         required time                          7.898    
                         arrival time                          -6.713    
  -------------------------------------------------------------------
                         slack                                  1.185    

Slack (MET) :             1.194ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.366ns  (logic 0.748ns (22.224%)  route 2.618ns (77.776%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.703     6.775    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X67Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[10]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X67Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[10]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X67Y199        FDRE (Setup_fdre_C_R)       -0.352     7.969    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[10]
  -------------------------------------------------------------------
                         required time                          7.969    
                         arrival time                          -6.775    
  -------------------------------------------------------------------
                         slack                                  1.194    

Slack (MET) :             1.194ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.366ns  (logic 0.748ns (22.224%)  route 2.618ns (77.776%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.703     6.775    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X67Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X67Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[11]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X67Y199        FDRE (Setup_fdre_C_R)       -0.352     7.969    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[11]
  -------------------------------------------------------------------
                         required time                          7.969    
                         arrival time                          -6.775    
  -------------------------------------------------------------------
                         slack                                  1.194    

Slack (MET) :             1.194ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[8]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.366ns  (logic 0.748ns (22.224%)  route 2.618ns (77.776%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.703     6.775    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X67Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[8]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X67Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[8]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X67Y199        FDRE (Setup_fdre_C_R)       -0.352     7.969    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[8]
  -------------------------------------------------------------------
                         required time                          7.969    
                         arrival time                          -6.775    
  -------------------------------------------------------------------
                         slack                                  1.194    

Slack (MET) :             1.194ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[9]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.366ns  (logic 0.748ns (22.224%)  route 2.618ns (77.776%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.703     6.775    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X67Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[9]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X67Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[9]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X67Y199        FDRE (Setup_fdre_C_R)       -0.352     7.969    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg2_reg[9]
  -------------------------------------------------------------------
                         required time                          7.969    
                         arrival time                          -6.775    
  -------------------------------------------------------------------
                         slack                                  1.194    

Slack (MET) :             1.221ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.267ns  (logic 0.748ns (22.892%)  route 2.519ns (77.108%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.605     6.677    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X66Y198        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[10]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[10]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X66Y198        FDRE (Setup_fdre_C_R)       -0.423     7.898    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[10]
  -------------------------------------------------------------------
                         required time                          7.898    
                         arrival time                          -6.677    
  -------------------------------------------------------------------
                         slack                                  1.221    

Slack (MET) :             1.221ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[11]/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        3.267ns  (logic 0.748ns (22.892%)  route 2.519ns (77.108%))
  Logic Levels:           3  (LUT4=2 LUT6=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 7.296 - 5.000 ) 
    Source Clock Delay      (SCD):    3.409ns
    Clock Pessimism Removal (CPR):    1.085ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.385     3.409    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_fdre_C_Q)         0.433     3.842 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]/Q
                         net (fo=2, routed)           0.770     4.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[7]
    SLICE_X66Y199        LUT6 (Prop_lut6_I1_O)        0.105     4.717 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_3/O
                         net (fo=1, routed)           0.649     5.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_reset_i_3
    SLICE_X68Y198        LUT4 (Prop_lut4_I0_O)        0.105     5.471 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_i_2/O
                         net (fo=2, routed)           0.496     5.967    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/p_5_in
    SLICE_X62Y198        LUT4 (Prop_lut4_I0_O)        0.105     6.072 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/counter_stg1[5]_i_1/O
                         net (fo=30, routed)          0.605     6.677    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1
    SLICE_X66Y198        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[11]/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.276     7.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X66Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[11]/C
                         clock pessimism              1.085     8.381    
                         clock uncertainty           -0.060     8.321    
    SLICE_X66Y198        FDRE (Setup_fdre_C_R)       -0.423     7.898    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg3_reg[11]
  -------------------------------------------------------------------
                         required time                          7.898    
                         arrival time                          -6.677    
  -------------------------------------------------------------------
                         slack                                  1.221    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.112ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/sync_block_gtrxreset/data_sync_reg6/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlocked_reg/R
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.299ns  (logic 0.141ns (47.171%)  route 0.158ns (52.829%))
  Logic Levels:           0  
  Clock Path Skew:        0.178ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.907ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.669     0.907    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y203                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/sync_block_gtrxreset/data_sync_reg6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y203        FDRE (Prop_fdre_C_Q)         0.141     1.048 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/sync_block_gtrxreset/data_sync_reg6/Q
                         net (fo=15, routed)          0.158     1.206    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/data_out
    SLICE_X48Y197        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlocked_reg/R
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlocked_reg/C
                         clock pessimism             -0.284     1.086    
    SLICE_X48Y197        FDRE (Hold_fdre_C_R)         0.009     1.095    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlocked_reg
  -------------------------------------------------------------------
                         required time                         -1.095    
                         arrival time                           1.206    
  -------------------------------------------------------------------
                         slack                                  0.112    

Slack (MET) :             0.127ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.619ns  (logic 0.414ns (66.926%)  route 0.205ns (33.074%))
  Logic Levels:           2  (CARRY4=2)
  Clock Path Skew:        0.357ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.462ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y199        FDRE (Prop_fdre_C_Q)         0.164     0.985 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/Q
                         net (fo=7, routed)           0.204     1.189    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]
    SLICE_X48Y199        CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.197     1.386 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[5]_i_2__0_CARRY4/CO[3]
                         net (fo=1, routed)           0.001     1.386    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[8]_i_2__0
    SLICE_X48Y200        CARRY4 (Prop_carry4_CI_O[0])
                                                      0.053     1.439 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[9]_i_2__0_CARRY4/O[0]
                         net (fo=1, routed)           0.000     1.439    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[8]_i_1__0
    SLICE_X48Y200        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.945     1.462    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y200                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[8]/C
                         clock pessimism             -0.284     1.178    
    SLICE_X48Y200        FDRE (Hold_fdre_C_D)         0.134     1.312    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[8]
  -------------------------------------------------------------------
                         required time                         -1.312    
                         arrival time                           1.439    
  -------------------------------------------------------------------
                         slack                                  0.127    

Slack (MET) :             0.140ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.632ns  (logic 0.427ns (67.607%)  route 0.205ns (32.393%))
  Logic Levels:           2  (CARRY4=2)
  Clock Path Skew:        0.357ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.462ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y199        FDRE (Prop_fdre_C_Q)         0.164     0.985 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/Q
                         net (fo=7, routed)           0.204     1.189    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]
    SLICE_X48Y199        CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.197     1.386 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[5]_i_2__0_CARRY4/CO[3]
                         net (fo=1, routed)           0.001     1.386    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[8]_i_2__0
    SLICE_X48Y200        CARRY4 (Prop_carry4_CI_O[2])
                                                      0.066     1.452 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[9]_i_2__0_CARRY4/O[2]
                         net (fo=1, routed)           0.000     1.452    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[10]_i_1__0
    SLICE_X48Y200        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.945     1.462    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y200                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[10]/C
                         clock pessimism             -0.284     1.178    
    SLICE_X48Y200        FDRE (Hold_fdre_C_D)         0.134     1.312    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[10]
  -------------------------------------------------------------------
                         required time                         -1.312    
                         arrival time                           1.452    
  -------------------------------------------------------------------
                         slack                                  0.140    

Slack (MET) :             0.158ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.302ns  (logic 0.189ns (62.674%)  route 0.113ns (37.326%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.446ns
    Source Clock Delay      (SCD):    0.895ns
    Clock Pessimism Removal (CPR):    0.538ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.657     0.895    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X43Y224                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y224        FDRE (Prop_fdre_C_Q)         0.141     1.036 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[0]/Q
                         net (fo=10, routed)          0.113     1.149    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg__0[0]
    SLICE_X42Y224        LUT3 (Prop_lut3_I0_O)        0.048     1.197 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/init_wait_count[2]_i_1__1/O
                         net (fo=1, routed)           0.000     1.197    mbsys_i/axi_ethernet_0/U0/pcs_pma/plusOp__0[2]
    SLICE_X42Y224        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.929     1.446    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y224                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[2]/C
                         clock pessimism             -0.538     0.908    
    SLICE_X42Y224        FDRE (Hold_fdre_C_D)         0.131     1.039    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.039    
                         arrival time                           1.197    
  -------------------------------------------------------------------
                         slack                                  0.158    

Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_count_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_reclocked_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.263ns  (logic 0.186ns (70.622%)  route 0.077ns (29.378%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.462ns
    Source Clock Delay      (SCD):    0.908ns
    Clock Pessimism Removal (CPR):    0.541ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.670     0.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X51Y202                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_count_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y202        FDRE (Prop_fdre_C_Q)         0.141     1.049 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_count_reg[9]/Q
                         net (fo=3, routed)           0.077     1.127    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_count_reg__0[9]
    SLICE_X50Y202        LUT5 (Prop_lut5_I2_O)        0.045     1.172 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_reclocked_i_1/O
                         net (fo=1, routed)           0.000     1.172    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_reclocked_i_1
    SLICE_X50Y202        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_reclocked_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.945     1.462    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X50Y202                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_reclocked_reg/C
                         clock pessimism             -0.541     0.921    
    SLICE_X50Y202        FDRE (Hold_fdre_C_D)         0.091     1.012    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/mmcm_lock_reclocked_reg
  -------------------------------------------------------------------
                         required time                         -1.012    
                         arrival time                           1.172    
  -------------------------------------------------------------------
                         slack                                  0.159    

Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.655ns  (logic 0.450ns (68.745%)  route 0.205ns (31.255%))
  Logic Levels:           2  (CARRY4=2)
  Clock Path Skew:        0.357ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.462ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y199        FDRE (Prop_fdre_C_Q)         0.164     0.985 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/Q
                         net (fo=7, routed)           0.204     1.189    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]
    SLICE_X48Y199        CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.197     1.386 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[5]_i_2__0_CARRY4/CO[3]
                         net (fo=1, routed)           0.001     1.386    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[8]_i_2__0
    SLICE_X48Y200        CARRY4 (Prop_carry4_CI_O[1])
                                                      0.089     1.475 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[9]_i_2__0_CARRY4/O[1]
                         net (fo=1, routed)           0.000     1.475    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[9]_i_1__0
    SLICE_X48Y200        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.945     1.462    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y200                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[9]/C
                         clock pessimism             -0.284     1.178    
    SLICE_X48Y200        FDRE (Hold_fdre_C_D)         0.134     1.312    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[9]
  -------------------------------------------------------------------
                         required time                         -1.312    
                         arrival time                           1.475    
  -------------------------------------------------------------------
                         slack                                  0.163    

Slack (MET) :             0.165ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.299ns  (logic 0.186ns (62.299%)  route 0.113ns (37.701%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.446ns
    Source Clock Delay      (SCD):    0.895ns
    Clock Pessimism Removal (CPR):    0.538ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.657     0.895    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X43Y224                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y224        FDRE (Prop_fdre_C_Q)         0.141     1.036 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[0]/Q
                         net (fo=10, routed)          0.113     1.149    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg__0[0]
    SLICE_X42Y224        LUT2 (Prop_lut2_I0_O)        0.045     1.194 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/init_wait_count[1]_i_1__1/O
                         net (fo=1, routed)           0.000     1.194    mbsys_i/axi_ethernet_0/U0/pcs_pma/plusOp__0[1]
    SLICE_X42Y224        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.929     1.446    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y224                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[1]/C
                         clock pessimism             -0.538     0.908    
    SLICE_X42Y224        FDRE (Hold_fdre_C_D)         0.121     1.029    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.029    
                         arrival time                           1.194    
  -------------------------------------------------------------------
                         slack                                  0.165    

Slack (MET) :             0.165ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.657ns  (logic 0.452ns (68.840%)  route 0.205ns (31.160%))
  Logic Levels:           2  (CARRY4=2)
  Clock Path Skew:        0.357ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.462ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y199        FDRE (Prop_fdre_C_Q)         0.164     0.985 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/Q
                         net (fo=7, routed)           0.204     1.189    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]
    SLICE_X48Y199        CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.197     1.386 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[5]_i_2__0_CARRY4/CO[3]
                         net (fo=1, routed)           0.001     1.386    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[8]_i_2__0
    SLICE_X48Y200        CARRY4 (Prop_carry4_CI_O[3])
                                                      0.091     1.477 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[9]_i_2__0_CARRY4/O[3]
                         net (fo=1, routed)           0.000     1.477    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[11]_i_1__0
    SLICE_X48Y200        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.945     1.462    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y200                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[11]/C
                         clock pessimism             -0.284     1.178    
    SLICE_X48Y200        FDRE (Hold_fdre_C_D)         0.134     1.312    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[11]
  -------------------------------------------------------------------
                         required time                         -1.312    
                         arrival time                           1.477    
  -------------------------------------------------------------------
                         slack                                  0.165    

Slack (MET) :             0.167ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.659ns  (logic 0.454ns (68.935%)  route 0.205ns (31.065%))
  Logic Levels:           3  (CARRY4=3)
  Clock Path Skew:        0.357ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.462ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y199        FDRE (Prop_fdre_C_Q)         0.164     0.985 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]/Q
                         net (fo=7, routed)           0.204     1.189    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[5]
    SLICE_X48Y199        CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.197     1.386 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[5]_i_2__0_CARRY4/CO[3]
                         net (fo=1, routed)           0.001     1.386    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[8]_i_2__0
    SLICE_X48Y200        CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.040     1.426 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[9]_i_2__0_CARRY4/CO[3]
                         net (fo=1, routed)           0.000     1.426    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[12]_i_2__0
    SLICE_X48Y201        CARRY4 (Prop_carry4_CI_O[0])
                                                      0.053     1.479 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_counter_reg[13]_i_2__0_CARRY4/O[0]
                         net (fo=1, routed)           0.000     1.479    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter_reg[12]_i_1__0
    SLICE_X48Y201        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.945     1.462    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X48Y201                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[12]/C
                         clock pessimism             -0.284     1.178    
    SLICE_X48Y201        FDRE (Hold_fdre_C_D)         0.134     1.312    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter_reg[12]
  -------------------------------------------------------------------
                         required time                         -1.312    
                         arrival time                           1.479    
  -------------------------------------------------------------------
                         slack                                  0.167    

Slack (MET) :             0.172ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_time_out_wait_bypass/data_sync_reg6/C
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_s3_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out2_mbsys_clk_wiz_1_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.255ns  (logic 0.141ns (55.255%)  route 0.114ns (44.745%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.494ns
    Source Clock Delay      (SCD):    0.940ns
    Clock Pessimism Removal (CPR):    0.541ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.702     0.940    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X34Y207                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_time_out_wait_bypass/data_sync_reg6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y207        FDRE (Prop_fdre_C_Q)         0.141     1.081 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_time_out_wait_bypass/data_sync_reg6/Q
                         net (fo=1, routed)           0.114     1.195    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_s2
    SLICE_X35Y207        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_s3_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.977     1.494    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X35Y207                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_s3_reg/C
                         clock pessimism             -0.541     0.953    
    SLICE_X35Y207        FDRE (Hold_fdre_C_D)         0.070     1.023    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_s3_reg
  -------------------------------------------------------------------
                         required time                         -1.023    
                         arrival time                           1.195    
  -------------------------------------------------------------------
                         slack                                  0.172    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out2_mbsys_clk_wiz_1_0
Waveform:           { 0 2.5 }
Period:             5.000
Sources:            { mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1 }

Check Type        Corner  Lib Pin                      Reference Pin  Required  Actual  Slack    Location           Pin                                                                                                                                       
Min Period        n/a     BUFG/I                       n/a            1.592     5.000   3.408    BUFGCTRL_X0Y20     mbsys_i/clk_wiz_1/U0/clkout2_buf/I                                                                                                        
Min Period        n/a     GTPE2_COMMON/PLL0LOCKDETCLK  n/a            1.538     5.000   3.462    GTPE2_COMMON_X0Y1  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/gtpe2_common_i/PLL0LOCKDETCLK                                                       
Min Period        n/a     MMCME2_ADV/CLKOUT1           n/a            1.249     5.000   3.751    MMCME2_ADV_X0Y4    mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1                                                                                                
Min Period        n/a     FDRE/C                       n/a            1.000     5.000   4.000    SLICE_X43Y224      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[0]/C                                                            
Min Period        n/a     FDRE/C                       n/a            1.000     5.000   4.000    SLICE_X42Y224      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[1]/C                                                            
Min Period        n/a     FDRE/C                       n/a            1.000     5.000   4.000    SLICE_X42Y224      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[2]/C                                                            
Min Period        n/a     FDRE/C                       n/a            1.000     5.000   4.000    SLICE_X42Y224      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[3]/C                                                            
Min Period        n/a     FDRE/C                       n/a            1.000     5.000   4.000    SLICE_X42Y224      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[4]/C                                                            
Min Period        n/a     FDRE/C                       n/a            1.000     5.000   4.000    SLICE_X42Y224      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[5]/C                                                            
Min Period        n/a     FDRE/C                       n/a            1.000     5.000   4.000    SLICE_X42Y225      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/init_wait_count_reg[6]/C                                                            
Max Period        n/a     MMCME2_ADV/CLKOUT1           n/a            213.360   5.000   208.360  MMCME2_ADV_X0Y4    mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1                                                                                                
Low Pulse Width   Slow    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X34Y205      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_time_cnt_reg[0]/C            
Low Pulse Width   Slow    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X34Y205      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_time_cnt_reg[1]/C            
Low Pulse Width   Slow    FDSE/C                       n/a            0.500     2.500   2.000    SLICE_X35Y205      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_time_cnt_reg[2]/C            
Low Pulse Width   Slow    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X35Y205      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_time_cnt_reg[3]/C            
Low Pulse Width   Slow    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X35Y205      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_time_cnt_reg[4]/C            
Low Pulse Width   Slow    FDSE/C                       n/a            0.500     2.500   2.000    SLICE_X35Y205      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_time_cnt_reg[5]/C            
Low Pulse Width   Slow    FDSE/C                       n/a            0.500     2.500   2.000    SLICE_X34Y205      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_time_cnt_reg[6]/C            
Low Pulse Width   Slow    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X43Y207      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/FSM_sequential_tx_state_reg[0]/C  
Low Pulse Width   Slow    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X43Y206      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/FSM_sequential_tx_state_reg[1]/C  
Low Pulse Width   Slow    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X43Y207      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/FSM_sequential_tx_state_reg[2]/C  
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X46Y196      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlock_counter_reg[0]/C                    
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X48Y196      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlock_counter_reg[1]/C                    
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X46Y196      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlock_counter_reg[2]/C                    
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X46Y196      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlock_counter_reg[3]/C                    
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X47Y203      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/RXUSERRDY_reg/C                   
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X47Y203      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/gtrxreset_i_reg/C                 
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X47Y203      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/rx_fsm_reset_done_int_reg/C       
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X47Y204      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_pll0lock/data_sync_reg1/C    
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X47Y204      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_pll0lock/data_sync_reg2/C    
High Pulse Width  Fast    FDRE/C                       n/a            0.500     2.500   2.000    SLICE_X47Y204      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_pll0lock/data_sync_reg3/C    



---------------------------------------------------------------------------------------------------
From Clock:  clkfbout_mbsys_clk_wiz_1_0
  To Clock:  clkfbout_mbsys_clk_wiz_1_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.408ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfbout_mbsys_clk_wiz_1_0
Waveform:           { 0 2.5 }
Period:             5.000
Sources:            { mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required  Actual  Slack    Location         Pin                                          
Min Period  n/a     BUFG/I               n/a            1.592     5.000   3.408    BUFGCTRL_X0Y22   mbsys_i/clk_wiz_1/U0/clkf_buf/I              
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249     5.000   3.751    MMCME2_ADV_X0Y4  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKFBIN   
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249     5.000   3.751    MMCME2_ADV_X0Y4  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKFBOUT  
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000   5.000   95.000   MMCME2_ADV_X0Y4  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKFBIN   
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360   5.000   208.360  MMCME2_ADV_X0Y4  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKFBOUT  



---------------------------------------------------------------------------------------------------
From Clock:  clk_user_inst/U0/clk_in1
  To Clock:  clk_user_inst/U0/clk_in1

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        1.100ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_user_inst/U0/clk_in1
Waveform:           { 0 2.5 }
Period:             5.000
Sources:            { clk_user_inst/U0/clk_in1 }

Check Type        Corner  Lib Pin           Reference Pin  Required  Actual  Slack   Location        Pin                                     
Min Period        n/a     PLLE2_ADV/CLKIN1  n/a            1.249     5.000   3.751   PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKIN1  
Max Period        n/a     PLLE2_ADV/CLKIN1  n/a            52.633    5.000   47.633  PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKIN1  
Low Pulse Width   Fast    PLLE2_ADV/CLKIN1  n/a            1.400     2.500   1.100   PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKIN1  
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1  n/a            1.400     2.500   1.100   PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKIN1  
High Pulse Width  Slow    PLLE2_ADV/CLKIN1  n/a            1.400     2.500   1.100   PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKIN1  
High Pulse Width  Fast    PLLE2_ADV/CLKIN1  n/a            1.400     2.500   1.100   PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKIN1  



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_clk_wiz_0
  To Clock:  clk_out1_clk_wiz_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       30.626ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_clk_wiz_0
Waveform:           { 0 15.9375 }
Period:             31.875
Sources:            { clk_user_inst/U0/plle2_adv_inst/CLKOUT0 }

Check Type  Corner  Lib Pin            Reference Pin  Required  Actual  Slack    Location        Pin                                      
Min Period  n/a     PLLE2_ADV/CLKOUT0  n/a            1.249     31.875  30.626   PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKOUT0  
Max Period  n/a     PLLE2_ADV/CLKOUT0  n/a            160.000   31.875  128.125  PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKOUT0  



---------------------------------------------------------------------------------------------------
From Clock:  clk_out2_clk_wiz_0
  To Clock:  clk_out2_clk_wiz_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        5.001ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out2_clk_wiz_0
Waveform:           { 0 3.125 }
Period:             6.250
Sources:            { clk_user_inst/U0/plle2_adv_inst/CLKOUT1 }

Check Type  Corner  Lib Pin            Reference Pin  Required  Actual  Slack    Location        Pin                                      
Min Period  n/a     PLLE2_ADV/CLKOUT1  n/a            1.249     6.250   5.001    PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKOUT1  
Max Period  n/a     PLLE2_ADV/CLKOUT1  n/a            160.000   6.250   153.750  PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKOUT1  



---------------------------------------------------------------------------------------------------
From Clock:  clk_out3_clk_wiz_0
  To Clock:  clk_out3_clk_wiz_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       23.408ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out3_clk_wiz_0
Waveform:           { 0 12.5 }
Period:             25.000
Sources:            { clk_user_inst/U0/plle2_adv_inst/CLKOUT2 }

Check Type  Corner  Lib Pin            Reference Pin  Required  Actual  Slack    Location        Pin                                      
Min Period  n/a     BUFG/I             n/a            1.592     25.000  23.408   BUFGCTRL_X0Y0   clk_user_inst/U0/clkout3_buf/I           
Min Period  n/a     PLLE2_ADV/CLKOUT2  n/a            1.249     25.000  23.751   PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKOUT2  
Max Period  n/a     PLLE2_ADV/CLKOUT2  n/a            160.000   25.000  135.000  PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKOUT2  



---------------------------------------------------------------------------------------------------
From Clock:  clk_out4_clk_wiz_0
  To Clock:  clk_out4_clk_wiz_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out4_clk_wiz_0
Waveform:           { 0 2.5 }
Period:             5.000
Sources:            { clk_user_inst/U0/plle2_adv_inst/CLKOUT3 }

Check Type  Corner  Lib Pin            Reference Pin  Required  Actual  Slack    Location        Pin                                      
Min Period  n/a     PLLE2_ADV/CLKOUT3  n/a            1.249     5.000   3.751    PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKOUT3  
Max Period  n/a     PLLE2_ADV/CLKOUT3  n/a            160.000   5.000   155.000  PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKOUT3  



---------------------------------------------------------------------------------------------------
From Clock:  clkfbout_clk_wiz_0
  To Clock:  clkfbout_clk_wiz_0

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.408ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clkfbout_clk_wiz_0
Waveform:           { 0 2.5 }
Period:             5.000
Sources:            { clk_user_inst/U0/plle2_adv_inst/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required  Actual  Slack    Location        Pin                                       
Min Period  n/a     BUFG/I              n/a            1.592     5.000   3.408    BUFGCTRL_X0Y4   clk_user_inst/U0/clkf_buf/I               
Min Period  n/a     PLLE2_ADV/CLKFBIN   n/a            1.249     5.000   3.751    PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKFBIN   
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249     5.000   3.751    PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKFBOUT  
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633    5.000   47.633   PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKFBIN   
Max Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            160.000   5.000   155.000  PLLE2_ADV_X0Y2  clk_user_inst/U0/plle2_adv_inst/CLKFBOUT  



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  To Clock:  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK

Setup :            0  Failing Endpoints,  Worst Slack       23.884ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.037ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       13.870ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             23.884ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.542ns  (logic 0.799ns (14.417%)  route 4.743ns (85.583%))
  Logic Levels:           4  (LUT1=1 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.116ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.686ns = ( 33.686 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.343ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.322     8.995    dbg_hub/inst/U_ICON/U_CMD/E[0]
    SLICE_X15Y150        LUT1 (Prop_lut1_I0_O)        0.105     9.100 r  dbg_hub/inst/U_ICON/U_CMD/shift_bit_count[3]_i_1/O
                         net (fo=4, routed)           0.587     9.687    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/I19[0]
    SLICE_X16Y150        FDRE                                         r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.376    33.686    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X16Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[0]/C
                         clock pessimism              0.343    34.029    
                         clock uncertainty           -0.035    33.994    
    SLICE_X16Y150        FDRE (Setup_fdre_C_R)       -0.423    33.571    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[0]
  -------------------------------------------------------------------
                         required time                         33.571    
                         arrival time                          -9.687    
  -------------------------------------------------------------------
                         slack                                 23.884    

Slack (MET) :             23.884ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.542ns  (logic 0.799ns (14.417%)  route 4.743ns (85.583%))
  Logic Levels:           4  (LUT1=1 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.116ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.686ns = ( 33.686 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.343ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.322     8.995    dbg_hub/inst/U_ICON/U_CMD/E[0]
    SLICE_X15Y150        LUT1 (Prop_lut1_I0_O)        0.105     9.100 r  dbg_hub/inst/U_ICON/U_CMD/shift_bit_count[3]_i_1/O
                         net (fo=4, routed)           0.587     9.687    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/I19[0]
    SLICE_X16Y150        FDRE                                         r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.376    33.686    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X16Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[1]/C
                         clock pessimism              0.343    34.029    
                         clock uncertainty           -0.035    33.994    
    SLICE_X16Y150        FDRE (Setup_fdre_C_R)       -0.423    33.571    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[1]
  -------------------------------------------------------------------
                         required time                         33.571    
                         arrival time                          -9.687    
  -------------------------------------------------------------------
                         slack                                 23.884    

Slack (MET) :             23.884ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.542ns  (logic 0.799ns (14.417%)  route 4.743ns (85.583%))
  Logic Levels:           4  (LUT1=1 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.116ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.686ns = ( 33.686 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.343ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.322     8.995    dbg_hub/inst/U_ICON/U_CMD/E[0]
    SLICE_X15Y150        LUT1 (Prop_lut1_I0_O)        0.105     9.100 r  dbg_hub/inst/U_ICON/U_CMD/shift_bit_count[3]_i_1/O
                         net (fo=4, routed)           0.587     9.687    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/I19[0]
    SLICE_X16Y150        FDRE                                         r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.376    33.686    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X16Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[2]/C
                         clock pessimism              0.343    34.029    
                         clock uncertainty           -0.035    33.994    
    SLICE_X16Y150        FDRE (Setup_fdre_C_R)       -0.423    33.571    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[2]
  -------------------------------------------------------------------
                         required time                         33.571    
                         arrival time                          -9.687    
  -------------------------------------------------------------------
                         slack                                 23.884    

Slack (MET) :             23.884ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.542ns  (logic 0.799ns (14.417%)  route 4.743ns (85.583%))
  Logic Levels:           4  (LUT1=1 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.116ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.686ns = ( 33.686 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.343ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.322     8.995    dbg_hub/inst/U_ICON/U_CMD/E[0]
    SLICE_X15Y150        LUT1 (Prop_lut1_I0_O)        0.105     9.100 r  dbg_hub/inst/U_ICON/U_CMD/shift_bit_count[3]_i_1/O
                         net (fo=4, routed)           0.587     9.687    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/I19[0]
    SLICE_X16Y150        FDRE                                         r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.376    33.686    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X16Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[3]/C
                         clock pessimism              0.343    34.029    
                         clock uncertainty           -0.035    33.994    
    SLICE_X16Y150        FDRE (Setup_fdre_C_R)       -0.423    33.571    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[3]
  -------------------------------------------------------------------
                         required time                         33.571    
                         arrival time                          -9.687    
  -------------------------------------------------------------------
                         slack                                 23.884    

Slack (MET) :             24.006ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMA/WE
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.489ns  (logic 0.799ns (14.557%)  route 4.690ns (85.443%))
  Logic Levels:           4  (LUT2=1 LUT6=3)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 f  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 r  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.019     8.692    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/I5[0]
    SLICE_X15Y150        LUT6 (Prop_lut6_I0_O)        0.105     8.797 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gic0.gc0.count_d1[3]_i_1/O
                         net (fo=37, routed)          0.837     9.633    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WE
    SLICE_X14Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMA/WE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WCLK
    SLICE_X14Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMA/CLK
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X14Y147        RAMD32 (Setup_ramd32_CLK_WE)
                                                     -0.435    33.639    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMA
  -------------------------------------------------------------------
                         required time                         33.639    
                         arrival time                          -9.633    
  -------------------------------------------------------------------
                         slack                                 24.006    

Slack (MET) :             24.006ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMA_D1/WE
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.489ns  (logic 0.799ns (14.557%)  route 4.690ns (85.443%))
  Logic Levels:           4  (LUT2=1 LUT6=3)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 f  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 r  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.019     8.692    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/I5[0]
    SLICE_X15Y150        LUT6 (Prop_lut6_I0_O)        0.105     8.797 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gic0.gc0.count_d1[3]_i_1/O
                         net (fo=37, routed)          0.837     9.633    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WE
    SLICE_X14Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMA_D1/WE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WCLK
    SLICE_X14Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMA_D1/CLK
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X14Y147        RAMD32 (Setup_ramd32_CLK_WE)
                                                     -0.435    33.639    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMA_D1
  -------------------------------------------------------------------
                         required time                         33.639    
                         arrival time                          -9.633    
  -------------------------------------------------------------------
                         slack                                 24.006    

Slack (MET) :             24.006ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB/WE
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.489ns  (logic 0.799ns (14.557%)  route 4.690ns (85.443%))
  Logic Levels:           4  (LUT2=1 LUT6=3)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 f  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 r  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.019     8.692    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/I5[0]
    SLICE_X15Y150        LUT6 (Prop_lut6_I0_O)        0.105     8.797 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gic0.gc0.count_d1[3]_i_1/O
                         net (fo=37, routed)          0.837     9.633    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WE
    SLICE_X14Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB/WE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WCLK
    SLICE_X14Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB/CLK
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X14Y147        RAMD32 (Setup_ramd32_CLK_WE)
                                                     -0.435    33.639    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB
  -------------------------------------------------------------------
                         required time                         33.639    
                         arrival time                          -9.633    
  -------------------------------------------------------------------
                         slack                                 24.006    

Slack (MET) :             24.006ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB_D1/WE
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.489ns  (logic 0.799ns (14.557%)  route 4.690ns (85.443%))
  Logic Levels:           4  (LUT2=1 LUT6=3)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 f  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 r  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.019     8.692    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/I5[0]
    SLICE_X15Y150        LUT6 (Prop_lut6_I0_O)        0.105     8.797 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gic0.gc0.count_d1[3]_i_1/O
                         net (fo=37, routed)          0.837     9.633    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WE
    SLICE_X14Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB_D1/WE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WCLK
    SLICE_X14Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB_D1/CLK
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X14Y147        RAMD32 (Setup_ramd32_CLK_WE)
                                                     -0.435    33.639    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB_D1
  -------------------------------------------------------------------
                         required time                         33.639    
                         arrival time                          -9.633    
  -------------------------------------------------------------------
                         slack                                 24.006    

Slack (MET) :             24.006ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMC/WE
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.489ns  (logic 0.799ns (14.557%)  route 4.690ns (85.443%))
  Logic Levels:           4  (LUT2=1 LUT6=3)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 f  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 r  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.019     8.692    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/I5[0]
    SLICE_X15Y150        LUT6 (Prop_lut6_I0_O)        0.105     8.797 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gic0.gc0.count_d1[3]_i_1/O
                         net (fo=37, routed)          0.837     9.633    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WE
    SLICE_X14Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMC/WE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WCLK
    SLICE_X14Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMC/CLK
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X14Y147        RAMD32 (Setup_ramd32_CLK_WE)
                                                     -0.435    33.639    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMC
  -------------------------------------------------------------------
                         required time                         33.639    
                         arrival time                          -9.633    
  -------------------------------------------------------------------
                         slack                                 24.006    

Slack (MET) :             24.006ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMC_D1/WE
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.489ns  (logic 0.799ns (14.557%)  route 4.690ns (85.443%))
  Logic Levels:           4  (LUT2=1 LUT6=3)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 f  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 r  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.552     7.112    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X15Y139        LUT6 (Prop_lut6_I0_O)        0.105     7.217 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_2/O
                         net (fo=7, routed)           0.351     7.568    dbg_hub/inst/U_ICON/U_CMD/I3[1]
    SLICE_X16Y139        LUT2 (Prop_lut2_I0_O)        0.105     7.673 r  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[15]_i_1/O
                         net (fo=18, routed)          1.019     8.692    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/I5[0]
    SLICE_X15Y150        LUT6 (Prop_lut6_I0_O)        0.105     8.797 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/gic0.gc0.count_d1[3]_i_1/O
                         net (fo=37, routed)          0.837     9.633    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WE
    SLICE_X14Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMC_D1/WE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WCLK
    SLICE_X14Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMC_D1/CLK
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X14Y147        RAMD32 (Setup_ramd32_CLK_WE)
                                                     -0.435    33.639    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMC_D1
  -------------------------------------------------------------------
                         required time                         33.639    
                         arrival time                          -9.633    
  -------------------------------------------------------------------
                         slack                                 24.006    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.364ns  (logic 0.164ns (45.033%)  route 0.200ns (54.967%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/idrck
    SLICE_X12Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y150        FDCE (Prop_fdce_C_Q)         0.164     2.204 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[1]/Q
                         net (fo=2, routed)           0.200     2.404    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/p_8_out[1]
    SLICE_X12Y149        FDCE                                         r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/idrck
    SLICE_X12Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X12Y149        FDCE (Hold_fdce_C_D)         0.053     2.366    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.366    
                         arrival time                           2.404    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.050ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.210ns  (logic 0.141ns (67.144%)  route 0.069ns (32.856%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.041ns
    Clock Pessimism Removal (CPR):    0.445ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.628     2.041    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y148        FDCE (Prop_fdce_C_Q)         0.141     2.182 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.069     2.251    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/DIA0
    SLICE_X14Y148        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/WCLK
    SLICE_X14Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA/CLK
                         clock pessimism             -0.445     2.054    
    SLICE_X14Y148        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.147     2.201    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA
  -------------------------------------------------------------------
                         required time                         -2.201    
                         arrival time                           2.251    
  -------------------------------------------------------------------
                         slack                                  0.050    

Slack (MET) :             0.096ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.199ns  (logic 0.128ns (64.295%)  route 0.071ns (35.705%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.041ns
    Clock Pessimism Removal (CPR):    0.445ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.628     2.041    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y148        FDCE (Prop_fdce_C_Q)         0.128     2.169 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[5]/Q
                         net (fo=2, routed)           0.071     2.240    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/DIC0
    SLICE_X14Y148        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/WCLK
    SLICE_X14Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC/CLK
                         clock pessimism             -0.445     2.054    
    SLICE_X14Y148        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.090     2.144    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC
  -------------------------------------------------------------------
                         required time                         -2.144    
                         arrival time                           2.240    
  -------------------------------------------------------------------
                         slack                                  0.096    

Slack (MET) :             0.100ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/CE
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.304ns  (logic 0.148ns (48.604%)  route 0.156ns (51.396%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X10Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X10Y150        FDRE (Prop_fdre_C_Q)         0.148     2.188 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg/Q
                         net (fo=2, routed)           0.156     2.344    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1
    SLICE_X10Y149        FDPE                                         r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X10Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism             -0.186     2.313    
    SLICE_X10Y149        FDPE (Hold_fdpe_C_CE)       -0.069     2.244    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -2.244    
                         arrival time                           2.344    
  -------------------------------------------------------------------
                         slack                                  0.100    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.263ns  (logic 0.141ns (53.591%)  route 0.122ns (46.409%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.041ns
    Clock Pessimism Removal (CPR):    0.445ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.628     2.041    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y147        FDCE (Prop_fdce_C_Q)         0.141     2.182 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/Q
                         net (fo=2, routed)           0.122     2.305    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/DIB0
    SLICE_X14Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/WCLK
    SLICE_X14Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB/CLK
                         clock pessimism             -0.445     2.054    
    SLICE_X14Y147        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.146     2.200    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_12_15/RAMB
  -------------------------------------------------------------------
                         required time                         -2.200    
                         arrival time                           2.305    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.264ns  (logic 0.141ns (53.388%)  route 0.123ns (46.612%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.041ns
    Clock Pessimism Removal (CPR):    0.445ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.628     2.041    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X13Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y147        FDCE (Prop_fdce_C_Q)         0.141     2.182 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[7]/Q
                         net (fo=2, routed)           0.123     2.306    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/DIA0
    SLICE_X12Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/WCLK
    SLICE_X12Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA/CLK
                         clock pessimism             -0.445     2.054    
    SLICE_X12Y147        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.147     2.201    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA
  -------------------------------------------------------------------
                         required time                         -2.201    
                         arrival time                           2.306    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.114ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1/I
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.078%)  route 0.110ns (43.922%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.041ns
    Clock Pessimism Removal (CPR):    0.445ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.628     2.041    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y148        FDCE (Prop_fdce_C_Q)         0.141     2.182 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[4]/Q
                         net (fo=2, routed)           0.110     2.293    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/DIB1
    SLICE_X14Y148        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/WCLK
    SLICE_X14Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
                         clock pessimism             -0.445     2.054    
    SLICE_X14Y148        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.124     2.178    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -2.178    
                         arrival time                           2.293    
  -------------------------------------------------------------------
                         slack                                  0.114    

Slack (MET) :             0.118ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA_D1/I
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.141ns (56.078%)  route 0.110ns (43.922%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.041ns
    Clock Pessimism Removal (CPR):    0.445ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.628     2.041    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X13Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y147        FDCE (Prop_fdce_C_Q)         0.141     2.182 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[8]/Q
                         net (fo=2, routed)           0.110     2.293    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/DIA1
    SLICE_X12Y147        RAMD32                                       r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/WCLK
    SLICE_X12Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA_D1/CLK
                         clock pessimism             -0.445     2.054    
    SLICE_X12Y147        RAMD32 (Hold_ramd32_CLK_I)
                                                      0.120     2.174    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_6_11/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -2.174    
                         arrival time                           2.293    
  -------------------------------------------------------------------
                         slack                                  0.118    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.141ns (71.838%)  route 0.055ns (28.162%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.525ns
    Source Clock Delay      (SCD):    2.065ns
    Clock Pessimism Removal (CPR):    0.460ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.652     2.065    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/idrck
    SLICE_X5Y138                                                      r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X5Y138         FDCE (Prop_fdce_C_Q)         0.141     2.206 r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/Q
                         net (fo=2, routed)           0.055     2.262    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[21]
    SLICE_X5Y138         FDCE                                         r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.926     2.525    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/idrck
    SLICE_X5Y138                                                      r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C
                         clock pessimism             -0.460     2.065    
    SLICE_X5Y138         FDCE (Hold_fdce_C_D)         0.075     2.140    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]
  -------------------------------------------------------------------
                         required time                         -2.140    
                         arrival time                           2.262    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.124ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/U_STAT/STAT_INIT_SLV_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_STAT/STAT_INIT_SLV_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.141ns (71.838%)  route 0.055ns (28.162%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.033ns
    Clock Pessimism Removal (CPR):    0.457ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.620     2.033    dbg_hub/inst/U_ICON/U_STAT/CLK
    SLICE_X19Y133                                                     r  dbg_hub/inst/U_ICON/U_STAT/STAT_INIT_SLV_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X19Y133        FDRE (Prop_fdre_C_Q)         0.141     2.174 r  dbg_hub/inst/U_ICON/U_STAT/STAT_INIT_SLV_reg[13]/Q
                         net (fo=2, routed)           0.055     2.230    dbg_hub/inst/U_ICON/U_STAT/STAT_INIT_SLV[13]
    SLICE_X19Y133        FDRE                                         r  dbg_hub/inst/U_ICON/U_STAT/STAT_INIT_SLV_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891     2.490    dbg_hub/inst/U_ICON/U_STAT/CLK
    SLICE_X19Y133                                                     r  dbg_hub/inst/U_ICON/U_STAT/STAT_INIT_SLV_reg[13]/C
                         clock pessimism             -0.457     2.033    
    SLICE_X19Y133        FDRE (Hold_fdre_C_D)         0.072     2.105    dbg_hub/inst/U_ICON/U_STAT/STAT_INIT_SLV_reg[13]
  -------------------------------------------------------------------
                         required time                         -2.105    
                         arrival time                           2.230    
  -------------------------------------------------------------------
                         slack                                  0.124    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
Waveform:           { 0 15 }
Period:             30.000
Sources:            { dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK }

Check Type        Corner  Lib Pin     Reference Pin  Required  Actual  Slack   Location       Pin                                                                                                                                                                                           
Min Period        n/a     BUFG/I      n/a            1.592     30.000  28.408  BUFGCTRL_X0Y1  dbg_hub/inst/u_bufg_icon/I                                                                                                                                                                    
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X10Y138  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/shift_reg_in_reg[0]/C                                                                                                                         
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X10Y138  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/shift_reg_in_reg[1]/C                                                                                                                         
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X13Y139  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_en_reg/C                                                                                                                                
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X12Y137  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[0]/C                                                                                                                         
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X12Y137  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[1]/C                                                                                                                         
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X12Y137  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[2]/C                                                                                                                         
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X12Y137  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD2/shift_reg_in_reg[3]/C                                                                                                                         
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X13Y140  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD3/shift_en_reg/C                                                                                                                                
Min Period        n/a     FDRE/C      n/a            1.000     30.000  29.000  SLICE_X12Y140  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD3/shift_reg_in_reg[0]/C                                                                                                                         
Low Pulse Width   Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA/CLK     
Low Pulse Width   Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA/CLK     
Low Pulse Width   Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK  
Low Pulse Width   Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK  
Low Pulse Width   Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB/CLK     
Low Pulse Width   Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB/CLK     
Low Pulse Width   Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK  
Low Pulse Width   Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK  
Low Pulse Width   Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC/CLK     
Low Pulse Width   Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC/CLK     
High Pulse Width  Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA/CLK     
High Pulse Width  Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA/CLK     
High Pulse Width  Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK  
High Pulse Width  Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK  
High Pulse Width  Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB/CLK     
High Pulse Width  Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB/CLK     
High Pulse Width  Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK  
High Pulse Width  Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK  
High Pulse Width  Slow    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC/CLK     
High Pulse Width  Fast    RAMD32/CLK  n/a            1.130     15.000  13.870  SLICE_X14Y148  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/RAM_reg_0_15_0_5/RAMC/CLK     



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
  To Clock:  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE

Setup :            0  Failing Endpoints,  Worst Slack       58.727ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.408ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       29.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             58.727ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/iDATA_CMD_reg/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.191ns  (logic 0.484ns (40.647%)  route 0.707ns (59.353%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.790ns = ( 63.790 - 60.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.469ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.410     5.048    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.105     5.153 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.297     5.449    dbg_hub/inst/U_ICON/n_0_U_SYNC
    SLICE_X21Y136        FDCE                                         r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.328    62.328    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.077    62.405 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.385    63.790    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                         clock pessimism              0.469    64.259    
                         clock uncertainty           -0.035    64.223    
    SLICE_X21Y136        FDCE (Setup_fdce_C_D)       -0.047    64.176    dbg_hub/inst/U_ICON/iDATA_CMD_reg
  -------------------------------------------------------------------
                         required time                         64.176    
                         arrival time                          -5.449    
  -------------------------------------------------------------------
                         slack                                 58.727    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.408ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/iDATA_CMD_reg/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        0.478ns  (logic 0.186ns (38.933%)  route 0.292ns (61.067%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.555ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    0.464ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446     1.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026     1.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620     2.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141     2.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.168     2.400    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.045     2.445 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.124     2.569    dbg_hub/inst/U_ICON/n_0_U_SYNC
    SLICE_X21Y136        FDCE                                         r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.636     1.636    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.029     1.665 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.891     2.555    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                         clock pessimism             -0.464     2.091    
    SLICE_X21Y136        FDCE (Hold_fdce_C_D)         0.070     2.161    dbg_hub/inst/U_ICON/iDATA_CMD_reg
  -------------------------------------------------------------------
                         required time                         -2.161    
                         arrival time                           2.569    
  -------------------------------------------------------------------
                         slack                                  0.408    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
Waveform:           { 0 30 }
Period:             60.000
Sources:            { dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE }

Check Type        Corner  Lib Pin  Reference Pin  Required  Actual  Slack   Location       Pin                                  
Min Period        n/a     BUFG/I   n/a            1.592     60.000  58.408  BUFGCTRL_X0Y5  dbg_hub/inst/u_bufg_icon_update/I    
Min Period        n/a     FDCE/C   n/a            1.000     60.000  59.000  SLICE_X21Y136  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C  
Low Pulse Width   Fast    FDCE/C   n/a            0.500     30.000  29.500  SLICE_X21Y136  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C  
Low Pulse Width   Slow    FDCE/C   n/a            0.500     30.000  29.500  SLICE_X21Y136  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C  
High Pulse Width  Slow    FDCE/C   n/a            0.500     30.000  29.500  SLICE_X21Y136  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C  
High Pulse Width  Fast    FDCE/C   n/a            0.500     30.000  29.500  SLICE_X21Y136  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C  



---------------------------------------------------------------------------------------------------
From Clock:  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  To Clock:  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK

Setup :            0  Failing Endpoints,  Worst Slack       12.623ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.076ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        6.870ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             12.623ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[18]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.959ns  (logic 0.538ns (18.182%)  route 2.421ns (81.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.742ns = ( 18.742 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.292     5.867    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y210        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[18]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.449    18.742    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[18]/C
                         clock pessimism              0.135    18.877    
                         clock uncertainty           -0.035    18.841    
    SLICE_X51Y210        FDRE (Setup_fdre_C_R)       -0.352    18.489    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[18]
  -------------------------------------------------------------------
                         required time                         18.489    
                         arrival time                          -5.867    
  -------------------------------------------------------------------
                         slack                                 12.623    

Slack (MET) :             12.623ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[19]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.959ns  (logic 0.538ns (18.182%)  route 2.421ns (81.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.742ns = ( 18.742 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.292     5.867    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y210        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[19]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.449    18.742    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[19]/C
                         clock pessimism              0.135    18.877    
                         clock uncertainty           -0.035    18.841    
    SLICE_X51Y210        FDRE (Setup_fdre_C_R)       -0.352    18.489    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[19]
  -------------------------------------------------------------------
                         required time                         18.489    
                         arrival time                          -5.867    
  -------------------------------------------------------------------
                         slack                                 12.623    

Slack (MET) :             12.623ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.959ns  (logic 0.538ns (18.182%)  route 2.421ns (81.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.742ns = ( 18.742 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.292     5.867    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y210        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.449    18.742    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[1]/C
                         clock pessimism              0.135    18.877    
                         clock uncertainty           -0.035    18.841    
    SLICE_X51Y210        FDRE (Setup_fdre_C_R)       -0.352    18.489    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[1]
  -------------------------------------------------------------------
                         required time                         18.489    
                         arrival time                          -5.867    
  -------------------------------------------------------------------
                         slack                                 12.623    

Slack (MET) :             12.623ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[22]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.959ns  (logic 0.538ns (18.182%)  route 2.421ns (81.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.742ns = ( 18.742 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.292     5.867    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y210        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[22]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.449    18.742    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[22]/C
                         clock pessimism              0.135    18.877    
                         clock uncertainty           -0.035    18.841    
    SLICE_X51Y210        FDRE (Setup_fdre_C_R)       -0.352    18.489    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[22]
  -------------------------------------------------------------------
                         required time                         18.489    
                         arrival time                          -5.867    
  -------------------------------------------------------------------
                         slack                                 12.623    

Slack (MET) :             12.623ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[23]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.959ns  (logic 0.538ns (18.182%)  route 2.421ns (81.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.742ns = ( 18.742 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.292     5.867    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y210        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[23]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.449    18.742    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[23]/C
                         clock pessimism              0.135    18.877    
                         clock uncertainty           -0.035    18.841    
    SLICE_X51Y210        FDRE (Setup_fdre_C_R)       -0.352    18.489    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[23]
  -------------------------------------------------------------------
                         required time                         18.489    
                         arrival time                          -5.867    
  -------------------------------------------------------------------
                         slack                                 12.623    

Slack (MET) :             12.623ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[27]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.959ns  (logic 0.538ns (18.182%)  route 2.421ns (81.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.742ns = ( 18.742 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.292     5.867    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y210        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[27]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.449    18.742    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[27]/C
                         clock pessimism              0.135    18.877    
                         clock uncertainty           -0.035    18.841    
    SLICE_X51Y210        FDRE (Setup_fdre_C_R)       -0.352    18.489    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[27]
  -------------------------------------------------------------------
                         required time                         18.489    
                         arrival time                          -5.867    
  -------------------------------------------------------------------
                         slack                                 12.623    

Slack (MET) :             12.623ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[28]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.959ns  (logic 0.538ns (18.182%)  route 2.421ns (81.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.742ns = ( 18.742 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.292     5.867    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y210        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[28]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.449    18.742    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[28]/C
                         clock pessimism              0.135    18.877    
                         clock uncertainty           -0.035    18.841    
    SLICE_X51Y210        FDRE (Setup_fdre_C_R)       -0.352    18.489    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[28]
  -------------------------------------------------------------------
                         required time                         18.489    
                         arrival time                          -5.867    
  -------------------------------------------------------------------
                         slack                                 12.623    

Slack (MET) :             12.623ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.959ns  (logic 0.538ns (18.182%)  route 2.421ns (81.818%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.742ns = ( 18.742 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.292     5.867    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y210        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.449    18.742    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[5]/C
                         clock pessimism              0.135    18.877    
                         clock uncertainty           -0.035    18.841    
    SLICE_X51Y210        FDRE (Setup_fdre_C_R)       -0.352    18.489    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[5]
  -------------------------------------------------------------------
                         required time                         18.489    
                         arrival time                          -5.867    
  -------------------------------------------------------------------
                         slack                                 12.623    

Slack (MET) :             12.776ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.807ns  (logic 0.538ns (19.168%)  route 2.269ns (80.832%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.743ns = ( 18.743 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.140     5.715    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y209        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[10]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.450    18.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[10]/C
                         clock pessimism              0.135    18.878    
                         clock uncertainty           -0.035    18.842    
    SLICE_X51Y209        FDRE (Setup_fdre_C_R)       -0.352    18.490    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[10]
  -------------------------------------------------------------------
                         required time                         18.490    
                         arrival time                          -5.715    
  -------------------------------------------------------------------
                         slack                                 12.776    

Slack (MET) :             12.776ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[20]/R
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@16.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        2.807ns  (logic 0.538ns (19.168%)  route 2.269ns (80.832%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.743ns = ( 18.743 - 16.000 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.553     2.908    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X46Y221                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y221        FDRE (Prop_fdre_C_Q)         0.433     3.341 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete_reg/Q
                         net (fo=8, routed)           1.129     4.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram_complete
    SLICE_X49Y211        LUT2 (Prop_lut2_I1_O)        0.105     4.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_data_reg[28]_i_1/O
                         net (fo=54, routed)          1.140     5.715    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1
    SLICE_X51Y209        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[20]/R
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         1.450    18.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X51Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[20]/C
                         clock pessimism              0.135    18.878    
                         clock uncertainty           -0.035    18.842    
    SLICE_X51Y209        FDRE (Setup_fdre_C_R)       -0.352    18.490    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg[20]
  -------------------------------------------------------------------
                         required time                         18.490    
                         arrival time                          -5.715    
  -------------------------------------------------------------------
                         slack                                 12.776    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.076ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMB/I
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.239ns  (logic 0.141ns (59.062%)  route 0.098ns (40.938%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.500ns
    Source Clock Delay      (SCD):    1.185ns
    Clock Pessimism Removal (CPR):    0.298ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.666     1.185    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X49Y212                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y212        FDRE (Prop_fdre_C_Q)         0.141     1.326 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[13]/Q
                         net (fo=1, routed)           0.098     1.423    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/DIB
    SLICE_X46Y211        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.942     1.500    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/WCLK
    SLICE_X46Y211                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMB/CLK
                         clock pessimism             -0.298     1.202    
    SLICE_X46Y211        RAMD64E (Hold_ramd64e_CLK_I)
                                                      0.146     1.348    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMB
  -------------------------------------------------------------------
                         required time                         -1.348    
                         arrival time                           1.423    
  -------------------------------------------------------------------
                         slack                                  0.076    

Slack (MET) :             0.079ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMB/I
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.239ns  (logic 0.141ns (59.062%)  route 0.098ns (40.938%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.497ns
    Source Clock Delay      (SCD):    1.185ns
    Clock Pessimism Removal (CPR):    0.298ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.666     1.185    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X49Y212                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y212        FDRE (Prop_fdre_C_Q)         0.141     1.326 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[16]/Q
                         net (fo=1, routed)           0.098     1.423    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/DIB
    SLICE_X46Y213        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.939     1.497    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/WCLK
    SLICE_X46Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMB/CLK
                         clock pessimism             -0.298     1.199    
    SLICE_X46Y213        RAMD64E (Hold_ramd64e_CLK_I)
                                                      0.146     1.345    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMB
  -------------------------------------------------------------------
                         required time                         -1.345    
                         arrival time                           1.423    
  -------------------------------------------------------------------
                         slack                                  0.079    

Slack (MET) :             0.083ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.547ns  (logic 0.432ns (79.019%)  route 0.115ns (20.981%))
  Logic Levels:           3  (CARRY4=3)
  Clock Path Skew:        0.358ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.504ns
    Source Clock Delay      (SCD):    1.101ns
    Clock Pessimism Removal (CPR):    0.044ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.583     1.101    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X43Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y198        FDRE (Prop_fdre_C_Q)         0.141     1.242 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[4]/Q
                         net (fo=2, routed)           0.114     1.356    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[4]
    SLICE_X43Y198        CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.197     1.553 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count_reg[5]_i_2__0_CARRY4/CO[3]
                         net (fo=1, routed)           0.000     1.553    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count_reg[8]_i_2__0
    SLICE_X43Y199        CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.039     1.592 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count_reg[9]_i_2__0_CARRY4/CO[3]
                         net (fo=1, routed)           0.001     1.593    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count_reg[12]_i_2__0
    SLICE_X43Y200        CARRY4 (Prop_carry4_CI_O[0])
                                                      0.055     1.648 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count_reg[12]_i_1__0_CARRY4/O[0]
                         net (fo=1, routed)           0.000     1.648    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count_reg[12]_i_1__0
    SLICE_X43Y200        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.946     1.504    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X43Y200                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[12]/C
                         clock pessimism             -0.044     1.460    
    SLICE_X43Y200        FDRE (Hold_fdre_C_D)         0.105     1.565    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[12]
  -------------------------------------------------------------------
                         required time                         -1.565    
                         arrival time                           1.648    
  -------------------------------------------------------------------
                         slack                                  0.083    

Slack (MET) :             0.105ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMA/WADR3
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.360ns  (logic 0.141ns (39.154%)  route 0.219ns (60.846%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.497ns
    Source Clock Delay      (SCD):    1.184ns
    Clock Pessimism Removal (CPR):    0.298ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.665     1.184    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X47Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y214        FDRE (Prop_fdre_C_Q)         0.141     1.325 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/Q
                         net (fo=53, routed)          0.219     1.544    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/ADDRD3
    SLICE_X46Y213        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMA/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.939     1.497    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/WCLK
    SLICE_X46Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMA/CLK
                         clock pessimism             -0.298     1.199    
    SLICE_X46Y213        RAMD64E (Hold_ramd64e_CLK_WADR3)
                                                      0.240     1.439    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMA
  -------------------------------------------------------------------
                         required time                         -1.439    
                         arrival time                           1.544    
  -------------------------------------------------------------------
                         slack                                  0.105    

Slack (MET) :             0.105ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMB/WADR3
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.360ns  (logic 0.141ns (39.154%)  route 0.219ns (60.846%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.497ns
    Source Clock Delay      (SCD):    1.184ns
    Clock Pessimism Removal (CPR):    0.298ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.665     1.184    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X47Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y214        FDRE (Prop_fdre_C_Q)         0.141     1.325 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/Q
                         net (fo=53, routed)          0.219     1.544    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/ADDRD3
    SLICE_X46Y213        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMB/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.939     1.497    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/WCLK
    SLICE_X46Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMB/CLK
                         clock pessimism             -0.298     1.199    
    SLICE_X46Y213        RAMD64E (Hold_ramd64e_CLK_WADR3)
                                                      0.240     1.439    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMB
  -------------------------------------------------------------------
                         required time                         -1.439    
                         arrival time                           1.544    
  -------------------------------------------------------------------
                         slack                                  0.105    

Slack (MET) :             0.105ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMC/WADR3
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.360ns  (logic 0.141ns (39.154%)  route 0.219ns (60.846%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.497ns
    Source Clock Delay      (SCD):    1.184ns
    Clock Pessimism Removal (CPR):    0.298ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.665     1.184    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X47Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y214        FDRE (Prop_fdre_C_Q)         0.141     1.325 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/Q
                         net (fo=53, routed)          0.219     1.544    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/ADDRD3
    SLICE_X46Y213        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMC/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.939     1.497    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/WCLK
    SLICE_X46Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMC/CLK
                         clock pessimism             -0.298     1.199    
    SLICE_X46Y213        RAMD64E (Hold_ramd64e_CLK_WADR3)
                                                      0.240     1.439    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMC
  -------------------------------------------------------------------
                         required time                         -1.439    
                         arrival time                           1.544    
  -------------------------------------------------------------------
                         slack                                  0.105    

Slack (MET) :             0.105ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMD/WADR3
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.360ns  (logic 0.141ns (39.154%)  route 0.219ns (60.846%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.497ns
    Source Clock Delay      (SCD):    1.184ns
    Clock Pessimism Removal (CPR):    0.298ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.665     1.184    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X47Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y214        FDRE (Prop_fdre_C_Q)         0.141     1.325 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[3]/Q
                         net (fo=53, routed)          0.219     1.544    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/ADDRD3
    SLICE_X46Y213        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMD/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.939     1.497    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/WCLK
    SLICE_X46Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMD/CLK
                         clock pessimism             -0.298     1.199    
    SLICE_X46Y213        RAMD64E (Hold_ramd64e_CLK_WADR3)
                                                      0.240     1.439    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_15_17/RAMD
  -------------------------------------------------------------------
                         required time                         -1.439    
                         arrival time                           1.544    
  -------------------------------------------------------------------
                         slack                                  0.105    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_9_11/RAMB/I
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.303ns  (logic 0.141ns (46.599%)  route 0.162ns (53.401%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.498ns
    Source Clock Delay      (SCD):    1.185ns
    Clock Pessimism Removal (CPR):    0.277ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.666     1.185    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X50Y212                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y212        FDRE (Prop_fdre_C_Q)         0.141     1.326 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data_reg_reg[10]/Q
                         net (fo=1, routed)           0.162     1.487    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_9_11/DIB
    SLICE_X46Y212        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_9_11/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.940     1.498    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_9_11/WCLK
    SLICE_X46Y212                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_9_11/RAMB/CLK
                         clock pessimism             -0.277     1.221    
    SLICE_X46Y212        RAMD64E (Hold_ramd64e_CLK_I)
                                                      0.146     1.367    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_9_11/RAMB
  -------------------------------------------------------------------
                         required time                         -1.367    
                         arrival time                           1.487    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.123ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/RAMA/WADR2
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.393ns  (logic 0.141ns (35.874%)  route 0.252ns (64.126%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.496ns
    Source Clock Delay      (SCD):    1.182ns
    Clock Pessimism Removal (CPR):    0.298ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.663     1.182    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X47Y217                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y217        FDRE (Prop_fdre_C_Q)         0.141     1.323 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[2]/Q
                         net (fo=53, routed)          0.252     1.575    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/ADDRD2
    SLICE_X48Y215        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/RAMA/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.938     1.496    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/WCLK
    SLICE_X48Y215                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/RAMA/CLK
                         clock pessimism             -0.298     1.198    
    SLICE_X48Y215        RAMD64E (Hold_ramd64e_CLK_WADR2)
                                                      0.254     1.452    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/RAMA
  -------------------------------------------------------------------
                         required time                         -1.452    
                         arrival time                           1.575    
  -------------------------------------------------------------------
                         slack                                  0.123    

Slack (MET) :             0.123ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/RAMB/WADR2
                            (rising edge-triggered cell RAMD64E clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns - mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise@0.000ns)
  Data Path Delay:        0.393ns  (logic 0.141ns (35.874%)  route 0.252ns (64.126%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.496ns
    Source Clock Delay      (SCD):    1.182ns
    Clock Pessimism Removal (CPR):    0.298ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.663     1.182    mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out
    SLICE_X47Y217                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y217        FDRE (Prop_fdre_C_Q)         0.141     1.323 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_reg[2]/Q
                         net (fo=53, routed)          0.252     1.575    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/ADDRD2
    SLICE_X48Y215        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/RAMB/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/I
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/O
                         net (fo=210, routed)         0.938     1.496    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/WCLK
    SLICE_X48Y215                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/RAMB/CLK
                         clock pessimism             -0.298     1.198    
    SLICE_X48Y215        RAMD64E (Hold_ramd64e_CLK_WADR2)
                                                      0.254     1.452    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_24_26/RAMB
  -------------------------------------------------------------------
                         required time                         -1.452    
                         arrival time                           1.575    
  -------------------------------------------------------------------
                         slack                                  0.123    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
Waveform:           { 0 8 }
Period:             16.000
Sources:            { mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK }

Check Type        Corner  Lib Pin                  Reference Pin  Required  Actual  Slack   Location            Pin                                                                                                                                                    
Min Period        n/a     GTPE2_CHANNEL/RXUSRCLK   n/a            3.030     16.000  12.970  GTPE2_CHANNEL_X0Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXUSRCLK                      
Min Period        n/a     GTPE2_CHANNEL/RXUSRCLK2  n/a            3.030     16.000  12.970  GTPE2_CHANNEL_X0Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXUSRCLK2                     
Min Period        n/a     GTPE2_CHANNEL/RXOUTCLK   n/a            2.424     16.000  13.576  GTPE2_CHANNEL_X0Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK                      
Min Period        n/a     BUFG/I                   n/a            1.592     16.000  14.408  BUFGCTRL_X0Y17      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg/I                                                                                    
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000  SLICE_X45Y199       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/run_phase_alignment_int_s3_reg/C               
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000  SLICE_X50Y203       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/rx_fsm_reset_done_int_s3_reg/C                 
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000  SLICE_X45Y199       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C  
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000  SLICE_X45Y199       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C  
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000  SLICE_X45Y199       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C  
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000  SLICE_X45Y199       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg4/C  
Low Pulse Width   Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMA/CLK                                 
Low Pulse Width   Fast    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMA/CLK                                 
Low Pulse Width   Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMB/CLK                                 
Low Pulse Width   Fast    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMB/CLK                                 
Low Pulse Width   Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMC/CLK                                 
Low Pulse Width   Fast    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMC/CLK                                 
Low Pulse Width   Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMD/CLK                                 
Low Pulse Width   Fast    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMD/CLK                                 
Low Pulse Width   Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X46Y211       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMA/CLK                               
Low Pulse Width   Fast    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X46Y211       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMA/CLK                               
High Pulse Width  Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMA/CLK                                 
High Pulse Width  Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMB/CLK                                 
High Pulse Width  Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMC/CLK                                 
High Pulse Width  Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X48Y213       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_0_2/RAMD/CLK                                 
High Pulse Width  Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X46Y211       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMA/CLK                               
High Pulse Width  Fast    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X46Y211       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMA/CLK                               
High Pulse Width  Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X46Y211       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMB/CLK                               
High Pulse Width  Fast    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X46Y211       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMB/CLK                               
High Pulse Width  Slow    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X46Y211       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMC/CLK                               
High Pulse Width  Fast    RAMD64E/CLK              n/a            1.130     8.000   6.870   SLICE_X46Y211       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/ram_reg_0_63_12_14/RAMC/CLK                               



---------------------------------------------------------------------------------------------------
From Clock:  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
  To Clock:  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        5.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
Waveform:           { 0 8 }
Period:             16.000
Sources:            { mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK }

Check Type        Corner  Lib Pin                 Reference Pin  Required  Actual  Slack   Location            Pin                                                                                                                                
Min Period        n/a     GTPE2_CHANNEL/TXOUTCLK  n/a            2.424     16.000  13.576  GTPE2_CHANNEL_X0Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK  
Min Period        n/a     BUFG/I                  n/a            1.592     16.000  14.408  BUFGCTRL_X0Y21      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/I                                                               
Min Period        n/a     MMCME2_ADV/CLKIN1       n/a            1.249     16.000  14.751  MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKIN1                                                          
Max Period        n/a     MMCME2_ADV/CLKIN1       n/a            100.000   16.000  84.000  MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKIN1                                                          
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1       n/a            3.000     8.000   5.000   MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKIN1                                                          
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1       n/a            3.000     8.000   5.000   MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKIN1                                                          
High Pulse Width  Slow    MMCME2_ADV/CLKIN1       n/a            3.000     8.000   5.000   MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKIN1                                                          
High Pulse Width  Fast    MMCME2_ADV/CLKIN1       n/a            3.000     8.000   5.000   MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKIN1                                                          



---------------------------------------------------------------------------------------------------
From Clock:  U0/core_clocking_i/clkfbout
  To Clock:  U0/core_clocking_i/clkfbout

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       14.751ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         U0/core_clocking_i/clkfbout
Waveform:           { 0 8 }
Period:             16.000
Sources:            { mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required  Actual  Slack    Location         Pin                                                                          
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249     16.000  14.751   MMCME2_ADV_X1Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKFBIN   
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249     16.000  14.751   MMCME2_ADV_X1Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKFBOUT  
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000   16.000  84.000   MMCME2_ADV_X1Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKFBIN   
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360   16.000  197.360  MMCME2_ADV_X1Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKFBOUT  



---------------------------------------------------------------------------------------------------
From Clock:  U0/core_clocking_i/clkout0
  To Clock:  U0/core_clocking_i/clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.545ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.069ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.286ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.545ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxs_dpmem_wr_data_d1_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.760ns  (logic 0.348ns (5.148%)  route 6.412ns (94.852%))
  Logic Levels:           0  
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.207ns = ( 14.207 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.412    13.308    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X108Y185       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxs_dpmem_wr_data_d1_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.292    14.207    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X108Y185                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxs_dpmem_wr_data_d1_reg[2]/C
                         clock pessimism              0.282    14.490    
                         clock uncertainty           -0.077    14.413    
    SLICE_X108Y185       FDRE (Setup_fdre_C_R)       -0.560    13.853    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxs_dpmem_wr_data_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         13.853    
                         arrival time                         -13.308    
  -------------------------------------------------------------------
                         slack                                  0.545    

Slack (MET) :             0.545ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxs_dpmem_wr_data_d1_reg[7]/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.760ns  (logic 0.348ns (5.148%)  route 6.412ns (94.852%))
  Logic Levels:           0  
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.207ns = ( 14.207 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.412    13.308    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X108Y185       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxs_dpmem_wr_data_d1_reg[7]/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.292    14.207    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X108Y185                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxs_dpmem_wr_data_d1_reg[7]/C
                         clock pessimism              0.282    14.490    
                         clock uncertainty           -0.077    14.413    
    SLICE_X108Y185       FDRE (Setup_fdre_C_R)       -0.560    13.853    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxs_dpmem_wr_data_d1_reg[7]
  -------------------------------------------------------------------
                         required time                         13.853    
                         arrival time                         -13.308    
  -------------------------------------------------------------------
                         slack                                  0.545    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync0_i/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.733ns  (logic 0.348ns (5.168%)  route 6.385ns (94.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.202ns = ( 14.202 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.385    13.281    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X112Y177       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync0_i/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.287    14.202    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X112Y177                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync0_i/C
                         clock pessimism              0.282    14.485    
                         clock uncertainty           -0.077    14.408    
    SLICE_X112Y177       FDRE (Setup_fdre_C_R)       -0.560    13.848    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync0_i
  -------------------------------------------------------------------
                         required time                         13.848    
                         arrival time                         -13.281    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync1_i/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.733ns  (logic 0.348ns (5.168%)  route 6.385ns (94.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.202ns = ( 14.202 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.385    13.281    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X112Y177       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync1_i/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.287    14.202    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X112Y177                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync1_i/C
                         clock pessimism              0.282    14.485    
                         clock uncertainty           -0.077    14.408    
    SLICE_X112Y177       FDRE (Setup_fdre_C_R)       -0.560    13.848    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync1_i
  -------------------------------------------------------------------
                         required time                         13.848    
                         arrival time                         -13.281    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync2_i/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.733ns  (logic 0.348ns (5.168%)  route 6.385ns (94.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.202ns = ( 14.202 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.385    13.281    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X112Y177       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync2_i/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.287    14.202    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X112Y177                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync2_i/C
                         clock pessimism              0.282    14.485    
                         clock uncertainty           -0.077    14.408    
    SLICE_X112Y177       FDRE (Setup_fdre_C_R)       -0.560    13.848    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync2_i
  -------------------------------------------------------------------
                         required time                         13.848    
                         arrival time                         -13.281    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync3_i/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.733ns  (logic 0.348ns (5.168%)  route 6.385ns (94.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.202ns = ( 14.202 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.385    13.281    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X112Y177       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync3_i/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.287    14.202    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X112Y177                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync3_i/C
                         clock pessimism              0.282    14.485    
                         clock uncertainty           -0.077    14.408    
    SLICE_X112Y177       FDRE (Setup_fdre_C_R)       -0.560    13.848    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync3_i
  -------------------------------------------------------------------
                         required time                         13.848    
                         arrival time                         -13.281    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync4_i/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.733ns  (logic 0.348ns (5.168%)  route 6.385ns (94.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.202ns = ( 14.202 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.385    13.281    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X112Y177       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync4_i/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.287    14.202    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X112Y177                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync4_i/C
                         clock pessimism              0.282    14.485    
                         clock uncertainty           -0.077    14.408    
    SLICE_X112Y177       FDRE (Setup_fdre_C_R)       -0.560    13.848    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync4_i
  -------------------------------------------------------------------
                         required time                         13.848    
                         arrival time                         -13.281    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync5_i/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.733ns  (logic 0.348ns (5.168%)  route 6.385ns (94.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.202ns = ( 14.202 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.385    13.281    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X112Y177       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync5_i/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.287    14.202    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X112Y177                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync5_i/C
                         clock pessimism              0.282    14.485    
                         clock uncertainty           -0.077    14.408    
    SLICE_X112Y177       FDRE (Setup_fdre_C_R)       -0.560    13.848    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync5_i
  -------------------------------------------------------------------
                         required time                         13.848    
                         arrival time                         -13.281    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync6_i/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.733ns  (logic 0.348ns (5.168%)  route 6.385ns (94.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.202ns = ( 14.202 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.385    13.281    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X112Y177       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync6_i/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.287    14.202    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X112Y177                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync6_i/C
                         clock pessimism              0.282    14.485    
                         clock uncertainty           -0.077    14.408    
    SLICE_X112Y177       FDRE (Setup_fdre_C_R)       -0.560    13.848    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync6_i
  -------------------------------------------------------------------
                         required time                         13.848    
                         arrival time                         -13.281    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
                            (rising edge-triggered cell FDSE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync7_i/R
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        6.733ns  (logic 0.348ns (5.168%)  route 6.385ns (94.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.202ns = ( 14.202 - 8.000 ) 
    Source Clock Delay      (SCD):    6.548ns
    Clock Pessimism Removal (CPR):    0.282ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.356     6.548    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X79Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y179        FDSE (Prop_fdse_C_Q)         0.348     6.896 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/sync_rst1_reg/Q
                         net (fo=963, routed)         6.385    13.281    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_reset
    SLICE_X112Y177       FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync7_i/R
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.287    14.202    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X112Y177                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync7_i/C
                         clock pessimism              0.282    14.485    
                         clock uncertainty           -0.077    14.408    
    SLICE_X112Y177       FDRE (Setup_fdre_C_R)       -0.560    13.848    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY/data_sync7_i
  -------------------------------------------------------------------
                         required time                         13.848    
                         arrival time                         -13.281    
  -------------------------------------------------------------------
                         slack                                  0.567    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rx_byte_counter/stat_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/dipa_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.424ns  (logic 0.226ns (53.350%)  route 0.198ns (46.650%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.264ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.270ns
    Source Clock Delay      (SCD):    2.612ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.554     2.612    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X83Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rx_byte_counter/stat_data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y181        FDRE (Prop_fdre_C_Q)         0.128     2.740 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rx_byte_counter/stat_data_reg[1]/Q
                         net (fo=1, routed)           0.198     2.937    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/stat_data__0[1]
    SLICE_X85Y181        LUT3 (Prop_lut3_I0_O)        0.098     3.035 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/dipa[1]_i_1/O
                         net (fo=1, routed)           0.000     3.035    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_dipa[1]_i_1
    SLICE_X85Y181        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/dipa_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.822     3.270    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X85Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/dipa_reg[1]/C
                         clock pessimism             -0.394     2.876    
    SLICE_X85Y181        FDRE (Hold_fdre_C_D)         0.091     2.967    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/dipa_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.967    
                         arrival time                           3.035    
  -------------------------------------------------------------------
                         slack                                  0.069    

Slack (MET) :             0.074ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxd_dpmem_wr_data_d1_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/I_RXD_MEM/FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/DIPADIP[0]
                            (rising edge-triggered cell RAMB36E1 clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.419ns  (logic 0.141ns (33.650%)  route 0.278ns (66.350%))
  Logic Levels:           0  
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.326ns
    Source Clock Delay      (SCD):    2.634ns
    Clock Pessimism Removal (CPR):    0.643ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.576     2.634    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    SLICE_X103Y182                                                    r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxd_dpmem_wr_data_d1_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y182       FDRE (Prop_fdre_C_Q)         0.141     2.775 r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxd_dpmem_wr_data_d1_reg[8]/Q
                         net (fo=1, routed)           0.278     3.053    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/rx_client_rxd_dpmem_wr_data_d1[8]
    RAMB36_X6Y35         RAMB36E1                                     r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/I_RXD_MEM/FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/DIPADIP[0]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.878     3.326    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/rx_mac_aclk
    RAMB36_X6Y35                                                      r  mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/I_RXD_MEM/FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/CLKARDCLK
                         clock pessimism             -0.643     2.682    
    RAMB36_X6Y35         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIPADIP[0])
                                                      0.296     2.978    mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/I_RXD_MEM/FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram
  -------------------------------------------------------------------
                         required time                         -2.978    
                         arrival time                           3.053    
  -------------------------------------------------------------------
                         slack                                  0.074    

Slack (MET) :             0.076ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/sync_rx_enable/data_sync_reg4/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx_enable_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.362ns  (logic 0.128ns (35.345%)  route 0.234ns (64.655%))
  Logic Levels:           0  
  Clock Path Skew:        0.269ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.274ns
    Source Clock Delay      (SCD):    2.611ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.553     2.611    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X83Y180                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/sync_rx_enable/data_sync_reg4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y180        FDRE (Prop_fdre_C_Q)         0.128     2.739 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/sync_rx_enable/data_sync_reg4/Q
                         net (fo=1, routed)           0.234     2.973    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx_enable_sync
    SLICE_X87Y186        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx_enable_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.826     3.274    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X87Y186                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx_enable_reg_reg/C
                         clock pessimism             -0.394     2.880    
    SLICE_X87Y186        FDRE (Hold_fdre_C_D)         0.017     2.897    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx_enable_reg_reg
  -------------------------------------------------------------------
                         required time                         -2.897    
                         arrival time                           2.973    
  -------------------------------------------------------------------
                         slack                                  0.076    

Slack (MET) :             0.079ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rx_byte_counter/stat_data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/fast_statistic_control[0].fast_statistics/sync_inc_vector/data_sync_reg0/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.406ns  (logic 0.141ns (34.718%)  route 0.265ns (65.282%))
  Logic Levels:           0  
  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.275ns
    Source Clock Delay      (SCD):    2.614ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.556     2.614    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X83Y183                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rx_byte_counter/stat_data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y183        FDRE (Prop_fdre_C_Q)         0.141     2.755 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rx_byte_counter/stat_data_reg[7]/Q
                         net (fo=1, routed)           0.265     3.020    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/stat_data[7]
    SLICE_X84Y187        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/fast_statistic_control[0].fast_statistics/sync_inc_vector/data_sync_reg0/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.827     3.275    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X84Y187                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/fast_statistic_control[0].fast_statistics/sync_inc_vector/data_sync_reg0/C
                         clock pessimism             -0.394     2.881    
    SLICE_X84Y187        FDRE (Hold_fdre_C_D)         0.060     2.941    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/fast_statistic_control[0].fast_statistics/sync_inc_vector/data_sync_reg0
  -------------------------------------------------------------------
                         required time                         -2.941    
                         arrival time                           3.020    
  -------------------------------------------------------------------
                         slack                                  0.079    

Slack (MET) :             0.080ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/DP/WADR2
                            (rising edge-triggered cell RAMD64E clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.294ns  (logic 0.128ns (43.496%)  route 0.166ns (56.504%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.271ns
    Source Clock Delay      (SCD):    2.613ns
    Clock Pessimism Removal (CPR):    0.645ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.555     2.613    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X81Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y181        FDRE (Prop_fdre_C_Q)         0.128     2.741 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/Q
                         net (fo=216, routed)         0.166     2.907    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/A2
    SLICE_X80Y181        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/DP/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.823     3.271    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/WCLK
    SLICE_X80Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/DP/CLK
                         clock pessimism             -0.645     2.626    
    SLICE_X80Y181        RAMD64E (Hold_ramd64e_CLK_WADR2)
                                                      0.201     2.827    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/DP
  -------------------------------------------------------------------
                         required time                         -2.827    
                         arrival time                           2.907    
  -------------------------------------------------------------------
                         slack                                  0.080    

Slack (MET) :             0.080ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/SP/WADR2
                            (rising edge-triggered cell RAMD64E clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.294ns  (logic 0.128ns (43.496%)  route 0.166ns (56.504%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.271ns
    Source Clock Delay      (SCD):    2.613ns
    Clock Pessimism Removal (CPR):    0.645ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.555     2.613    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X81Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y181        FDRE (Prop_fdre_C_Q)         0.128     2.741 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/Q
                         net (fo=216, routed)         0.166     2.907    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/A2
    SLICE_X80Y181        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/SP/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.823     3.271    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/WCLK
    SLICE_X80Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/SP/CLK
                         clock pessimism             -0.645     2.626    
    SLICE_X80Y181        RAMD64E (Hold_ramd64e_CLK_WADR2)
                                                      0.201     2.827    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[6].RAM64X1D_inst/SP
  -------------------------------------------------------------------
                         required time                         -2.827    
                         arrival time                           2.907    
  -------------------------------------------------------------------
                         slack                                  0.080    

Slack (MET) :             0.080ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/DP/WADR2
                            (rising edge-triggered cell RAMD64E clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.294ns  (logic 0.128ns (43.496%)  route 0.166ns (56.504%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.271ns
    Source Clock Delay      (SCD):    2.613ns
    Clock Pessimism Removal (CPR):    0.645ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.555     2.613    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X81Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y181        FDRE (Prop_fdre_C_Q)         0.128     2.741 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/Q
                         net (fo=216, routed)         0.166     2.907    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/A2
    SLICE_X80Y181        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/DP/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.823     3.271    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/WCLK
    SLICE_X80Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/DP/CLK
                         clock pessimism             -0.645     2.626    
    SLICE_X80Y181        RAMD64E (Hold_ramd64e_CLK_WADR2)
                                                      0.201     2.827    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/DP
  -------------------------------------------------------------------
                         required time                         -2.827    
                         arrival time                           2.907    
  -------------------------------------------------------------------
                         slack                                  0.080    

Slack (MET) :             0.080ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/SP/WADR2
                            (rising edge-triggered cell RAMD64E clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.294ns  (logic 0.128ns (43.496%)  route 0.166ns (56.504%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.271ns
    Source Clock Delay      (SCD):    2.613ns
    Clock Pessimism Removal (CPR):    0.645ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.555     2.613    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X81Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y181        FDRE (Prop_fdre_C_Q)         0.128     2.741 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/addra_reg[2]/Q
                         net (fo=216, routed)         0.166     2.907    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/A2
    SLICE_X80Y181        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/SP/WADR2
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.823     3.271    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/WCLK
    SLICE_X80Y181                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/SP/CLK
                         clock pessimism             -0.645     2.626    
    SLICE_X80Y181        RAMD64E (Hold_ramd64e_CLK_WADR2)
                                                      0.201     2.827    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_parity[7].RAM64X1D_inst/SP
  -------------------------------------------------------------------
                         required time                         -2.827    
                         arrival time                           2.907    
  -------------------------------------------------------------------
                         slack                                  0.080    

Slack (MET) :             0.081ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/accum_lower_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[12].RAM64X1D_inst/SP/I
                            (rising edge-triggered cell RAMD64E clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.242ns  (logic 0.141ns (58.222%)  route 0.101ns (41.777%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.266ns
    Source Clock Delay      (SCD):    2.608ns
    Clock Pessimism Removal (CPR):    0.643ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.550     2.608    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_ref_clk
    SLICE_X86Y173                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/accum_lower_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y173        FDRE (Prop_fdre_C_Q)         0.141     2.749 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/accum_lower_reg[12]/Q
                         net (fo=2, routed)           0.101     2.850    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[12].RAM64X1D_inst/D
    SLICE_X84Y172        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[12].RAM64X1D_inst/SP/I
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.818     3.266    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[12].RAM64X1D_inst/WCLK
    SLICE_X84Y172                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[12].RAM64X1D_inst/SP/CLK
                         clock pessimism             -0.643     2.623    
    SLICE_X84Y172        RAMD64E (Hold_ramd64e_CLK_I)
                                                      0.146     2.769    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[12].RAM64X1D_inst/SP
  -------------------------------------------------------------------
                         required time                         -2.769    
                         arrival time                           2.850    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.083ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/load_count_pipe_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/byte_wide_ram[6].header_field_dist_ram/DP/WADR1
                            (rising edge-triggered cell RAMD64E clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.405ns  (logic 0.141ns (34.799%)  route 0.264ns (65.201%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.279ns
    Source Clock Delay      (SCD):    2.622ns
    Clock Pessimism Removal (CPR):    0.644ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.564     2.622    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_clk
    SLICE_X71Y179                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/load_count_pipe_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y179        FDRE (Prop_fdre_C_Q)         0.141     2.763 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/load_count_pipe_reg[1]/Q
                         net (fo=25, routed)          0.264     3.027    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/byte_wide_ram[6].header_field_dist_ram/A1
    SLICE_X72Y178        RAMD64E                                      r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/byte_wide_ram[6].header_field_dist_ram/DP/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.831     3.279    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/byte_wide_ram[6].header_field_dist_ram/WCLK
    SLICE_X72Y178                                                     r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/byte_wide_ram[6].header_field_dist_ram/DP/CLK
                         clock pessimism             -0.644     2.635    
    SLICE_X72Y178        RAMD64E (Hold_ramd64e_CLK_WADR1)
                                                      0.309     2.944    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/byte_wide_ram[6].header_field_dist_ram/DP
  -------------------------------------------------------------------
                         required time                         -2.944    
                         arrival time                           3.027    
  -------------------------------------------------------------------
                         slack                                  0.083    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         U0/core_clocking_i/clkout0
Waveform:           { 0 4 }
Period:             8.000
Sources:            { mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin               Reference Pin  Required  Actual  Slack    Location            Pin                                                                                                                                                                                                                                                                                 
Min Period        n/a     GTPE2_CHANNEL/DRPCLK  n/a            5.714     8.000   2.286    GTPE2_CHANNEL_X0Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/DRPCLK                                                                                                                                                     
Min Period        n/a     RAMB36E1/CLKARDCLK    n/a            2.170     8.000   5.830    RAMB36_X6Y35        mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/I_RXD_MEM/FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/CLKARDCLK  
Min Period        n/a     RAMB36E1/CLKARDCLK    n/a            2.170     8.000   5.830    RAMB36_X6Y36        mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_DP_MEM_IF_I/I_RXS_MEM/FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/CLKARDCLK  
Min Period        n/a     RAMB36E1/CLKARDCLK    n/a            2.170     8.000   5.830    RAMB36_X7Y31        mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_MEM_INTERFACE/TXC_MEM/FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_init.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/CLKARDCLK     
Min Period        n/a     RAMB36E1/CLKARDCLK    n/a            2.170     8.000   5.830    RAMB36_X6Y31        mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_MEM_INTERFACE/TXD_MEM/FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram/CLKARDCLK   
Min Period        n/a     BUFG/I                n/a            1.592     8.000   6.408    BUFGCTRL_X0Y16      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/I                                                                                                                                                                                                                
Min Period        n/a     MMCME2_ADV/CLKOUT0    n/a            1.249     8.000   6.751    MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0                                                                                                                                                                                                          
Min Period        n/a     FDPE/C                n/a            1.000     8.000   7.000    SLICE_X125Y165      mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AXITX_2_TXCLIENT_FSM_GO/ClkB_reset_inst/async_rst0_reg/C                                                                                                                                                                                       
Min Period        n/a     FDPE/C                n/a            1.000     8.000   7.000    SLICE_X125Y165      mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AXITX_2_TXCLIENT_FSM_GO/ClkB_reset_inst/async_rst1_reg/C                                                                                                                                                                                       
Min Period        n/a     FDPE/C                n/a            1.000     8.000   7.000    SLICE_X125Y165      mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AXITX_2_TXCLIENT_FSM_GO/ClkB_reset_inst/async_rst2_reg/C                                                                                                                                                                                       
Max Period        n/a     MMCME2_ADV/CLKOUT0    n/a            213.360   8.000   205.360  MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0                                                                                                                                                                                                          
Low Pulse Width   Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y169       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[0].RAM64X1D_inst/DP/CLK                                                                                                                                                
Low Pulse Width   Fast    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y169       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[0].RAM64X1D_inst/DP/CLK                                                                                                                                                
Low Pulse Width   Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y169       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[0].RAM64X1D_inst/SP/CLK                                                                                                                                                
Low Pulse Width   Fast    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y169       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[0].RAM64X1D_inst/SP/CLK                                                                                                                                                
Low Pulse Width   Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y169       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[10].RAM64X1D_inst/DP/CLK                                                                                                                                               
Low Pulse Width   Fast    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y169       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[10].RAM64X1D_inst/DP/CLK                                                                                                                                               
Low Pulse Width   Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y169       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[10].RAM64X1D_inst/SP/CLK                                                                                                                                               
Low Pulse Width   Fast    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y169       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[10].RAM64X1D_inst/SP/CLK                                                                                                                                               
Low Pulse Width   Fast    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y172       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[11].RAM64X1D_inst/DP/CLK                                                                                                                                               
Low Pulse Width   Fast    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y172       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[11].RAM64X1D_inst/SP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y172       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[11].RAM64X1D_inst/DP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y172       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[11].RAM64X1D_inst/SP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y172       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[12].RAM64X1D_inst/DP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y172       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[12].RAM64X1D_inst/SP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y177       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[20].RAM64X1D_inst/DP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y177       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[20].RAM64X1D_inst/SP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y177       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[21].RAM64X1D_inst/DP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y177       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[21].RAM64X1D_inst/SP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y178       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[24].RAM64X1D_inst/DP/CLK                                                                                                                                               
High Pulse Width  Slow    RAMD64E/CLK           n/a            1.130     4.000   2.870    SLICE_X84Y178       mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[24].RAM64X1D_inst/SP/CLK                                                                                                                                               



---------------------------------------------------------------------------------------------------
From Clock:  U0/core_clocking_i/clkout1
  To Clock:  U0/core_clocking_i/clkout1

Setup :            0  Failing Endpoints,  Worst Slack       12.781ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.139ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        7.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             12.781ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.939ns  (logic 0.589ns (20.039%)  route 2.350ns (79.961%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.439ns = ( 22.439 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.365ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.902     9.771    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y215        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.524    22.439    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y215                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/C
                         clock pessimism              0.365    22.805    
                         clock uncertainty           -0.085    22.720    
    SLICE_X32Y215        FDRE (Setup_fdre_C_CE)      -0.168    22.552    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]
  -------------------------------------------------------------------
                         required time                         22.552    
                         arrival time                          -9.771    
  -------------------------------------------------------------------
                         slack                                 12.781    

Slack (MET) :             12.918ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.829ns  (logic 0.589ns (20.817%)  route 2.240ns (79.183%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.440ns = ( 22.440 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.792     9.661    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y214        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.525    22.440    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/C
                         clock pessimism              0.391    22.832    
                         clock uncertainty           -0.085    22.747    
    SLICE_X32Y214        FDRE (Setup_fdre_C_CE)      -0.168    22.579    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]
  -------------------------------------------------------------------
                         required time                         22.579    
                         arrival time                          -9.661    
  -------------------------------------------------------------------
                         slack                                 12.918    

Slack (MET) :             12.918ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.829ns  (logic 0.589ns (20.817%)  route 2.240ns (79.183%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.440ns = ( 22.440 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.792     9.661    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y214        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.525    22.440    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/C
                         clock pessimism              0.391    22.832    
                         clock uncertainty           -0.085    22.747    
    SLICE_X32Y214        FDRE (Setup_fdre_C_CE)      -0.168    22.579    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]
  -------------------------------------------------------------------
                         required time                         22.579    
                         arrival time                          -9.661    
  -------------------------------------------------------------------
                         slack                                 12.918    

Slack (MET) :             12.918ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.829ns  (logic 0.589ns (20.817%)  route 2.240ns (79.183%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.440ns = ( 22.440 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.792     9.661    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y214        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.525    22.440    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/C
                         clock pessimism              0.391    22.832    
                         clock uncertainty           -0.085    22.747    
    SLICE_X32Y214        FDRE (Setup_fdre_C_CE)      -0.168    22.579    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]
  -------------------------------------------------------------------
                         required time                         22.579    
                         arrival time                          -9.661    
  -------------------------------------------------------------------
                         slack                                 12.918    

Slack (MET) :             12.918ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.829ns  (logic 0.589ns (20.817%)  route 2.240ns (79.183%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.440ns = ( 22.440 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.391ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.792     9.661    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y214        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.525    22.440    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                         clock pessimism              0.391    22.832    
                         clock uncertainty           -0.085    22.747    
    SLICE_X32Y214        FDRE (Setup_fdre_C_CE)      -0.168    22.579    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
  -------------------------------------------------------------------
                         required time                         22.579    
                         arrival time                          -9.661    
  -------------------------------------------------------------------
                         slack                                 12.918    

Slack (MET) :             13.012ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.711ns  (logic 0.589ns (21.729%)  route 2.122ns (78.271%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.441ns = ( 22.441 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.365ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.673     9.542    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y213        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.526    22.441    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C
                         clock pessimism              0.365    22.807    
                         clock uncertainty           -0.085    22.722    
    SLICE_X32Y213        FDRE (Setup_fdre_C_CE)      -0.168    22.554    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]
  -------------------------------------------------------------------
                         required time                         22.554    
                         arrival time                          -9.542    
  -------------------------------------------------------------------
                         slack                                 13.012    

Slack (MET) :             13.012ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.711ns  (logic 0.589ns (21.729%)  route 2.122ns (78.271%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.441ns = ( 22.441 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.365ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.673     9.542    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y213        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.526    22.441    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/C
                         clock pessimism              0.365    22.807    
                         clock uncertainty           -0.085    22.722    
    SLICE_X32Y213        FDRE (Setup_fdre_C_CE)      -0.168    22.554    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]
  -------------------------------------------------------------------
                         required time                         22.554    
                         arrival time                          -9.542    
  -------------------------------------------------------------------
                         slack                                 13.012    

Slack (MET) :             13.012ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.711ns  (logic 0.589ns (21.729%)  route 2.122ns (78.271%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.441ns = ( 22.441 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.365ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.673     9.542    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y213        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.526    22.441    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/C
                         clock pessimism              0.365    22.807    
                         clock uncertainty           -0.085    22.722    
    SLICE_X32Y213        FDRE (Setup_fdre_C_CE)      -0.168    22.554    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]
  -------------------------------------------------------------------
                         required time                         22.554    
                         arrival time                          -9.542    
  -------------------------------------------------------------------
                         slack                                 13.012    

Slack (MET) :             13.012ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.711ns  (logic 0.589ns (21.729%)  route 2.122ns (78.271%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.441ns = ( 22.441 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.365ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.673     9.542    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y213        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.526    22.441    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y213                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/C
                         clock pessimism              0.365    22.807    
                         clock uncertainty           -0.085    22.722    
    SLICE_X32Y213        FDRE (Setup_fdre_C_CE)      -0.168    22.554    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]
  -------------------------------------------------------------------
                         required time                         22.554    
                         arrival time                          -9.542    
  -------------------------------------------------------------------
                         slack                                 13.012    

Slack (MET) :             13.131ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/CE
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        2.592ns  (logic 0.589ns (22.724%)  route 2.003ns (77.276%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.442ns = ( 22.442 - 16.000 ) 
    Source Clock Delay      (SCD):    6.832ns
    Clock Pessimism Removal (CPR):    0.365ns
  Clock Uncertainty:      0.085ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.640     6.832    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y214                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y214        FDRE (Prop_fdre_C_Q)         0.379     7.211 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/Q
                         net (fo=2, routed)           0.788     7.998    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]
    SLICE_X33Y211        LUT5 (Prop_lut5_I0_O)        0.105     8.103 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/time_out_wait_bypass_i_2/O
                         net (fo=2, routed)           0.661     8.764    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_wait_bypass_i_2
    SLICE_X33Y210        LUT4 (Prop_lut4_I0_O)        0.105     8.869 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/wait_bypass_count[0]_i_2/O
                         net (fo=17, routed)          0.554     9.424    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2
    SLICE_X32Y212        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.527    22.442    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X32Y212                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/C
                         clock pessimism              0.365    22.808    
                         clock uncertainty           -0.085    22.723    
    SLICE_X32Y212        FDRE (Setup_fdre_C_CE)      -0.168    22.555    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]
  -------------------------------------------------------------------
                         required time                         22.555    
                         arrival time                          -9.424    
  -------------------------------------------------------------------
                         slack                                 13.131    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[9]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.827ns  (logic 0.141ns (17.045%)  route 0.686ns (82.955%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X59Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y197        FDRE (Prop_fdre_C_Q)         0.141     2.779 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[9]/Q
                         net (fo=1, routed)           0.686     3.465    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int[9]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[9]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXDATA[9])
                                                      0.108     3.326    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.326    
                         arrival time                           3.465    
  -------------------------------------------------------------------
                         slack                                  0.139    

Slack (MET) :             0.144ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispmode_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXCHARDISPMODE[0]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.808ns  (logic 0.141ns (17.446%)  route 0.667ns (82.554%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispmode_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y198        FDRE (Prop_fdre_C_Q)         0.141     2.779 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispmode_int_reg[0]/Q
                         net (fo=1, routed)           0.667     3.446    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispmode_int[0]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXCHARDISPMODE[0]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXCHARDISPMODE[0])
                                                      0.084     3.302    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.302    
                         arrival time                           3.446    
  -------------------------------------------------------------------
                         slack                                  0.144    

Slack (MET) :             0.151ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispval_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXCHARDISPVAL[0]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.836ns  (logic 0.141ns (16.868%)  route 0.695ns (83.132%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispval_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y198        FDRE (Prop_fdre_C_Q)         0.141     2.779 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispval_int_reg[0]/Q
                         net (fo=1, routed)           0.695     3.474    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispval_int[0]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXCHARDISPVAL[0]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXCHARDISPVAL[0])
                                                      0.105     3.323    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.323    
                         arrival time                           3.474    
  -------------------------------------------------------------------
                         slack                                  0.151    

Slack (MET) :             0.177ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[8]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.812ns  (logic 0.128ns (15.767%)  route 0.684ns (84.233%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y198        FDRE (Prop_fdre_C_Q)         0.128     2.766 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[8]/Q
                         net (fo=1, routed)           0.684     3.450    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int[8]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[8]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXDATA[8])
                                                      0.055     3.273    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.273    
                         arrival time                           3.450    
  -------------------------------------------------------------------
                         slack                                  0.177    

Slack (MET) :             0.181ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[5]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.816ns  (logic 0.128ns (15.679%)  route 0.688ns (84.321%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y198        FDRE (Prop_fdre_C_Q)         0.128     2.766 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[5]/Q
                         net (fo=1, routed)           0.688     3.454    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int[5]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[5]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXDATA[5])
                                                      0.055     3.273    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.273    
                         arrival time                           3.454    
  -------------------------------------------------------------------
                         slack                                  0.181    

Slack (MET) :             0.181ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[14]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.815ns  (logic 0.128ns (15.696%)  route 0.687ns (84.304%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y198        FDRE (Prop_fdre_C_Q)         0.128     2.766 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/Q
                         net (fo=1, routed)           0.687     3.453    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int[14]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[14]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXDATA[14])
                                                      0.054     3.272    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.272    
                         arrival time                           3.453    
  -------------------------------------------------------------------
                         slack                                  0.181    

Slack (MET) :             0.183ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_txreset/reset_sync1/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_txreset/reset_sync2/D
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.205ns  (logic 0.148ns (72.157%)  route 0.057ns (27.843%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.392ns
    Source Clock Delay      (SCD):    2.727ns
    Clock Pessimism Removal (CPR):    0.664ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.669     2.727    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X46Y203                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_txreset/reset_sync1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y203        FDPE (Prop_fdpe_C_Q)         0.148     2.875 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_txreset/reset_sync1/Q
                         net (fo=1, routed)           0.057     2.932    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_txreset/reset_sync_reg1
    SLICE_X46Y203        FDPE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_txreset/reset_sync2/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.944     3.392    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X46Y203                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_txreset/reset_sync2/C
                         clock pessimism             -0.664     2.727    
    SLICE_X46Y203        FDPE (Hold_fdpe_C_D)         0.022     2.749    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_txreset/reset_sync2
  -------------------------------------------------------------------
                         required time                         -2.749    
                         arrival time                           2.932    
  -------------------------------------------------------------------
                         slack                                  0.183    

Slack (MET) :             0.184ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispval_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXCHARDISPVAL[1]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.869ns  (logic 0.141ns (16.221%)  route 0.728ns (83.779%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispval_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y198        FDRE (Prop_fdre_C_Q)         0.141     2.779 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispval_int_reg[1]/Q
                         net (fo=1, routed)           0.728     3.507    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txchardispval_int[1]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXCHARDISPVAL[1]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXCHARDISPVAL[1])
                                                      0.105     3.323    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.323    
                         arrival time                           3.507    
  -------------------------------------------------------------------
                         slack                                  0.184    

Slack (MET) :             0.187ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[0]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.875ns  (logic 0.141ns (16.110%)  route 0.734ns (83.890%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X59Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y199        FDRE (Prop_fdre_C_Q)         0.141     2.779 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[0]/Q
                         net (fo=1, routed)           0.734     3.513    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int[0]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[0]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXDATA[0])
                                                      0.108     3.326    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.326    
                         arrival time                           3.513    
  -------------------------------------------------------------------
                         slack                                  0.187    

Slack (MET) :             0.188ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[15]
                            (rising edge-triggered cell GTPE2_CHANNEL clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.823ns  (logic 0.128ns (15.549%)  route 0.695ns (84.451%))
  Logic Levels:           0  
  Clock Path Skew:        0.580ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.612ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.394ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y198        FDRE (Prop_fdre_C_Q)         0.128     2.766 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[15]/Q
                         net (fo=1, routed)           0.695     3.461    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int[15]
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXDATA[15]
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.165     3.612    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    GTPE2_CHANNEL_X0Y4                                                r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2
                         clock pessimism             -0.394     3.218    
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL (Hold_gtpe2_channel_TXUSRCLK2_TXDATA[15])
                                                      0.055     3.273    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i
  -------------------------------------------------------------------
                         required time                         -3.273    
                         arrival time                           3.461    
  -------------------------------------------------------------------
                         slack                                  0.188    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         U0/core_clocking_i/clkout1
Waveform:           { 0 8 }
Period:             16.000
Sources:            { mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1 }

Check Type        Corner  Lib Pin                  Reference Pin  Required  Actual  Slack    Location            Pin                                                                                                                                                    
Min Period        n/a     GTPE2_CHANNEL/TXUSRCLK   n/a            3.030     16.000  12.970   GTPE2_CHANNEL_X0Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK                      
Min Period        n/a     GTPE2_CHANNEL/TXUSRCLK2  n/a            3.030     16.000  12.970   GTPE2_CHANNEL_X0Y4  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXUSRCLK2                     
Min Period        n/a     BUFG/I                   n/a            1.592     16.000  14.408   BUFGCTRL_X0Y18      mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/I                                                                                    
Min Period        n/a     MMCME2_ADV/CLKOUT1       n/a            1.249     16.000  14.751   MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1                                                                             
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000   SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/C               
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000   SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C  
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000   SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C  
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000   SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C  
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000   SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg4/C  
Min Period        n/a     FDRE/C                   n/a            1.000     16.000  15.000   SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg5/C  
Max Period        n/a     MMCME2_ADV/CLKOUT1       n/a            213.360   16.000  197.360  MMCME2_ADV_X1Y4     mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1                                                                             
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/C               
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C  
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C  
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C  
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg4/C  
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg5/C  
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg6/C  
Low Pulse Width   Slow    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y210       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C                     
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y210       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C                     
Low Pulse Width   Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X34Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C                 
High Pulse Width  Slow    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/C               
High Pulse Width  Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/C               
High Pulse Width  Slow    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C  
High Pulse Width  Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C  
High Pulse Width  Slow    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C  
High Pulse Width  Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C  
High Pulse Width  Slow    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C  
High Pulse Width  Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C  
High Pulse Width  Slow    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg4/C  
High Pulse Width  Fast    FDRE/C                   n/a            0.500     8.000   7.500    SLICE_X33Y209       mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg4/C  



---------------------------------------------------------------------------------------------------
From Clock:  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  To Clock:  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK

Setup :            0  Failing Endpoints,  Worst Slack       14.080ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.103ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       15.812ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             14.080ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/CE
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        2.337ns  (logic 0.589ns (25.200%)  route 1.748ns (74.800%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.050ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.456ns = ( 20.123 - 16.667 ) 
    Source Clock Delay      (SCD):    3.909ns
    Clock Pessimism Removal (CPR):    0.403ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446     2.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081     2.527 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.382     3.909    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X77Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y129        FDCE (Prop_fdce_C_Q)         0.379     4.288 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter_reg[0]/Q
                         net (fo=6, routed)           0.824     5.112    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/p_1_in
    SLICE_X80Y129        LUT6 (Prop_lut6_I1_O)        0.105     5.217 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE_i_2/O
                         net (fo=1, routed)           0.638     5.855    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_SYNC_FDRE_i_2
    SLICE_X79Y129        LUT5 (Prop_lut5_I2_O)        0.105     5.960 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE_i_1/O
                         net (fo=1, routed)           0.286     6.246    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CE
    SLICE_X78Y129        FDRE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    18.780    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    18.857 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.266    20.123    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
                         clock pessimism              0.403    20.526    
                         clock uncertainty           -0.035    20.490    
    SLICE_X78Y129        FDRE (Setup_fdre_C_CE)      -0.164    20.326    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE
  -------------------------------------------------------------------
                         required time                         20.326    
                         arrival time                          -6.246    
  -------------------------------------------------------------------
                         slack                                 14.080    

Slack (MET) :             14.502ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count_reg[7]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        2.062ns  (logic 0.594ns (28.806%)  route 1.468ns (71.194%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.458ns = ( 36.791 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.343ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.229    21.180    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I0_O)        0.105    21.285 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Shift_31_INST_0/O
                         net (fo=16, routed)          1.239    22.524    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X86Y129        LUT6 (Prop_lut6_I0_O)        0.105    22.629 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count[7]_i_1/O
                         net (fo=1, routed)           0.000    22.629    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[7]
    SLICE_X86Y129        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.268    36.791    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X86Y129                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count_reg[7]/C
                         clock pessimism              0.343    37.134    
                         clock uncertainty           -0.035    37.099    
    SLICE_X86Y129        FDCE (Setup_fdce_C_D)        0.032    37.131    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count_reg[7]
  -------------------------------------------------------------------
                         required time                         37.131    
                         arrival time                         -22.629    
  -------------------------------------------------------------------
                         slack                                 14.502    

Slack (MET) :             14.601ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_error_reg/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        2.080ns  (logic 0.594ns (28.564%)  route 1.486ns (71.436%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.454ns = ( 36.787 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.419ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.689    21.639    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I4_O)        0.105    21.744 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun_i_3/O
                         net (fo=2, routed)           0.797    22.541    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun1
    SLICE_X80Y127        LUT6 (Prop_lut6_I1_O)        0.105    22.646 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_error_i_1/O
                         net (fo=1, routed)           0.000    22.646    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_mb_instr_error_i_1
    SLICE_X80Y127        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_error_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.264    36.787    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X80Y127                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_error_reg/C
                         clock pessimism              0.419    37.206    
                         clock uncertainty           -0.035    37.171    
    SLICE_X80Y127        FDCE (Setup_fdce_C_D)        0.076    37.247    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_error_reg
  -------------------------------------------------------------------
                         required time                         37.247    
                         arrival time                         -22.646    
  -------------------------------------------------------------------
                         slack                                 14.601    

Slack (MET) :             14.702ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count_reg[4]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        1.861ns  (logic 0.594ns (31.910%)  route 1.267ns (68.090%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.098ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.459ns = ( 36.792 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.343ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.229    21.180    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I0_O)        0.105    21.285 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Shift_31_INST_0/O
                         net (fo=16, routed)          1.038    22.323    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Shift
    SLICE_X87Y130        LUT6 (Prop_lut6_I0_O)        0.105    22.428 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count[4]_i_1/O
                         net (fo=1, routed)           0.000    22.428    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/p_0_in[4]
    SLICE_X87Y130        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.269    36.792    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X87Y130                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count_reg[4]/C
                         clock pessimism              0.343    37.135    
                         clock uncertainty           -0.035    37.100    
    SLICE_X87Y130        FDCE (Setup_fdce_C_D)        0.030    37.130    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_count_reg[4]
  -------------------------------------------------------------------
                         required time                         37.130    
                         arrival time                         -22.428    
  -------------------------------------------------------------------
                         slack                                 14.702    

Slack (MET) :             14.800ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun_reg/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        1.878ns  (logic 0.594ns (31.634%)  route 1.284ns (68.366%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.454ns = ( 36.787 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.419ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.689    21.639    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I4_O)        0.105    21.744 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun_i_3/O
                         net (fo=2, routed)           0.595    22.339    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun1
    SLICE_X80Y127        LUT6 (Prop_lut6_I1_O)        0.105    22.444 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun_i_1/O
                         net (fo=1, routed)           0.000    22.444    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_mb_instr_overrun_i_1
    SLICE_X80Y127        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.264    36.787    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X80Y127                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun_reg/C
                         clock pessimism              0.419    37.206    
                         clock uncertainty           -0.035    37.171    
    SLICE_X80Y127        FDCE (Setup_fdce_C_D)        0.074    37.245    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/mb_instr_overrun_reg
  -------------------------------------------------------------------
                         required time                         37.245    
                         arrival time                         -22.444    
  -------------------------------------------------------------------
                         slack                                 14.800    

Slack (MET) :             14.887ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        1.539ns  (logic 0.489ns (31.774%)  route 1.050ns (68.225%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.460ns = ( 36.793 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.403ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.229    21.180    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I0_O)        0.105    21.285 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Shift_31_INST_0/O
                         net (fo=16, routed)          0.821    22.106    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/E[0]
    SLICE_X82Y141        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.270    36.793    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X82Y141                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[1]/C
                         clock pessimism              0.403    37.196    
                         clock uncertainty           -0.035    37.161    
    SLICE_X82Y141        FDCE (Setup_fdce_C_CE)      -0.168    36.993    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[1]
  -------------------------------------------------------------------
                         required time                         36.993    
                         arrival time                         -22.106    
  -------------------------------------------------------------------
                         slack                                 14.887    

Slack (MET) :             14.887ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[2]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        1.539ns  (logic 0.489ns (31.774%)  route 1.050ns (68.225%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.460ns = ( 36.793 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.403ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.229    21.180    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I0_O)        0.105    21.285 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Shift_31_INST_0/O
                         net (fo=16, routed)          0.821    22.106    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/E[0]
    SLICE_X82Y141        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.270    36.793    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X82Y141                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[2]/C
                         clock pessimism              0.403    37.196    
                         clock uncertainty           -0.035    37.161    
    SLICE_X82Y141        FDCE (Setup_fdce_C_CE)      -0.168    36.993    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[2]
  -------------------------------------------------------------------
                         required time                         36.993    
                         arrival time                         -22.106    
  -------------------------------------------------------------------
                         slack                                 14.887    

Slack (MET) :             14.887ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[3]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        1.539ns  (logic 0.489ns (31.774%)  route 1.050ns (68.225%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.460ns = ( 36.793 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.403ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.229    21.180    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I0_O)        0.105    21.285 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Shift_31_INST_0/O
                         net (fo=16, routed)          0.821    22.106    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/E[0]
    SLICE_X82Y141        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.270    36.793    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X82Y141                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[3]/C
                         clock pessimism              0.403    37.196    
                         clock uncertainty           -0.035    37.161    
    SLICE_X82Y141        FDCE (Setup_fdce_C_CE)      -0.168    36.993    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[3]
  -------------------------------------------------------------------
                         required time                         36.993    
                         arrival time                         -22.106    
  -------------------------------------------------------------------
                         slack                                 14.887    

Slack (MET) :             14.887ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[4]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        1.539ns  (logic 0.489ns (31.774%)  route 1.050ns (68.225%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.460ns = ( 36.793 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.403ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.229    21.180    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I0_O)        0.105    21.285 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Shift_31_INST_0/O
                         net (fo=16, routed)          0.821    22.106    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/E[0]
    SLICE_X82Y141        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.270    36.793    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X82Y141                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[4]/C
                         clock pessimism              0.403    37.196    
                         clock uncertainty           -0.035    37.161    
    SLICE_X82Y141        FDCE (Setup_fdce_C_CE)      -0.168    36.993    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[4]
  -------------------------------------------------------------------
                         required time                         36.993    
                         arrival time                         -22.106    
  -------------------------------------------------------------------
                         slack                                 14.887    

Slack (MET) :             14.887ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C
                            (falling edge-triggered cell FDRE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[5]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall@16.667ns)
  Data Path Delay:        1.539ns  (logic 0.489ns (31.774%)  route 1.050ns (68.225%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.460ns = ( 36.793 - 33.333 ) 
    Source Clock Delay      (SCD):    3.900ns = ( 20.567 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.403ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.446    19.113    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081    19.194 f  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.373    20.567    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X78Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y129        FDRE (Prop_fdre_C_Q)         0.384    20.951 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE/Q
                         net (fo=4, routed)           0.229    21.180    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/sync
    SLICE_X79Y129        LUT6 (Prop_lut6_I0_O)        0.105    21.285 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Shift_31_INST_0/O
                         net (fo=16, routed)          0.821    22.106    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/E[0]
    SLICE_X82Y141        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           2.113    35.446    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.077    35.523 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         1.270    36.793    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X82Y141                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[5]/C
                         clock pessimism              0.403    37.196    
                         clock uncertainty           -0.035    37.161    
    SLICE_X82Y141        FDCE (Setup_fdce_C_CE)      -0.168    36.993    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.fifo_Din_reg[5]
  -------------------------------------------------------------------
                         required time                         36.993    
                         arrival time                         -22.106    
  -------------------------------------------------------------------
                         slack                                 14.887    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.103ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tdo_reg_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tdo_reg_reg[4]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.237ns  (logic 0.186ns (78.333%)  route 0.051ns (21.667%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.314ns
    Source Clock Delay      (SCD):    1.863ns
    Clock Pessimism Removal (CPR):    0.438ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.564     1.863    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X81Y138                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tdo_reg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y138        FDCE (Prop_fdce_C_Q)         0.141     2.004 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tdo_reg_reg[3]/Q
                         net (fo=1, routed)           0.051     2.055    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.RX_FIFO_I/I1[1]
    SLICE_X80Y138        LUT5 (Prop_lut5_I0_O)        0.045     2.100 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.RX_FIFO_I/Use_UART.tdo_reg[4]_i_1/O
                         net (fo=1, routed)           0.000     2.100    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_9_Use_UART.RX_FIFO_I
    SLICE_X80Y138        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tdo_reg_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.835     2.314    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/I1
    SLICE_X80Y138                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tdo_reg_reg[4]/C
                         clock pessimism             -0.438     1.876    
    SLICE_X80Y138        FDCE (Hold_fdce_C_D)         0.121     1.997    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tdo_reg_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.997    
                         arrival time                           2.100    
  -------------------------------------------------------------------
                         slack                                  0.103    

Slack (MET) :             0.150ns  (arrival time - required time)
  Source:                 mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[7].sync_bit/Single_Synchronize.use_async_reset.sync_reg/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[7]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.240ns  (logic 0.141ns (58.643%)  route 0.099ns (41.357%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    1.853ns
    Clock Pessimism Removal (CPR):    0.434ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.554     1.853    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[7].sync_bit/Dbg_Clk
    SLICE_X87Y126                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[7].sync_bit/Single_Synchronize.use_async_reset.sync_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y126        FDCE (Prop_fdce_C_Q)         0.141     1.994 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[7].sync_bit/Single_Synchronize.use_async_reset.sync_reg/Q
                         net (fo=1, routed)           0.099     2.093    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_7_sync_dbg_hit
    SLICE_X85Y127        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.823     2.302    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X85Y127                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[7]/C
                         clock pessimism             -0.434     1.868    
    SLICE_X85Y127        FDCE (Hold_fdce_C_D)         0.075     1.943    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[7]
  -------------------------------------------------------------------
                         required time                         -1.943    
                         arrival time                           2.093    
  -------------------------------------------------------------------
                         slack                                  0.150    

Slack (MET) :             0.156ns  (arrival time - required time)
  Source:                 mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[22]/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[21]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.268ns  (logic 0.141ns (52.614%)  route 0.127ns (47.386%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.322ns
    Source Clock Delay      (SCD):    1.872ns
    Clock Pessimism Removal (CPR):    0.414ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.573     1.872    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X101Y122                                                    r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y122       FDCE (Prop_fdce_C_Q)         0.141     2.013 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[22]/Q
                         net (fo=3, routed)           0.127     2.140    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_shift_datain_reg[22]
    SLICE_X102Y122       FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.843     2.322    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X102Y122                                                    r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[21]/C
                         clock pessimism             -0.414     1.908    
    SLICE_X102Y122       FDCE (Hold_fdce_C_D)         0.076     1.984    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[21]
  -------------------------------------------------------------------
                         required time                         -1.984    
                         arrival time                           2.140    
  -------------------------------------------------------------------
                         slack                                  0.156    

Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[2]/D
                            (rising edge-triggered cell FDPE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.219ns  (logic 0.164ns (74.792%)  route 0.055ns (25.208%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.321ns
    Source Clock Delay      (SCD):    1.872ns
    Clock Pessimism Removal (CPR):    0.449ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.573     1.872    mbsys_i/mdm_1/U0/MDM_Core_I1/I1
    SLICE_X72Y134                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y134        FDCE (Prop_fdce_C_Q)         0.164     2.036 r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[3]/Q
                         net (fo=1, routed)           0.055     2.091    mbsys_i/mdm_1/U0/MDM_Core_I1/n_0_Config_Reg_reg[3]
    SLICE_X72Y134        FDPE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.842     2.321    mbsys_i/mdm_1/U0/MDM_Core_I1/I1
    SLICE_X72Y134                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[2]/C
                         clock pessimism             -0.449     1.872    
    SLICE_X72Y134        FDPE (Hold_fdpe_C_D)         0.060     1.932    mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.932    
                         arrival time                           2.091    
  -------------------------------------------------------------------
                         slack                                  0.159    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[25]/C
                            (rising edge-triggered cell FDPE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[12]_srl13_MDM_Core_I1_Config_Reg_reg_c_55/D
                            (rising edge-triggered cell SRL16E clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.242ns  (logic 0.128ns (52.975%)  route 0.114ns (47.025%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.319ns
    Source Clock Delay      (SCD):    1.870ns
    Clock Pessimism Removal (CPR):    0.436ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.571     1.870    mbsys_i/mdm_1/U0/MDM_Core_I1/I1
    SLICE_X73Y132                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y132        FDPE (Prop_fdpe_C_Q)         0.128     1.998 r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[25]/Q
                         net (fo=1, routed)           0.114     2.112    mbsys_i/mdm_1/U0/MDM_Core_I1/n_0_Config_Reg_reg[25]
    SLICE_X72Y132        SRL16E                                       r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[12]_srl13_MDM_Core_I1_Config_Reg_reg_c_55/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.840     2.319    mbsys_i/mdm_1/U0/MDM_Core_I1/I1
    SLICE_X72Y132                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[12]_srl13_MDM_Core_I1_Config_Reg_reg_c_55/CLK
                         clock pessimism             -0.436     1.883    
    SLICE_X72Y132        SRL16E (Hold_srl16e_CLK_D)
                                                      0.063     1.946    mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[12]_srl13_MDM_Core_I1_Config_Reg_reg_c_55
  -------------------------------------------------------------------
                         required time                         -1.946    
                         arrival time                           2.112    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[30]/C
                            (rising edge-triggered cell FDPE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[28]_srl2_MDM_Core_I1_Config_Reg_reg_c_44/D
                            (rising edge-triggered cell SRL16E clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.241ns  (logic 0.128ns (53.178%)  route 0.113ns (46.822%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.319ns
    Source Clock Delay      (SCD):    1.870ns
    Clock Pessimism Removal (CPR):    0.436ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.571     1.870    mbsys_i/mdm_1/U0/MDM_Core_I1/I1
    SLICE_X73Y132                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[30]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y132        FDPE (Prop_fdpe_C_Q)         0.128     1.998 r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[30]/Q
                         net (fo=1, routed)           0.113     2.111    mbsys_i/mdm_1/U0/MDM_Core_I1/n_0_Config_Reg_reg[30]
    SLICE_X72Y132        SRL16E                                       r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[28]_srl2_MDM_Core_I1_Config_Reg_reg_c_44/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.840     2.319    mbsys_i/mdm_1/U0/MDM_Core_I1/I1
    SLICE_X72Y132                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[28]_srl2_MDM_Core_I1_Config_Reg_reg_c_44/CLK
                         clock pessimism             -0.436     1.883    
    SLICE_X72Y132        SRL16E (Hold_srl16e_CLK_D)
                                                      0.062     1.945    mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[28]_srl2_MDM_Core_I1_Config_Reg_reg_c_44
  -------------------------------------------------------------------
                         required time                         -1.945    
                         arrival time                           2.111    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[3].sync_bit/Single_Synchronize.use_async_reset.sync_reg/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.249ns  (logic 0.141ns (56.528%)  route 0.108ns (43.472%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.304ns
    Source Clock Delay      (SCD):    1.857ns
    Clock Pessimism Removal (CPR):    0.434ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.558     1.857    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[3].sync_bit/Dbg_Clk
    SLICE_X87Y130                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[3].sync_bit/Single_Synchronize.use_async_reset.sync_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y130        FDCE (Prop_fdce_C_Q)         0.141     1.998 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[3].sync_bit/Single_Synchronize.use_async_reset.sync_reg/Q
                         net (fo=1, routed)           0.108     2.106    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_3_sync_dbg_hit
    SLICE_X87Y129        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.825     2.304    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X87Y129                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[3]/C
                         clock pessimism             -0.434     1.870    
    SLICE_X87Y129        FDCE (Hold_fdce_C_D)         0.070     1.940    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.940    
                         arrival time                           2.106    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.168ns  (arrival time - required time)
  Source:                 mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[6]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.267ns  (logic 0.141ns (52.817%)  route 0.126ns (47.183%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.322ns
    Source Clock Delay      (SCD):    1.872ns
    Clock Pessimism Removal (CPR):    0.414ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.573     1.872    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X101Y122                                                    r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y122       FDCE (Prop_fdce_C_Q)         0.141     2.013 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[7]/Q
                         net (fo=2, routed)           0.126     2.139    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_shift_datain_reg[7]
    SLICE_X102Y122       FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.843     2.322    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X102Y122                                                    r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[6]/C
                         clock pessimism             -0.414     1.908    
    SLICE_X102Y122       FDCE (Hold_fdce_C_D)         0.063     1.971    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[6]
  -------------------------------------------------------------------
                         required time                         -1.971    
                         arrival time                           2.139    
  -------------------------------------------------------------------
                         slack                                  0.168    

Slack (MET) :             0.176ns  (arrival time - required time)
  Source:                 mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[8]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.252ns  (logic 0.141ns (55.929%)  route 0.111ns (44.071%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.318ns
    Source Clock Delay      (SCD):    1.870ns
    Clock Pessimism Removal (CPR):    0.435ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.571     1.870    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X99Y122                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y122        FDCE (Prop_fdce_C_Q)         0.141     2.011 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/shift_datain_reg[9]/Q
                         net (fo=2, routed)           0.111     2.122    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_shift_datain_reg[9]
    SLICE_X96Y122        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.839     2.318    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X96Y122                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[8]/C
                         clock pessimism             -0.435     1.883    
    SLICE_X96Y122        FDCE (Hold_fdce_C_D)         0.063     1.946    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Instr_Reg_TCK_reg[8]
  -------------------------------------------------------------------
                         required time                         -1.946    
                         arrival time                           2.122    
  -------------------------------------------------------------------
                         slack                                  0.176    

Slack (MET) :             0.181ns  (arrival time - required time)
  Source:                 mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[12].sync_bit/Single_Synchronize.use_async_reset.sync_reg/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[12]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise@0.000ns)
  Data Path Delay:        0.243ns  (logic 0.141ns (58.128%)  route 0.102ns (41.872%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    1.853ns
    Clock Pessimism Removal (CPR):    0.434ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.273     1.273    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.299 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.554     1.853    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[12].sync_bit/Dbg_Clk
    SLICE_X87Y126                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[12].sync_bit/Single_Synchronize.use_async_reset.sync_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y126        FDCE (Prop_fdce_C_Q)         0.141     1.994 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/sync_dbg_hit/sync_bits[12].sync_bit/Single_Synchronize.use_async_reset.sync_reg/Q
                         net (fo=1, routed)           0.102     2.095    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_12_sync_dbg_hit
    SLICE_X87Y127        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
                         net (fo=1, routed)           1.450     1.450    mbsys_i/mdm_1/U0/I
    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.029     1.479 r  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/O
                         net (fo=273, routed)         0.823     2.302    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Clk
    SLICE_X87Y127                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[12]/C
                         clock pessimism             -0.434     1.868    
    SLICE_X87Y127        FDCE (Hold_fdce_C_D)         0.047     1.915    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/status_reg_reg[12]
  -------------------------------------------------------------------
                         required time                         -1.915    
                         arrival time                           2.095    
  -------------------------------------------------------------------
                         slack                                  0.181    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK
Waveform:           { 0 16.6665 }
Period:             33.333
Sources:            { mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK }

Check Type        Corner  Lib Pin      Reference Pin  Required  Actual  Slack   Location       Pin                                                                                                                                                                                                    
Min Period        n/a     BUFG/I       n/a            1.592     33.333  31.741  BUFGCTRL_X0Y2  mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK/I                                                                                                                                                         
Min Period        n/a     FDCE/C       n/a            1.000     33.333  32.333  SLICE_X72Y133  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[0]/C                                                                                                                                                       
Min Period        n/a     FDCE/C       n/a            1.000     33.333  32.333  SLICE_X73Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[10]/C                                                                                                                                                      
Min Period        n/a     FDRE/C       n/a            1.000     33.333  32.333  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[11]_MDM_Core_I1_Config_Reg_reg_c_56/C                                                                                                                      
Min Period        n/a     FDPE/C       n/a            1.000     33.333  32.333  SLICE_X72Y133  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[1]/C                                                                                                                                                       
Min Period        n/a     FDPE/C       n/a            1.000     33.333  32.333  SLICE_X73Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[25]/C                                                                                                                                                      
Min Period        n/a     FDCE/C       n/a            1.000     33.333  32.333  SLICE_X73Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[26]/C                                                                                                                                                      
Min Period        n/a     FDRE/C       n/a            1.000     33.333  32.333  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[27]_MDM_Core_I1_Config_Reg_reg_c_45/C                                                                                                                      
Min Period        n/a     FDPE/C       n/a            1.000     33.333  32.333  SLICE_X72Y134  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[2]/C                                                                                                                                                       
Min Period        n/a     FDPE/C       n/a            1.000     33.333  32.333  SLICE_X73Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[30]/C                                                                                                                                                      
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X84Y129  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/SRL16E_1/Use_unisim.MB_SRL16E_I1/CLK                                                                 
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X84Y129  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/SRL16E_4/Use_unisim.MB_SRL16E_I1/CLK                                                                 
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X84Y129  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/SRL16E_7/Use_unisim.MB_SRL16E_I1/CLK                                                                 
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X84Y129  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/SRL16E_8/Use_unisim.MB_SRL16E_I1/CLK                                                                 
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X98Y133  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].address_hit_I/Compare[0].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK  
Low Pulse Width   Fast    SRLC16E/CLK  n/a            0.854     16.666  15.812  SLICE_X98Y133  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].address_hit_I/Compare[1].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK  
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[12]_srl13_MDM_Core_I1_Config_Reg_reg_c_55/CLK                                                                                                              
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[28]_srl2_MDM_Core_I1_Config_Reg_reg_c_44/CLK                                                                                                               
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[5]_srl4_MDM_Core_I1_Config_Reg_reg_c_46/CLK                                                                                                                
Low Pulse Width   Fast    SRL16E/CLK   n/a            0.854     16.666  15.812  SLICE_X80Y131  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_1/CLK                                                                                                                             
High Pulse Width  Slow    SRLC16E/CLK  n/a            0.854     16.666  15.812  SLICE_X96Y137  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].address_hit_I/Compare[6].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK  
High Pulse Width  Slow    SRLC16E/CLK  n/a            0.854     16.666  15.812  SLICE_X96Y138  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].address_hit_I/Compare[7].SRLC16E_I/Use_unisim.MB_SRL16CE_I1/CLK  
High Pulse Width  Slow    SRL16E/CLK   n/a            0.854     16.667  15.813  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[12]_srl13_MDM_Core_I1_Config_Reg_reg_c_55/CLK                                                                                                              
High Pulse Width  Fast    SRL16E/CLK   n/a            0.854     16.667  15.813  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[12]_srl13_MDM_Core_I1_Config_Reg_reg_c_55/CLK                                                                                                              
High Pulse Width  Slow    SRL16E/CLK   n/a            0.854     16.667  15.813  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[28]_srl2_MDM_Core_I1_Config_Reg_reg_c_44/CLK                                                                                                               
High Pulse Width  Fast    SRL16E/CLK   n/a            0.854     16.667  15.813  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[28]_srl2_MDM_Core_I1_Config_Reg_reg_c_44/CLK                                                                                                               
High Pulse Width  Slow    SRL16E/CLK   n/a            0.854     16.667  15.813  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[5]_srl4_MDM_Core_I1_Config_Reg_reg_c_46/CLK                                                                                                                
High Pulse Width  Fast    SRL16E/CLK   n/a            0.854     16.667  15.813  SLICE_X72Y132  mbsys_i/mdm_1/U0/MDM_Core_I1/Config_Reg_reg[5]_srl4_MDM_Core_I1_Config_Reg_reg_c_46/CLK                                                                                                                
High Pulse Width  Slow    SRL16E/CLK   n/a            0.854     16.667  15.813  SLICE_X80Y131  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_1/CLK                                                                                                                             
High Pulse Width  Fast    SRL16E/CLK   n/a            0.854     16.667  15.813  SLICE_X80Y131  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_Config_SRL16E.SRL16E_1/CLK                                                                                                                             



---------------------------------------------------------------------------------------------------
From Clock:  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  To Clock:  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE

Setup :            0  Failing Endpoints,  Worst Slack       11.724ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.320ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       16.167ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.724ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/single_Step_TClk_reg/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        4.665ns  (logic 0.883ns (18.929%)  route 3.782ns (81.071%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.074ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.228ns = ( 36.561 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.325    22.960    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.235 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_1/O
                         net (fo=9, routed)           1.701    24.935    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X101Y120       FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/single_Step_TClk_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.293    36.561    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X101Y120                                                    r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/single_Step_TClk_reg/C
                         clock pessimism              0.302    36.863    
                         clock uncertainty           -0.035    36.828    
    SLICE_X101Y120       FDCE (Setup_fdce_C_CE)      -0.168    36.660    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/single_Step_TClk_reg
  -------------------------------------------------------------------
                         required time                         36.660    
                         arrival time                         -24.935    
  -------------------------------------------------------------------
                         slack                                 11.724    

Slack (MET) :             11.854ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        4.568ns  (logic 0.883ns (19.329%)  route 3.685ns (80.671%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.073ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.229ns = ( 36.562 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.325    22.960    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.235 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_1/O
                         net (fo=9, routed)           1.604    24.839    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X102Y121       FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.294    36.562    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X102Y121                                                    r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[0]/C
                         clock pessimism              0.302    36.864    
                         clock uncertainty           -0.035    36.829    
    SLICE_X102Y121       FDCE (Setup_fdce_C_CE)      -0.136    36.693    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         36.693    
                         arrival time                         -24.839    
  -------------------------------------------------------------------
                         slack                                 11.854    

Slack (MET) :             11.987ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_reg/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        4.432ns  (logic 0.883ns (19.924%)  route 3.549ns (80.076%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.076ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.226ns = ( 36.559 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.325    22.960    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.235 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_1/O
                         net (fo=9, routed)           1.468    24.703    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X100Y122       FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.291    36.559    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X100Y122                                                    r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_reg/C
                         clock pessimism              0.302    36.861    
                         clock uncertainty           -0.035    36.826    
    SLICE_X100Y122       FDCE (Setup_fdce_C_CE)      -0.136    36.690    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_reg
  -------------------------------------------------------------------
                         required time                         36.690    
                         arrival time                         -24.703    
  -------------------------------------------------------------------
                         slack                                 11.987    

Slack (MET) :             12.007ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[4]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        4.410ns  (logic 0.883ns (20.024%)  route 3.527ns (79.976%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.224ns = ( 36.557 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.325    22.960    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.235 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_1/O
                         net (fo=9, routed)           1.446    24.680    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X98Y121        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.289    36.557    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X98Y121                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[4]/C
                         clock pessimism              0.302    36.859    
                         clock uncertainty           -0.035    36.824    
    SLICE_X98Y121        FDCE (Setup_fdce_C_CE)      -0.136    36.688    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[4]
  -------------------------------------------------------------------
                         required time                         36.688    
                         arrival time                         -24.680    
  -------------------------------------------------------------------
                         slack                                 12.007    

Slack (MET) :             12.007ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[5]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        4.410ns  (logic 0.883ns (20.024%)  route 3.527ns (79.976%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.078ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.224ns = ( 36.557 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.325    22.960    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.235 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_1/O
                         net (fo=9, routed)           1.446    24.680    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X98Y121        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.289    36.557    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X98Y121                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[5]/C
                         clock pessimism              0.302    36.859    
                         clock uncertainty           -0.035    36.824    
    SLICE_X98Y121        FDCE (Setup_fdce_C_CE)      -0.136    36.688    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[5]
  -------------------------------------------------------------------
                         required time                         36.688    
                         arrival time                         -24.680    
  -------------------------------------------------------------------
                         slack                                 12.007    

Slack (MET) :             12.253ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[3]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        4.163ns  (logic 0.883ns (21.213%)  route 3.280ns (78.787%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.222ns = ( 36.555 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.325    22.960    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.235 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_1/O
                         net (fo=9, routed)           1.199    24.433    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X96Y123        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.287    36.555    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X96Y123                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[3]/C
                         clock pessimism              0.302    36.857    
                         clock uncertainty           -0.035    36.822    
    SLICE_X96Y123        FDCE (Setup_fdce_C_CE)      -0.136    36.686    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         36.686    
                         arrival time                         -24.433    
  -------------------------------------------------------------------
                         slack                                 12.253    

Slack (MET) :             12.293ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/normal_stop_TClk_reg/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        4.121ns  (logic 0.883ns (21.428%)  route 3.238ns (78.572%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.081ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.221ns = ( 36.554 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.325    22.960    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.235 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_1/O
                         net (fo=9, routed)           1.157    24.391    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X94Y121        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/normal_stop_TClk_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.286    36.554    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X94Y121                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/normal_stop_TClk_reg/C
                         clock pessimism              0.302    36.856    
                         clock uncertainty           -0.035    36.821    
    SLICE_X94Y121        FDCE (Setup_fdce_C_CE)      -0.136    36.685    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/normal_stop_TClk_reg
  -------------------------------------------------------------------
                         required time                         36.685    
                         arrival time                         -24.391    
  -------------------------------------------------------------------
                         slack                                 12.293    

Slack (MET) :             12.383ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        3.988ns  (logic 0.883ns (22.143%)  route 3.105ns (77.857%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.092ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.210ns = ( 36.543 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.667    23.302    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.577 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg[0]_i_1/O
                         net (fo=2, routed)           0.682    24.258    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Command_Reg_En
    SLICE_X89Y124        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.275    36.543    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X89Y124                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_reg[0]/C
                         clock pessimism              0.302    36.845    
                         clock uncertainty           -0.035    36.810    
    SLICE_X89Y124        FDCE (Setup_fdce_C_CE)      -0.168    36.642    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         36.642    
                         arrival time                         -24.258    
  -------------------------------------------------------------------
                         slack                                 12.383    

Slack (MET) :             12.383ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        3.988ns  (logic 0.883ns (22.143%)  route 3.105ns (77.857%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.092ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.210ns = ( 36.543 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.667    23.302    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.577 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg[0]_i_1/O
                         net (fo=2, routed)           0.682    24.258    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Command_Reg_En
    SLICE_X89Y124        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.275    36.543    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X89Y124                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_reg[1]/C
                         clock pessimism              0.302    36.845    
                         clock uncertainty           -0.035    36.810    
    SLICE_X89Y124        FDCE (Setup_fdce_C_CE)      -0.168    36.642    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         36.642    
                         arrival time                         -24.258    
  -------------------------------------------------------------------
                         slack                                 12.383    

Slack (MET) :             12.485ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[8]/CE
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        3.895ns  (logic 0.883ns (22.673%)  route 3.012ns (77.327%))
  Logic Levels:           3  (LUT3=1 LUT4=1 LUT5=1)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.218ns = ( 36.551 - 33.333 ) 
    Source Clock Delay      (SCD):    3.604ns = ( 20.271 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.302ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.373    20.271    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y129        FDCE (Prop_fdce_C_Q)         0.384    20.655 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/Q
                         net (fo=17, routed)          1.023    21.678    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[5]
    SLICE_X79Y129        LUT3 (Prop_lut3_I2_O)        0.105    21.783 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Dbg_Reg_En_0[5]_INST_0/O
                         net (fo=12, routed)          0.733    22.516    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Reg_En[5]
    SLICE_X81Y128        LUT4 (Prop_lut4_I3_O)        0.119    22.635 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_3/O
                         net (fo=2, routed)           0.325    22.960    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_TClk_i_3
    SLICE_X81Y127        LUT5 (Prop_lut5_I0_O)        0.275    23.235 r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/continue_from_brk_TClk_i_1/O
                         net (fo=9, routed)           0.930    24.165    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En
    SLICE_X95Y124        FDCE                                         r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.283    36.551    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Dbg_Update
    SLICE_X95Y124                                                     r  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[8]/C
                         clock pessimism              0.302    36.853    
                         clock uncertainty           -0.035    36.818    
    SLICE_X95Y124        FDCE (Setup_fdce_C_CE)      -0.168    36.650    mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[8]
  -------------------------------------------------------------------
                         required time                         36.650    
                         arrival time                         -24.165    
  -------------------------------------------------------------------
                         slack                                 12.485    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.320ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@0.000ns)
  Data Path Delay:        0.441ns  (logic 0.209ns (47.380%)  route 0.232ns (52.620%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.125ns
    Source Clock Delay      (SCD):    1.698ns
    Clock Pessimism Removal (CPR):    0.427ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114     1.114    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026     1.140 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.558     1.698    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X80Y130                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y130        FDCE (Prop_fdce_C_Q)         0.164     1.862 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/Q
                         net (fo=2, routed)           0.232     2.094    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tx_buffered
    SLICE_X80Y130        LUT6 (Prop_lut6_I5_O)        0.045     2.139 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_i_1/O
                         net (fo=1, routed)           0.000     2.139    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Use_UART.tx_buffered_i_1
    SLICE_X80Y130        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269     1.269    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029     1.298 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.827     2.125    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X80Y130                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/C
                         clock pessimism             -0.427     1.698    
    SLICE_X80Y130        FDCE (Hold_fdce_C_D)         0.121     1.819    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg
  -------------------------------------------------------------------
                         required time                         -1.819    
                         arrival time                           2.139    
  -------------------------------------------------------------------
                         slack                                  0.320    

Slack (MET) :             0.320ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@0.000ns)
  Data Path Delay:        0.441ns  (logic 0.209ns (47.380%)  route 0.232ns (52.620%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.125ns
    Source Clock Delay      (SCD):    1.698ns
    Clock Pessimism Removal (CPR):    0.427ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114     1.114    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026     1.140 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.558     1.698    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X80Y130                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y130        FDCE (Prop_fdce_C_Q)         0.164     1.862 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/Q
                         net (fo=2, routed)           0.232     2.094    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl
    SLICE_X80Y130        LUT3 (Prop_lut3_I2_O)        0.045     2.139 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl[0]_i_1/O
                         net (fo=1, routed)           0.000     2.139    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_completion_ctrl[0]_i_1
    SLICE_X80Y130        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269     1.269    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029     1.298 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.827     2.125    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X80Y130                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C
                         clock pessimism             -0.427     1.698    
    SLICE_X80Y130        FDCE (Hold_fdce_C_D)         0.121     1.819    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.819    
                         arrival time                           2.139    
  -------------------------------------------------------------------
                         slack                                  0.320    

Slack (MET) :             0.508ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/D
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.585ns  (logic 0.191ns (32.634%)  route 0.394ns (67.365%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.126ns = ( 18.792 - 16.667 ) 
    Source Clock Delay      (SCD):    1.699ns = ( 18.365 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.427ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.559    18.365    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y131        FDCE (Prop_fdce_C_Q)         0.146    18.511 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/Q
                         net (fo=19, routed)          0.271    18.782    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd_noblock
    SLICE_X78Y129        LUT1 (Prop_lut1_I0_O)        0.045    18.827 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I_i_1/O
                         net (fo=2, routed)           0.123    18.951    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/D
    SLICE_X79Y131        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/D
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.828    18.792    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C  (IS_INVERTED)
                         clock pessimism             -0.427    18.365    
    SLICE_X79Y131        FDCE (Hold_fdce_C_D)         0.077    18.442    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I
  -------------------------------------------------------------------
                         required time                        -18.442    
                         arrival time                          18.951    
  -------------------------------------------------------------------
                         slack                                  0.508    

Slack (MET) :             0.666ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[0]/CE
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.660ns  (logic 0.191ns (28.924%)  route 0.469ns (71.076%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.124ns = ( 18.790 - 16.667 ) 
    Source Clock Delay      (SCD):    1.706ns = ( 18.372 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.392ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.566    18.372    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.146    18.518 f  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/Q
                         net (fo=8, routed)           0.266    18.785    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[1]
    SLICE_X78Y131        LUT5 (Prop_lut5_I2_O)        0.045    18.830 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[0]_i_1/O
                         net (fo=8, routed)           0.203    19.033    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1
    SLICE_X79Y129        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.826    18.790    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[0]/C  (IS_INVERTED)
                         clock pessimism             -0.392    18.398    
    SLICE_X79Y129        FDCE (Hold_fdce_C_CE)       -0.032    18.366    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[0]
  -------------------------------------------------------------------
                         required time                        -18.366    
                         arrival time                          19.033    
  -------------------------------------------------------------------
                         slack                                  0.666    

Slack (MET) :             0.666ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[1]/CE
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.660ns  (logic 0.191ns (28.924%)  route 0.469ns (71.076%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.124ns = ( 18.790 - 16.667 ) 
    Source Clock Delay      (SCD):    1.706ns = ( 18.372 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.392ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.566    18.372    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.146    18.518 f  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/Q
                         net (fo=8, routed)           0.266    18.785    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[1]
    SLICE_X78Y131        LUT5 (Prop_lut5_I2_O)        0.045    18.830 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[0]_i_1/O
                         net (fo=8, routed)           0.203    19.033    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1
    SLICE_X79Y129        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.826    18.790    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[1]/C  (IS_INVERTED)
                         clock pessimism             -0.392    18.398    
    SLICE_X79Y129        FDCE (Hold_fdce_C_CE)       -0.032    18.366    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[1]
  -------------------------------------------------------------------
                         required time                        -18.366    
                         arrival time                          19.033    
  -------------------------------------------------------------------
                         slack                                  0.666    

Slack (MET) :             0.666ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[3]/CE
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.660ns  (logic 0.191ns (28.924%)  route 0.469ns (71.076%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.124ns = ( 18.790 - 16.667 ) 
    Source Clock Delay      (SCD):    1.706ns = ( 18.372 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.392ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.566    18.372    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.146    18.518 f  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/Q
                         net (fo=8, routed)           0.266    18.785    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[1]
    SLICE_X78Y131        LUT5 (Prop_lut5_I2_O)        0.045    18.830 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[0]_i_1/O
                         net (fo=8, routed)           0.203    19.033    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1
    SLICE_X79Y129        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.826    18.790    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[3]/C  (IS_INVERTED)
                         clock pessimism             -0.392    18.398    
    SLICE_X79Y129        FDCE (Hold_fdce_C_CE)       -0.032    18.366    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[3]
  -------------------------------------------------------------------
                         required time                        -18.366    
                         arrival time                          19.033    
  -------------------------------------------------------------------
                         slack                                  0.666    

Slack (MET) :             0.762ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[2]/CE
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.756ns  (logic 0.191ns (25.255%)  route 0.565ns (74.745%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.124ns = ( 18.790 - 16.667 ) 
    Source Clock Delay      (SCD):    1.706ns = ( 18.372 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.392ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.566    18.372    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.146    18.518 f  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/Q
                         net (fo=8, routed)           0.266    18.785    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[1]
    SLICE_X78Y131        LUT5 (Prop_lut5_I2_O)        0.045    18.830 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[0]_i_1/O
                         net (fo=8, routed)           0.299    19.129    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1
    SLICE_X81Y129        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.826    18.790    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[2]/C  (IS_INVERTED)
                         clock pessimism             -0.392    18.398    
    SLICE_X81Y129        FDCE (Hold_fdce_C_CE)       -0.032    18.366    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[2]
  -------------------------------------------------------------------
                         required time                        -18.366    
                         arrival time                          19.129    
  -------------------------------------------------------------------
                         slack                                  0.762    

Slack (MET) :             0.762ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[4]/CE
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.756ns  (logic 0.191ns (25.255%)  route 0.565ns (74.745%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.124ns = ( 18.790 - 16.667 ) 
    Source Clock Delay      (SCD):    1.706ns = ( 18.372 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.392ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.566    18.372    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.146    18.518 f  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/Q
                         net (fo=8, routed)           0.266    18.785    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[1]
    SLICE_X78Y131        LUT5 (Prop_lut5_I2_O)        0.045    18.830 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[0]_i_1/O
                         net (fo=8, routed)           0.299    19.129    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1
    SLICE_X81Y129        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.826    18.790    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[4]/C  (IS_INVERTED)
                         clock pessimism             -0.392    18.398    
    SLICE_X81Y129        FDCE (Hold_fdce_C_CE)       -0.032    18.366    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[4]
  -------------------------------------------------------------------
                         required time                        -18.366    
                         arrival time                          19.129    
  -------------------------------------------------------------------
                         slack                                  0.762    

Slack (MET) :             0.762ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/CE
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.756ns  (logic 0.191ns (25.255%)  route 0.565ns (74.745%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.124ns = ( 18.790 - 16.667 ) 
    Source Clock Delay      (SCD):    1.706ns = ( 18.372 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.392ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.566    18.372    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.146    18.518 f  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/Q
                         net (fo=8, routed)           0.266    18.785    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[1]
    SLICE_X78Y131        LUT5 (Prop_lut5_I2_O)        0.045    18.830 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[0]_i_1/O
                         net (fo=8, routed)           0.299    19.129    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1
    SLICE_X81Y129        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.826    18.790    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]/C  (IS_INVERTED)
                         clock pessimism             -0.392    18.398    
    SLICE_X81Y129        FDCE (Hold_fdce_C_CE)       -0.032    18.366    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[5]
  -------------------------------------------------------------------
                         required time                        -18.366    
                         arrival time                          19.129    
  -------------------------------------------------------------------
                         slack                                  0.762    

Slack (MET) :             0.762ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[6]/CE
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.756ns  (logic 0.191ns (25.255%)  route 0.565ns (74.745%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.124ns = ( 18.790 - 16.667 ) 
    Source Clock Delay      (SCD):    1.706ns = ( 18.372 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.392ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.566    18.372    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.146    18.518 f  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/Q
                         net (fo=8, routed)           0.266    18.785    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[1]
    SLICE_X78Y131        LUT5 (Prop_lut5_I2_O)        0.045    18.830 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command[0]_i_1/O
                         net (fo=8, routed)           0.299    19.129    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1
    SLICE_X81Y129        FDCE                                         r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.826    18.790    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X81Y129                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[6]/C  (IS_INVERTED)
                         clock pessimism             -0.392    18.398    
    SLICE_X81Y129        FDCE (Hold_fdce_C_CE)       -0.032    18.366    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_reg[6]
  -------------------------------------------------------------------
                         required time                        -18.366    
                         arrival time                          19.129    
  -------------------------------------------------------------------
                         slack                                  0.762    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
Waveform:           { 0 16.6665 }
Period:             33.333
Sources:            { mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE }

Check Type        Corner  Lib Pin  Reference Pin  Required  Actual  Slack   Location        Pin                                                                                                                       
Min Period        n/a     BUFG/I   n/a            1.592     33.333  31.741  BUFGCTRL_X0Y3   mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/I                                                                                 
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X77Y132   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Debug_Rst_i_reg/C                                                             
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X77Y132   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Debug_SYS_Rst_i_reg/C                                                         
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X79Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C                                                                       
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X78Y128   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg/C                                                        
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X80Y130   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/C                                                    
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X80Y129   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[0]/C                                                            
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X80Y129   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[1]/C                                                            
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X80Y129   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[2]/C                                                            
Min Period        n/a     FDCE/C   n/a            1.000     33.333  32.333  SLICE_X80Y129   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[3]/C                                                            
Low Pulse Width   Slow    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X80Y130   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/C                                                    
Low Pulse Width   Slow    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X80Y130   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg[0]/C                                                      
Low Pulse Width   Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X76Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_1_reg[0]/C                                                                     
Low Pulse Width   Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X76Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_1_reg[1]/C                                                                     
Low Pulse Width   Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X76Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_1_reg[2]/C                                                                     
Low Pulse Width   Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X76Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_1_reg[3]/C                                                                     
Low Pulse Width   Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X102Y121  mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/control_reg_reg[0]/C    
Low Pulse Width   Slow    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X93Y122   mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/force_stop_TClk_reg/C   
Low Pulse Width   Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X93Y122   mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/force_stop_TClk_reg/C   
Low Pulse Width   Slow    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X94Y121   mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/normal_stop_TClk_reg/C  
High Pulse Width  Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X77Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[0]/C                                                                       
High Pulse Width  Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X77Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C                                                                       
High Pulse Width  Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X77Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[2]/C                                                                       
High Pulse Width  Fast    FDCE/C   n/a            0.500     16.666  16.166  SLICE_X77Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[3]/C                                                                       
High Pulse Width  Slow    FDCE/C   n/a            0.500     16.667  16.167  SLICE_X79Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C                                                                       
High Pulse Width  Fast    FDCE/C   n/a            0.500     16.667  16.167  SLICE_X79Y131   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C                                                                       
High Pulse Width  Slow    FDCE/C   n/a            0.500     16.667  16.167  SLICE_X78Y128   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg/C                                                        
High Pulse Width  Slow    FDCE/C   n/a            0.500     16.667  16.167  SLICE_X80Y130   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.tx_buffered_reg/C                                                    
High Pulse Width  Slow    FDCE/C   n/a            0.500     16.667  16.167  SLICE_X80Y129   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[0]/C                                                            
High Pulse Width  Slow    FDCE/C   n/a            0.500     16.667  16.167  SLICE_X80Y129   mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_1_reg[1]/C                                                            



---------------------------------------------------------------------------------------------------
From Clock:  U0/core_clocking_i/clkout0
  To Clock:  clk_out1_mbsys_clk_wiz_1_0

Setup :            0  Failing Endpoints,  Worst Slack        3.759ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.759ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.273ns  (logic 0.538ns (23.673%)  route 1.735ns (76.327%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.735     2.168    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X85Y175        LUT6 (Prop_lut6_I4_O)        0.105     2.273 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[1]_i_1__0/O
                         net (fo=1, routed)           0.000     2.273    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[1]_i_1__0
    SLICE_X85Y175        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X85Y175        FDRE (Setup_fdre_C_D)        0.032     6.032    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[1]
  -------------------------------------------------------------------
                         required time                          6.032    
                         arrival time                          -2.273    
  -------------------------------------------------------------------
                         slack                                  3.759    

Slack (MET) :             3.772ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.258ns  (logic 0.538ns (23.829%)  route 1.720ns (76.171%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.720     2.153    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X85Y174        LUT6 (Prop_lut6_I4_O)        0.105     2.258 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[0]_i_1__1/O
                         net (fo=1, routed)           0.000     2.258    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[0]_i_1__1
    SLICE_X85Y174        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X85Y174        FDRE (Setup_fdre_C_D)        0.030     6.030    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[0]
  -------------------------------------------------------------------
                         required time                          6.030    
                         arrival time                          -2.258    
  -------------------------------------------------------------------
                         slack                                  3.772    

Slack (MET) :             3.868ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.162ns  (logic 0.538ns (24.882%)  route 1.624ns (75.118%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.624     2.057    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X85Y175        LUT6 (Prop_lut6_I4_O)        0.105     2.162 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[15]_i_1__1/O
                         net (fo=1, routed)           0.000     2.162    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[15]_i_1__1
    SLICE_X85Y175        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X85Y175        FDRE (Setup_fdre_C_D)        0.030     6.030    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[15]
  -------------------------------------------------------------------
                         required time                          6.030    
                         arrival time                          -2.162    
  -------------------------------------------------------------------
                         slack                                  3.868    

Slack (MET) :             3.909ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.121ns  (logic 0.538ns (25.360%)  route 1.583ns (74.640%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.583     2.016    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X83Y172        LUT6 (Prop_lut6_I4_O)        0.105     2.121 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[14]_i_1__0/O
                         net (fo=1, routed)           0.000     2.121    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[14]_i_1__0
    SLICE_X83Y172        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X83Y172        FDRE (Setup_fdre_C_D)        0.030     6.030    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[14]
  -------------------------------------------------------------------
                         required time                          6.030    
                         arrival time                          -2.121    
  -------------------------------------------------------------------
                         slack                                  3.909    

Slack (MET) :             3.911ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.121ns  (logic 0.538ns (25.360%)  route 1.583ns (74.640%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.583     2.016    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X83Y172        LUT6 (Prop_lut6_I4_O)        0.105     2.121 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[6]_i_1__0/O
                         net (fo=1, routed)           0.000     2.121    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[6]_i_1__0
    SLICE_X83Y172        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X83Y172        FDRE (Setup_fdre_C_D)        0.032     6.032    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[6]
  -------------------------------------------------------------------
                         required time                          6.032    
                         arrival time                          -2.121    
  -------------------------------------------------------------------
                         slack                                  3.911    

Slack (MET) :             3.971ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.061ns  (logic 0.538ns (26.107%)  route 1.523ns (73.893%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.523     1.956    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X85Y174        LUT6 (Prop_lut6_I4_O)        0.105     2.061 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[16]_i_1__1/O
                         net (fo=1, routed)           0.000     2.061    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[16]_i_1__1
    SLICE_X85Y174        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X85Y174        FDRE (Setup_fdre_C_D)        0.032     6.032    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[16]
  -------------------------------------------------------------------
                         required time                          6.032    
                         arrival time                          -2.061    
  -------------------------------------------------------------------
                         slack                                  3.971    

Slack (MET) :             3.987ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.046ns  (logic 0.538ns (26.300%)  route 1.508ns (73.700%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.508     1.941    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X85Y175        LUT6 (Prop_lut6_I4_O)        0.105     2.046 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[30]_i_1__1/O
                         net (fo=1, routed)           0.000     2.046    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[30]_i_1__1
    SLICE_X85Y175        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X85Y175        FDRE (Setup_fdre_C_D)        0.033     6.033    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[30]
  -------------------------------------------------------------------
                         required time                          6.033    
                         arrival time                          -2.046    
  -------------------------------------------------------------------
                         slack                                  3.987    

Slack (MET) :             3.990ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.042ns  (logic 0.538ns (26.351%)  route 1.504ns (73.649%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.504     1.937    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X85Y175        LUT6 (Prop_lut6_I4_O)        0.105     2.042 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[23]_i_1__1/O
                         net (fo=1, routed)           0.000     2.042    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[23]_i_1__1
    SLICE_X85Y175        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X85Y175        FDRE (Setup_fdre_C_D)        0.032     6.032    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[23]
  -------------------------------------------------------------------
                         required time                          6.032    
                         arrival time                          -2.042    
  -------------------------------------------------------------------
                         slack                                  3.990    

Slack (MET) :             4.025ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        2.005ns  (logic 0.538ns (26.829%)  route 1.467ns (73.171%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.467     1.900    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X82Y173        LUT6 (Prop_lut6_I4_O)        0.105     2.005 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[11]_i_1__0/O
                         net (fo=1, routed)           0.000     2.005    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[11]_i_1__0
    SLICE_X82Y173        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X82Y173        FDRE (Setup_fdre_C_D)        0.030     6.030    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[11]
  -------------------------------------------------------------------
                         required time                          6.030    
                         arrival time                          -2.005    
  -------------------------------------------------------------------
                         slack                                  4.025    

Slack (MET) :             4.035ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Path Group:             clk_out1_mbsys_clk_wiz_1_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        1.997ns  (logic 0.538ns (26.934%)  route 1.459ns (73.066%))
  Logic Levels:           1  (LUT6=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y181                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/C
    SLICE_X80Y181        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[71]/Q
                         net (fo=32, routed)          1.459     1.892    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref[71]
    SLICE_X82Y173        LUT6 (Prop_lut6_I4_O)        0.105     1.997 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ip2bus_data[13]_i_1__1/O
                         net (fo=1, routed)           0.000     1.997    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[13]_i_1__1
    SLICE_X82Y173        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X82Y173        FDRE (Setup_fdre_C_D)        0.032     6.032    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/ip2bus_data_reg[13]
  -------------------------------------------------------------------
                         required time                          6.032    
                         arrival time                          -1.997    
  -------------------------------------------------------------------
                         slack                                  4.035    





---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
  To Clock:  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK

Setup :            0  Failing Endpoints,  Worst Slack       57.744ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack       30.047ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             57.744ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[10]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.490ns  (logic 0.484ns (32.490%)  route 1.006ns (67.510%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.563ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.696ns = ( 33.696 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.406     5.044    dbg_hub/inst/bscan_inst/iDATA_CMD
    SLICE_X21Y136        LUT2 (Prop_lut2_I1_O)        0.105     5.149 r  dbg_hub/inst/bscan_inst/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.600     5.748    dbg_hub/inst/U_ICON/U_CMD/I4[0]
    SLICE_X17Y136        FDCE                                         r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[10]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.386    63.696    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X17Y136                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[10]/C
                         clock pessimism              0.000    63.696    
                         clock uncertainty           -0.035    63.660    
    SLICE_X17Y136        FDCE (Setup_fdce_C_CE)      -0.168    63.492    dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[10]
  -------------------------------------------------------------------
                         required time                         63.492    
                         arrival time                          -5.748    
  -------------------------------------------------------------------
                         slack                                 57.744    

Slack (MET) :             57.744ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[8]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.490ns  (logic 0.484ns (32.490%)  route 1.006ns (67.510%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.563ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.696ns = ( 33.696 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.406     5.044    dbg_hub/inst/bscan_inst/iDATA_CMD
    SLICE_X21Y136        LUT2 (Prop_lut2_I1_O)        0.105     5.149 r  dbg_hub/inst/bscan_inst/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.600     5.748    dbg_hub/inst/U_ICON/U_CMD/I4[0]
    SLICE_X17Y136        FDCE                                         r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.386    63.696    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X17Y136                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[8]/C
                         clock pessimism              0.000    63.696    
                         clock uncertainty           -0.035    63.660    
    SLICE_X17Y136        FDCE (Setup_fdce_C_CE)      -0.168    63.492    dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[8]
  -------------------------------------------------------------------
                         required time                         63.492    
                         arrival time                          -5.748    
  -------------------------------------------------------------------
                         slack                                 57.744    

Slack (MET) :             57.744ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[9]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.490ns  (logic 0.484ns (32.490%)  route 1.006ns (67.510%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.563ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.696ns = ( 33.696 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.406     5.044    dbg_hub/inst/bscan_inst/iDATA_CMD
    SLICE_X21Y136        LUT2 (Prop_lut2_I1_O)        0.105     5.149 r  dbg_hub/inst/bscan_inst/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.600     5.748    dbg_hub/inst/U_ICON/U_CMD/I4[0]
    SLICE_X17Y136        FDCE                                         r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[9]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.386    63.696    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X17Y136                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[9]/C
                         clock pessimism              0.000    63.696    
                         clock uncertainty           -0.035    63.660    
    SLICE_X17Y136        FDCE (Setup_fdce_C_CE)      -0.168    63.492    dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[9]
  -------------------------------------------------------------------
                         required time                         63.492    
                         arrival time                          -5.748    
  -------------------------------------------------------------------
                         slack                                 57.744    

Slack (MET) :             57.778ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.488ns  (logic 0.484ns (32.532%)  route 1.004ns (67.468%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.563ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.696ns = ( 33.696 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.406     5.044    dbg_hub/inst/bscan_inst/iDATA_CMD
    SLICE_X21Y136        LUT2 (Prop_lut2_I1_O)        0.105     5.149 r  dbg_hub/inst/bscan_inst/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.598     5.746    dbg_hub/inst/U_ICON/U_CMD/I4[0]
    SLICE_X18Y136        FDCE                                         r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.386    63.696    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X18Y136                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              0.000    63.696    
                         clock uncertainty           -0.035    63.660    
    SLICE_X18Y136        FDCE (Setup_fdce_C_CE)      -0.136    63.524    dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         63.524    
                         arrival time                          -5.746    
  -------------------------------------------------------------------
                         slack                                 57.778    

Slack (MET) :             57.789ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/SYNC_reg/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.187ns  (logic 0.484ns (40.766%)  route 0.703ns (59.234%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.565ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.694ns = ( 33.694 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.410     5.048    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.105     5.153 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.293     5.446    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X22Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/SYNC_reg/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.384    63.694    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X22Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/SYNC_reg/C
                         clock pessimism              0.000    63.694    
                         clock uncertainty           -0.035    63.658    
    SLICE_X22Y136        FDRE (Setup_fdre_C_R)       -0.423    63.235    dbg_hub/inst/U_ICON/U_SYNC/SYNC_reg
  -------------------------------------------------------------------
                         required time                         63.235    
                         arrival time                          -5.446    
  -------------------------------------------------------------------
                         slack                                 57.789    

Slack (MET) :             57.789ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.187ns  (logic 0.484ns (40.766%)  route 0.703ns (59.234%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.565ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.694ns = ( 33.694 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.410     5.048    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.105     5.153 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.293     5.446    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X22Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.384    63.694    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X22Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[0]/C
                         clock pessimism              0.000    63.694    
                         clock uncertainty           -0.035    63.658    
    SLICE_X22Y136        FDRE (Setup_fdre_C_R)       -0.423    63.235    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[0]
  -------------------------------------------------------------------
                         required time                         63.235    
                         arrival time                          -5.446    
  -------------------------------------------------------------------
                         slack                                 57.789    

Slack (MET) :             57.789ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.187ns  (logic 0.484ns (40.766%)  route 0.703ns (59.234%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.565ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.694ns = ( 33.694 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.410     5.048    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.105     5.153 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.293     5.446    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X22Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.384    63.694    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X22Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[1]/C
                         clock pessimism              0.000    63.694    
                         clock uncertainty           -0.035    63.658    
    SLICE_X22Y136        FDRE (Setup_fdre_C_R)       -0.423    63.235    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[1]
  -------------------------------------------------------------------
                         required time                         63.235    
                         arrival time                          -5.446    
  -------------------------------------------------------------------
                         slack                                 57.789    

Slack (MET) :             57.860ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.187ns  (logic 0.484ns (40.766%)  route 0.703ns (59.234%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.565ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.694ns = ( 33.694 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.410     5.048    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.105     5.153 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.293     5.446    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X23Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.384    63.694    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X23Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[2]/C
                         clock pessimism              0.000    63.694    
                         clock uncertainty           -0.035    63.658    
    SLICE_X23Y136        FDRE (Setup_fdre_C_R)       -0.352    63.306    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[2]
  -------------------------------------------------------------------
                         required time                         63.306    
                         arrival time                          -5.446    
  -------------------------------------------------------------------
                         slack                                 57.860    

Slack (MET) :             57.860ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.187ns  (logic 0.484ns (40.766%)  route 0.703ns (59.234%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.565ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.694ns = ( 33.694 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.410     5.048    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.105     5.153 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.293     5.446    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X23Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.384    63.694    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X23Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[3]/C
                         clock pessimism              0.000    63.694    
                         clock uncertainty           -0.035    63.658    
    SLICE_X23Y136        FDRE (Setup_fdre_C_R)       -0.352    63.306    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[3]
  -------------------------------------------------------------------
                         required time                         63.306    
                         arrival time                          -5.446    
  -------------------------------------------------------------------
                         slack                                 57.860    

Slack (MET) :             57.860ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            60.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@60.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@0.000ns)
  Data Path Delay:        1.187ns  (logic 0.484ns (40.766%)  route 0.703ns (59.234%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.565ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.694ns = ( 33.694 - 30.000 ) 
    Source Clock Delay      (SCD):    4.259ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           2.684     2.684    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.081     2.765 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           1.494     4.259    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.379     4.638 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.410     5.048    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.105     5.153 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.293     5.446    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X23Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    62.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    62.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.384    63.694    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X23Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[4]/C
                         clock pessimism              0.000    63.694    
                         clock uncertainty           -0.035    63.658    
    SLICE_X23Y136        FDRE (Setup_fdre_C_R)       -0.352    63.306    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[4]
  -------------------------------------------------------------------
                         required time                         63.306    
                         arrival time                          -5.446    
  -------------------------------------------------------------------
                         slack                                 57.860    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             30.047ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/SYNC_reg/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.490ns  (logic 0.186ns (37.939%)  route 0.304ns (62.061%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.168    62.400    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.045    62.445 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.136    62.582    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X22Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/SYNC_reg/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X22Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/SYNC_reg/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X22Y136        FDRE (Hold_fdre_C_R)         0.009    32.535    dbg_hub/inst/U_ICON/U_SYNC/SYNC_reg
  -------------------------------------------------------------------
                         required time                        -32.535    
                         arrival time                          62.582    
  -------------------------------------------------------------------
                         slack                                 30.047    

Slack (MET) :             30.047ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.490ns  (logic 0.186ns (37.939%)  route 0.304ns (62.061%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.168    62.400    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.045    62.445 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.136    62.582    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X22Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X22Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[0]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X22Y136        FDRE (Hold_fdre_C_R)         0.009    32.535    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[0]
  -------------------------------------------------------------------
                         required time                        -32.535    
                         arrival time                          62.582    
  -------------------------------------------------------------------
                         slack                                 30.047    

Slack (MET) :             30.047ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.490ns  (logic 0.186ns (37.939%)  route 0.304ns (62.061%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.168    62.400    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.045    62.445 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.136    62.582    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X22Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X22Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[1]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X22Y136        FDRE (Hold_fdre_C_R)         0.009    32.535    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[1]
  -------------------------------------------------------------------
                         required time                        -32.535    
                         arrival time                          62.582    
  -------------------------------------------------------------------
                         slack                                 30.047    

Slack (MET) :             30.066ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[12]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.461ns  (logic 0.186ns (40.361%)  route 0.275ns (59.639%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.166    62.398    dbg_hub/inst/bscan_inst/iDATA_CMD
    SLICE_X21Y136        LUT2 (Prop_lut2_I1_O)        0.045    62.443 r  dbg_hub/inst/bscan_inst/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.109    62.552    dbg_hub/inst/U_ICON/U_CMD/I4[0]
    SLICE_X21Y135        FDCE                                         r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[12]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[12]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X21Y135        FDCE (Hold_fdce_C_CE)       -0.039    32.487    dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[12]
  -------------------------------------------------------------------
                         required time                        -32.487    
                         arrival time                          62.552    
  -------------------------------------------------------------------
                         slack                                 30.066    

Slack (MET) :             30.066ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.461ns  (logic 0.186ns (40.361%)  route 0.275ns (59.639%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.166    62.398    dbg_hub/inst/bscan_inst/iDATA_CMD
    SLICE_X21Y136        LUT2 (Prop_lut2_I1_O)        0.045    62.443 r  dbg_hub/inst/bscan_inst/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.109    62.552    dbg_hub/inst/U_ICON/U_CMD/I4[0]
    SLICE_X21Y135        FDCE                                         r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X21Y135        FDCE (Hold_fdce_C_CE)       -0.039    32.487    dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                        -32.487    
                         arrival time                          62.552    
  -------------------------------------------------------------------
                         slack                                 30.066    

Slack (MET) :             30.066ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[14]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.461ns  (logic 0.186ns (40.361%)  route 0.275ns (59.639%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.166    62.398    dbg_hub/inst/bscan_inst/iDATA_CMD
    SLICE_X21Y136        LUT2 (Prop_lut2_I1_O)        0.045    62.443 r  dbg_hub/inst/bscan_inst/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.109    62.552    dbg_hub/inst/U_ICON/U_CMD/I4[0]
    SLICE_X21Y135        FDCE                                         r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[14]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[14]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X21Y135        FDCE (Hold_fdce_C_CE)       -0.039    32.487    dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[14]
  -------------------------------------------------------------------
                         required time                        -32.487    
                         arrival time                          62.552    
  -------------------------------------------------------------------
                         slack                                 30.066    

Slack (MET) :             30.066ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[15]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.461ns  (logic 0.186ns (40.361%)  route 0.275ns (59.639%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.166    62.398    dbg_hub/inst/bscan_inst/iDATA_CMD
    SLICE_X21Y136        LUT2 (Prop_lut2_I1_O)        0.045    62.443 r  dbg_hub/inst/bscan_inst/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.109    62.552    dbg_hub/inst/U_ICON/U_CMD/I4[0]
    SLICE_X21Y135        FDCE                                         r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[15]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[15]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X21Y135        FDCE (Hold_fdce_C_CE)       -0.039    32.487    dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[15]
  -------------------------------------------------------------------
                         required time                        -32.487    
                         arrival time                          62.552    
  -------------------------------------------------------------------
                         slack                                 30.066    

Slack (MET) :             30.074ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.490ns  (logic 0.186ns (37.939%)  route 0.304ns (62.061%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.168    62.400    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.045    62.445 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.136    62.582    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X23Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X23Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[2]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X23Y136        FDRE (Hold_fdre_C_R)        -0.018    32.508    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[2]
  -------------------------------------------------------------------
                         required time                        -32.508    
                         arrival time                          62.582    
  -------------------------------------------------------------------
                         slack                                 30.074    

Slack (MET) :             30.074ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.490ns  (logic 0.186ns (37.939%)  route 0.304ns (62.061%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.168    62.400    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.045    62.445 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.136    62.582    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X23Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X23Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[3]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X23Y136        FDRE (Hold_fdre_C_R)        -0.018    32.508    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[3]
  -------------------------------------------------------------------
                         required time                        -32.508    
                         arrival time                          62.582    
  -------------------------------------------------------------------
                         slack                                 30.074    

Slack (MET) :             30.074ns  (arrival time - required time)
  Source:                 dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE  {rise@0.000ns fall@30.000ns period=60.000ns})
  Destination:            dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            -30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise@60.000ns)
  Data Path Delay:        0.490ns  (logic 0.186ns (37.939%)  route 0.304ns (62.061%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.490ns
    Source Clock Delay      (SCD):    2.091ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Timing Exception:       MultiCycle Path   Setup -end   2    Hold  -start 1  

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE rise edge)
                                                     60.000    60.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    60.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/UPDATE
                         net (fo=1, routed)           1.446    61.446    dbg_hub/inst/UPDATE_temp
    BUFGCTRL_X0Y5        BUFG (Prop_bufg_I_O)         0.026    61.472 r  dbg_hub/inst/u_bufg_icon_update/O
                         net (fo=1, routed)           0.620    62.091    dbg_hub/inst/U_ICON/UPDATE
    SLICE_X21Y136                                                     r  dbg_hub/inst/U_ICON/iDATA_CMD_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y136        FDCE (Prop_fdce_C_Q)         0.141    62.232 f  dbg_hub/inst/U_ICON/iDATA_CMD_reg/Q
                         net (fo=2, routed)           0.168    62.400    dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD
    SLICE_X21Y136        LUT1 (Prop_lut1_I0_O)        0.045    62.445 r  dbg_hub/inst/U_ICON/U_SYNC/iDATA_CMD_i_1/O
                         net (fo=9, routed)           0.136    62.582    dbg_hub/inst/U_ICON/U_SYNC/SR[0]
    SLICE_X23Y136        FDRE                                         r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571    31.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    31.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.891    32.490    dbg_hub/inst/U_ICON/U_SYNC/CLK
    SLICE_X23Y136                                                     r  dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[4]/C
                         clock pessimism              0.000    32.490    
                         clock uncertainty            0.035    32.526    
    SLICE_X23Y136        FDRE (Hold_fdre_C_R)        -0.018    32.508    dbg_hub/inst/U_ICON/U_SYNC/iSYNC_WORD_reg[4]
  -------------------------------------------------------------------
                         required time                        -32.508    
                         arrival time                          62.582    
  -------------------------------------------------------------------
                         slack                                 30.074    





---------------------------------------------------------------------------------------------------
From Clock:  U0/core_clocking_i/clkout0
  To Clock:  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK

Setup :            0  Failing Endpoints,  Worst Slack        7.086ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.086ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[5].sync_rd_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
  Data Path Delay:        0.745ns  (logic 0.348ns (46.694%)  route 0.397ns (53.306%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 8.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y216                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[5]/C
    SLICE_X47Y216        FDRE (Prop_fdre_C_Q)         0.348     0.348 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[5]/Q
                         net (fo=1, routed)           0.397     0.745    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray[5]
    SLICE_X47Y217        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[5].sync_rd_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.000     8.000    
    SLICE_X47Y217        FDRE (Setup_fdre_C_D)       -0.169     7.831    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[5].sync_rd_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                          7.831    
                         arrival time                          -0.745    
  -------------------------------------------------------------------
                         slack                                  7.086    

Slack (MET) :             7.132ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[2].sync_rd_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
  Data Path Delay:        0.864ns  (logic 0.379ns (43.842%)  route 0.485ns (56.158%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 8.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y216                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[2]/C
    SLICE_X47Y216        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[2]/Q
                         net (fo=1, routed)           0.485     0.864    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray[2]
    SLICE_X48Y217        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[2].sync_rd_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.000     8.000    
    SLICE_X48Y217        FDRE (Setup_fdre_C_D)       -0.004     7.996    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[2].sync_rd_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                          7.996    
                         arrival time                          -0.864    
  -------------------------------------------------------------------
                         slack                                  7.132    

Slack (MET) :             7.173ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[0].sync_rd_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
  Data Path Delay:        0.795ns  (logic 0.379ns (47.677%)  route 0.416ns (52.323%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 8.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y215                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[0]/C
    SLICE_X50Y215        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[0]/Q
                         net (fo=1, routed)           0.416     0.795    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray[0]
    SLICE_X50Y217        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[0].sync_rd_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.000     8.000    
    SLICE_X50Y217        FDRE (Setup_fdre_C_D)       -0.032     7.968    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[0].sync_rd_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                          7.968    
                         arrival time                          -0.795    
  -------------------------------------------------------------------
                         slack                                  7.173    

Slack (MET) :             7.216ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[4].sync_rd_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
  Data Path Delay:        0.752ns  (logic 0.379ns (50.425%)  route 0.373ns (49.575%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 8.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y216                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[4]/C
    SLICE_X47Y216        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[4]/Q
                         net (fo=1, routed)           0.373     0.752    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray[4]
    SLICE_X49Y216        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[4].sync_rd_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.000     8.000    
    SLICE_X49Y216        FDRE (Setup_fdre_C_D)       -0.032     7.968    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[4].sync_rd_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                          7.968    
                         arrival time                          -0.752    
  -------------------------------------------------------------------
                         slack                                  7.216    

Slack (MET) :             7.223ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[1].sync_rd_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
  Data Path Delay:        0.608ns  (logic 0.348ns (57.263%)  route 0.260ns (42.737%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 8.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y215                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[1]/C
    SLICE_X50Y215        FDRE (Prop_fdre_C_Q)         0.348     0.348 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[1]/Q
                         net (fo=1, routed)           0.260     0.608    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray[1]
    SLICE_X50Y216        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[1].sync_rd_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.000     8.000    
    SLICE_X50Y216        FDRE (Setup_fdre_C_D)       -0.169     7.831    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[1].sync_rd_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                          7.831    
                         arrival time                          -0.608    
  -------------------------------------------------------------------
                         slack                                  7.223    

Slack (MET) :             7.227ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[3].sync_rd_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Path Group:             mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
  Data Path Delay:        0.607ns  (logic 0.348ns (57.360%)  route 0.259ns (42.640%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 8.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y216                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[3]/C
    SLICE_X47Y216        FDRE (Prop_fdre_C_Q)         0.348     0.348 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray_reg[3]/Q
                         net (fo=1, routed)           0.259     0.607    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_addr_gray[3]
    SLICE_X49Y217        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[3].sync_rd_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.000     8.000    
    SLICE_X49Y217        FDRE (Setup_fdre_C_D)       -0.166     7.834    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_rd_addrgray[3].sync_rd_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                          7.834    
                         arrival time                          -0.607    
  -------------------------------------------------------------------
                         slack                                  7.227    





---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_mbsys_clk_wiz_1_0
  To Clock:  U0/core_clocking_i/clkout0

Setup :            0  Failing Endpoints,  Worst Slack        1.572ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.572ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[35]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.386ns  (logic 0.484ns (11.036%)  route 3.902ns (88.964%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y165                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/C
    SLICE_X73Y165        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/Q
                         net (fo=90, routed)          3.505     3.884    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[28].RAM64X1D_inst/DPRA1
    SLICE_X84Y179        RAMD64E (Prop_ramd64e_RADR1_O)
                                                      0.105     3.989 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[28].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.397     4.386    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[28].RAM64X1D_inst
    SLICE_X83Y177        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[35]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X83Y177        FDRE (Setup_fdre_C_D)       -0.042     5.958    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[35]
  -------------------------------------------------------------------
                         required time                          5.958    
                         arrival time                          -4.386    
  -------------------------------------------------------------------
                         slack                                  1.572    

Slack (MET) :             1.725ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[36]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.236ns  (logic 0.484ns (11.427%)  route 3.752ns (88.573%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y165                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/C
    SLICE_X73Y165        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/Q
                         net (fo=90, routed)          3.366     3.745    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[29].RAM64X1D_inst/DPRA1
    SLICE_X84Y179        RAMD64E (Prop_ramd64e_RADR1_O)
                                                      0.105     3.850 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[29].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.385     4.236    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[29].RAM64X1D_inst
    SLICE_X83Y177        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[36]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X83Y177        FDRE (Setup_fdre_C_D)       -0.039     5.961    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[36]
  -------------------------------------------------------------------
                         required time                          5.961    
                         arrival time                          -4.236    
  -------------------------------------------------------------------
                         slack                                  1.725    

Slack (MET) :             1.788ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.180ns  (logic 0.484ns (11.580%)  route 3.696ns (88.420%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y164                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
    SLICE_X73Y164        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/Q
                         net (fo=99, routed)          3.209     3.588    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[1].RAM64X1D_inst/DPRA0
    SLICE_X88Y174        RAMD64E (Prop_ramd64e_RADR0_O)
                                                      0.105     3.693 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[1].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.486     4.180    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[1].RAM64X1D_inst
    SLICE_X87Y174        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X87Y174        FDRE (Setup_fdre_C_D)       -0.032     5.968    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[8]
  -------------------------------------------------------------------
                         required time                          5.968    
                         arrival time                          -4.180    
  -------------------------------------------------------------------
                         slack                                  1.788    

Slack (MET) :             1.814ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.111ns  (logic 0.484ns (11.773%)  route 3.627ns (88.227%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y164                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
    SLICE_X73Y164        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/Q
                         net (fo=99, routed)          3.313     3.692    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[19].RAM64X1D_inst/DPRA0
    SLICE_X88Y174        RAMD64E (Prop_ramd64e_RADR0_O)
                                                      0.105     3.797 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[19].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.314     4.111    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[19].RAM64X1D_inst
    SLICE_X87Y174        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X87Y174        FDRE (Setup_fdre_C_D)       -0.075     5.925    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[26]
  -------------------------------------------------------------------
                         required time                          5.925    
                         arrival time                          -4.111    
  -------------------------------------------------------------------
                         slack                                  1.814    

Slack (MET) :             1.845ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[37]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.113ns  (logic 0.484ns (11.766%)  route 3.629ns (88.234%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y164                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[6]/C
    SLICE_X71Y164        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[6]/Q
                         net (fo=90, routed)          3.264     3.643    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[30].RAM64X1D_inst/DPRA3
    SLICE_X84Y174        RAMD64E (Prop_ramd64e_RADR3_O)
                                                      0.105     3.748 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[30].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.365     4.113    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[30].RAM64X1D_inst
    SLICE_X87Y174        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[37]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X87Y174        FDRE (Setup_fdre_C_D)       -0.042     5.958    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[37]
  -------------------------------------------------------------------
                         required time                          5.958    
                         arrival time                          -4.113    
  -------------------------------------------------------------------
                         slack                                  1.845    

Slack (MET) :             1.847ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.094ns  (logic 0.484ns (11.821%)  route 3.610ns (88.179%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y165                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/C
    SLICE_X73Y165        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/Q
                         net (fo=90, routed)          3.227     3.606    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[24].RAM64X1D_inst/DPRA1
    SLICE_X84Y178        RAMD64E (Prop_ramd64e_RADR1_O)
                                                      0.105     3.711 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[24].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.384     4.094    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[24].RAM64X1D_inst
    SLICE_X83Y177        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X83Y177        FDRE (Setup_fdre_C_D)       -0.059     5.941    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[31]
  -------------------------------------------------------------------
                         required time                          5.941    
                         arrival time                          -4.094    
  -------------------------------------------------------------------
                         slack                                  1.847    

Slack (MET) :             1.890ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.066ns  (logic 0.484ns (11.904%)  route 3.582ns (88.096%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y164                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
    SLICE_X73Y164        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/Q
                         net (fo=99, routed)          3.166     3.545    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[2].RAM64X1D_inst/DPRA0
    SLICE_X84Y174        RAMD64E (Prop_ramd64e_RADR0_O)
                                                      0.105     3.650 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[2].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.415     4.066    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[2].RAM64X1D_inst
    SLICE_X87Y174        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X87Y174        FDRE (Setup_fdre_C_D)       -0.044     5.956    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[9]
  -------------------------------------------------------------------
                         required time                          5.956    
                         arrival time                          -4.066    
  -------------------------------------------------------------------
                         slack                                  1.890    

Slack (MET) :             1.895ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.058ns  (logic 0.484ns (11.926%)  route 3.574ns (88.074%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y164                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
    SLICE_X73Y164        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/Q
                         net (fo=99, routed)          2.952     3.331    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[26].RAM64X1D_inst/DPRA0
    SLICE_X88Y176        RAMD64E (Prop_ramd64e_RADR0_O)
                                                      0.105     3.436 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[26].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.622     4.058    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[26].RAM64X1D_inst
    SLICE_X87Y175        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X87Y175        FDRE (Setup_fdre_C_D)       -0.047     5.953    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[33]
  -------------------------------------------------------------------
                         required time                          5.953    
                         arrival time                          -4.058    
  -------------------------------------------------------------------
                         slack                                  1.895    

Slack (MET) :             1.928ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[69]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.040ns  (logic 0.484ns (11.980%)  route 3.556ns (88.020%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y165                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/C
    SLICE_X73Y165        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[4]/Q
                         net (fo=90, routed)          2.994     3.373    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[62].RAM64X1D_inst/DPRA1
    SLICE_X80Y180        RAMD64E (Prop_ramd64e_RADR1_O)
                                                      0.105     3.478 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[62].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.562     4.040    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[62].RAM64X1D_inst
    SLICE_X83Y177        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[69]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X83Y177        FDRE (Setup_fdre_C_D)       -0.032     5.968    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[69]
  -------------------------------------------------------------------
                         required time                          5.968    
                         arrival time                          -4.040    
  -------------------------------------------------------------------
                         slack                                  1.928    

Slack (MET) :             1.947ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0)
  Destination:            mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.000ns  (MaxDelay Path 6.000ns)
  Data Path Delay:        4.009ns  (logic 0.484ns (12.072%)  route 3.525ns (87.928%))
  Logic Levels:           1  (RAMD64E=1)
  Timing Exception:       MaxDelay Path 6.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y164                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/C
    SLICE_X73Y164        FDRE (Prop_fdre_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bus2ip_addr_reg_reg[3]/Q
                         net (fo=99, routed)          3.032     3.411    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[14].RAM64X1D_inst/DPRA0
    SLICE_X84Y173        RAMD64E (Prop_ramd64e_RADR0_O)
                                                      0.105     3.516 r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/gen_distributed_mem[14].RAM64X1D_inst/DP/O
                         net (fo=1, routed)           0.494     4.009    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/gen_distributed_mem[14].RAM64X1D_inst
    SLICE_X85Y173        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.000     6.000    
    SLICE_X85Y173        FDRE (Setup_fdre_C_D)       -0.044     5.956    mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rd_data_ref_reg[21]
  -------------------------------------------------------------------
                         required time                          5.956    
                         arrival time                          -4.009    
  -------------------------------------------------------------------
                         slack                                  1.947    





---------------------------------------------------------------------------------------------------
From Clock:  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK
  To Clock:  U0/core_clocking_i/clkout0

Setup :            0  Failing Endpoints,  Worst Slack       14.937ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             14.937ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[2].sync_wr_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (MaxDelay Path 16.000ns)
  Data Path Delay:        0.904ns  (logic 0.398ns (44.013%)  route 0.506ns (55.987%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 16.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y214                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[2]/C
    SLICE_X44Y214        FDRE (Prop_fdre_C_Q)         0.398     0.398 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[2]/Q
                         net (fo=1, routed)           0.506     0.904    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[2]
    SLICE_X43Y213        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[2].sync_wr_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                   16.000    16.000    
    SLICE_X43Y213        FDRE (Setup_fdre_C_D)       -0.159    15.841    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[2].sync_wr_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                         15.841    
                         arrival time                          -0.904    
  -------------------------------------------------------------------
                         slack                                 14.937    

Slack (MET) :             14.972ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[5]/C
                            (rising edge-triggered cell FDSE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[5].sync_wr_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (MaxDelay Path 16.000ns)
  Data Path Delay:        0.859ns  (logic 0.348ns (40.518%)  route 0.511ns (59.482%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 16.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y217                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[5]/C
    SLICE_X45Y217        FDSE (Prop_fdse_C_Q)         0.348     0.348 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[5]/Q
                         net (fo=1, routed)           0.511     0.859    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/data_in
    SLICE_X45Y218        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[5].sync_wr_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                   16.000    16.000    
    SLICE_X45Y218        FDRE (Setup_fdre_C_D)       -0.169    15.831    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[5].sync_wr_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                         15.831    
                         arrival time                          -0.859    
  -------------------------------------------------------------------
                         slack                                 14.972    

Slack (MET) :             15.142ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[1].sync_wr_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (MaxDelay Path 16.000ns)
  Data Path Delay:        0.826ns  (logic 0.433ns (52.432%)  route 0.393ns (47.568%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 16.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y214                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[1]/C
    SLICE_X44Y214        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[1]/Q
                         net (fo=1, routed)           0.393     0.826    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[1]
    SLICE_X43Y214        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[1].sync_wr_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                   16.000    16.000    
    SLICE_X43Y214        FDRE (Setup_fdre_C_D)       -0.032    15.968    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[1].sync_wr_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                         15.968    
                         arrival time                          -0.826    
  -------------------------------------------------------------------
                         slack                                 15.142    

Slack (MET) :             15.154ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[3].sync_wr_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (MaxDelay Path 16.000ns)
  Data Path Delay:        0.814ns  (logic 0.433ns (53.173%)  route 0.381ns (46.827%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 16.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y214                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[3]/C
    SLICE_X44Y214        FDRE (Prop_fdre_C_Q)         0.433     0.433 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[3]/Q
                         net (fo=1, routed)           0.381     0.814    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[3]
    SLICE_X43Y215        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[3].sync_wr_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                   16.000    16.000    
    SLICE_X43Y215        FDRE (Setup_fdre_C_D)       -0.032    15.968    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[3].sync_wr_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                         15.968    
                         arrival time                          -0.814    
  -------------------------------------------------------------------
                         slack                                 15.154    

Slack (MET) :             15.220ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[4].sync_wr_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (MaxDelay Path 16.000ns)
  Data Path Delay:        0.776ns  (logic 0.379ns (48.834%)  route 0.397ns (51.166%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 16.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y217                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[4]/C
    SLICE_X45Y217        FDSE (Prop_fdse_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[4]/Q
                         net (fo=1, routed)           0.397     0.776    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[4]
    SLICE_X44Y217        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[4].sync_wr_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                   16.000    16.000    
    SLICE_X44Y217        FDRE (Setup_fdre_C_D)       -0.004    15.996    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[4].sync_wr_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                         15.996    
                         arrival time                          -0.776    
  -------------------------------------------------------------------
                         slack                                 15.220    

Slack (MET) :             15.224ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[0]/C
                            (rising edge-triggered cell FDSE clocked by mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK)
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[0].sync_wr_addrgray/data_sync_reg1/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0)
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            16.000ns  (MaxDelay Path 16.000ns)
  Data Path Delay:        0.772ns  (logic 0.379ns (49.086%)  route 0.393ns (50.914%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 16.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y218                                     0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[0]/C
    SLICE_X43Y218        FDSE (Prop_fdse_C_Q)         0.379     0.379 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[0]/Q
                         net (fo=1, routed)           0.393     0.772    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_addr_gray_reg[0]
    SLICE_X44Y218        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[0].sync_wr_addrgray/data_sync_reg1/D
  -------------------------------------------------------------------    -------------------

                         max delay                   16.000    16.000    
    SLICE_X44Y218        FDRE (Setup_fdre_C_D)       -0.004    15.996    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reclock_wr_addrgray[0].sync_wr_addrgray/data_sync_reg1
  -------------------------------------------------------------------
                         required time                         15.996    
                         arrival time                          -0.772    
  -------------------------------------------------------------------
                         slack                                 15.224    





---------------------------------------------------------------------------------------------------
From Clock:  U0/core_clocking_i/clkout1
  To Clock:  U0/core_clocking_i/clkout0

Setup :            0  Failing Endpoints,  Worst Slack        5.867ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.153ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             5.867ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbufstatus_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbuferr_reg/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        1.673ns  (logic 0.379ns (22.655%)  route 1.294ns (77.345%))
  Logic Levels:           0  
  Clock Path Skew:        -0.209ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.200ns = ( 14.200 - 8.000 ) 
    Source Clock Delay      (SCD):    6.585ns
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.393     6.585    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X59Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbufstatus_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y197        FDRE (Prop_fdre_C_Q)         0.379     6.964 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbufstatus_reg_reg[1]/Q
                         net (fo=1, routed)           1.294     8.258    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/txbufstatus_reg_reg[1]
    SLICE_X57Y195        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbuferr_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.285    14.200    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X57Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbuferr_reg/C
                         clock pessimism              0.176    14.376    
                         clock uncertainty           -0.205    14.171    
    SLICE_X57Y195        FDRE (Setup_fdre_C_D)       -0.047    14.124    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbuferr_reg
  -------------------------------------------------------------------
                         required time                         14.124    
                         arrival time                          -8.258    
  -------------------------------------------------------------------
                         slack                                  5.867    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.153ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbufstatus_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbuferr_reg/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             U0/core_clocking_i/clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout1 rise@0.000ns)
  Data Path Delay:        0.773ns  (logic 0.141ns (18.242%)  route 0.632ns (81.758%))
  Logic Levels:           0  
  Clock Path Skew:        0.345ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.299ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X59Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbufstatus_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y197        FDRE (Prop_fdre_C_Q)         0.141     2.779 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbufstatus_reg_reg[1]/Q
                         net (fo=1, routed)           0.632     3.411    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/txbufstatus_reg_reg[1]
    SLICE_X57Y195        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbuferr_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.851     3.299    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X57Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbuferr_reg/C
                         clock pessimism             -0.316     2.983    
                         clock uncertainty            0.205     3.188    
    SLICE_X57Y195        FDRE (Hold_fdre_C_D)         0.070     3.258    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txbuferr_reg
  -------------------------------------------------------------------
                         required time                         -3.258    
                         arrival time                           3.411    
  -------------------------------------------------------------------
                         slack                                  0.153    





---------------------------------------------------------------------------------------------------
From Clock:  U0/core_clocking_i/clkout0
  To Clock:  U0/core_clocking_i/clkout1

Setup :            0  Failing Endpoints,  Worst Slack        5.594ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.154ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             5.594ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.946ns  (logic 0.379ns (19.477%)  route 1.567ns (80.523%))
  Logic Levels:           0  
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.198ns = ( 22.198 - 16.000 ) 
    Source Clock Delay      (SCD):    6.586ns = ( 14.586 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.394    14.586    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X57Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y198        FDRE (Prop_fdre_C_Q)         0.379    14.965 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[15]/Q
                         net (fo=1, routed)           1.567    16.532    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[15]
    SLICE_X58Y198        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.283    22.198    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[15]/C
                         clock pessimism              0.176    22.374    
                         clock uncertainty           -0.205    22.169    
    SLICE_X58Y198        FDRE (Setup_fdre_C_D)       -0.044    22.125    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[15]
  -------------------------------------------------------------------
                         required time                         22.125    
                         arrival time                         -16.532    
  -------------------------------------------------------------------
                         slack                                  5.594    

Slack (MET) :             5.661ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.891ns  (logic 0.433ns (22.895%)  route 1.458ns (77.105%))
  Logic Levels:           0  
  Clock Path Skew:        -0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.198ns = ( 22.198 - 16.000 ) 
    Source Clock Delay      (SCD):    6.585ns = ( 14.585 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.393    14.585    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X60Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y199        FDRE (Prop_fdre_C_Q)         0.433    15.018 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[6]/Q
                         net (fo=1, routed)           1.458    16.476    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[6]
    SLICE_X59Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.283    22.198    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X59Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[6]/C
                         clock pessimism              0.176    22.374    
                         clock uncertainty           -0.205    22.169    
    SLICE_X59Y199        FDRE (Setup_fdre_C_D)       -0.032    22.137    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[6]
  -------------------------------------------------------------------
                         required time                         22.137    
                         arrival time                         -16.476    
  -------------------------------------------------------------------
                         slack                                  5.661    

Slack (MET) :             5.700ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_double_reg/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_reg/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.839ns  (logic 0.379ns (20.613%)  route 1.460ns (79.387%))
  Logic Levels:           0  
  Clock Path Skew:        -0.210ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.201ns = ( 22.201 - 16.000 ) 
    Source Clock Delay      (SCD):    6.587ns = ( 14.587 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.395    14.587    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X53Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_double_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y197        FDRE (Prop_fdre_C_Q)         0.379    14.966 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_double_reg/Q
                         net (fo=1, routed)           1.460    16.425    mbsys_i/axi_ethernet_0/U0/pcs_pma/txpowerdown_double
    SLICE_X53Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.286    22.201    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X53Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_reg/C
                         clock pessimism              0.176    22.377    
                         clock uncertainty           -0.205    22.172    
    SLICE_X53Y199        FDRE (Setup_fdre_C_D)       -0.047    22.125    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_reg
  -------------------------------------------------------------------
                         required time                         22.125    
                         arrival time                         -16.425    
  -------------------------------------------------------------------
                         slack                                  5.700    

Slack (MET) :             5.758ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.633ns  (logic 0.348ns (21.306%)  route 1.285ns (78.694%))
  Logic Levels:           0  
  Clock Path Skew:        -0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.198ns = ( 22.198 - 16.000 ) 
    Source Clock Delay      (SCD):    6.585ns = ( 14.585 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.393    14.585    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X58Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y197        FDRE (Prop_fdre_C_Q)         0.348    14.933 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[12]/Q
                         net (fo=1, routed)           1.285    16.218    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[12]
    SLICE_X58Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.283    22.198    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[12]/C
                         clock pessimism              0.176    22.374    
                         clock uncertainty           -0.205    22.169    
    SLICE_X58Y199        FDRE (Setup_fdre_C_D)       -0.193    21.976    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[12]
  -------------------------------------------------------------------
                         required time                         21.976    
                         arrival time                         -16.218    
  -------------------------------------------------------------------
                         slack                                  5.758    

Slack (MET) :             5.759ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.657ns  (logic 0.398ns (24.019%)  route 1.259ns (75.981%))
  Logic Levels:           0  
  Clock Path Skew:        -0.210ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.195ns = ( 22.195 - 16.000 ) 
    Source Clock Delay      (SCD):    6.581ns = ( 14.581 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.389    14.581    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X62Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y199        FDRE (Prop_fdre_C_Q)         0.398    14.979 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[4]/Q
                         net (fo=1, routed)           1.259    16.238    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[4]
    SLICE_X63Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.280    22.195    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X63Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[4]/C
                         clock pessimism              0.176    22.371    
                         clock uncertainty           -0.205    22.166    
    SLICE_X63Y199        FDRE (Setup_fdre_C_D)       -0.169    21.997    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[4]
  -------------------------------------------------------------------
                         required time                         21.997    
                         arrival time                         -16.238    
  -------------------------------------------------------------------
                         slack                                  5.759    

Slack (MET) :             5.782ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.760ns  (logic 0.379ns (21.533%)  route 1.381ns (78.467%))
  Logic Levels:           0  
  Clock Path Skew:        -0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.198ns = ( 22.198 - 16.000 ) 
    Source Clock Delay      (SCD):    6.585ns = ( 14.585 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.393    14.585    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X59Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y198        FDRE (Prop_fdre_C_Q)         0.379    14.964 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[10]/Q
                         net (fo=1, routed)           1.381    16.345    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[10]
    SLICE_X59Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.283    22.198    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X59Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[10]/C
                         clock pessimism              0.176    22.374    
                         clock uncertainty           -0.205    22.169    
    SLICE_X59Y199        FDRE (Setup_fdre_C_D)       -0.042    22.127    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[10]
  -------------------------------------------------------------------
                         required time                         22.127    
                         arrival time                         -16.345    
  -------------------------------------------------------------------
                         slack                                  5.782    

Slack (MET) :             5.789ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.750ns  (logic 0.433ns (24.745%)  route 1.317ns (75.255%))
  Logic Levels:           0  
  Clock Path Skew:        -0.210ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.195ns = ( 22.195 - 16.000 ) 
    Source Clock Delay      (SCD):    6.581ns = ( 14.581 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.389    14.581    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X62Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y199        FDRE (Prop_fdre_C_Q)         0.433    15.014 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[13]/Q
                         net (fo=1, routed)           1.317    16.331    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[13]
    SLICE_X63Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.280    22.195    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X63Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[13]/C
                         clock pessimism              0.176    22.371    
                         clock uncertainty           -0.205    22.166    
    SLICE_X63Y199        FDRE (Setup_fdre_C_D)       -0.047    22.119    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[13]
  -------------------------------------------------------------------
                         required time                         22.119    
                         arrival time                         -16.331    
  -------------------------------------------------------------------
                         slack                                  5.789    

Slack (MET) :             5.792ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.615ns  (logic 0.348ns (21.546%)  route 1.267ns (78.454%))
  Logic Levels:           0  
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.198ns = ( 22.198 - 16.000 ) 
    Source Clock Delay      (SCD):    6.586ns = ( 14.586 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.394    14.586    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X57Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y198        FDRE (Prop_fdre_C_Q)         0.348    14.934 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[7]/Q
                         net (fo=1, routed)           1.267    16.201    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[7]
    SLICE_X58Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.283    22.198    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[7]/C
                         clock pessimism              0.176    22.374    
                         clock uncertainty           -0.205    22.169    
    SLICE_X58Y199        FDRE (Setup_fdre_C_D)       -0.176    21.993    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[7]
  -------------------------------------------------------------------
                         required time                         21.993    
                         arrival time                         -16.201    
  -------------------------------------------------------------------
                         slack                                  5.792    

Slack (MET) :             5.820ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.706ns  (logic 0.433ns (25.376%)  route 1.273ns (74.625%))
  Logic Levels:           0  
  Clock Path Skew:        -0.210ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.195ns = ( 22.195 - 16.000 ) 
    Source Clock Delay      (SCD):    6.581ns = ( 14.581 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.389    14.581    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X62Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y199        FDRE (Prop_fdre_C_Q)         0.433    15.014 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[2]/Q
                         net (fo=1, routed)           1.273    16.287    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[2]
    SLICE_X63Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.280    22.195    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X63Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[2]/C
                         clock pessimism              0.176    22.371    
                         clock uncertainty           -0.205    22.166    
    SLICE_X63Y199        FDRE (Setup_fdre_C_D)       -0.059    22.107    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[2]
  -------------------------------------------------------------------
                         required time                         22.107    
                         arrival time                         -16.287    
  -------------------------------------------------------------------
                         slack                                  5.820    

Slack (MET) :             5.824ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout1 rise@16.000ns - U0/core_clocking_i/clkout0 rise@8.000ns)
  Data Path Delay:        1.594ns  (logic 0.348ns (21.832%)  route 1.246ns (78.168%))
  Logic Levels:           0  
  Clock Path Skew:        -0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.198ns = ( 22.198 - 16.000 ) 
    Source Clock Delay      (SCD):    6.585ns = ( 14.585 - 8.000 ) 
    Clock Pessimism Removal (CPR):    0.176ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     9.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     9.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662    11.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077    11.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017    13.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081    13.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.393    14.585    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X58Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y197        FDRE (Prop_fdre_C_Q)         0.348    14.933 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[14]/Q
                         net (fo=1, routed)           1.246    16.179    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[14]
    SLICE_X58Y198        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                     16.000    16.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000    16.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216    17.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077    17.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    18.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.073    18.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.920    20.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.077    20.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          1.283    22.198    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/C
                         clock pessimism              0.176    22.374    
                         clock uncertainty           -0.205    22.169    
    SLICE_X58Y198        FDRE (Setup_fdre_C_D)       -0.167    22.002    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]
  -------------------------------------------------------------------
                         required time                         22.002    
                         arrival time                         -16.179    
  -------------------------------------------------------------------
                         slack                                  5.824    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.154ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.768ns  (logic 0.164ns (21.344%)  route 0.604ns (78.656%))
  Logic Levels:           0  
  Clock Path Skew:        0.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.296ns
    Source Clock Delay      (SCD):    2.636ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.578     2.636    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X62Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y199        FDRE (Prop_fdre_C_Q)         0.164     2.800 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[2]/Q
                         net (fo=1, routed)           0.604     3.404    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[2]
    SLICE_X63Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.849     3.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X63Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[2]/C
                         clock pessimism             -0.316     2.980    
                         clock uncertainty            0.205     3.185    
    SLICE_X63Y199        FDRE (Hold_fdre_C_D)         0.066     3.251    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.251    
                         arrival time                           3.404    
  -------------------------------------------------------------------
                         slack                                  0.154    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.773ns  (logic 0.141ns (18.231%)  route 0.632ns (81.769%))
  Logic Levels:           0  
  Clock Path Skew:        0.342ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.298ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.582     2.640    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X57Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y198        FDRE (Prop_fdre_C_Q)         0.141     2.781 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[3]/Q
                         net (fo=1, routed)           0.632     3.413    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[3]
    SLICE_X58Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.850     3.298    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[3]/C
                         clock pessimism             -0.316     2.982    
                         clock uncertainty            0.205     3.187    
    SLICE_X58Y199        FDRE (Hold_fdre_C_D)         0.070     3.257    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[3]
  -------------------------------------------------------------------
                         required time                         -3.257    
                         arrival time                           3.413    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.158ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.729ns  (logic 0.128ns (17.559%)  route 0.601ns (82.441%))
  Logic Levels:           0  
  Clock Path Skew:        0.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.298ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X58Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y197        FDRE (Prop_fdre_C_Q)         0.128     2.766 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[14]/Q
                         net (fo=1, routed)           0.601     3.367    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[14]
    SLICE_X58Y198        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.850     3.298    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]/C
                         clock pessimism             -0.316     2.982    
                         clock uncertainty            0.205     3.187    
    SLICE_X58Y198        FDRE (Hold_fdre_C_D)         0.022     3.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[14]
  -------------------------------------------------------------------
                         required time                         -3.209    
                         arrival time                           3.367    
  -------------------------------------------------------------------
                         slack                                  0.158    

Slack (MET) :             0.162ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.785ns  (logic 0.141ns (17.961%)  route 0.644ns (82.039%))
  Logic Levels:           0  
  Clock Path Skew:        0.342ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.298ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.582     2.640    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X57Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y198        FDRE (Prop_fdre_C_Q)         0.141     2.781 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[5]/Q
                         net (fo=1, routed)           0.644     3.425    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[5]
    SLICE_X58Y198        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.850     3.298    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[5]/C
                         clock pessimism             -0.316     2.982    
                         clock uncertainty            0.205     3.187    
    SLICE_X58Y198        FDRE (Hold_fdre_C_D)         0.076     3.263    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.263    
                         arrival time                           3.425    
  -------------------------------------------------------------------
                         slack                                  0.162    

Slack (MET) :             0.170ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.731ns  (logic 0.128ns (17.503%)  route 0.603ns (82.497%))
  Logic Levels:           0  
  Clock Path Skew:        0.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.298ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X58Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y197        FDRE (Prop_fdre_C_Q)         0.128     2.766 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[12]/Q
                         net (fo=1, routed)           0.603     3.369    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[12]
    SLICE_X58Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.850     3.298    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[12]/C
                         clock pessimism             -0.316     2.982    
                         clock uncertainty            0.205     3.187    
    SLICE_X58Y199        FDRE (Hold_fdre_C_D)         0.013     3.200    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[12]
  -------------------------------------------------------------------
                         required time                         -3.200    
                         arrival time                           3.369    
  -------------------------------------------------------------------
                         slack                                  0.170    

Slack (MET) :             0.171ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.790ns  (logic 0.141ns (17.848%)  route 0.649ns (82.152%))
  Logic Levels:           0  
  Clock Path Skew:        0.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.300ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.582     2.640    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X57Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y198        FDRE (Prop_fdre_C_Q)         0.141     2.781 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[11]/Q
                         net (fo=1, routed)           0.649     3.430    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[11]
    SLICE_X57Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.853     3.300    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X57Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[11]/C
                         clock pessimism             -0.316     2.984    
                         clock uncertainty            0.205     3.189    
    SLICE_X57Y199        FDRE (Hold_fdre_C_D)         0.070     3.259    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[11]
  -------------------------------------------------------------------
                         required time                         -3.259    
                         arrival time                           3.430    
  -------------------------------------------------------------------
                         slack                                  0.171    

Slack (MET) :             0.174ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.740ns  (logic 0.148ns (19.999%)  route 0.592ns (80.001%))
  Logic Levels:           0  
  Clock Path Skew:        0.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.296ns
    Source Clock Delay      (SCD):    2.636ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.578     2.636    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X62Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y199        FDRE (Prop_fdre_C_Q)         0.148     2.784 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[4]/Q
                         net (fo=1, routed)           0.592     3.376    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[4]
    SLICE_X63Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.849     3.296    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X63Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[4]/C
                         clock pessimism             -0.316     2.980    
                         clock uncertainty            0.205     3.185    
    SLICE_X63Y199        FDRE (Hold_fdre_C_D)         0.017     3.202    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[4]
  -------------------------------------------------------------------
                         required time                         -3.202    
                         arrival time                           3.376    
  -------------------------------------------------------------------
                         slack                                  0.174    

Slack (MET) :             0.176ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.793ns  (logic 0.164ns (20.679%)  route 0.629ns (79.321%))
  Logic Levels:           0  
  Clock Path Skew:        0.346ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.298ns
    Source Clock Delay      (SCD):    2.636ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.578     2.636    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X62Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y199        FDRE (Prop_fdre_C_Q)         0.164     2.800 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[0]/Q
                         net (fo=1, routed)           0.629     3.429    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[0]
    SLICE_X59Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.850     3.298    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X59Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[0]/C
                         clock pessimism             -0.316     2.982    
                         clock uncertainty            0.205     3.187    
    SLICE_X59Y199        FDRE (Hold_fdre_C_D)         0.066     3.253    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.253    
                         arrival time                           3.429    
  -------------------------------------------------------------------
                         slack                                  0.176    

Slack (MET) :             0.176ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.750ns  (logic 0.128ns (17.061%)  route 0.622ns (82.939%))
  Logic Levels:           0  
  Clock Path Skew:        0.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.298ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.580     2.638    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X58Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y197        FDRE (Prop_fdre_C_Q)         0.128     2.766 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_double_reg[8]/Q
                         net (fo=1, routed)           0.622     3.388    mbsys_i/axi_ethernet_0/U0/pcs_pma/txdata_double[8]
    SLICE_X58Y198        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.850     3.298    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X58Y198                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[8]/C
                         clock pessimism             -0.316     2.982    
                         clock uncertainty            0.205     3.187    
    SLICE_X58Y198        FDRE (Hold_fdre_C_D)         0.025     3.212    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txdata_int_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.212    
                         arrival time                           3.388    
  -------------------------------------------------------------------
                         slack                                  0.176    

Slack (MET) :             0.182ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_double_reg/C
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_reg/D
                            (rising edge-triggered cell FDRE clocked by U0/core_clocking_i/clkout1  {rise@0.000ns fall@8.000ns period=16.000ns})
  Path Group:             U0/core_clocking_i/clkout1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout1 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.800ns  (logic 0.141ns (17.634%)  route 0.659ns (82.366%))
  Logic Levels:           0  
  Clock Path Skew:        0.343ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.300ns
    Source Clock Delay      (SCD):    2.641ns
    Clock Pessimism Removal (CPR):    0.316ns
  Clock Uncertainty:      0.205ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.154ns
    Phase Error              (PE):    0.120ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.583     2.641    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X53Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_double_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y197        FDRE (Prop_fdre_C_Q)         0.141     2.782 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_double_reg/Q
                         net (fo=1, routed)           0.659     3.440    mbsys_i/axi_ethernet_0/U0/pcs_pma/txpowerdown_double
    SLICE_X53Y199        FDRE                                         r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout1 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1
    BUFGCTRL_X0Y18       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk/O
                         net (fo=64, routed)          0.853     3.300    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out
    SLICE_X53Y199                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_reg/C
                         clock pessimism             -0.316     2.984    
                         clock uncertainty            0.205     3.189    
    SLICE_X53Y199        FDRE (Hold_fdre_C_D)         0.070     3.259    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/txpowerdown_reg
  -------------------------------------------------------------------
                         required time                         -3.259    
                         arrival time                           3.440    
  -------------------------------------------------------------------
                         slack                                  0.182    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  U0/core_clocking_i/clkout0
  To Clock:  U0/core_clocking_i/clkout0

Setup :            0  Failing Endpoints,  Worst Slack        5.748ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.376ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             5.748ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_o_reg/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.680ns  (logic 0.348ns (20.711%)  route 1.332ns (79.289%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.743ns
    Clock Pessimism Removal (CPR):    0.349ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.551     6.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.348     7.091 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          1.332     8.423    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X50Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_o_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_o_reg/C
                         clock pessimism              0.349    14.716    
                         clock uncertainty           -0.077    14.639    
    SLICE_X50Y206        FDCE (Recov_fdce_C_CLR)     -0.468    14.171    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_o_reg
  -------------------------------------------------------------------
                         required time                         14.171    
                         arrival time                          -8.423    
  -------------------------------------------------------------------
                         slack                                  5.748    

Slack (MET) :             5.748ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_s_reg/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.680ns  (logic 0.348ns (20.711%)  route 1.332ns (79.289%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.743ns
    Clock Pessimism Removal (CPR):    0.349ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.551     6.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.348     7.091 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          1.332     8.423    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X50Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_s_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_s_reg/C
                         clock pessimism              0.349    14.716    
                         clock uncertainty           -0.077    14.639    
    SLICE_X50Y206        FDCE (Recov_fdce_C_CLR)     -0.468    14.171    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_s_reg
  -------------------------------------------------------------------
                         required time                         14.171    
                         arrival time                          -8.423    
  -------------------------------------------------------------------
                         slack                                  5.748    

Slack (MET) :             5.748ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss_reg/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.680ns  (logic 0.348ns (20.711%)  route 1.332ns (79.289%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.743ns
    Clock Pessimism Removal (CPR):    0.349ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.551     6.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.348     7.091 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          1.332     8.423    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X50Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss_reg/C
                         clock pessimism              0.349    14.716    
                         clock uncertainty           -0.077    14.639    
    SLICE_X50Y206        FDCE (Recov_fdce_C_CLR)     -0.468    14.171    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss_reg
  -------------------------------------------------------------------
                         required time                         14.171    
                         arrival time                          -8.423    
  -------------------------------------------------------------------
                         slack                                  5.748    

Slack (MET) :             5.748ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/state_reg[2]/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.680ns  (logic 0.348ns (20.711%)  route 1.332ns (79.289%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.743ns
    Clock Pessimism Removal (CPR):    0.349ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.551     6.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.348     7.091 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          1.332     8.423    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X50Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/state_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/state_reg[2]/C
                         clock pessimism              0.349    14.716    
                         clock uncertainty           -0.077    14.639    
    SLICE_X50Y206        FDCE (Recov_fdce_C_CLR)     -0.468    14.171    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/state_reg[2]
  -------------------------------------------------------------------
                         required time                         14.171    
                         arrival time                          -8.423    
  -------------------------------------------------------------------
                         slack                                  5.748    

Slack (MET) :             5.749ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/state_reg[2]/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.734ns  (logic 0.348ns (20.071%)  route 1.386ns (79.929%))
  Logic Levels:           0  
  Clock Path Skew:        -0.012ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.744ns
    Clock Pessimism Removal (CPR):    0.365ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.552     6.744    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X47Y222                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y222        FDPE (Prop_fdpe_C_Q)         0.348     7.092 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=21, routed)          1.386     8.477    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6
    SLICE_X48Y205        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/state_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X48Y205                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/state_reg[2]/C
                         clock pessimism              0.365    14.732    
                         clock uncertainty           -0.077    14.655    
    SLICE_X48Y205        FDCE (Recov_fdce_C_CLR)     -0.429    14.226    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/state_reg[2]
  -------------------------------------------------------------------
                         required time                         14.226    
                         arrival time                          -8.477    
  -------------------------------------------------------------------
                         slack                                  5.749    

Slack (MET) :             5.752ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[0]/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.677ns  (logic 0.348ns (20.757%)  route 1.329ns (79.243%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.743ns
    Clock Pessimism Removal (CPR):    0.349ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.551     6.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.348     7.091 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          1.329     8.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X51Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X51Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[0]/C
                         clock pessimism              0.349    14.716    
                         clock uncertainty           -0.077    14.639    
    SLICE_X51Y206        FDCE (Recov_fdce_C_CLR)     -0.468    14.171    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[0]
  -------------------------------------------------------------------
                         required time                         14.171    
                         arrival time                          -8.419    
  -------------------------------------------------------------------
                         slack                                  5.752    

Slack (MET) :             5.752ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[1]/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.677ns  (logic 0.348ns (20.757%)  route 1.329ns (79.243%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.743ns
    Clock Pessimism Removal (CPR):    0.349ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.551     6.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.348     7.091 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          1.329     8.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X51Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X51Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[1]/C
                         clock pessimism              0.349    14.716    
                         clock uncertainty           -0.077    14.639    
    SLICE_X51Y206        FDCE (Recov_fdce_C_CLR)     -0.468    14.171    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[1]
  -------------------------------------------------------------------
                         required time                         14.171    
                         arrival time                          -8.419    
  -------------------------------------------------------------------
                         slack                                  5.752    

Slack (MET) :             5.752ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[3]/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.677ns  (logic 0.348ns (20.757%)  route 1.329ns (79.243%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.743ns
    Clock Pessimism Removal (CPR):    0.349ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.551     6.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.348     7.091 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          1.329     8.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X51Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X51Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[3]/C
                         clock pessimism              0.349    14.716    
                         clock uncertainty           -0.077    14.639    
    SLICE_X51Y206        FDCE (Recov_fdce_C_CLR)     -0.468    14.171    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[3]
  -------------------------------------------------------------------
                         required time                         14.171    
                         arrival time                          -8.419    
  -------------------------------------------------------------------
                         slack                                  5.752    

Slack (MET) :             5.752ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[6]/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.677ns  (logic 0.348ns (20.757%)  route 1.329ns (79.243%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.743ns
    Clock Pessimism Removal (CPR):    0.349ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.551     6.743    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.348     7.091 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          1.329     8.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X51Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[6]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X51Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[6]/C
                         clock pessimism              0.349    14.716    
                         clock uncertainty           -0.077    14.639    
    SLICE_X51Y206        FDCE (Recov_fdce_C_CLR)     -0.468    14.171    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[6]
  -------------------------------------------------------------------
                         required time                         14.171    
                         arrival time                          -8.419    
  -------------------------------------------------------------------
                         slack                                  5.752    

Slack (MET) :             5.783ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rxpmareset_o_reg/CLR
                            (recovery check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            8.000ns  (U0/core_clocking_i/clkout0 rise@8.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        1.734ns  (logic 0.348ns (20.071%)  route 1.386ns (79.929%))
  Logic Levels:           0  
  Clock Path Skew:        -0.012ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.366ns = ( 14.366 - 8.000 ) 
    Source Clock Delay      (SCD):    6.744ns
    Clock Pessimism Removal (CPR):    0.365ns
  Clock Uncertainty:      0.077ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.136ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.274     1.274    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.081     1.355 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.662     3.017    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.077     3.094 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           2.017     5.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.081     5.191 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.552     6.744    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X47Y222                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y222        FDPE (Prop_fdpe_C_Q)         0.348     7.092 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=21, routed)          1.386     8.477    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6
    SLICE_X48Y205        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rxpmareset_o_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      8.000     8.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     8.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           1.216     9.216    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.077     9.293 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           1.552    10.845    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.073    10.918 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.920    12.838    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.077    12.915 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        1.451    14.366    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X48Y205                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rxpmareset_o_reg/C
                         clock pessimism              0.365    14.732    
                         clock uncertainty           -0.077    14.655    
    SLICE_X48Y205        FDCE (Recov_fdce_C_CLR)     -0.395    14.260    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rxpmareset_o_reg
  -------------------------------------------------------------------
                         required time                         14.260    
                         arrival time                          -8.477    
  -------------------------------------------------------------------
                         slack                                  5.783    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.376ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss_reg/C
                            (rising edge-triggered cell FDCE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/drp_op_done_o_reg/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.346ns  (logic 0.141ns (40.740%)  route 0.205ns (59.260%))
  Logic Levels:           0  
  Clock Path Skew:        0.037ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.392ns
    Source Clock Delay      (SCD):    2.727ns
    Clock Pessimism Removal (CPR):    0.627ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.669     2.727    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y206        FDCE (Prop_fdce_C_Q)         0.141     2.868 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss_reg/Q
                         net (fo=3, routed)           0.205     3.073    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss
    SLICE_X48Y206        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/drp_op_done_o_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.944     3.392    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X48Y206                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/drp_op_done_o_reg/C
                         clock pessimism             -0.627     2.764    
    SLICE_X48Y206        FDCE (Remov_fdce_C_CLR)     -0.067     2.697    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/drp_op_done_o_reg
  -------------------------------------------------------------------
                         required time                         -2.697    
                         arrival time                           3.073    
  -------------------------------------------------------------------
                         slack                                  0.376    

Slack (MET) :             0.545ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[5]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.444ns  (logic 0.128ns (28.804%)  route 0.316ns (71.196%))
  Logic Levels:           0  
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.390ns
    Source Clock Delay      (SCD):    2.717ns
    Clock Pessimism Removal (CPR):    0.627ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.659     2.717    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X47Y222                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y222        FDPE (Prop_fdpe_C_Q)         0.128     2.845 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=21, routed)          0.316     3.162    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6
    SLICE_X50Y210        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.942     3.390    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[5]/C
                         clock pessimism             -0.627     2.762    
    SLICE_X50Y210        FDCE (Remov_fdce_C_CLR)     -0.146     2.616    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.616    
                         arrival time                           3.162    
  -------------------------------------------------------------------
                         slack                                  0.545    

Slack (MET) :             0.567ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[13]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.468ns  (logic 0.128ns (27.352%)  route 0.340ns (72.648%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    2.716ns
    Clock Pessimism Removal (CPR):    0.627ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.658     2.716    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.128     2.844 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          0.340     3.184    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X50Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[13]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.943     3.391    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[13]/C
                         clock pessimism             -0.627     2.763    
    SLICE_X50Y209        FDCE (Remov_fdce_C_CLR)     -0.146     2.617    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[13]
  -------------------------------------------------------------------
                         required time                         -2.617    
                         arrival time                           3.184    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[15]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.468ns  (logic 0.128ns (27.352%)  route 0.340ns (72.648%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    2.716ns
    Clock Pessimism Removal (CPR):    0.627ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.658     2.716    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.128     2.844 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          0.340     3.184    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X50Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[15]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.943     3.391    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[15]/C
                         clock pessimism             -0.627     2.763    
    SLICE_X50Y209        FDCE (Remov_fdce_C_CLR)     -0.146     2.617    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[15]
  -------------------------------------------------------------------
                         required time                         -2.617    
                         arrival time                           3.184    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.567ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[5]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.468ns  (logic 0.128ns (27.352%)  route 0.340ns (72.648%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    2.716ns
    Clock Pessimism Removal (CPR):    0.627ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.658     2.716    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X45Y223                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y223        FDPE (Prop_fdpe_C_Q)         0.128     2.844 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=25, routed)          0.340     3.184    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6
    SLICE_X50Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.943     3.391    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X50Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[5]/C
                         clock pessimism             -0.627     2.763    
    SLICE_X50Y209        FDCE (Remov_fdce_C_CLR)     -0.146     2.617    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/rd_data_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.617    
                         arrival time                           3.184    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.640ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[10]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.544ns  (logic 0.128ns (23.524%)  route 0.416ns (76.476%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    2.717ns
    Clock Pessimism Removal (CPR):    0.648ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.659     2.717    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X47Y222                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y222        FDPE (Prop_fdpe_C_Q)         0.128     2.845 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=21, routed)          0.416     3.261    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6
    SLICE_X48Y208        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[10]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.943     3.391    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X48Y208                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[10]/C
                         clock pessimism             -0.648     2.742    
    SLICE_X48Y208        FDCE (Remov_fdce_C_CLR)     -0.121     2.621    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[10]
  -------------------------------------------------------------------
                         required time                         -2.621    
                         arrival time                           3.261    
  -------------------------------------------------------------------
                         slack                                  0.640    

Slack (MET) :             0.640ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[12]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.544ns  (logic 0.128ns (23.524%)  route 0.416ns (76.476%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    2.717ns
    Clock Pessimism Removal (CPR):    0.648ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.659     2.717    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X47Y222                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y222        FDPE (Prop_fdpe_C_Q)         0.128     2.845 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=21, routed)          0.416     3.261    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6
    SLICE_X48Y208        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[12]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.943     3.391    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X48Y208                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[12]/C
                         clock pessimism             -0.648     2.742    
    SLICE_X48Y208        FDCE (Remov_fdce_C_CLR)     -0.121     2.621    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[12]
  -------------------------------------------------------------------
                         required time                         -2.621    
                         arrival time                           3.261    
  -------------------------------------------------------------------
                         slack                                  0.640    

Slack (MET) :             0.640ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[14]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.544ns  (logic 0.128ns (23.524%)  route 0.416ns (76.476%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    2.717ns
    Clock Pessimism Removal (CPR):    0.648ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.659     2.717    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X47Y222                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y222        FDPE (Prop_fdpe_C_Q)         0.128     2.845 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=21, routed)          0.416     3.261    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6
    SLICE_X48Y208        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[14]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.943     3.391    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X48Y208                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[14]/C
                         clock pessimism             -0.648     2.742    
    SLICE_X48Y208        FDCE (Remov_fdce_C_CLR)     -0.121     2.621    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[14]
  -------------------------------------------------------------------
                         required time                         -2.621    
                         arrival time                           3.261    
  -------------------------------------------------------------------
                         slack                                  0.640    

Slack (MET) :             0.640ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[8]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.544ns  (logic 0.128ns (23.524%)  route 0.416ns (76.476%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    2.717ns
    Clock Pessimism Removal (CPR):    0.648ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.659     2.717    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X47Y222                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y222        FDPE (Prop_fdpe_C_Q)         0.128     2.845 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=21, routed)          0.416     3.261    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6
    SLICE_X48Y208        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[8]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.943     3.391    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X48Y208                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[8]/C
                         clock pessimism             -0.648     2.742    
    SLICE_X48Y208        FDCE (Remov_fdce_C_CLR)     -0.121     2.621    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[8]
  -------------------------------------------------------------------
                         required time                         -2.621    
                         arrival time                           3.261    
  -------------------------------------------------------------------
                         slack                                  0.640    

Slack (MET) :             0.655ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
                            (rising edge-triggered cell FDPE clocked by U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[11]/CLR
                            (removal check against rising-edge clock U0/core_clocking_i/clkout0  {rise@0.000ns fall@4.000ns period=8.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (U0/core_clocking_i/clkout0 rise@0.000ns - U0/core_clocking_i/clkout0 rise@0.000ns)
  Data Path Delay:        0.555ns  (logic 0.128ns (23.080%)  route 0.427ns (76.920%))
  Logic Levels:           0  
  Clock Path Skew:        0.046ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.391ns
    Source Clock Delay      (SCD):    2.717ns
    Clock Pessimism Removal (CPR):    0.627ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.492     0.492    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.026     0.518 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.690     1.209    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.050     1.259 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.773     2.032    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026     2.058 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.659     2.717    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X47Y222                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y222        FDPE (Prop_fdpe_C_Q)         0.128     2.845 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6/Q
                         net (fo=21, routed)          0.427     3.272    mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6
    SLICE_X51Y208        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[11]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock U0/core_clocking_i/clkout0 rise edge)
                                                      0.000     0.000 r  
    GTPE2_CHANNEL_X0Y4   GTPE2_CHANNEL                0.000     0.000 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK
                         net (fo=1, routed)           0.529     0.529    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/txoutclk
    BUFGCTRL_X0Y21       BUFG (Prop_bufg_I_O)         0.029     0.558 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk/O
                         net (fo=1, routed)           0.964     1.522    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg
    MMCME2_ADV_X1Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                      0.053     1.575 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.844     2.418    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029     2.447 r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2/O
                         net (fo=4063, routed)        0.943     3.391    mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out
    SLICE_X51Y208                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[11]/C
                         clock pessimism             -0.627     2.763    
    SLICE_X51Y208        FDCE (Remov_fdce_C_CLR)     -0.146     2.617    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/rd_data_reg[11]
  -------------------------------------------------------------------
                         required time                         -2.617    
                         arrival time                           3.272    
  -------------------------------------------------------------------
                         slack                                  0.655    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_mbsys_clk_wiz_1_0
  To Clock:  clk_out1_mbsys_clk_wiz_1_0

Setup :            0  Failing Endpoints,  Worst Slack        4.111ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.337ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.111ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[12]/CLR
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.384ns  (logic 0.484ns (8.989%)  route 4.900ns (91.011%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.108ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.311ns = ( 12.311 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.594     7.396    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aresetn
    SLICE_X104Y156       LUT3 (Prop_lut3_I1_O)        0.105     7.501 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/gfifo_gen.gmm2s.vacancy_i[12]_i_1/O
                         net (fo=78, routed)          1.306     8.807    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/O1
    SLICE_X105Y164       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[12]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.291    12.311    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/s_axi_aclk
    SLICE_X105Y164                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[12]/C
                         clock pessimism              1.004    13.315    
                         clock uncertainty           -0.066    13.249    
    SLICE_X105Y164       FDCE (Recov_fdce_C_CLR)     -0.331    12.918    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[12]
  -------------------------------------------------------------------
                         required time                         12.918    
                         arrival time                          -8.807    
  -------------------------------------------------------------------
                         slack                                  4.111    

Slack (MET) :             4.176ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.RST_FULL_GEN_reg/CLR
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.310ns  (logic 0.484ns (9.115%)  route 4.826ns (90.885%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.117ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns = ( 12.302 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.426     7.227    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_axi_aresetn
    SLICE_X105Y165       LUT3 (Prop_lut3_I1_O)        0.105     7.332 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gpr1.dout_i[21]_i_1/O
                         net (fo=116, routed)         1.401     8.733    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/srst_wrst_busy
    SLICE_X110Y174       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.RST_FULL_GEN_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.282    12.302    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aclk
    SLICE_X110Y174                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.RST_FULL_GEN_reg/C
                         clock pessimism              1.004    13.306    
                         clock uncertainty           -0.066    13.240    
    SLICE_X110Y174       FDCE (Recov_fdce_C_CLR)     -0.331    12.909    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.RST_FULL_GEN_reg
  -------------------------------------------------------------------
                         required time                         12.909    
                         arrival time                          -8.733    
  -------------------------------------------------------------------
                         slack                                  4.176    

Slack (MET) :             4.215ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/PRE
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.310ns  (logic 0.484ns (9.115%)  route 4.826ns (90.885%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.117ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns = ( 12.302 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.426     7.227    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_axi_aresetn
    SLICE_X105Y165       LUT3 (Prop_lut3_I1_O)        0.105     7.332 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gpr1.dout_i[21]_i_1/O
                         net (fo=116, routed)         1.401     8.733    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/srst_wrst_busy
    SLICE_X110Y174       FDPE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.282    12.302    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aclk
    SLICE_X110Y174                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg/C
                         clock pessimism              1.004    13.306    
                         clock uncertainty           -0.066    13.240    
    SLICE_X110Y174       FDPE (Recov_fdpe_C_PRE)     -0.292    12.948    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d1_reg
  -------------------------------------------------------------------
                         required time                         12.948    
                         arrival time                          -8.733    
  -------------------------------------------------------------------
                         slack                                  4.215    

Slack (MET) :             4.215ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/PRE
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.310ns  (logic 0.484ns (9.115%)  route 4.826ns (90.885%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.117ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns = ( 12.302 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.426     7.227    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_axi_aresetn
    SLICE_X105Y165       LUT3 (Prop_lut3_I1_O)        0.105     7.332 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gpr1.dout_i[21]_i_1/O
                         net (fo=116, routed)         1.401     8.733    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/srst_wrst_busy
    SLICE_X110Y174       FDPE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.282    12.302    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aclk
    SLICE_X110Y174                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg/C
                         clock pessimism              1.004    13.306    
                         clock uncertainty           -0.066    13.240    
    SLICE_X110Y174       FDPE (Recov_fdpe_C_PRE)     -0.292    12.948    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d2_reg
  -------------------------------------------------------------------
                         required time                         12.948    
                         arrival time                          -8.733    
  -------------------------------------------------------------------
                         slack                                  4.215    

Slack (MET) :             4.215ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg/PRE
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.310ns  (logic 0.484ns (9.115%)  route 4.826ns (90.885%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.117ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns = ( 12.302 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.426     7.227    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_axi_aresetn
    SLICE_X105Y165       LUT3 (Prop_lut3_I1_O)        0.105     7.332 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gpr1.dout_i[21]_i_1/O
                         net (fo=116, routed)         1.401     8.733    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/srst_wrst_busy
    SLICE_X110Y174       FDPE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.282    12.302    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aclk
    SLICE_X110Y174                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg/C
                         clock pessimism              1.004    13.306    
                         clock uncertainty           -0.066    13.240    
    SLICE_X110Y174       FDPE (Recov_fdpe_C_PRE)     -0.292    12.948    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/grstd1.grst_full.grst_f.rst_d3_reg
  -------------------------------------------------------------------
                         required time                         12.948    
                         arrival time                          -8.733    
  -------------------------------------------------------------------
                         slack                                  4.215    

Slack (MET) :             4.220ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[10]/CLR
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.276ns  (logic 0.484ns (9.174%)  route 4.792ns (90.826%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.312ns = ( 12.312 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.594     7.396    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aresetn
    SLICE_X104Y156       LUT3 (Prop_lut3_I1_O)        0.105     7.501 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/gfifo_gen.gmm2s.vacancy_i[12]_i_1/O
                         net (fo=78, routed)          1.197     8.699    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/O1
    SLICE_X105Y163       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[10]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.292    12.312    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/s_axi_aclk
    SLICE_X105Y163                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[10]/C
                         clock pessimism              1.004    13.316    
                         clock uncertainty           -0.066    13.250    
    SLICE_X105Y163       FDCE (Recov_fdce_C_CLR)     -0.331    12.919    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[10]
  -------------------------------------------------------------------
                         required time                         12.919    
                         arrival time                          -8.699    
  -------------------------------------------------------------------
                         slack                                  4.220    

Slack (MET) :             4.220ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[11]/CLR
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.276ns  (logic 0.484ns (9.174%)  route 4.792ns (90.826%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.312ns = ( 12.312 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.594     7.396    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aresetn
    SLICE_X104Y156       LUT3 (Prop_lut3_I1_O)        0.105     7.501 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/gfifo_gen.gmm2s.vacancy_i[12]_i_1/O
                         net (fo=78, routed)          1.197     8.699    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/O1
    SLICE_X105Y163       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[11]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.292    12.312    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/s_axi_aclk
    SLICE_X105Y163                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[11]/C
                         clock pessimism              1.004    13.316    
                         clock uncertainty           -0.066    13.250    
    SLICE_X105Y163       FDCE (Recov_fdce_C_CLR)     -0.331    12.919    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[11]
  -------------------------------------------------------------------
                         required time                         12.919    
                         arrival time                          -8.699    
  -------------------------------------------------------------------
                         slack                                  4.220    

Slack (MET) :             4.220ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[8]/CLR
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.276ns  (logic 0.484ns (9.174%)  route 4.792ns (90.826%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.312ns = ( 12.312 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.594     7.396    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aresetn
    SLICE_X104Y156       LUT3 (Prop_lut3_I1_O)        0.105     7.501 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/gfifo_gen.gmm2s.vacancy_i[12]_i_1/O
                         net (fo=78, routed)          1.197     8.699    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/O1
    SLICE_X105Y163       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[8]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.292    12.312    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/s_axi_aclk
    SLICE_X105Y163                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[8]/C
                         clock pessimism              1.004    13.316    
                         clock uncertainty           -0.066    13.250    
    SLICE_X105Y163       FDCE (Recov_fdce_C_CLR)     -0.331    12.919    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[8]
  -------------------------------------------------------------------
                         required time                         12.919    
                         arrival time                          -8.699    
  -------------------------------------------------------------------
                         slack                                  4.220    

Slack (MET) :             4.220ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[9]/CLR
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.276ns  (logic 0.484ns (9.174%)  route 4.792ns (90.826%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.312ns = ( 12.312 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.594     7.396    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aresetn
    SLICE_X104Y156       LUT3 (Prop_lut3_I1_O)        0.105     7.501 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/gfifo_gen.gmm2s.vacancy_i[12]_i_1/O
                         net (fo=78, routed)          1.197     8.699    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/O1
    SLICE_X105Y163       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[9]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.292    12.312    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/s_axi_aclk
    SLICE_X105Y163                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[9]/C
                         clock pessimism              1.004    13.316    
                         clock uncertainty           -0.066    13.250    
    SLICE_X105Y163       FDCE (Recov_fdce_C_CLR)     -0.331    12.919    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[9]
  -------------------------------------------------------------------
                         required time                         12.919    
                         arrival time                          -8.699    
  -------------------------------------------------------------------
                         slack                                  4.220    

Slack (MET) :             4.246ns  (required time - arrival time)
  Source:                 mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@10.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        5.251ns  (logic 0.484ns (9.217%)  route 4.767ns (90.783%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.106ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.313ns = ( 12.313 - 10.000 ) 
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    1.004ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.112ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.399     3.423    mbsys_i/rst_clk_wiz_1_100M/U0/slowest_sync_clk
    SLICE_X75Y142                                                     r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y142        FDRE (Prop_fdre_C_Q)         0.379     3.802 r  mbsys_i/rst_clk_wiz_1_100M/U0/ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]/Q
                         net (fo=83, routed)          3.594     7.396    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aresetn
    SLICE_X104Y156       LUT3 (Prop_lut3_I1_O)        0.105     7.501 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/gfifo_gen.gmm2s.vacancy_i[12]_i_1/O
                         net (fo=78, routed)          1.173     8.674    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/O1
    SLICE_X105Y162       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                     10.000    10.000 r  
    F10                                               0.000    10.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000    10.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000    10.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000    10.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418    11.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167    12.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.321     9.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           1.679    10.943    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.077    11.020 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       1.293    12.313    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/s_axi_aclk
    SLICE_X105Y162                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[4]/C
                         clock pessimism              1.004    13.317    
                         clock uncertainty           -0.066    13.251    
    SLICE_X105Y162       FDCE (Recov_fdce_C_CLR)     -0.331    12.920    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.gaxis_pkt_fifo_cc.gdc_pkt.axis_dc_pkt_fifo_reg[4]
  -------------------------------------------------------------------
                         required time                         12.920    
                         arrival time                          -8.674    
  -------------------------------------------------------------------
                         slack                                  4.246    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.337ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.308ns  (logic 0.164ns (53.278%)  route 0.144ns (46.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.419ns
    Source Clock Delay      (SCD):    0.868ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.630     0.868    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X8Y148                                                      r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y148         FDPE (Prop_fdpe_C_Q)         0.164     1.032 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.144     1.175    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/I1[0]
    SLICE_X10Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.902     1.419    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X10Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]/C
                         clock pessimism             -0.513     0.906    
    SLICE_X10Y148        FDCE (Remov_fdce_C_CLR)     -0.067     0.839    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -0.839    
                         arrival time                           1.175    
  -------------------------------------------------------------------
                         slack                                  0.337    

Slack (MET) :             0.337ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.308ns  (logic 0.164ns (53.278%)  route 0.144ns (46.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.419ns
    Source Clock Delay      (SCD):    0.868ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.630     0.868    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X8Y148                                                      r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y148         FDPE (Prop_fdpe_C_Q)         0.164     1.032 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.144     1.175    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/I1[0]
    SLICE_X10Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.902     1.419    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X10Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]/C
                         clock pessimism             -0.513     0.906    
    SLICE_X10Y148        FDCE (Remov_fdce_C_CLR)     -0.067     0.839    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -0.839    
                         arrival time                           1.175    
  -------------------------------------------------------------------
                         slack                                  0.337    

Slack (MET) :             0.337ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.308ns  (logic 0.164ns (53.278%)  route 0.144ns (46.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.419ns
    Source Clock Delay      (SCD):    0.868ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.630     0.868    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X8Y148                                                      r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y148         FDPE (Prop_fdpe_C_Q)         0.164     1.032 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.144     1.175    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/I1[0]
    SLICE_X10Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.902     1.419    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X10Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]/C
                         clock pessimism             -0.513     0.906    
    SLICE_X10Y148        FDCE (Remov_fdce_C_CLR)     -0.067     0.839    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -0.839    
                         arrival time                           1.175    
  -------------------------------------------------------------------
                         slack                                  0.337    

Slack (MET) :             0.337ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.308ns  (logic 0.164ns (53.278%)  route 0.144ns (46.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.419ns
    Source Clock Delay      (SCD):    0.868ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.630     0.868    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X8Y148                                                      r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y148         FDPE (Prop_fdpe_C_Q)         0.164     1.032 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.144     1.175    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/I1[0]
    SLICE_X10Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.902     1.419    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X10Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C
                         clock pessimism             -0.513     0.906    
    SLICE_X10Y148        FDCE (Remov_fdce_C_CLR)     -0.067     0.839    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -0.839    
                         arrival time                           1.175    
  -------------------------------------------------------------------
                         slack                                  0.337    

Slack (MET) :             0.337ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.308ns  (logic 0.164ns (53.278%)  route 0.144ns (46.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.419ns
    Source Clock Delay      (SCD):    0.868ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.630     0.868    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X8Y148                                                      r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y148         FDPE (Prop_fdpe_C_Q)         0.164     1.032 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.144     1.175    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/I1[0]
    SLICE_X10Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.902     1.419    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X10Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C
                         clock pessimism             -0.513     0.906    
    SLICE_X10Y148        FDCE (Remov_fdce_C_CLR)     -0.067     0.839    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -0.839    
                         arrival time                           1.175    
  -------------------------------------------------------------------
                         slack                                  0.337    

Slack (MET) :             0.337ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.308ns  (logic 0.164ns (53.278%)  route 0.144ns (46.722%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.419ns
    Source Clock Delay      (SCD):    0.868ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.630     0.868    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X8Y148                                                      r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y148         FDPE (Prop_fdpe_C_Q)         0.164     1.032 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=10, routed)          0.144     1.175    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/I1[0]
    SLICE_X10Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.902     1.419    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X10Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C
                         clock pessimism             -0.513     0.906    
    SLICE_X10Y148        FDCE (Remov_fdce_C_CLR)     -0.067     0.839    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -0.839    
                         arrival time                           1.175    
  -------------------------------------------------------------------
                         slack                                  0.337    

Slack (MET) :             0.352ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[10]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.276ns  (logic 0.141ns (51.068%)  route 0.135ns (48.932%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.375ns
    Source Clock Delay      (SCD):    0.825ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.587     0.825    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aclk
    SLICE_X111Y155                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y155       FDPE (Prop_fdpe_C_Q)         0.141     0.966 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=44, routed)          0.135     1.101    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Q[0]
    SLICE_X109Y155       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[10]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.858     1.375    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_axi_aclk
    SLICE_X109Y155                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[10]/C
                         clock pessimism             -0.534     0.841    
    SLICE_X109Y155       FDCE (Remov_fdce_C_CLR)     -0.092     0.749    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[10]
  -------------------------------------------------------------------
                         required time                         -0.749    
                         arrival time                           1.101    
  -------------------------------------------------------------------
                         slack                                  0.352    

Slack (MET) :             0.352ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[11]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.276ns  (logic 0.141ns (51.068%)  route 0.135ns (48.932%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.375ns
    Source Clock Delay      (SCD):    0.825ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.587     0.825    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aclk
    SLICE_X111Y155                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y155       FDPE (Prop_fdpe_C_Q)         0.141     0.966 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=44, routed)          0.135     1.101    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Q[0]
    SLICE_X109Y155       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[11]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.858     1.375    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_axi_aclk
    SLICE_X109Y155                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[11]/C
                         clock pessimism             -0.534     0.841    
    SLICE_X109Y155       FDCE (Remov_fdce_C_CLR)     -0.092     0.749    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[11]
  -------------------------------------------------------------------
                         required time                         -0.749    
                         arrival time                           1.101    
  -------------------------------------------------------------------
                         slack                                  0.352    

Slack (MET) :             0.352ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.276ns  (logic 0.141ns (51.068%)  route 0.135ns (48.932%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.375ns
    Source Clock Delay      (SCD):    0.825ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.587     0.825    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aclk
    SLICE_X111Y155                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y155       FDPE (Prop_fdpe_C_Q)         0.141     0.966 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=44, routed)          0.135     1.101    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Q[0]
    SLICE_X109Y155       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.858     1.375    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_axi_aclk
    SLICE_X109Y155                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]/C
                         clock pessimism             -0.534     0.841    
    SLICE_X109Y155       FDCE (Remov_fdce_C_CLR)     -0.092     0.749    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[8]
  -------------------------------------------------------------------
                         required time                         -0.749    
                         arrival time                           1.101    
  -------------------------------------------------------------------
                         slack                                  0.352    

Slack (MET) :             0.352ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[9]/CLR
                            (removal check against rising-edge clock clk_out1_mbsys_clk_wiz_1_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out1_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.276ns  (logic 0.141ns (51.068%)  route 0.135ns (48.932%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.375ns
    Source Clock Delay      (SCD):    0.825ns
    Clock Pessimism Removal (CPR):    0.534ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.587     0.825    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/s_axi_aclk
    SLICE_X111Y155                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y155       FDPE (Prop_fdpe_C_Q)         0.141     0.966 f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]/Q
                         net (fo=44, routed)          0.135     1.101    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Q[0]
    SLICE_X109Y155       FDCE                                         f  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[9]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y19       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout1_buf/O
                         net (fo=12602, routed)       0.858     1.375    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/s_axi_aclk
    SLICE_X109Y155                                                    r  mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[9]/C
                         clock pessimism             -0.534     0.841    
    SLICE_X109Y155       FDCE (Remov_fdce_C_CLR)     -0.092     0.749    mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[9]
  -------------------------------------------------------------------
                         required time                         -0.749    
                         arrival time                           1.101    
  -------------------------------------------------------------------
                         slack                                  0.352    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out2_mbsys_clk_wiz_1_0
  To Clock:  clk_out2_mbsys_clk_wiz_1_0

Setup :            0  Failing Endpoints,  Worst Slack        2.597ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.557ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.597ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        2.145ns  (logic 0.379ns (17.671%)  route 1.766ns (82.329%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.469ns = ( 7.469 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.010ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.766     5.564    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y210        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.449     7.469    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y210                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/C
                         clock pessimism              1.010     8.479    
                         clock uncertainty           -0.060     8.419    
    SLICE_X42Y210        FDCE (Recov_fdce_C_CLR)     -0.258     8.161    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_done_reg
  -------------------------------------------------------------------
                         required time                          8.161    
                         arrival time                          -5.564    
  -------------------------------------------------------------------
                         slack                                  2.597    

Slack (MET) :             2.672ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        2.036ns  (logic 0.379ns (18.612%)  route 1.657ns (81.388%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.470ns = ( 7.470 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.010ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.657     5.456    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.450     7.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/C
                         clock pessimism              1.010     8.480    
                         clock uncertainty           -0.060     8.420    
    SLICE_X42Y209        FDCE (Recov_fdce_C_CLR)     -0.292     8.128    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]
  -------------------------------------------------------------------
                         required time                          8.128    
                         arrival time                          -5.456    
  -------------------------------------------------------------------
                         slack                                  2.672    

Slack (MET) :             2.672ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        2.036ns  (logic 0.379ns (18.612%)  route 1.657ns (81.388%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.470ns = ( 7.470 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.010ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.657     5.456    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.450     7.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/C
                         clock pessimism              1.010     8.480    
                         clock uncertainty           -0.060     8.420    
    SLICE_X42Y209        FDCE (Recov_fdce_C_CLR)     -0.292     8.128    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]
  -------------------------------------------------------------------
                         required time                          8.128    
                         arrival time                          -5.456    
  -------------------------------------------------------------------
                         slack                                  2.672    

Slack (MET) :             2.672ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        2.036ns  (logic 0.379ns (18.612%)  route 1.657ns (81.388%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.470ns = ( 7.470 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.010ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.657     5.456    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[6]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.450     7.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[6]/C
                         clock pessimism              1.010     8.480    
                         clock uncertainty           -0.060     8.420    
    SLICE_X42Y209        FDCE (Recov_fdce_C_CLR)     -0.292     8.128    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[6]
  -------------------------------------------------------------------
                         required time                          8.128    
                         arrival time                          -5.456    
  -------------------------------------------------------------------
                         slack                                  2.672    

Slack (MET) :             2.697ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        2.046ns  (logic 0.379ns (18.520%)  route 1.667ns (81.480%))
  Logic Levels:           0  
  Clock Path Skew:        0.062ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.471ns = ( 7.471 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.010ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.667     5.466    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X44Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.451     7.471    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X44Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/C
                         clock pessimism              1.010     8.481    
                         clock uncertainty           -0.060     8.421    
    SLICE_X44Y209        FDCE (Recov_fdce_C_CLR)     -0.258     8.163    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]
  -------------------------------------------------------------------
                         required time                          8.163    
                         arrival time                          -5.466    
  -------------------------------------------------------------------
                         slack                                  2.697    

Slack (MET) :             2.706ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        2.036ns  (logic 0.379ns (18.612%)  route 1.657ns (81.388%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.470ns = ( 7.470 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.010ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.657     5.456    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.450     7.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/C
                         clock pessimism              1.010     8.480    
                         clock uncertainty           -0.060     8.420    
    SLICE_X42Y209        FDCE (Recov_fdce_C_CLR)     -0.258     8.162    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]
  -------------------------------------------------------------------
                         required time                          8.162    
                         arrival time                          -5.456    
  -------------------------------------------------------------------
                         slack                                  2.706    

Slack (MET) :             2.706ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        2.036ns  (logic 0.379ns (18.612%)  route 1.657ns (81.388%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.470ns = ( 7.470 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.010ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.657     5.456    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.450     7.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/C
                         clock pessimism              1.010     8.480    
                         clock uncertainty           -0.060     8.420    
    SLICE_X42Y209        FDCE (Recov_fdce_C_CLR)     -0.258     8.162    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]
  -------------------------------------------------------------------
                         required time                          8.162    
                         arrival time                          -5.456    
  -------------------------------------------------------------------
                         slack                                  2.706    

Slack (MET) :             2.706ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[5]/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        2.036ns  (logic 0.379ns (18.612%)  route 1.657ns (81.388%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.470ns = ( 7.470 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.010ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.657     5.456    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.450     7.470    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[5]/C
                         clock pessimism              1.010     8.480    
                         clock uncertainty           -0.060     8.420    
    SLICE_X42Y209        FDCE (Recov_fdce_C_CLR)     -0.258     8.162    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[5]
  -------------------------------------------------------------------
                         required time                          8.162    
                         arrival time                          -5.456    
  -------------------------------------------------------------------
                         slack                                  2.706    

Slack (MET) :             3.246ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        1.392ns  (logic 0.379ns (27.223%)  route 1.013ns (72.777%))
  Logic Levels:           0  
  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.306ns = ( 7.306 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.069ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          1.013     4.812    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y196        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.286     7.306    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y196                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/C
                         clock pessimism              1.069     8.375    
                         clock uncertainty           -0.060     8.315    
    SLICE_X42Y196        FDCE (Recov_fdce_C_CLR)     -0.258     8.057    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg
  -------------------------------------------------------------------
                         required time                          8.057    
                         arrival time                          -4.812    
  -------------------------------------------------------------------
                         slack                                  3.246    

Slack (MET) :             3.407ns  (required time - arrival time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@5.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        1.158ns  (logic 0.379ns (32.738%)  route 0.779ns (67.262%))
  Logic Levels:           0  
  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.306ns = ( 7.306 - 5.000 ) 
    Source Clock Delay      (SCD):    3.419ns
    Clock Pessimism Removal (CPR):    1.069ns
  Clock Uncertainty:      0.060ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.098ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      2.355     2.355 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.343     3.698    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.521     0.177 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.766     1.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.081     2.024 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.395     3.419    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.379     3.798 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.779     4.577    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X43Y195        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      5.000     5.000 r  
    F10                                               0.000     5.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     5.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     5.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     5.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      1.418     6.418 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           1.167     7.585    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -3.321     4.264 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           1.679     5.943    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.077     6.020 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         1.286     7.306    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X43Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/C
                         clock pessimism              1.069     8.375    
                         clock uncertainty           -0.060     8.315    
    SLICE_X43Y195        FDCE (Recov_fdce_C_CLR)     -0.331     7.984    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]
  -------------------------------------------------------------------
                         required time                          7.984    
                         arrival time                          -4.577    
  -------------------------------------------------------------------
                         slack                                  3.407    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.557ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.526ns  (logic 0.141ns (26.822%)  route 0.385ns (73.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.385     1.346    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y195        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/C
                         clock pessimism             -0.513     0.857    
    SLICE_X42Y195        FDCE (Remov_fdce_C_CLR)     -0.067     0.790    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]
  -------------------------------------------------------------------
                         required time                         -0.790    
                         arrival time                           1.346    
  -------------------------------------------------------------------
                         slack                                  0.557    

Slack (MET) :             0.557ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.526ns  (logic 0.141ns (26.822%)  route 0.385ns (73.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.385     1.346    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y195        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/C
                         clock pessimism             -0.513     0.857    
    SLICE_X42Y195        FDCE (Remov_fdce_C_CLR)     -0.067     0.790    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]
  -------------------------------------------------------------------
                         required time                         -0.790    
                         arrival time                           1.346    
  -------------------------------------------------------------------
                         slack                                  0.557    

Slack (MET) :             0.557ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.526ns  (logic 0.141ns (26.822%)  route 0.385ns (73.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.385     1.346    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y195        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/C
                         clock pessimism             -0.513     0.857    
    SLICE_X42Y195        FDCE (Remov_fdce_C_CLR)     -0.067     0.790    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]
  -------------------------------------------------------------------
                         required time                         -0.790    
                         arrival time                           1.346    
  -------------------------------------------------------------------
                         slack                                  0.557    

Slack (MET) :             0.557ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.526ns  (logic 0.141ns (26.822%)  route 0.385ns (73.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.385     1.346    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y195        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/C
                         clock pessimism             -0.513     0.857    
    SLICE_X42Y195        FDCE (Remov_fdce_C_CLR)     -0.067     0.790    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]
  -------------------------------------------------------------------
                         required time                         -0.790    
                         arrival time                           1.346    
  -------------------------------------------------------------------
                         slack                                  0.557    

Slack (MET) :             0.557ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[5]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.526ns  (logic 0.141ns (26.822%)  route 0.385ns (73.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.385     1.346    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y195        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[5]/C
                         clock pessimism             -0.513     0.857    
    SLICE_X42Y195        FDCE (Remov_fdce_C_CLR)     -0.067     0.790    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[5]
  -------------------------------------------------------------------
                         required time                         -0.790    
                         arrival time                           1.346    
  -------------------------------------------------------------------
                         slack                                  0.557    

Slack (MET) :             0.557ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[6]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.526ns  (logic 0.141ns (26.822%)  route 0.385ns (73.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.385     1.346    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y195        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[6]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[6]/C
                         clock pessimism             -0.513     0.857    
    SLICE_X42Y195        FDCE (Remov_fdce_C_CLR)     -0.067     0.790    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[6]
  -------------------------------------------------------------------
                         required time                         -0.790    
                         arrival time                           1.346    
  -------------------------------------------------------------------
                         slack                                  0.557    

Slack (MET) :             0.582ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.526ns  (logic 0.141ns (26.822%)  route 0.385ns (73.178%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.385     1.346    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X43Y195        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X43Y195                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/C
                         clock pessimism             -0.513     0.857    
    SLICE_X43Y195        FDCE (Remov_fdce_C_CLR)     -0.092     0.765    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]
  -------------------------------------------------------------------
                         required time                         -0.765    
                         arrival time                           1.346    
  -------------------------------------------------------------------
                         slack                                  0.582    

Slack (MET) :             0.669ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.638ns  (logic 0.141ns (22.094%)  route 0.497ns (77.906%))
  Logic Levels:           0  
  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.370ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.497     1.459    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y196        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.853     1.370    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y196                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/C
                         clock pessimism             -0.513     0.857    
    SLICE_X42Y196        FDCE (Remov_fdce_C_CLR)     -0.067     0.790    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg
  -------------------------------------------------------------------
                         required time                         -0.790    
                         arrival time                           1.459    
  -------------------------------------------------------------------
                         slack                                  0.669    

Slack (MET) :             0.693ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.982ns  (logic 0.141ns (14.353%)  route 0.841ns (85.647%))
  Logic Levels:           0  
  Clock Path Skew:        0.356ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.461ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.841     1.803    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X44Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.944     1.461    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X44Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/C
                         clock pessimism             -0.284     1.177    
    SLICE_X44Y209        FDCE (Remov_fdce_C_CLR)     -0.067     1.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.110    
                         arrival time                           1.803    
  -------------------------------------------------------------------
                         slack                                  0.693    

Slack (MET) :             0.706ns  (arrival time - required time)
  Source:                 mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
                            (rising edge-triggered cell FDPE clocked by clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR
                            (removal check against rising-edge clock clk_out2_mbsys_clk_wiz_1_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns - clk_out2_mbsys_clk_wiz_1_0 rise@0.000ns)
  Data Path Delay:        0.995ns  (logic 0.141ns (14.166%)  route 0.854ns (85.834%))
  Logic Levels:           0  
  Clock Path Skew:        0.356ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.461ns
    Source Clock Delay      (SCD):    0.821ns
    Clock Pessimism Removal (CPR):    0.284ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.441     0.441 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.491     0.932    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.407    -0.474 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.687     0.212    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.026     0.238 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.583     0.821    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X49Y197                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y197        FDPE (Prop_fdpe_C_Q)         0.141     0.962 f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/pma_reset_pipe_reg[3]/Q
                         net (fo=38, routed)          0.854     1.816    mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out
    SLICE_X42Y209        FDCE                                         f  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_out2_mbsys_clk_wiz_1_0 rise edge)
                                                      0.000     0.000 r  
    F10                                               0.000     0.000 r  MGTREFCLK1P
                         net (fo=0)                   0.000     0.000    MGTREFCLK1P
    F10                  IBUF (Prop_ibuf_I_O)         0.000     0.000 r  MGTREFCLK1P_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.000    MGTREFCLK1P_IBUF
    IBUFDS_GTE2_X0Y3     IBUFDS_GTE2 (Prop_ibufds_gte2_I_O)
                                                      0.732     0.732 r  IBUFDS_GTE2_inst_1/O
                         net (fo=2, routed)           0.754     1.486    mbsys_i/clk_wiz_1/U0/clk_in1
    MMCME2_ADV_X0Y4      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
                                                     -1.741    -0.255 r  mbsys_i/clk_wiz_1/U0/mmcm_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.743     0.488    mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0
    BUFGCTRL_X0Y20       BUFG (Prop_bufg_I_O)         0.029     0.517 r  mbsys_i/clk_wiz_1/U0/clkout2_buf/O
                         net (fo=259, routed)         0.944     1.461    mbsys_i/axi_ethernet_0/U0/pcs_pma/independent_clock_bufg
    SLICE_X42Y209                                                     r  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/C
                         clock pessimism             -0.284     1.177    
    SLICE_X42Y209        FDCE (Remov_fdce_C_CLR)     -0.067     1.110    mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.110    
                         arrival time                           1.816    
  -------------------------------------------------------------------
                         slack                                  0.706    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
  To Clock:  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK

Setup :            0  Failing Endpoints,  Worst Slack       24.667ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.116ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             24.667ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        5.005ns  (logic 0.694ns (13.867%)  route 4.311ns (86.133%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.740     9.149    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/AR[0]
    SLICE_X10Y149        FDPE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X10Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X10Y149        FDPE (Recov_fdpe_C_PRE)     -0.258    33.816    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         33.816    
                         arrival time                          -9.149    
  -------------------------------------------------------------------
                         slack                                 24.667    

Slack (MET) :             24.697ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[12]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.902ns  (logic 0.694ns (14.159%)  route 4.208ns (85.841%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.637     9.046    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y147        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[12]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[12]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y147        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[12]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -9.046    
  -------------------------------------------------------------------
                         slack                                 24.697    

Slack (MET) :             24.697ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[13]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.902ns  (logic 0.694ns (14.159%)  route 4.208ns (85.841%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.637     9.046    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y147        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[13]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[13]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y147        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[13]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -9.046    
  -------------------------------------------------------------------
                         slack                                 24.697    

Slack (MET) :             24.697ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[14]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.902ns  (logic 0.694ns (14.159%)  route 4.208ns (85.841%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.637     9.046    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y147        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[14]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[14]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y147        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[14]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -9.046    
  -------------------------------------------------------------------
                         slack                                 24.697    

Slack (MET) :             24.697ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.902ns  (logic 0.694ns (14.159%)  route 4.208ns (85.841%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.637     9.046    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y147        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y147                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y147        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[15]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -9.046    
  -------------------------------------------------------------------
                         slack                                 24.697    

Slack (MET) :             24.819ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[1]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.780ns  (logic 0.694ns (14.520%)  route 4.086ns (85.480%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.515     8.924    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[1]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y148        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[1]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -8.924    
  -------------------------------------------------------------------
                         slack                                 24.819    

Slack (MET) :             24.819ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[2]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.780ns  (logic 0.694ns (14.520%)  route 4.086ns (85.480%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.515     8.924    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[2]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y148        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[2]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -8.924    
  -------------------------------------------------------------------
                         slack                                 24.819    

Slack (MET) :             24.819ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[3]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.780ns  (logic 0.694ns (14.520%)  route 4.086ns (85.480%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.515     8.924    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[3]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y148        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[3]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -8.924    
  -------------------------------------------------------------------
                         slack                                 24.819    

Slack (MET) :             24.819ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[4]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.780ns  (logic 0.694ns (14.520%)  route 4.086ns (85.480%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.515     8.924    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[4]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y148        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[4]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -8.924    
  -------------------------------------------------------------------
                         slack                                 24.819    

Slack (MET) :             24.819ns  (required time - arrival time)
  Source:                 dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[5]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            30.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@30.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        4.780ns  (logic 0.694ns (14.520%)  route 4.086ns (85.480%))
  Logic Levels:           3  (LUT2=1 LUT6=2)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.701ns = ( 33.701 - 30.000 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    0.409ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.572     2.572    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     2.653 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.492     4.145    dbg_hub/inst/U_ICON/U_CMD/CLK
    SLICE_X21Y135                                                     r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X21Y135        FDCE (Prop_fdce_C_Q)         0.379     4.524 r  dbg_hub/inst/U_ICON/U_CMD/iTARGET_reg[13]/Q
                         net (fo=4, routed)           0.931     5.455    dbg_hub/inst/U_ICON/U_CMD/iCORE_ID[1]
    SLICE_X20Y136        LUT6 (Prop_lut6_I4_O)        0.105     5.560 f  dbg_hub/inst/U_ICON/U_CMD/LC_STAT_INIT_SLV[127]_i_3/O
                         net (fo=9, routed)           1.175     6.735    dbg_hub/inst/U_ICON/U_CMD/n_0_LC_STAT_INIT_SLV[127]_i_3
    SLICE_X13Y139        LUT6 (Prop_lut6_I0_O)        0.105     6.840 f  dbg_hub/inst/U_ICON/U_CMD/shift_reg_in[17]_i_1/O
                         net (fo=23, routed)          0.464     7.304    dbg_hub/inst/U_ICON/U_CMD/O5
    SLICE_X14Y140        LUT2 (Prop_lut2_I0_O)        0.105     7.409 f  dbg_hub/inst/U_ICON/U_CMD/ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1/O
                         net (fo=36, routed)          1.515     8.924    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/AR[0]
    SLICE_X15Y148        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                     30.000    30.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000    30.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           2.233    32.233    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.077    32.310 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         1.391    33.701    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/idrck
    SLICE_X15Y148                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[5]/C
                         clock pessimism              0.409    34.110    
                         clock uncertainty           -0.035    34.074    
    SLICE_X15Y148        FDCE (Recov_fdce_C_CLR)     -0.331    33.743    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[5]
  -------------------------------------------------------------------
                         required time                         33.743    
                         arrival time                          -8.924    
  -------------------------------------------------------------------
                         slack                                 24.819    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.116ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.141ns (43.711%)  route 0.182ns (56.289%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=17, routed)          0.182     2.362    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/I4[0]
    SLICE_X14Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/idrck
    SLICE_X14Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X14Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.362    
  -------------------------------------------------------------------
                         slack                                  0.116    

Slack (MET) :             0.116ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.141ns (43.711%)  route 0.182ns (56.289%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=17, routed)          0.182     2.362    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/I4[0]
    SLICE_X14Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/idrck
    SLICE_X14Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X14Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.362    
  -------------------------------------------------------------------
                         slack                                  0.116    

Slack (MET) :             0.116ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.141ns (43.711%)  route 0.182ns (56.289%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=17, routed)          0.182     2.362    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/I4[0]
    SLICE_X14Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/idrck
    SLICE_X14Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X14Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.362    
  -------------------------------------------------------------------
                         slack                                  0.116    

Slack (MET) :             0.116ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.141ns (43.711%)  route 0.182ns (56.289%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=17, routed)          0.182     2.362    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/I4[0]
    SLICE_X14Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/idrck
    SLICE_X14Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[1]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X14Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.362    
  -------------------------------------------------------------------
                         slack                                  0.116    

Slack (MET) :             0.116ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.141ns (43.711%)  route 0.182ns (56.289%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=17, routed)          0.182     2.362    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/I4[0]
    SLICE_X14Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/idrck
    SLICE_X14Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[2]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X14Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.362    
  -------------------------------------------------------------------
                         slack                                  0.116    

Slack (MET) :             0.116ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.141ns (43.711%)  route 0.182ns (56.289%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=17, routed)          0.182     2.362    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/I4[0]
    SLICE_X14Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/idrck
    SLICE_X14Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[3]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X14Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.362    
  -------------------------------------------------------------------
                         slack                                  0.116    

Slack (MET) :             0.116ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.141ns (43.711%)  route 0.182ns (56.289%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=17, routed)          0.182     2.362    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/I4[0]
    SLICE_X14Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/idrck
    SLICE_X14Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[2]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X14Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.362    
  -------------------------------------------------------------------
                         slack                                  0.116    

Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.346ns  (logic 0.141ns (40.804%)  route 0.205ns (59.196%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.205     2.385    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]
    SLICE_X12Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/idrck
    SLICE_X12Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X12Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.385    
  -------------------------------------------------------------------
                         slack                                  0.139    

Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.346ns  (logic 0.141ns (40.804%)  route 0.205ns (59.196%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.205     2.385    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]
    SLICE_X12Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/idrck
    SLICE_X12Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X12Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.385    
  -------------------------------------------------------------------
                         slack                                  0.139    

Slack (MET) :             0.139ns  (arrival time - required time)
  Source:                 dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Destination:            dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK  {rise@0.000ns fall@15.000ns period=30.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns - dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise@0.000ns)
  Data Path Delay:        0.346ns  (logic 0.141ns (40.804%)  route 0.205ns (59.196%))
  Logic Levels:           0  
  Clock Path Skew:        0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.040ns
    Clock Pessimism Removal (CPR):    0.186ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.388     1.388    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     1.414 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.626     2.040    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/idrck
    SLICE_X13Y150                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y150        FDPE (Prop_fdpe_C_Q)         0.141     2.181 f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.205     2.385    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[0]
    SLICE_X12Y149        FDCE                                         f  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y0           BSCANE2                      0.000     0.000 r  dbg_hub/inst/bscan_inst/SERIES7_BSCAN.bscan_inst/DRCK
                         net (fo=1, routed)           1.571     1.571    dbg_hub/inst/DRCK
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     1.600 r  dbg_hub/inst/u_bufg_icon/O
                         net (fo=457, routed)         0.900     2.499    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/idrck
    SLICE_X12Y149                                                     r  dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C
                         clock pessimism             -0.186     2.313    
    SLICE_X12Y149        FDCE (Remov_fdce_C_CLR)     -0.067     2.246    dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.385    
  -------------------------------------------------------------------
                         slack                                  0.139    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
  To Clock:  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE

Setup :            0  Failing Endpoints,  Worst Slack       14.147ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.622ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             14.147ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg/CLR
                            (recovery check against rising-edge clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@33.333ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        2.124ns  (logic 0.489ns (23.024%)  route 1.635ns (76.976%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.199ns = ( 36.532 - 33.333 ) 
    Source Clock Delay      (SCD):    3.606ns = ( 20.273 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.378ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.375    20.273    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y131        FDCE (Prop_fdce_C_Q)         0.384    20.657 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/Q
                         net (fo=19, routed)          0.962    21.619    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd_noblock
    SLICE_X78Y128        LUT2 (Prop_lut2_I1_O)        0.105    21.724 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_i_2/O
                         net (fo=1, routed)           0.673    22.397    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Use_UART.execute_i_2
    SLICE_X78Y128        FDCE                                         f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                     33.333    33.333 r  
    BSCAN_X0Y1           BSCANE2                      0.000    33.333 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    35.191    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    35.268 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.264    36.532    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X78Y128                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg/C
                         clock pessimism              0.378    36.910    
                         clock uncertainty           -0.035    36.875    
    SLICE_X78Y128        FDCE (Recov_fdce_C_CLR)     -0.331    36.544    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg
  -------------------------------------------------------------------
                         required time                         36.544    
                         arrival time                         -22.397    
  -------------------------------------------------------------------
                         slack                                 14.147    

Slack (MET) :             31.321ns  (required time - arrival time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[0]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/CLR
                            (recovery check against rising-edge clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            33.333ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@50.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        1.600ns  (logic 0.489ns (30.564%)  route 1.111ns (69.436%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.050ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.203ns = ( 53.203 - 50.000 ) 
    Source Clock Delay      (SCD):    3.615ns = ( 20.282 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.362ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           2.150    18.817    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.081    18.898 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.384    20.282    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[0]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.384    20.666 r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[0]/Q
                         net (fo=8, routed)           0.820    21.486    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[0]
    SLICE_X79Y131        LUT5 (Prop_lut5_I4_O)        0.105    21.591 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[0].LUT_Delay_i_1/O
                         net (fo=1, routed)           0.291    21.882    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Insert_Delays[0].LUT_Delay_i_1
    SLICE_X79Y131        FDCE                                         f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     50.000    50.000 f  
    BSCAN_X0Y1           BSCANE2                      0.000    50.000 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.858    51.858    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.077    51.935 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          1.268    53.203    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C  (IS_INVERTED)
                         clock pessimism              0.362    53.565    
                         clock uncertainty           -0.035    53.529    
    SLICE_X79Y131        FDCE (Recov_fdce_C_CLR)     -0.327    53.202    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I
  -------------------------------------------------------------------
                         required time                         53.202    
                         arrival time                         -21.882    
  -------------------------------------------------------------------
                         slack                                 31.321    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.622ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/CLR
                            (removal check against rising-edge clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        0.565ns  (logic 0.191ns (33.818%)  route 0.374ns (66.182%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.126ns = ( 18.792 - 16.667 ) 
    Source Clock Delay      (SCD):    1.706ns = ( 18.372 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.392ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.566    18.372    mbsys_i/mdm_1/U0/MDM_Core_I1/CLK
    SLICE_X77Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y131        FDCE (Prop_fdce_C_Q)         0.146    18.518 f  mbsys_i/mdm_1/U0/MDM_Core_I1/PORT_Selector_reg[1]/Q
                         net (fo=8, routed)           0.258    18.776    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Q[1]
    SLICE_X79Y131        LUT5 (Prop_lut5_I2_O)        0.045    18.821 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[0].LUT_Delay_i_1/O
                         net (fo=1, routed)           0.116    18.937    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Insert_Delays[0].LUT_Delay_i_1
    SLICE_X79Y131        FDCE                                         f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269    17.936    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029    17.965 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.828    18.792    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C  (IS_INVERTED)
                         clock pessimism             -0.392    18.400    
    SLICE_X79Y131        FDCE (Remov_fdce_C_CLR)     -0.085    18.315    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I
  -------------------------------------------------------------------
                         required time                        -18.315    
                         arrival time                          18.937    
  -------------------------------------------------------------------
                         slack                                  0.622    

Slack (MET) :             17.717ns  (arrival time - required time)
  Source:                 mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C
                            (falling edge-triggered cell FDCE clocked by mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Destination:            mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg/CLR
                            (removal check against rising-edge clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE  {rise@0.000ns fall@16.667ns period=33.333ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            -16.667ns  (mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise@0.000ns - mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall@16.667ns)
  Data Path Delay:        1.005ns  (logic 0.191ns (19.008%)  route 0.814ns (80.992%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.123ns
    Source Clock Delay      (SCD):    1.699ns = ( 18.365 - 16.667 ) 
    Clock Pessimism Removal (CPR):    0.413ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE fall edge)
                                                     16.667    16.667 f  
    BSCAN_X0Y1           BSCANE2                      0.000    16.667 f  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.114    17.781    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.026    17.807 f  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.559    18.365    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X79Y131                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/C  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y131        FDCE (Prop_fdce_C_Q)         0.146    18.511 r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I/Q
                         net (fo=19, routed)          0.432    18.943    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd_noblock
    SLICE_X78Y128        LUT2 (Prop_lut2_I1_O)        0.045    18.988 f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_i_2/O
                         net (fo=1, routed)           0.382    19.370    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Use_UART.execute_i_2
    SLICE_X78Y128        FDCE                                         f  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE rise edge)
                                                      0.000     0.000 r  
    BSCAN_X0Y1           BSCANE2                      0.000     0.000 r  mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE
                         net (fo=1, routed)           1.269     1.269    mbsys_i/mdm_1/U0/Dbg_Update_0__0
    BUFGCTRL_X0Y3        BUFG (Prop_bufg_I_O)         0.029     1.298 r  mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst/O
                         net (fo=41, routed)          0.825     2.123    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CLK
    SLICE_X78Y128                                                     r  mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg/C
                         clock pessimism             -0.413     1.710    
                         clock uncertainty            0.035     1.745    
    SLICE_X78Y128        FDCE (Remov_fdce_C_CLR)     -0.092     1.653    mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.execute_reg
  -------------------------------------------------------------------
                         required time                         -1.653    
                         arrival time                          19.370    
  -------------------------------------------------------------------
                         slack                                 17.717    





