Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------- | Tool Version : Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:20:35 MST 2015 | Date : Wed Apr 22 12:15:22 2015 | Host : phys-pc458-4 running 64-bit Service Pack 1 (build 7601) | Command : report_drc -------------------------------------------------------------------------------------- Report DRC Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: design_1 Design limits: Ruledeck: default Max violations: Violations found: 9 2. REPORT DETAILS ----------------- CFGBVS-1#1 Warning Missing CFGBVS and CONFIG_VOLTAGE Design Properties Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. Related violations: DPIP-1#1 Warning Input pipelining DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_lower/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#2 Warning Input pipelining DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_upper/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#3 Warning Input pipelining DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPIP-1#4 Warning Input pipelining DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance. Related violations: DPOP-1#1 Warning Output pipelining DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_lower/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. Related violations: DPOP-1#2 Warning Output pipelining DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. Related violations: DPOP-1#3 Warning Output pipelining DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined. Related violations: RTSTAT-10#1 Warning No routable loads 6 net(s) have no routable loads. The problem net(s) are EXT_AXI_arprot, EXT_AXI_awprot. Related violations: