Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:20:35 MST 2015
| Date         : Wed Apr 22 12:13:00 2015
| Host         : phys-pc458-4 running 64-bit Service Pack 1  (build 7601)
| Command      : report_control_sets -verbose -file toplevel_control_sets_placed.rpt
| Design       : toplevel
| Device       : xc7a200t
--------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+-------------------------------------------------------------------+-------+
|                               Status                              | Count |
+-------------------------------------------------------------------+-------+
| Number of unique control sets                                     |   740 |
| Minimum Number of register sites lost to control set restrictions |  2059 |
+-------------------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |            4031 |         1195 |
| No           | No                    | Yes                    |             430 |          119 |
| No           | Yes                   | No                     |            2965 |          942 |
| Yes          | No                    | No                     |            2581 |          800 |
| Yes          | No                    | Yes                    |             346 |           87 |
| Yes          | Yes                   | No                     |            5044 |         1766 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+---------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|                    Clock Signal                   |                                                                                               Enable Signal                                                                                               |                                                                                              Set/Reset Signal                                                                                              | Slice Load Count | Bel Load Count |
+---------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/rd_rst_asreg_d1                               | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                             |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[12]_i_1                                                                                                                           |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[13]_i_1                                                                                                                           |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                 |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_1                                                                                                                           |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                 |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_rd_req                                                                                                                                                   |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd                                                                                                                                                 |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg                  | dbg_hub/inst/U_ICON/U_CMD/O9[0]                                                                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[1]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[6]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[3]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CAPTURE5_out                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_man_reset.sync_mgmt_reset_host_i/async_rst4_reg                                                                                               |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[4]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int6                                                                                                          |                                                                                                                                                                                                            |                1 |              1 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_rst_asreg_d1                                                 | dbg_hub/inst/U_ICON/U_CMD/O9[0]                                                                                                                                                                            |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/O5                                                                                                                                         |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[5]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int5q                                                                                                         |                                                                                                                                                                                                            |                1 |              1 |
|  dbg_hub/inst/UPDATE                              |                                                                                                                                                                                                           | dbg_hub/inst/bscan_inst/AR[0]                                                                                                                                                                              |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1__0 |                1 |              1 |
| ~mbsys_i/mdm_1/U0/Dbg_Update_0                    |                                                                                                                                                                                                           | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Insert_Delays[0].LUT_Delay_i_1                                                                                                                             |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1   |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_start_single_step_reg                                                                                |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/async_rst4                                                                                                                                        |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/O4                                                                                                                                         |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_normal_stop_cmd_i_reg                                                                                |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_wrce[0]                                                                                                                  |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[9]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_reg                                                                                |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/O4                                                                                                       |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_34_out                                                                                                                                                      |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_33_out                                                                                                                                                      |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/tx_byte_counter/SYNC_STATS_RESET/async_rst4_reg                                                               |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_sync_rx_reset_i/async_rst4_reg                                                                                                                |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_32_out                                                                                                                                                      |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_sync_tx_reset_i/async_rst4_reg                                                                                                                |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/n_0_mem_R[7]_i_1                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/O72                                                                                                    |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/async_rst4                                                                                                        |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    |                                                                                                                                                                                                           | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Use_UART.execute_i_2                                                                                                                                       |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/mem_start_div                                                                                              | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Data_Flow_Logic_I/O8[0]                                                                                                             |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WHCMPCE/wcnt_hcmp_ce                                                                                                       | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/cmp_reset                                                                                                                               |                1 |              1 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg                  | dbg_hub/inst/U_ICON/U_CMD/O9[0]                                                                                                                                                                            |                1 |              1 |
| ~mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CE                                                                                                                                                            | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/D                                                                                                                                                              |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/RESET_INT                                                                                                           |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[8]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_ld[1]                                                                                                                                       |                                                                                                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int5q                                                                                                                |                                                                                                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int6                                                                                                                 |                                                                                                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[7]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/capture_1                                                                                                |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_rst_asreg_d1                                                 | dbg_hub/inst/U_ICON/U_CMD/O9[0]                                                                                                                                                                            |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WLCMPCE/wcnt_lcmp_ce                                                                                                       | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/cmp_reset                                                                                                                               |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCMPCE/scnt_cmp_ce                                                                                                         | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/U_CMPRESET/cmp_reset                                                                                                                               |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_axi_wvalid[5]                                                                                                      | EXT_AXI_wready0_out                                                                                                                                                                                        |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_axi_awvalid[5]                                                                                                     | EXT_AXI_awready1_out                                                                                                                                                                                       |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[0]_i_1                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss                                                              |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/O64                                                                                                                                    |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_31_out                                                                                                                                                      |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_30_out                                                                                                                                                      |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[10]_i_1                                                                                                                           |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_axi_arvalid[5]                                                                                                     | EXT_AXI_arready3_out                                                                                                                                                                                       |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[14]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_FRAME_COUNT[11]_i_1                                                                                                                           |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/I76[0]                                                                                                                                |                                                                                                                                                                                                            |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_15                                                                                        |                                                                                                                                                                                                            |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/wr_rst_asreg_d1                               | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                             |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1   |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0 |                2 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__15                                                                                                                                                 |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int4q                                                                                                         |                                                                                                                                                                                                            |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__10                                                                                                                                                 |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__11                                                                                                                                                 |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__16                                                                                                                                                 |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/Q[1]                                                             |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1__0                  |                1 |              2 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    |                                                                                                                                                                                                           |                                                                                                                                                                                                            |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__14                                                                                                                                                 |                1 |              2 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Debug_Rst_i0                                                                                                                                                  |                                                                                                                                                                                                            |                1 |              2 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Command_Reg_En                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_clear                                                                                        |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__6                                                                                                                                                  |                1 |              2 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1                     |                1 |              2 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/O1                                                                                                                                                                              |                                                                                                                                                                                                            |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXCLIENT/ClkB_reset_inst/async_rst4                                                                                                       |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXCLIENT/ClkB_reset_inst/async_rst4                                                                                                       |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_GTX/ClkB_reset_inst/async_rst4                                                                                                            |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__5                                                                                                                                                  |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1                                                                                                                                                     |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__19                                                                                                                                                 |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__12                                                                                                                                                 |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int4q                                                                                                                |                                                                                                                                                                                                            |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__4                                                                                                                                                  |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/p_3_out                                                                                                             |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__3                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__13                                                                                                                                                 |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__2                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__7                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__8                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__9                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__0                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__1                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__18                                                                                                                                                 |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_sync_rst1_i_1__17                                                                                                                                                 |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1                     |                1 |              2 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/O6                                                                                                                                                                              | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/O1                                                                                                                                                         |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/mdm_1/U0/MDM_Core_I1/O1                                                                                                                                                                            |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                              |                2 |              3 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_Tx_Client_TxC_2_Mem_Addr_int[2]_i_1                                                                                                                              |                                                                                                                                                                                                            |                2 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                    |                2 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_ld[1]                                                                                                                                            |                                                                                                                                                                                                            |                1 |              3 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0                  |                2 |              3 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/O3                                                                                                                                                                              |                                                                                                                                                                                                            |                1 |              3 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/O6                                                                                                                                                                              |                                                                                                                                                                                                            |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[10].mu_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/n_0_bus2ip_addr_i[5]_i_1                                                                                                                      | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                            |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[0].cnt_srl_reg/clear                                                                                                                                     |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[25].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[3].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[6].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[5].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[4].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_pfc_tx/FSM_onehot_legacy_state[4]_i_1                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[7].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/clear                                                                                                                                     |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[13].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[31].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[27].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[28].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[30].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/n_0_IP2Bus_WrAck_i_1                                                                                                                                        |                3 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[10].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[17].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/rxd_axistream_current_state0                                                                                                           |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[8].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[0].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_addr_reg0                                                                                                | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_mgmt_host_reset                                                                                                                               |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[18].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[15].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[16].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[26].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[9].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_FSM_sequential_rx_state[3]_i_1                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out                                                                                                                                                            |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_FSM_sequential_tx_state[3]_i_1                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out                                                                                                                                                            |                2 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/LOOPBACK_REG                                                                                   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                              |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[11].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | n_0_axi_we_axi_reg_13_i_1                                                                                                                                                                                  |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | n_0_axi_we_axi_reg_14_i_1                                                                                                                                                                                  |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | n_0_axi_we_axi_reg_15_i_1                                                                                                                                                                                  |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | n_0_axi_we_axi_reg_8_i_1                                                                                                                                                                                   |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_srl_fff/clear                                                                                                                                                    |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_Axi_Str_TxD_2_Mem_We[3]_i_1                                                                                                                                       |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[12].mu_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[23].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[22].tc_srl_reg/clear                                                                                                                                          |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_iport0_o[0]                                                                                                                                               |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[9].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[1].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/rst_clk_wiz_1_100M/U0/bus_struct_reset[0]                                                                                                                                                          |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[20].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear                                                                                                                                  |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2                                                                                                                                   | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                                                                                                       |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.RX_FIFO_I/O1                                                                                                                                         | mbsys_i/mdm_1/U0/MDM_Core_I1/n_0_Use_Uart.reset_RX_FIFO_reg                                                                                                                                                |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.TX_FIFO_I/O1                                                                                                                                         | mbsys_i/mdm_1/U0/MDM_Core_I1/n_0_Use_Uart.reset_TX_FIFO_reg                                                                                                                                                |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/CE041_out                                                                                                                                 | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                3 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[21].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/I74[0]                                                                                                                                | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/I5[0]                                                                                                                                                 |                                                                                                                                                                                                            |                3 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[12].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[14].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/TRANSMITTER/CONFIG_K28p5                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/mgt_tx_reset                                                                                                                      |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/n_0_USE_ROCKET_IO.TXDATA[7]_i_1                                                                                                   |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/n_0_USE_ROCKET_IO.NO_1588.RXCLKCORCNT_INT[2]_i_1                                                                                  |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/xsdb_memory_read_inst/n_0_curr_read_block[3]_i_1                                                                                                                               |                                                                                                                                                                                                            |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/n_0_FSM_sequential_STATE[3]_i_1                                                                                                   |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[24].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx/bad_pfc_opcode_int                                                                                                                        |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_ld[1]                                                                                                                                            |                                                                                                                                                                                                            |                2 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram0                                                                                               |                2 |              4 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/mdm_1/U0/MDM_Core_I1/TDI_Shifter0                                                                                                                                                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/sel_n_reset                                                                                                                                                                   |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/flush_pipe                                                                                                                                             |                3 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/rst_d2                                         |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[2].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/broadcastaddressmatch_int                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_address_match_i_1                                                                                                                             |                1 |              4 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/mdm_1/U0/MDM_Core_I1/MDM_SEL                                                                                                                                                                      | mbsys_i/mdm_1/U0/MDM_Core_I1/sel_n_reset                                                                                                                                                                   |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[29].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[6].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[1].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_bus2ip_cs_int[3]_i_1                                                                                                                          |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/reset_time_out_reg                                                                             |                3 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[19].tc_srl_reg/clear                                                                                                                                          |                1 |              4 |
| ~mbsys_i/mdm_1/U0/Dbg_Update_0                    |                                                                                                                                                                                                           | mbsys_i/mdm_1/U0/MDM_Core_I1/sel_n_reset                                                                                                                                                                   |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[5].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[2].tc_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/U_ICON/U_CMD/I11[0]                                                                                                                                                                           |                1 |              4 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD5/SR[0]                                                                                                                                                      |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/clear                                                                                                                                     |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/n_0_BIT_COUNT[3]_i_1                                                                                                             |                                                                                                                                                                                                            |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_address_filters[0].configurable_match_cap[0]_i_2                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_address_filters[0].configurable_match_cap[0]_i_1                                                                                              |                1 |              4 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/O2                                                                                                                                                                              |                                                                                                                                                                                                            |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[2].cnt_srl_reg/clear                                                                                                                                     |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_pma_reset_pipe[3]_i_1                                                                                                                                                |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[4].mu_srl_reg/clear                                                                                                                                           |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/sgmii_clk_en                                                                                                                                                            | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/REG5_OUT                                                                                                                                    |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_async_rst0_i_1__2                                                                                                                             |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/n_0_reg_do[9]_i_1                                                                                                                                       |                2 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/rst_clk_wiz_1_100M/U0/EXT_LPF/lpf_int                                                                                                                                                              |                4 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/enablealign                                                                                                                       |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/mgt_rx_reset                                                                                                                      |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_counter0                                                                                          | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram0                                                                                               |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | n_0_axi_we_axi_reg_4_i_1                                                                                                                                                                                   |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/mgt_tx_reset                                                                                                                      |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/ClkARst                                                                                                                                                |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/tx_init_in_prog                                                                                                                                                       |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_rst                                                                                                                                           |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_rx_rst_asynch                                                                                                                                 |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_tx_rst_asynch                                                                                                                                 |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/p_0_out                                                                                                             |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/p_1_out                                                                                                             |                2 |              5 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                          |                                                                                                                                                                                                            |                4 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_gtrxreset_in1_out                                                                                               |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/clk_div_stage1/reg5                                                                                                      |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6                                              |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/E[0]                                                                                                       | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                2 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                       |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CE_REG1_OUT7_out                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CE_REG5_OUT                                                                                                                                 |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/conf/int_tx_ifg_del_en                                                                                                         |                                                                                                                                                                                                            |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CE_REG1_OUT8_out                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CE_REG5_OUT                                                                                                                                 |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_6                                                                                         | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/I7[0]                                                                                                                                                  |                2 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Halted                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                4 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/REG5_OUT                                                                                                                                    |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/INT_CRC_MODE                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_STATUS_VALID_i_1                                                                                                                              |                3 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/n_0_ADDR_WR[4]_i_1                                                                                                               | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                              |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/p_8_in                                                                                                                      | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/SR[0]                                                                                                                                                         |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/clk_en                                                                                                                  | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/clk_div_stage2/reg5                                                                                                      |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_ADDSUB_I/n_0_mem_left_shift_4[0]_i_1                                                                              |                3 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/mdio_enabled.phy/mdio_clk_fall                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_state_count[5]_i_1                                                                                                                            |                2 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_load_count[2]_i_1                                                                                                                             |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx/data_count                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx/bad_pfc_opcode_int                                                                                                                        |                2 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2RX_CLIENT                                                                                                                                                       |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_capture_address[5]_i_1                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_mgmt_host_reset                                                                                                                               |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/n_0_reg_do[15]_i_1                                                                                                                                      |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/O4[0]                                                                                                                        |                                                                                                                                                                                                            |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_int_ma_clk_divide[5]_i_1                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_mgmt_host_reset                                                                                                                               |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_IFG_COUNT[7]_i_2                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_IFG_COUNT[7]_i_1                                                                                                                              |                3 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                                  |                4 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/sgmii_logic/gen_sync_reset/reset_sync6                                                                                                            |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | n_0_axi_we_axi_reg_5_i_1                                                                                                                                                                                   |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/O1                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[5].Gen_Instr_DFF/use_Reg_Neg_DI                                                            |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gdcf.dc/cntr_en                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/srst_wrst_busy                                   |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/halt_detection_inst/SS[0]                                                                                                                                      |                3 |              6 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_count[0]__0_i_1                                                                                                                                           |                                                                                                                                                                                                            |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_mdio_enabled.count_int[5]_i_1                                                                                                                 |                1 |              6 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/Q[2]                                                             |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1                                                                                                                                                  |                2 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_FSM_sequential_receive_frame_current_state[4]_i_1                                                                                                                |                                                                                                                                                                                                            |                2 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_counter[5]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_counter[5]_i_1                                                                                                                                |                2 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_quanta_count[5]_i_1                                                                                                                           |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/n_0_icount_out[5]_i_1                                                                                                                                                | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bus2ip_reset                                                                                                                                                          |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/p_2_out[0]                                                                                                        | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/U_NS1/O3                                                                                                                                                         |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/rst_clk_wiz_1_100M/U0/SEQ/seq_cnt_en                                                                                                                                                              | mbsys_i/rst_clk_wiz_1_100M/U0/SEQ/SEQ_COUNTER/clear                                                                                                                                                        |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/p_8_out[0]                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_next_count_read[6]_i_1                                                                                                                        |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/conf/int_rx_ps_lt_disable                                                                                                      |                                                                                                                                                                                                            |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/clear                                                                                                                                                |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/n_0_tx_pause_frame_i_1                                                                                                                                               |                                                                                                                                                                                                            |                1 |              7 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_LT_CHECK_HELD_i_1                                                                                                                            | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_time_cnt[6]_i_2                                                                                                                                                | mbsys_i/axi_ethernet_0/U0/pcs_pma/clear                                                                                                                                                                    |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/p_0_in13_out                                                                                                                                               |                                                                                                                                                                                                            |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_time_cnt[6]_i_2__0                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_time_cnt[6]_i_1__0                                                                                                                                              |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst                                                                                                                                                    |                3 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/start2                                                                                                                                              | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                                                                                                                  |                1 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_init_wait_count[6]_i_1                                                                                                                                              | mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out                                                                                                                                                            |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_init_wait_count[6]_i_1__0                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out                                                                                                                                                            |                2 |              7 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_Tx_Client_TxC_2_Mem_Addr_int[2]_i_1                                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_Tx_Client_TxC_2_Mem_Addr_int[9]_i_1                                                                                                                               |                1 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/n_0_bus2ip_addr_i[8]_i_1                                                                                                              | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                    |                1 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/srst_wrst_busy                                   |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/clear                                                                                                                                                 |                1 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/SR[0]                                                                                                                                      |                3 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.TX_FIFO_I/CI                                                                                                                                         |                                                                                                                                                                                                            |                1 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_init_wait_count[7]_i_1                                                                                                                                              |                                                                                                                                                                                                            |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_CORE_DOES_NO_HD_IFG.INT_IFG_DEL_MASKED[7]_i_1                                                                                                 |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/CE027_out                                                                                                                                 | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                5 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/O10                                                                                                                                                      | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                4 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/O12                                                                                                                                                      | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                4 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/O9                                                                                                                                                       | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axis_mac_tready                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                3 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_update_bram_cnt[7]_i_2                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/update_bram_cnt0                                                                                      |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[2]                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int2q                                                                                                                |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int2q                                                                                                         |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int1q                                                                                                         |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_shim/rx_mac_tdata0                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/ADV_TRIG_MEM_READ.u_fsm_memory_read_inst/E[0]                                                                                                                                  |                                                                                                                                                                                                            |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gmii_isolate                                                                                                                      |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_tx_data[7]_i_1                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                3 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                 |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_pause_opcode_early[7]_i_1                                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx/bad_pfc_opcode_int                                                                                                                        |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_XSDB_BUS_CONTROLLER/O2[0]                                                                                                                                                       | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/Q[1]                                                             |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_X36_1I263_i_1__0                                                                                                                             |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int3q                                                                                                         |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Use_UART.tdo_reg[0]_i_1                                                                                                                                   |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter0                                                                                                                                                  |                                                                                                                                                                                                            |                3 |              8 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/E[0]                                                                                                                                                          |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_X36_1I263_i_1                                                                                                                                |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].address_hit_I/Compare[0].SRLC16E_I/SRL16_En                         |                                                                                                                                                                                                            |                7 |              8 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_10                                                                                                                                                    |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/set_byte_en_pipe[1]                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                1 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/set_byte_en_pipe[0]                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                1 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_txd[7]_i_1                                                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_pause_value_sample[7]_i_1                                                                                                                     |                1 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/ADV_TRIG_MEM_READ.u_fsm_memory_read_inst/n_0_CFG_DATA_O[15]_i_1                                                                                                                 |                1 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int3q                                                                                                                |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/O4                                                                                                          |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxs_mem_addr_cntr[8]_i_1                                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_Axi_Str_TxC_2_Mem_Addr_int[9]_i_1                                                                                                                                 |                4 |              8 |
| ~mbsys_i/mdm_1/U0/Dbg_Update_0                    | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1                                                                                                                                            |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/O11                                                                                                                                                      | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int1q                                                                                                                |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_pause_source_shift[47]_i_1                                                                                                                    |                5 |              8 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/U_ICON/U_SYNC/SR[0]                                                                                                                                                                           |                2 |              8 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/E[0]                                | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/Q[2]                                                             |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_DATA_REG[3][7]_i_1                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_DATA_REG[2][7]_i_1                                                                                                                            |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[7]_i_1                                                                                                                 | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                       |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_ClkBAxiEthBClkCrsBusOut[7]_i_1                                                                                                                                   |                                                                                                                                                                                                            |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/set_byte_en                                                                                                                            | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                3 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.RX_FIFO_I/CI                                                                                                                                         |                                                                                                                                                                                                            |                1 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_stats_block.statistics_counters/tx_byte_counter/SYNC_STATS_RESET/sync_rst1_reg                                                                |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/Axi_Str_TxC_AReset                                                                                                                                          |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_AUTO_NEG.AUTO_NEGOTIATION/PULSE4096                                                                            | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/n_0_LINK_TIMER[8]_i_1                                                                                                             |                2 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/p_79_in                                                                                               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                4 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxs_mem_last_read_out_ptr_toconvertto_gray_clean[8]_i_1                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |                2 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxs_mem_last_read_out_ptr_true_reg[8]_i_1                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |                4 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxs_mem_next_available4write_ptr_1_reg[8]_i_1                                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |                3 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/rxs_mem_last_read_out_ptr_toconvertto_gray0                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |                2 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/CE                                                                                                                                        | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                4 |              9 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6                                             |                2 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[5]                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |                2 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/reset2axi_str_txd                                                                                                                                                     |                6 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxs_mem_next_available4write_ptr_reg[8]_i_1                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |                3 |              9 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/sgmii_clk_en                                                                                                                                                            | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/REG0_OUT2                                                                                                                                   |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_mmcm_lock_count[9]_i_2                                                                                                                                              | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_mmcm_lock_count[9]_i_1                                                                                                                                               |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_mmcm_lock_count[9]_i_2__0                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_mmcm_lock_count[9]_i_1__0                                                                                                                                            |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxd_mem_next_available4write_ptr_1_reg[9]_i_1                                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_Axi_Str_TxC_2_Mem_Din_int[9]_i_1                                                                                                                                  |                6 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/p_14_out                                                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/srst_wrst_busy                                   |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxd_mem_last_read_out_ptr_reg[9]_i_1                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxd_mem_addr_cntr[9]_i_1__0                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/srst_wrst_busy                                   |                4 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/txd_rd_pntr_10                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/reset2axi_str_txd                                                                                                                                                     |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCE/E[0]                                                                                                                   | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_sample_counter/U_SCRST/SR[0]                                                                                                                 |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/E[0]                                                                                                                                                          |                                                                                                                                                                                                            |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/txd_mem_full1                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/reset2axi_str_txd                                                                                                                                                     |                5 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/xsdb_memory_read_inst/n_0_read_addr[9]_i_1                                                                                                                                     |                                                                                                                                                                                                            |                4 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/txc_rd_addr2_pntr_10                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_FSM_sequential_txc_wr_cs[3]_i_1                                                                                                                                   |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_gcc0.gc0.count_d1[4]_i_1                                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/srst_wrst_busy                                   |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2PCSPMA                                                                                                                                                          |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_Tx_Client_TxC_2_Mem_Din_int[9]_i_1                                                                                                                                |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_cap_ctrl/u_cap_addrgen/u_cap_window_counter/U_WCE/E[0]                                                                                                                   | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/Q[0]                                                                                                                                                           |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/PLL0RESET_IN                                                                                                                                                          |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/txc_wr_pntr_10                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                3 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxd_mem_addr_cntr[9]_i_1                                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                3 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_txc_wr_pntr[9]_i_1                                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_update_bram_cnt_reg[9]_i_2                                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/update_bram_cnt0                                                                                                                        |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_txd_rd_pntr[9]_i_1                                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/reset2axi_str_txd                                                                                                                                                     |                4 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_txc_rd_addr2_pntr[9]_i_1                                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_FSM_sequential_txc_wr_cs[3]_i_1                                                                                                                                   |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/REG0_OUT2                                                                                                                                   |                3 |             10 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/bscan_inst/I4[0]                                                                                                                                                                             | dbg_hub/inst/bscan_inst/AR[0]                                                                                                                                                                              |                4 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/vector_decode_inst/rx_stats_valid                                                                                                                                    |                                                                                                                                                                                                            |                4 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_LENGTH_TYPE[10]_i_1                                                                                                                           |                4 |             11 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/rxd_mem_last_read_out_ptr_gray_d10                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |                5 |             11 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_DATA_COUNTER[10]_i_2                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_DATA_COUNTER[10]_i_1                                                                                                                          |                3 |             11 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           |                                                                                                                                                                                                            |                6 |             11 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_FSM_sequential_txc_wr_cs[3]_i_1                                                                                                                                   |                8 |             11 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0]                                | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/O1[1]                                                            |                2 |             12 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_int_ma_mdio_op[1]_i_1                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_mgmt_host_reset                                                                                                                               |                3 |             12 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_txd_rd_addr[0]_i_1                                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                4 |             12 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/eqOp                                                                                                                | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1                                                                                                                                                  |                3 |             12 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg30                                                                                                       | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_counter_stg1[5]_i_1                                                                                                                                                  |                3 |             12 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_XSDB_BUS_CONTROLLER/E[0]                                                                                                                                                        | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/O1[1]                                                            |                4 |             12 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/txc_rd_end_dly1                                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                4 |             12 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_phy_reset_count[0]_i_1                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_COMBINE_RESETS/AXI_RESET_TO_GTX/ClkB_reset_inst/sync_rst1_reg                                                                                                     |                4 |             12 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/RECEIVER/SYNC_STATUS_REG0                                                                                           |                5 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/cntr_en            | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                            |                4 |             13 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rxrecreset                                                                                                                           |                5 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/O28                            | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                             |                4 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[0]                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |                6 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/O30               | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                             |                4 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/E[0]                                                                                                                                | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/sig_Bus2IP_Reset                                                                                                                                            |                3 |             13 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2__0                                                                                                                                         | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_1__0                                                                                                                                          |                4 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/start2                                                                                                                                        | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/O19                                                                                                                                                         |                3 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/WR_RST                                         |                4 |             14 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0]                                                                                                                 |                6 |             14 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_STATISTICS_LENGTH[13]_i_1                                                                                                                    |                                                                                                                                                                                                            |                3 |             14 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/AR[0]                                           |                4 |             14 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/MDC_RISING_REG1                                                                                | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                              |                5 |             14 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/ClkBRst                                                                                                                                                               |                4 |             14 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_int_rx_frame_length[14]_i_1                                                                                                                  |                                                                                                                                                                                                            |                3 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_BYTE_COUNT[0][14]_i_1                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_STATUS_VALID_i_1                                                                                                                              |                3 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_MAX_FRAME_LENGTH_HELD[14]_i_1                                                                                                                | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                3 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/Q[1]                                                                                                                                                           |                9 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_int_tx_frame_length[14]_i_1                                                                                                                  |                                                                                                                                                                                                            |                2 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/pma_reset_out                                                                                                                                                            |                9 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_AUTO_NEG.AUTO_NEGOTIATION/RX_CONFIG_SNAPSHOT                                                                   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                              |                3 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_STATISTICS_LENGTH[13]_i_1                                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_LENGTH_TYPE[10]_i_1                                                                                                                           |                5 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/data_out                                                                                                            |                6 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/fifoWrEn                                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxd_word_cnt[0]_i_1                                                                                                                                               |                5 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_6/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__10                                                                                                                   |                                                                                                                                                                                                            |                6 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_pause_count[0]_i_1                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                5 |             16 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/E[0]                                                                                                                                                                            | dbg_hub/inst/U_ICON/U_CMD/O9[0]                                                                                                                                                                            |                4 |             16 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/I9[0]                                                                                                                                                                           | dbg_hub/inst/U_ICON/U_CMD/O9[0]                                                                                                                                                                            |                2 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_compare_wr[0]                                                                                            |                                                                                                                                                                                                            |                4 |             16 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O2[0]                               |                                                                                                                                                                                                            |                3 |             16 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O3                                  |                                                                                                                                                                                                            |                5 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_LEN[15]_i_1                                                                                                                                  | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_STATUS_VALID_i_1                                                                                                                              |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_16/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1                                                                                                                      |                                                                                                                                                                                                            |                9 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_bus2ip_addr_i[17]_i_1                                                                                                                                            | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                |                5 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/load_wr                                                                                                      |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_addr_filter_top/address_filter_inst/addr_reg_cpu_field_wr.ram_field_wr_uc_reg                                                                |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_frame_length_bytes[0]_i_2                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_frame_length_bytes[0]_i_1                                                                                                                                         |                5 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_7/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__3                                                                                                                    |                                                                                                                                                                                                            |                6 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_18/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__11                                                                                                                  |                                                                                                                                                                                                            |                8 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_17/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__2                                                                                                                   |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_int_ma_tx_data[15]_i_1                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_mgmt_host_reset                                                                                                                               |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_84/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__15                                                                                                                  |                                                                                                                                                                                                            |                5 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_83/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__4                                                                                                                   |                                                                                                                                                                                                            |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__1                                                                                                                   |                                                                                                                                                                                                            |                8 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_81/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__13                                                                                                                  |                                                                                                                                                                                                            |                5 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_85/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__0                                                                                                                   |                                                                                                                                                                                                            |                7 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_ClkBSignalOut_i_1__6                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/ClkBRst                                                                                                                                                               |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_82/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__14                                                                                                                  |                                                                                                                                                                                                            |                5 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_80/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__12                                                                                                                  |                                                                                                                                                                                                            |                7 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/adv_rb_drdy1                                                                                                                                                        |                                                                                                                                                                                                            |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/ADV_TRIG_STREAM.reg_stream_ffc/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__8                                                                                           |                                                                                                                                                                                                            |                3 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_raw_checksum[15]_i_1                                                                                                                                              |                8 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/reg_test0                                                                                                                                              |                                                                                                                                                                                                            |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__5                                                                                                                   |                                                                                                                                                                                                            |                6 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/ADV_TRIG_MEM_READ.u_fsm_memory_read_inst/n_0_BRAM_DATA[15]_i_1                                                                                                                 |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_19/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__6                                                                                                                   |                                                                                                                                                                                                            |                7 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_stream_ffd/I_EN_CTL_EQ1.U_CTL/n_0_xsdb_reg[15]_i_1__7                                                                                                           |                                                                                                                                                                                                            |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_field_wr[3]                                                                                              |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_field_wr[2]                                                                                              |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/xsdb_memory_read_inst/E[0]                                                                                                                                                     |                                                                                                                                                                                                            |                8 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[1]                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_XSDB_BUS_CONTROLLER/O1                                                                                                                                                          |                                                                                                                                                                                                            |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[9]                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |                5 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_rd_data[15]_i_1__0                                                                                                                                                  | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_sync6                                              |                5 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_rd_data[15]_i_1                                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_sync6                                             |                5 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/original_rd_data0                                                         |                                                                                                                                                                                                            |                3 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/original_rd_data0                                                        |                                                                                                                                                                                                            |                2 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/RX_CONFIG_VALID                                                                                                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_AUTO_NEG.AUTO_NEGOTIATION/RX_CONFIG_REG_REG0                                                                    |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/MDIO_INTERFACE_1/SHIFT_REG0                                                                    |                                                                                                                                                                                                            |                5 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/n_0_slaveRegDo_mux_3[15]_i_1                                                                                                                                         |                6 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/n_0_slaveRegDo_mux_6[15]_i_1                                                                                                                                         |                5 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[5].Gen_Instr_DFF/I77[0]                                                                   | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                6 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/wepa                                                                                                             |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/conf/int_ma_rx_data0                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_mgmt_host_reset                                                                                                                               |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_field_wr[1]                                                                                              |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/Q[0]                                                             |                3 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_pause_value_to_tx[15]_i_1                                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | n_0_axi_addr_write[15]_i_2                                                                                                                                                                                | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |                3 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_pause_value[15]_i_1                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |                3 |             16 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/Q[1]                                                             |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_clk_a2b_bus[15]_i_1                                                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2PCSPMA                                                                                                                                                          |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_field_wr[0]                                                                                              |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_compare_wr[3]                                                                                            |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_compare_wr[2]                                                                                            |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_compare_wr[1]                                                                                            |                                                                                                                                                                                                            |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/BUS2IP_CS                                                                                                                                                            | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/Shim2IP_CS1                                                                                                                                               |                6 |             17 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2                                                                                                                                | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                                                                                                    |                3 |             17 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/O1[0]                                                            |                3 |             17 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_STATUS_VALID_i_1                                                                                                                              |                6 |             17 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_6                                                                                         | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Data_Flow_Logic_I/SR[0]                                                                                                             |                6 |             17 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_2                                                                                                                                            | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_wait_bypass_count[0]_i_1                                                                                                                                             |                5 |             17 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/n_0_addr[16]_i_1                                                                                                                                        | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/O1                                                                                                                                                         |                5 |             17 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_XSDB_BURST_WD_LEN_CONTROLLER/n_0_burst_wd[0]_i_1                                                                                                                                | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/O1                                                                                                                                                         |                5 |             17 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                             |                7 |             18 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD5/n_0_ctl_reg[17]_i_1                                                                                                                                       | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/O1                                                                                                                                                         |                3 |             18 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/O5                                                                                                                                                                              | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/O1                                                                                                                                                         |                3 |             18 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v1_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/O1[0]                                                            |                3 |             18 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/p_0_in                                                                                                                                                | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_COMBINE_RESETS/AXI_RESET_TO_GTX/ClkB_reset_inst/sync_rst1_reg                                                                                                     |                4 |             19 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter[0]_i_1                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/reset_time_out                                                                                                                                                           |                5 |             19 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/mm2s_prmry_reset_out_n                                                                                                                                      |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0]                          | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                 |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                           |                6 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/COUNTER.u_count/G_COUNTER[0].U_COUNTER/n_0_counter[16]_i_1                                                                                                                     |                                                                                                                                                                                                            |                5 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/mm2s_cntrl_reset_out_n                                                                                                                                      |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_txd_rd_pntr_hold_plus3[9]_i_1                                                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/reset2axi_str_txd                                                                                                                                                     |                5 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/COUNTER.u_count/G_COUNTER[3].U_COUNTER/n_0_counter[16]_i_1                                                                                                                     |                                                                                                                                                                                                            |                5 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/ClkARst                                                                                                                                                |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_6                                                                                         | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                9 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_time_out_counter[0]_i_1__0                                                                                                                                          | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/reset_time_out_reg                                                                             |                5 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/COUNTER.u_count/G_COUNTER[2].U_COUNTER/n_0_counter[16]_i_1                                                                                                                     |                                                                                                                                                                                                            |                5 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/COUNTER.u_count/G_COUNTER[1].U_COUNTER/n_0_counter[16]_i_1                                                                                                                     |                                                                                                                                                                                                            |                7 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                            |                8 |             21 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_6                                                                                         | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/O3[0]                                                                                                       |                6 |             21 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O10[0]                        | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                 |               22 |             22 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_axi_arvalid[5]                                                                                                     | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |                6 |             22 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_toggle_i_1                                                                                                                                                          | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/mgt_tx_reset                                                                                                                      |                6 |             22 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O2[0]                         | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                 |               11 |             22 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/O15                | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/O24                 |                8 |             22 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   |                                                                                                                                                                                                           | mbsys_i/mdm_1/U0/MDM_Core_I1/shift_n_reset                                                                                                                                                                 |                5 |             23 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/sig_Bus2IP_Reset                                                                                                                                            |               16 |             23 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_INT_MAX_FRAME_LENGTH[14]_i_1                                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_STATUS_VALID_i_1                                                                                                                              |                5 |             23 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0]               | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/AR[0]                                           |                4 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_XSDB_BUS_CONTROLLER/E[0]                                                                                                                                                        |                                                                                                                                                                                                            |                3 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/sel               | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                           |                3 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bus2ip_reset                                                                                                                                                          |               11 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/mem_div_iterate1                                                                                      |                                                                                                                                                                                                            |                8 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/O1                                                                                                         | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/mem_reset_Q                                                                                                 |                5 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/n_0_mem_R[7]_i_1                                                                                           |                                                                                                                                                                                                            |                6 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/sel                | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                            |                4 |             24 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/sync_rst1                                                                                                         |                6 |             24 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v1_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0]                                |                                                                                                                                                                                                            |                3 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                7 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[10].mu_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                5 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[2].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                5 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_frame_length_words[14]_i_1                                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |               10 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                4 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[5].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                6 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[1].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                5 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[4].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                6 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[12].mu_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                6 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                5 |             25 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/SR[0]                                                                                                                                                         |                9 |             26 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Data_Flow_Logic_I/O8[0]                                                                                                             |                7 |             26 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_statistics_valid                                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rx_statistics_vector_i[26]_i_1                                                                                                                                    |                9 |             26 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_statistics_vector[25]_i_1                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                4 |             26 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/O1                                                                                                                                                         |               13 |             27 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD4/n_0_ctl_reg[27]_i_1                                                                                                                                       | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/O1                                                                                                                                                         |                8 |             28 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/p_0_in45_in                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_count_read[6]_i_1                                                                                                                             |                7 |             28 |
|  dbg_hub/inst/idrck                               | dbg_hub/inst/U_ICON/U_CMD/O4                                                                                                                                                                              | dbg_hub/inst/UUT_MASTER/U_ICON_INTERFACE/U_CMD1/O1                                                                                                                                                         |                4 |             28 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rxs_mem_next_available4write_ptr_reg[8]_i_1__0                                                                                                                   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                9 |             28 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |               15 |             28 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_mdio_data[30]_i_1                                                                                                                            |                                                                                                                                                                                                            |                5 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O10                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O1                                |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O9                                |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O8                                |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O7                                |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O6                                |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_txc_mem_wr_addr_0[9]_i_1                                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_FSM_sequential_txc_wr_cs[3]_i_1                                                                                                                                   |                6 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O15                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O14                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O13                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O5                                |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O11                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O18                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O17                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O4                                |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O12                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O16                               |                                                                                                                                                                                                            |                8 |             30 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/mgt_rx_reset                                                                                                                      |               11 |             31 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/CFG_BRAM_RD_DATA0                                                                                                                                          |                                                                                                                                                                                                            |                6 |             31 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/txd_wr_en                                                                                                                                                  | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/n_0_gtxd.sig_txd_packet_size[0]_i_1                                                                                                                         |                8 |             31 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_STATUS_VALID_i_1                                                                                                                              |               10 |             31 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[11]                                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_24                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/n_0_sig_ip2bus_data[0]_i_1                                                                                                                                  |               21 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/txd_wr_en                                                                                                                                                  | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                             |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_25                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/I48[0]                                                                                                                              | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/sig_Bus2IP_Reset                                                                                                                                            |               17 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_26                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[31]_i_1__2                                                                                                                        |                6 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_27                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_wrce[0]                                                                                                                            | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |               10 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[31]_i_1                                                                                                                           | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                                  |               32 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[31]_i_1__0                                                                                                                        |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/INPUT_DOUBLE_REGS3/E[0]                                                                                                                                  | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                6 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/INPUT_DOUBLE_REGS3/O21[0]                                                                                                                                | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                |                5 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_28                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_29                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_3                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_32                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_33                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_34                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[6]                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |               10 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[7]                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_35                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[8]                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_4                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               17 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_36                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_37                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_38                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/Shim2IP_WrCE[10]                                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_39                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_5                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I8[0]                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_6                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               17 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_7                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_8                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               17 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/E[0]                                                                                                  | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_9                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_s_axi_rdata_i[31]_i_1                                                                                                                                            | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                |                6 |             32 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_txgen/TX_SM1/PREAMBLE_PIPE_reg[2]                                                                                                             |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | n_0_axi_we_axi_reg_10_reg                                                                                                                                                                                 | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_15                                                                                        | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_Logic_I/R                                                                                                                             |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | n_0_axi_we_axi_reg_20_reg                                                                                                                                                                                 | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | n_0_axi_we_axi_reg_30_reg                                                                                                                                                                                 | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[31]_i_1                                                                                                                     | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                            |               16 |             32 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_CALC[31]_i_2                                                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_CALC[31]_i_1__0                                                                                                                               |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/n_0_s_axi_rdata_reg[31]_i_1                                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bus2ip_reset                                                                                                                                                          |               10 |             32 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Dbg_Instr_TCK                                                                                       |                                                                                                                                                                                                            |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/p_51_in                                                                                              |                                                                                                                                                                                                            |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_6                                                                                         | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/SR[0]                                                                                                                                                  |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/Q[4]                                                                                                                                                           |                6 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Start_Div                                                                                                                          |                                                                                                                                                                                                            |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/Q[3]                                                                                                                                                           |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/Q[2]                                                                                                                                                           |               32 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/I6[0]                                                                                                                                                  |               27 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/I76[0]                                                                                                                                | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Start_Div                                                                                                                           |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_13                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[31]_i_1                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                    |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/irq                                                                                                                                                          |                                                                                                                                                                                                            |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_rvalid[0]                                                                                                      | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/p_0_in1_in                                                                                                           | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0]                                                                                                                 |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_cpu_data_shift[31]_i_1                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_mgmt_host_reset                                                                                                                               |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_axi_wvalid[5]                                                                                                      | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               10 |             32 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_bytes_14_and_15_d19[15]_i_1                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[31]_i_2                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/n_0_ip2bus_data[31]_i_1                                                                                                                           |               10 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_0                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_1                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_11                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_12                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               18 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_31                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_14                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               17 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_15                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_16                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_17                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_18                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               17 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_19                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_2                                                                                                                                                                                          | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_21                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_22                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | axi_we_axi_reg_23                                                                                                                                                                                         | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                 |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Q0                                                                                                      | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/I75[0]                                                                                                                   |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[5].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[26].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[15].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[29].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                7 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[6].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[17].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[11].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                6 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[12].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                7 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[2].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                7 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[22].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[20].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[31].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[13].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |               11 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[21].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |               11 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[30].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[24].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                9 |             33 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/p_8_out[0]                                                                                                       |                                                                                                                                                                                                            |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/E[0]                                                                                                                 |                                                                                                                                                                                                            |               17 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[1].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/reg_slice_r/aa_rready                                                                                                                  |                                                                                                                                                                                                            |               15 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[25].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[23].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                7 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[7].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                7 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[4].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[8].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                7 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[14].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[9].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[16].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |               10 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[10].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |               12 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[0].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |               10 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[18].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[3].tc_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[27].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |               10 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O16[0]             |                                                                                                                                                                                                            |               14 |             33 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_COMBINE_RESETS/AXI_RESET_TO_GTX/ClkB_reset_inst/sync_rst1_reg                                                                                                     |                8 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[19].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/TC_SRL[28].tc_srl_reg/shift_en_o                                                                                                                                    |                                                                                                                                                                                                            |                7 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_6                                                                                         |                                                                                                                                                                                                            |                8 |             34 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_gpr1.dout_i[35]_i_1                                                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/srst_wrst_busy                                   |                6 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0]              | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/WR_RST                                         |                7 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_15                                                                                        | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/I8[0]                                                                                                                                                  |               16 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/p_15_out                                                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/srst_wrst_busy                                   |               10 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O3[0]             |                                                                                                                                                                                                            |               13 |             37 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_reset_ctrl/Q[0]                                                                                                                                                           |               21 |             37 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[2].cnt_srl_reg/shift_en_o                                                                                                                               |                                                                                                                                                                                                            |               10 |             37 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[1].cnt_srl_reg/shift_en_o                                                                                                                               |                                                                                                                                                                                                            |               11 |             37 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[0].cnt_srl_reg/shift_en_o                                                                                                                               |                                                                                                                                                                                                            |               10 |             37 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/CNT.CNT_SRL[3].cnt_srl_reg/shift_en_o                                                                                                                               |                                                                                                                                                                                                            |               10 |             37 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out | mbsys_i/axi_ethernet_0/U0/pcs_pma/wr_enable                                                                                                                                                               |                                                                                                                                                                                                            |               10 |             40 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk_out    |                                                                                                                                                                                                           |                                                                                                                                                                                                            |               12 |             40 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/O3                             |                8 |             40 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O3                            | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                 |               12 |             42 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/rd_enable                                                                                                                                                               | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reset_modified                                                                                                |                8 |             43 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/mgt_tx_reset                                                                                                                      |               12 |             47 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_multicast_addr_upper_d10[15]_i_1                                                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |               11 |             48 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/O85                                                                                                   | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |               16 |             48 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_gcc0.gc0.count_d1[4]_i_1                                                                                                                                         |                                                                                                                                                                                                            |                6 |             48 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[6].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                9 |             49 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[9].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                8 |             49 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                9 |             49 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/MU_SRL[0].mu_srl_reg/shift_en_o                                                                                                                                     |                                                                                                                                                                                                            |                8 |             49 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/sgmii_clk_en                                                                                                                                                            | mbsys_i/axi_ethernet_0/U0/pcs_pma/n_0_U0/pcs_pma_block_i/sgmii_logic/gen_sync_reset/reset_sync6                                                                                                            |               12 |             50 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_reset                                                                                                                                       |               16 |             51 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reset_modified                                                                                                |               11 |             53 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_data1                                                                                                      |               10 |             54 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_reset_out                                                                                                                                      |               24 |             60 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   | mbsys_i/mdm_1/U0/Dbg_Capture_0                                                                                                                                                                            |                                                                                                                                                                                                            |               19 |             61 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/n_0_fsm_mem_data_reg_r1_64_127_0_2_i_1                                                                                                                     |                                                                                                                                                                                                            |               16 |             64 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/O7                                                                                                                          |                                                                                                                                                                                                            |                8 |             64 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/ADV_TRIG.u_adv_trig/n_0_fsm_mem_data_reg_r1_0_63_0_2_i_1                                                                                                                       |                                                                                                                                                                                                            |               16 |             64 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_rx_data_valid_array[1][0]_i_1                                                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |               16 |             65 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/rxuserclk2_out |                                                                                                                                                                                                           |                                                                                                                                                                                                            |               15 |             69 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2AXI_STR_RXS                                                                                                                                                     |               28 |             69 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/s_den_o                                                                                                                                                |                                                                                                                                                                                                            |               20 |             69 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/U_ICON/U_CMD/O10                                                                                                                                                                              |               14 |             70 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/enb                                                                                                              |                                                                                                                                                                                                            |               17 |             72 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[4].Gen_Sel_DFF/O3                                                                              |                                                                                                                                                                                                            |               11 |             75 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/n_0_FSM_sequential_receive_frame_current_state[4]_i_1                                                                                                                | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |               28 |             77 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AxiReset                                                                                                                                                              |               21 |             85 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_ce_sample                                                                                                                                     |                                                                                                                                                                                                            |               24 |             85 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                    |                                                                                                                                                                                                           |                                                                                                                                                                                                            |               20 |             87 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                              |               28 |             93 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/p_0_in45_in                                                                                                      |                                                                                                                                                                                                            |               40 |             96 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/sgmii_clk_en                                                                                                                                                            |                                                                                                                                                                                                            |               37 |             98 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_srl_fff/shift_en_o                                                                                                                                              |                                                                                                                                                                                                            |               26 |             99 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                   |                                                                                                                                                                                                           |                                                                                                                                                                                                            |               35 |            114 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/pcs_pma/sgmii_clk_en                                                                                                                                                            | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |               42 |            122 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | U_CS_EAXI/U0/ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/use_probe_debug_circuit                                                                                                                    |               32 |            124 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/wea                                                                                                              |                                                                                                                                                                                                            |               32 |            128 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/O6[9]                                                                                                                                 |                                                                                                                                                                                                            |               16 |            128 |
|  dbg_hub/inst/idrck                               |                                                                                                                                                                                                           | dbg_hub/inst/U_ICON/U_CMD/SR[0]                                                                                                                                                                            |               28 |            135 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_15                                                                                        | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |               53 |            135 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/int_mgmt_host_reset                                                                                                                               |               42 |            157 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |               76 |            172 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RESET2PCSPMA                                                                                                                                                          |               29 |            204 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/O1                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                 |               65 |            216 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_reset_out                                                                                                                                      |               81 |            368 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/userclk2_out   |                                                                                                                                                                                                           |                                                                                                                                                                                                            |              293 |           1063 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                    |                                                                                                                                                                                                           |                                                                                                                                                                                                            |              852 |           2847 |
+---------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+


