*** Running vivado with args -log clk_wiz_0.vds -m64 -mode batch -messageDb vivado.pb -source clk_wiz_0.tcl ****** Vivado v2014.4.1 (64-bit) **** SW Build 1149489 on Thu Feb 19 16:20:35 MST 2015 **** IP Build 1147552 on Wed Feb 18 14:25:16 MST 2015 ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. source clk_wiz_0.tcl # set_param gui.test TreeTableDev # debug::add_scope template.lib 1 # set_msg_config -id {HDL 9-1061} -limit 100000 # set_msg_config -id {HDL 9-1654} -limit 100000 # create_project -in_memory -part xc7a200tfbg484-2 # set_param project.compositeFile.enableAutoGeneration 0 # set_param synth.vivado.isSynthRun true # set_msg_config -id {IP_Flow 19-2162} -severity warning -new_severity info # set_property webtalk.parent_dir C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.cache/wt [current_project] # set_property parent.project_path C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.xpr [current_project] # set_property default_lib xil_defaultlib [current_project] # set_property target_language VHDL [current_project] # read_ip C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2014.4/data/ip'. WARNING: [IP_Flow 19-3664] IP 'clk_wiz_0' generated file not found 'c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'clk_wiz_0' generated file not found 'c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'clk_wiz_0' generated file not found 'c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'clk_wiz_0' generated file not found 'c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'clk_wiz_0' generated file not found 'c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.vhdl'. Please regenerate to continue. # set_property used_in_implementation false [get_files -all c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp] # set_property is_locked true [get_files C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci] # read_xdc dont_touch.xdc # set_property used_in_implementation false [get_files dont_touch.xdc] # catch { write_hwdef -file clk_wiz_0.hwdef } INFO: [Vivado_Tcl 4-279] hardware handoff file cannot be generated as there is no block diagram instance in the design # synth_design -top clk_wiz_0 -part xc7a200tfbg484-2 -mode out_of_context Command: synth_design -top clk_wiz_0 -part xc7a200tfbg484-2 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t' --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 250.867 ; gain = 86.836 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vhd:89] INFO: [Synth 8-3491] module 'clk_wiz_0_clk_wiz' declared at 'c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:77' bound to instance 'U0' of component 'clk_wiz_0_clk_wiz' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vhd:107] INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:89] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: 1 - type: bool Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-113] binding component instance 'clkin1_ibufg' to cell 'IBUF' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:122] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT bound to: 8 - type: integer Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float Parameter CLKIN1_PERIOD bound to: 5.000000 - type: float Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float Parameter CLKOUT0_DIVIDE bound to: 51 - type: integer Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float Parameter CLKOUT1_DIVIDE bound to: 10 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float Parameter CLKOUT2_DIVIDE bound to: 40 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float Parameter CLKOUT3_DIVIDE bound to: 8 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float Parameter COMPENSATION bound to: ZHOLD - type: string Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 Parameter IS_PWRDWN_INVERTED bound to: 1'b0 Parameter IS_RST_INVERTED bound to: 1'b0 Parameter REF_JITTER1 bound to: 0.000000 - type: float Parameter REF_JITTER2 bound to: 0.000000 - type: float Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'plle2_adv_inst' to cell 'PLLE2_ADV' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:134] INFO: [Synth 8-113] binding component instance 'clkf_buf' to cell 'BUFG' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:187] INFO: [Synth 8-113] binding component instance 'clkout1_buf' to cell 'BUFG' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:194] INFO: [Synth 8-113] binding component instance 'clkout2_buf' to cell 'BUFG' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:201] INFO: [Synth 8-113] binding component instance 'clkout3_buf' to cell 'BUFG' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:206] INFO: [Synth 8-113] binding component instance 'clkout4_buf' to cell 'BUFG' [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:211] INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (1#1) [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.vhd:89] INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (2#1) [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vhd:89] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 284.965 ; gain = 120.934 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 284.965 ; gain = 120.934 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a200t/ClockRegion.xml Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a200t/ClockBuffers.xml Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/PinFunctions.xml... Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a200t/fbg484/Package.xml Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/artix7/IOStandards.xml Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/ConfigModes.xml INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'U0' Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'U0' Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'U0' Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'U0' Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'U0' Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'U0' INFO: [Timing 38-2] Deriving generated clocks INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to anoth XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc] Finished Parsing XDC File [C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc] Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 542.805 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a200tfbg484-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module clk_wiz_0 Detailed RTL Component Info : Module clk_wiz_0_clk_wiz Detailed RTL Component Info : --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 740 (col length:100) BRAMs: 730 (col length: RAMB18 100 RAMB36 50) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- Start Parallel Synthesis Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- Start Cross Boundary Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Cross Boundary Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- Finished Parallel Reinference : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 542.805 ; gain = 378.773 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Area Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- Finished Parallel Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 542.805 ; gain = 378.773 Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ Finished Parallel Synthesis Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 542.805 ; gain = 378.773 --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 570.973 ; gain = 406.941 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 570.973 ; gain = 406.941 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 580.359 ; gain = 416.328 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 580.359 ; gain = 416.328 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 580.359 ; gain = 416.328 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 580.359 ; gain = 416.328 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 5| |2 |PLLE2_ADV | 1| |3 |IBUF | 1| +------+----------+------+ Report Instance Areas: +------+---------+------------------+------+ | |Instance |Module |Cells | +------+---------+------------------+------+ |1 |top | | 7| |2 | U0 |clk_wiz_0_clk_wiz | 7| +------+---------+------------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 580.359 ; gain = 416.328 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:23 . Memory (MB): peak = 580.359 ; gain = 119.078 Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 580.359 ; gain = 416.328 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'U0' Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'U0' Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'U0' Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'U0' Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'U0' INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:56] INFO: [Timing 38-2] Deriving generated clocks [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:56] get_clocks: Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1022.961 ; gain = 427.484 Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'U0' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 28 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 1022.961 ; gain = 822.070 # rename_ref -prefix_all clk_wiz_0_ # write_checkpoint -noxdef clk_wiz_0.dcp # catch { report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb } report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1022.961 ; gain = 0.000 # if { [catch { # file copy -force C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp # } _RESULT ] } { # error "ERROR: Unable to successfully create or copy the sub-design checkpoint file." # } # if { [catch { # write_verilog -force -mode synth_stub C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v # } _RESULT ] } { # puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" # } # if { [catch { # write_vhdl -force -mode synth_stub C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl # } _RESULT ] } { # puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" # } # if { [catch { # write_verilog -force -mode funcsim C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.v # } _RESULT ] } { # puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" # } # if { [catch { # write_vhdl -force -mode funcsim C:/Users/kjohns/Documents/a7_mmfe_xadc_udp_v2.xpr/a7_mmfe_xadc_udp_v2/a7_mmfe_xadc_udp_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.vhdl # } _RESULT ] } { # puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" # } INFO: [Common 17-206] Exiting Vivado at Wed Apr 22 09:08:54 2015...