-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:microblaze:9.4 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY microblaze_v9_4; USE microblaze_v9_4.MicroBlaze; ENTITY mbsys_microblaze_0_0 IS PORT ( Clk : IN STD_LOGIC; Reset : IN STD_LOGIC; Interrupt : IN STD_LOGIC; Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31); Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1); Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31); Instr : IN STD_LOGIC_VECTOR(0 TO 31); IFetch : OUT STD_LOGIC; I_AS : OUT STD_LOGIC; IReady : IN STD_LOGIC; IWAIT : IN STD_LOGIC; ICE : IN STD_LOGIC; IUE : IN STD_LOGIC; Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31); Data_Read : IN STD_LOGIC_VECTOR(0 TO 31); Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31); D_AS : OUT STD_LOGIC; Read_Strobe : OUT STD_LOGIC; Write_Strobe : OUT STD_LOGIC; DReady : IN STD_LOGIC; DWait : IN STD_LOGIC; DCE : IN STD_LOGIC; DUE : IN STD_LOGIC; Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3); M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DP_AWVALID : OUT STD_LOGIC; M_AXI_DP_AWREADY : IN STD_LOGIC; M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DP_WVALID : OUT STD_LOGIC; M_AXI_DP_WREADY : IN STD_LOGIC; M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DP_BVALID : IN STD_LOGIC; M_AXI_DP_BREADY : OUT STD_LOGIC; M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DP_ARVALID : OUT STD_LOGIC; M_AXI_DP_ARREADY : IN STD_LOGIC; M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DP_RVALID : IN STD_LOGIC; M_AXI_DP_RREADY : OUT STD_LOGIC; Dbg_Clk : IN STD_LOGIC; Dbg_TDI : IN STD_LOGIC; Dbg_TDO : OUT STD_LOGIC; Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7); Dbg_Shift : IN STD_LOGIC; Dbg_Capture : IN STD_LOGIC; Dbg_Update : IN STD_LOGIC; Debug_Rst : IN STD_LOGIC; M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_AWLOCK : OUT STD_LOGIC; M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_AWVALID : OUT STD_LOGIC; M_AXI_IC_AWREADY : IN STD_LOGIC; M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_WLAST : OUT STD_LOGIC; M_AXI_IC_WVALID : OUT STD_LOGIC; M_AXI_IC_WREADY : IN STD_LOGIC; M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_BVALID : IN STD_LOGIC; M_AXI_IC_BREADY : OUT STD_LOGIC; M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_ARLOCK : OUT STD_LOGIC; M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_ARVALID : OUT STD_LOGIC; M_AXI_IC_ARREADY : IN STD_LOGIC; M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_RLAST : IN STD_LOGIC; M_AXI_IC_RVALID : IN STD_LOGIC; M_AXI_IC_RREADY : OUT STD_LOGIC; M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_AWLOCK : OUT STD_LOGIC; M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_AWVALID : OUT STD_LOGIC; M_AXI_DC_AWREADY : IN STD_LOGIC; M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_WLAST : OUT STD_LOGIC; M_AXI_DC_WVALID : OUT STD_LOGIC; M_AXI_DC_WREADY : IN STD_LOGIC; M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_BVALID : IN STD_LOGIC; M_AXI_DC_BREADY : OUT STD_LOGIC; M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_ARLOCK : OUT STD_LOGIC; M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_ARVALID : OUT STD_LOGIC; M_AXI_DC_ARREADY : IN STD_LOGIC; M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_RLAST : IN STD_LOGIC; M_AXI_DC_RVALID : IN STD_LOGIC; M_AXI_DC_RREADY : OUT STD_LOGIC ); END mbsys_microblaze_0_0; ARCHITECTURE mbsys_microblaze_0_0_arch OF mbsys_microblaze_0_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF mbsys_microblaze_0_0_arch: ARCHITECTURE IS "yes"; COMPONENT MicroBlaze IS GENERIC ( C_SCO : INTEGER; C_FREQ : INTEGER; C_USE_CONFIG_RESET : INTEGER; C_NUM_SYNC_FF_CLK : INTEGER; C_NUM_SYNC_FF_CLK_IRQ : INTEGER; C_NUM_SYNC_FF_CLK_DEBUG : INTEGER; C_NUM_SYNC_FF_DBG_CLK : INTEGER; C_FAULT_TOLERANT : INTEGER; C_ECC_USE_CE_EXCEPTION : INTEGER; C_LOCKSTEP_SLAVE : INTEGER; C_ENDIANNESS : INTEGER; C_FAMILY : STRING; C_DATA_SIZE : INTEGER; C_INSTANCE : STRING; C_AVOID_PRIMITIVES : INTEGER; C_AREA_OPTIMIZED : INTEGER; C_OPTIMIZATION : INTEGER; C_INTERCONNECT : INTEGER; C_BASE_VECTORS : STD_LOGIC_VECTOR; C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER; C_M_AXI_DP_DATA_WIDTH : INTEGER; C_M_AXI_DP_ADDR_WIDTH : INTEGER; C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER; C_M_AXI_D_BUS_EXCEPTION : INTEGER; C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER; C_M_AXI_IP_DATA_WIDTH : INTEGER; C_M_AXI_IP_ADDR_WIDTH : INTEGER; C_M_AXI_I_BUS_EXCEPTION : INTEGER; C_D_LMB : INTEGER; C_D_AXI : INTEGER; C_I_LMB : INTEGER; C_I_AXI : INTEGER; C_USE_MSR_INSTR : INTEGER; C_USE_PCMP_INSTR : INTEGER; C_USE_BARREL : INTEGER; C_USE_DIV : INTEGER; C_USE_HW_MUL : INTEGER; C_USE_FPU : INTEGER; C_USE_REORDER_INSTR : INTEGER; C_UNALIGNED_EXCEPTIONS : INTEGER; C_ILL_OPCODE_EXCEPTION : INTEGER; C_DIV_ZERO_EXCEPTION : INTEGER; C_FPU_EXCEPTION : INTEGER; C_FSL_LINKS : INTEGER; C_USE_EXTENDED_FSL_INSTR : INTEGER; C_FSL_EXCEPTION : INTEGER; C_USE_STACK_PROTECTION : INTEGER; C_USE_INTERRUPT : INTEGER; C_USE_EXT_BRK : INTEGER; C_USE_EXT_NM_BRK : INTEGER; C_USE_MMU : INTEGER; C_MMU_DTLB_SIZE : INTEGER; C_MMU_ITLB_SIZE : INTEGER; C_MMU_TLB_ACCESS : INTEGER; C_MMU_ZONES : INTEGER; C_MMU_PRIVILEGED_INSTR : INTEGER; C_USE_BRANCH_TARGET_CACHE : INTEGER; C_BRANCH_TARGET_CACHE_SIZE : INTEGER; C_PC_WIDTH : INTEGER; C_PVR : INTEGER; C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7); C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31); C_DYNAMIC_BUS_SIZING : INTEGER; C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31); C_OPCODE_0x0_ILLEGAL : INTEGER; C_DEBUG_ENABLED : INTEGER; C_NUMBER_OF_PC_BRK : INTEGER; C_NUMBER_OF_RD_ADDR_BRK : INTEGER; C_NUMBER_OF_WR_ADDR_BRK : INTEGER; C_DEBUG_EVENT_COUNTERS : INTEGER; C_DEBUG_LATENCY_COUNTERS : INTEGER; C_DEBUG_COUNTER_WIDTH : INTEGER; C_DEBUG_TRACE_SIZE : INTEGER; C_DEBUG_EXTERNAL_TRACE : INTEGER; C_DEBUG_PROFILE_SIZE : INTEGER; C_INTERRUPT_IS_EDGE : INTEGER; C_EDGE_IS_POSITIVE : INTEGER; C_ASYNC_INTERRUPT : INTEGER; C_M0_AXIS_DATA_WIDTH : INTEGER; C_S0_AXIS_DATA_WIDTH : INTEGER; C_M1_AXIS_DATA_WIDTH : INTEGER; C_S1_AXIS_DATA_WIDTH : INTEGER; C_M2_AXIS_DATA_WIDTH : INTEGER; C_S2_AXIS_DATA_WIDTH : INTEGER; C_M3_AXIS_DATA_WIDTH : INTEGER; C_S3_AXIS_DATA_WIDTH : INTEGER; C_M4_AXIS_DATA_WIDTH : INTEGER; C_S4_AXIS_DATA_WIDTH : INTEGER; C_M5_AXIS_DATA_WIDTH : INTEGER; C_S5_AXIS_DATA_WIDTH : INTEGER; C_M6_AXIS_DATA_WIDTH : INTEGER; C_S6_AXIS_DATA_WIDTH : INTEGER; C_M7_AXIS_DATA_WIDTH : INTEGER; C_S7_AXIS_DATA_WIDTH : INTEGER; C_M8_AXIS_DATA_WIDTH : INTEGER; C_S8_AXIS_DATA_WIDTH : INTEGER; C_M9_AXIS_DATA_WIDTH : INTEGER; C_S9_AXIS_DATA_WIDTH : INTEGER; C_M10_AXIS_DATA_WIDTH : INTEGER; C_S10_AXIS_DATA_WIDTH : INTEGER; C_M11_AXIS_DATA_WIDTH : INTEGER; C_S11_AXIS_DATA_WIDTH : INTEGER; C_M12_AXIS_DATA_WIDTH : INTEGER; C_S12_AXIS_DATA_WIDTH : INTEGER; C_M13_AXIS_DATA_WIDTH : INTEGER; C_S13_AXIS_DATA_WIDTH : INTEGER; C_M14_AXIS_DATA_WIDTH : INTEGER; C_S14_AXIS_DATA_WIDTH : INTEGER; C_M15_AXIS_DATA_WIDTH : INTEGER; C_S15_AXIS_DATA_WIDTH : INTEGER; C_ICACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31); C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31); C_USE_ICACHE : INTEGER; C_ALLOW_ICACHE_WR : INTEGER; C_ADDR_TAG_BITS : INTEGER; C_CACHE_BYTE_SIZE : INTEGER; C_ICACHE_LINE_LEN : INTEGER; C_ICACHE_ALWAYS_USED : INTEGER; C_ICACHE_STREAMS : INTEGER; C_ICACHE_VICTIMS : INTEGER; C_ICACHE_FORCE_TAG_LUTRAM : INTEGER; C_ICACHE_DATA_WIDTH : INTEGER; C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER; C_M_AXI_IC_DATA_WIDTH : INTEGER; C_M_AXI_IC_ADDR_WIDTH : INTEGER; C_M_AXI_IC_USER_VALUE : INTEGER; C_M_AXI_IC_AWUSER_WIDTH : INTEGER; C_M_AXI_IC_ARUSER_WIDTH : INTEGER; C_M_AXI_IC_WUSER_WIDTH : INTEGER; C_M_AXI_IC_RUSER_WIDTH : INTEGER; C_M_AXI_IC_BUSER_WIDTH : INTEGER; C_DCACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31); C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31); C_USE_DCACHE : INTEGER; C_ALLOW_DCACHE_WR : INTEGER; C_DCACHE_ADDR_TAG : INTEGER; C_DCACHE_BYTE_SIZE : INTEGER; C_DCACHE_LINE_LEN : INTEGER; C_DCACHE_ALWAYS_USED : INTEGER; C_DCACHE_USE_WRITEBACK : INTEGER; C_DCACHE_VICTIMS : INTEGER; C_DCACHE_FORCE_TAG_LUTRAM : INTEGER; C_DCACHE_DATA_WIDTH : INTEGER; C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER; C_M_AXI_DC_DATA_WIDTH : INTEGER; C_M_AXI_DC_ADDR_WIDTH : INTEGER; C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER; C_M_AXI_DC_USER_VALUE : INTEGER; C_M_AXI_DC_AWUSER_WIDTH : INTEGER; C_M_AXI_DC_ARUSER_WIDTH : INTEGER; C_M_AXI_DC_WUSER_WIDTH : INTEGER; C_M_AXI_DC_RUSER_WIDTH : INTEGER; C_M_AXI_DC_BUSER_WIDTH : INTEGER ); PORT ( Clk : IN STD_LOGIC; Reset : IN STD_LOGIC; Mb_Reset : IN STD_LOGIC; Config_Reset : IN STD_LOGIC; Scan_Reset : IN STD_LOGIC; Scan_Reset_Sel : IN STD_LOGIC; Dbg_Disable : IN STD_LOGIC; Interrupt : IN STD_LOGIC; Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31); Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1); Ext_BRK : IN STD_LOGIC; Ext_NM_BRK : IN STD_LOGIC; Dbg_Stop : IN STD_LOGIC; Dbg_Intr : OUT STD_LOGIC; MB_Halted : OUT STD_LOGIC; MB_Error : OUT STD_LOGIC; Wakeup : IN STD_LOGIC_VECTOR(0 TO 1); Sleep : OUT STD_LOGIC; Dbg_Wakeup : OUT STD_LOGIC; Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1); LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095); LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095); LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095); Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31); Instr : IN STD_LOGIC_VECTOR(0 TO 31); IFetch : OUT STD_LOGIC; I_AS : OUT STD_LOGIC; IReady : IN STD_LOGIC; IWAIT : IN STD_LOGIC; ICE : IN STD_LOGIC; IUE : IN STD_LOGIC; M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IP_AWLOCK : OUT STD_LOGIC; M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IP_AWVALID : OUT STD_LOGIC; M_AXI_IP_AWREADY : IN STD_LOGIC; M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IP_WLAST : OUT STD_LOGIC; M_AXI_IP_WVALID : OUT STD_LOGIC; M_AXI_IP_WREADY : IN STD_LOGIC; M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IP_BVALID : IN STD_LOGIC; M_AXI_IP_BREADY : OUT STD_LOGIC; M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IP_ARLOCK : OUT STD_LOGIC; M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IP_ARVALID : OUT STD_LOGIC; M_AXI_IP_ARREADY : IN STD_LOGIC; M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IP_RLAST : IN STD_LOGIC; M_AXI_IP_RVALID : IN STD_LOGIC; M_AXI_IP_RREADY : OUT STD_LOGIC; Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31); Data_Read : IN STD_LOGIC_VECTOR(0 TO 31); Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31); D_AS : OUT STD_LOGIC; Read_Strobe : OUT STD_LOGIC; Write_Strobe : OUT STD_LOGIC; DReady : IN STD_LOGIC; DWait : IN STD_LOGIC; DCE : IN STD_LOGIC; DUE : IN STD_LOGIC; Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3); M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DP_AWLOCK : OUT STD_LOGIC; M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DP_AWVALID : OUT STD_LOGIC; M_AXI_DP_AWREADY : IN STD_LOGIC; M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DP_WLAST : OUT STD_LOGIC; M_AXI_DP_WVALID : OUT STD_LOGIC; M_AXI_DP_WREADY : IN STD_LOGIC; M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DP_BVALID : IN STD_LOGIC; M_AXI_DP_BREADY : OUT STD_LOGIC; M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DP_ARLOCK : OUT STD_LOGIC; M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DP_ARVALID : OUT STD_LOGIC; M_AXI_DP_ARREADY : IN STD_LOGIC; M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DP_RLAST : IN STD_LOGIC; M_AXI_DP_RVALID : IN STD_LOGIC; M_AXI_DP_RREADY : OUT STD_LOGIC; Dbg_Clk : IN STD_LOGIC; Dbg_TDI : IN STD_LOGIC; Dbg_TDO : OUT STD_LOGIC; Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7); Dbg_Shift : IN STD_LOGIC; Dbg_Capture : IN STD_LOGIC; Dbg_Update : IN STD_LOGIC; Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7); Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7); Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7); Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7); Dbg_Trace_Clk : IN STD_LOGIC; Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35); Dbg_Trace_Ready : IN STD_LOGIC; Dbg_Trace_Valid : OUT STD_LOGIC; Debug_Rst : IN STD_LOGIC; Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31); Trace_Valid_Instr : OUT STD_LOGIC; Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31); Trace_Reg_Write : OUT STD_LOGIC; Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4); Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14); Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7); Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31); Trace_Exception_Taken : OUT STD_LOGIC; Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4); Trace_Jump_Taken : OUT STD_LOGIC; Trace_Delay_Slot : OUT STD_LOGIC; Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31); Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31); Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3); Trace_Data_Access : OUT STD_LOGIC; Trace_Data_Read : OUT STD_LOGIC; Trace_Data_Write : OUT STD_LOGIC; Trace_DCache_Req : OUT STD_LOGIC; Trace_DCache_Hit : OUT STD_LOGIC; Trace_DCache_Rdy : OUT STD_LOGIC; Trace_DCache_Read : OUT STD_LOGIC; Trace_ICache_Req : OUT STD_LOGIC; Trace_ICache_Hit : OUT STD_LOGIC; Trace_ICache_Rdy : OUT STD_LOGIC; Trace_OF_PipeRun : OUT STD_LOGIC; Trace_EX_PipeRun : OUT STD_LOGIC; Trace_MEM_PipeRun : OUT STD_LOGIC; Trace_MB_Halted : OUT STD_LOGIC; Trace_Jump_Hit : OUT STD_LOGIC; M0_AXIS_TLAST : OUT STD_LOGIC; M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M0_AXIS_TVALID : OUT STD_LOGIC; M0_AXIS_TREADY : IN STD_LOGIC; M1_AXIS_TLAST : OUT STD_LOGIC; M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M1_AXIS_TVALID : OUT STD_LOGIC; M1_AXIS_TREADY : IN STD_LOGIC; M2_AXIS_TLAST : OUT STD_LOGIC; M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M2_AXIS_TVALID : OUT STD_LOGIC; M2_AXIS_TREADY : IN STD_LOGIC; M3_AXIS_TLAST : OUT STD_LOGIC; M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M3_AXIS_TVALID : OUT STD_LOGIC; M3_AXIS_TREADY : IN STD_LOGIC; M4_AXIS_TLAST : OUT STD_LOGIC; M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M4_AXIS_TVALID : OUT STD_LOGIC; M4_AXIS_TREADY : IN STD_LOGIC; M5_AXIS_TLAST : OUT STD_LOGIC; M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M5_AXIS_TVALID : OUT STD_LOGIC; M5_AXIS_TREADY : IN STD_LOGIC; M6_AXIS_TLAST : OUT STD_LOGIC; M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M6_AXIS_TVALID : OUT STD_LOGIC; M6_AXIS_TREADY : IN STD_LOGIC; M7_AXIS_TLAST : OUT STD_LOGIC; M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M7_AXIS_TVALID : OUT STD_LOGIC; M7_AXIS_TREADY : IN STD_LOGIC; M8_AXIS_TLAST : OUT STD_LOGIC; M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M8_AXIS_TVALID : OUT STD_LOGIC; M8_AXIS_TREADY : IN STD_LOGIC; M9_AXIS_TLAST : OUT STD_LOGIC; M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M9_AXIS_TVALID : OUT STD_LOGIC; M9_AXIS_TREADY : IN STD_LOGIC; M10_AXIS_TLAST : OUT STD_LOGIC; M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M10_AXIS_TVALID : OUT STD_LOGIC; M10_AXIS_TREADY : IN STD_LOGIC; M11_AXIS_TLAST : OUT STD_LOGIC; M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M11_AXIS_TVALID : OUT STD_LOGIC; M11_AXIS_TREADY : IN STD_LOGIC; M12_AXIS_TLAST : OUT STD_LOGIC; M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M12_AXIS_TVALID : OUT STD_LOGIC; M12_AXIS_TREADY : IN STD_LOGIC; M13_AXIS_TLAST : OUT STD_LOGIC; M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M13_AXIS_TVALID : OUT STD_LOGIC; M13_AXIS_TREADY : IN STD_LOGIC; M14_AXIS_TLAST : OUT STD_LOGIC; M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M14_AXIS_TVALID : OUT STD_LOGIC; M14_AXIS_TREADY : IN STD_LOGIC; M15_AXIS_TLAST : OUT STD_LOGIC; M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M15_AXIS_TVALID : OUT STD_LOGIC; M15_AXIS_TREADY : IN STD_LOGIC; S0_AXIS_TLAST : IN STD_LOGIC; S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S0_AXIS_TVALID : IN STD_LOGIC; S0_AXIS_TREADY : OUT STD_LOGIC; S1_AXIS_TLAST : IN STD_LOGIC; S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S1_AXIS_TVALID : IN STD_LOGIC; S1_AXIS_TREADY : OUT STD_LOGIC; S2_AXIS_TLAST : IN STD_LOGIC; S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S2_AXIS_TVALID : IN STD_LOGIC; S2_AXIS_TREADY : OUT STD_LOGIC; S3_AXIS_TLAST : IN STD_LOGIC; S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S3_AXIS_TVALID : IN STD_LOGIC; S3_AXIS_TREADY : OUT STD_LOGIC; S4_AXIS_TLAST : IN STD_LOGIC; S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S4_AXIS_TVALID : IN STD_LOGIC; S4_AXIS_TREADY : OUT STD_LOGIC; S5_AXIS_TLAST : IN STD_LOGIC; S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S5_AXIS_TVALID : IN STD_LOGIC; S5_AXIS_TREADY : OUT STD_LOGIC; S6_AXIS_TLAST : IN STD_LOGIC; S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S6_AXIS_TVALID : IN STD_LOGIC; S6_AXIS_TREADY : OUT STD_LOGIC; S7_AXIS_TLAST : IN STD_LOGIC; S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S7_AXIS_TVALID : IN STD_LOGIC; S7_AXIS_TREADY : OUT STD_LOGIC; S8_AXIS_TLAST : IN STD_LOGIC; S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S8_AXIS_TVALID : IN STD_LOGIC; S8_AXIS_TREADY : OUT STD_LOGIC; S9_AXIS_TLAST : IN STD_LOGIC; S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S9_AXIS_TVALID : IN STD_LOGIC; S9_AXIS_TREADY : OUT STD_LOGIC; S10_AXIS_TLAST : IN STD_LOGIC; S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S10_AXIS_TVALID : IN STD_LOGIC; S10_AXIS_TREADY : OUT STD_LOGIC; S11_AXIS_TLAST : IN STD_LOGIC; S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S11_AXIS_TVALID : IN STD_LOGIC; S11_AXIS_TREADY : OUT STD_LOGIC; S12_AXIS_TLAST : IN STD_LOGIC; S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S12_AXIS_TVALID : IN STD_LOGIC; S12_AXIS_TREADY : OUT STD_LOGIC; S13_AXIS_TLAST : IN STD_LOGIC; S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S13_AXIS_TVALID : IN STD_LOGIC; S13_AXIS_TREADY : OUT STD_LOGIC; S14_AXIS_TLAST : IN STD_LOGIC; S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S14_AXIS_TVALID : IN STD_LOGIC; S14_AXIS_TREADY : OUT STD_LOGIC; S15_AXIS_TLAST : IN STD_LOGIC; S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S15_AXIS_TVALID : IN STD_LOGIC; S15_AXIS_TREADY : OUT STD_LOGIC; M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_AWLOCK : OUT STD_LOGIC; M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_AWVALID : OUT STD_LOGIC; M_AXI_IC_AWREADY : IN STD_LOGIC; M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_WLAST : OUT STD_LOGIC; M_AXI_IC_WVALID : OUT STD_LOGIC; M_AXI_IC_WREADY : IN STD_LOGIC; M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_BVALID : IN STD_LOGIC; M_AXI_IC_BREADY : OUT STD_LOGIC; M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_WACK : OUT STD_LOGIC; M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_ARLOCK : OUT STD_LOGIC; M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_ARVALID : OUT STD_LOGIC; M_AXI_IC_ARREADY : IN STD_LOGIC; M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_IC_RLAST : IN STD_LOGIC; M_AXI_IC_RVALID : IN STD_LOGIC; M_AXI_IC_RREADY : OUT STD_LOGIC; M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_IC_RACK : OUT STD_LOGIC; M_AXI_IC_ACVALID : IN STD_LOGIC; M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_IC_ACREADY : OUT STD_LOGIC; M_AXI_IC_CRVALID : OUT STD_LOGIC; M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); M_AXI_IC_CRREADY : IN STD_LOGIC; M_AXI_IC_CDVALID : OUT STD_LOGIC; M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_IC_CDLAST : OUT STD_LOGIC; M_AXI_IC_CDREADY : IN STD_LOGIC; M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_AWLOCK : OUT STD_LOGIC; M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_AWVALID : OUT STD_LOGIC; M_AXI_DC_AWREADY : IN STD_LOGIC; M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_WLAST : OUT STD_LOGIC; M_AXI_DC_WVALID : OUT STD_LOGIC; M_AXI_DC_WREADY : IN STD_LOGIC; M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_BVALID : IN STD_LOGIC; M_AXI_DC_BREADY : OUT STD_LOGIC; M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_WACK : OUT STD_LOGIC; M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_ARLOCK : OUT STD_LOGIC; M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_ARVALID : OUT STD_LOGIC; M_AXI_DC_ARREADY : IN STD_LOGIC; M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); M_AXI_DC_RLAST : IN STD_LOGIC; M_AXI_DC_RVALID : IN STD_LOGIC; M_AXI_DC_RREADY : OUT STD_LOGIC; M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0); M_AXI_DC_RACK : OUT STD_LOGIC; M_AXI_DC_ACVALID : IN STD_LOGIC; M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0); M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0); M_AXI_DC_ACREADY : OUT STD_LOGIC; M_AXI_DC_CRVALID : OUT STD_LOGIC; M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); M_AXI_DC_CRREADY : IN STD_LOGIC; M_AXI_DC_CDVALID : OUT STD_LOGIC; M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); M_AXI_DC_CDLAST : OUT STD_LOGIC; M_AXI_DC_CDREADY : IN STD_LOGIC ); END COMPONENT MicroBlaze; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF mbsys_microblaze_0_0_arch: ARCHITECTURE IS "MicroBlaze,Vivado 2014.4.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF mbsys_microblaze_0_0_arch : ARCHITECTURE IS "mbsys_microblaze_0_0,MicroBlaze,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF mbsys_microblaze_0_0_arch: ARCHITECTURE IS "mbsys_microblaze_0_0,MicroBlaze,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze,x_ipVersion=9.4,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_SCO=0,C_FREQ=100000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_ENDIANNESS=1,C_FAMILY=artix7,C_DATA_SIZE=32,C_INSTANCE=mbsys_microblaze_0_0,C_AVOID_PRIMITIVES=0,C_AREA_OPTIMIZED=0,C_OPTIMIZATION=0,C_INTERCONNECT=2,C_BASE_VECTORS=0x00000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_M_AXI_D_BUS_EXCEPTION=0,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=0,C_D_LMB=1,C_D_AXI=1,C_I_LMB=1,C_I_AXI=0,C_USE_MSR_INSTR=0,C_USE_PCMP_INSTR=0,C_USE_BARREL=1,C_USE_DIV=1,C_USE_HW_MUL=1,C_USE_FPU=1,C_USE_REORDER_INSTR=1,C_UNALIGNED_EXCEPTIONS=0,C_ILL_OPCODE_EXCEPTION=0,C_DIV_ZERO_EXCEPTION=0,C_FPU_EXCEPTION=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=1,C_FSL_EXCEPTION=0,C_USE_STACK_PROTECTION=0,C_USE_INTERRUPT=2,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_USE_MMU=0,C_MMU_DTLB_SIZE=4,C_MMU_ITLB_SIZE=2,C_MMU_TLB_ACCESS=3,C_MMU_ZONES=16,C_MMU_PRIVILEGED_INSTR=0,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=32,C_PVR=0,C_PVR_USER1=0x00,C_PVR_USER2=0x00000000,C_DYNAMIC_BUS_SIZING=0,C_RESET_MSR=0x00000000,C_OPCODE_0x0_ILLEGAL=0,C_DEBUG_ENABLED=1,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=5,C_DEBUG_LATENCY_COUNTERS=1,C_DEBUG_COUNTER_WIDTH=32,C_DEBUG_TRACE_SIZE=8192,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WIDTH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x20000000,C_ICACHE_HIGHADDR=0x2007ffff,C_USE_ICACHE=1,C_ALLOW_ICACHE_WR=1,C_ADDR_TAG_BITS=4,C_CACHE_BYTE_SIZE=32768,C_ICACHE_LINE_LEN=4,C_ICACHE_ALWAYS_USED=1,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x20000000,C_DCACHE_HIGHADDR=0x2007ffff,C_USE_DCACHE=1,C_ALLOW_DCACHE_WR=1,C_DCACHE_ADDR_TAG=4,C_DCACHE_BYTE_SIZE=32768,C_DCACHE_LINE_LEN=4,C_DCACHE_ALWAYS_USED=1,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORCE_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST"; ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS"; ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK"; ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS"; ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS"; ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY"; ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT"; ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE"; ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE"; ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS"; ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS"; ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS"; ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE"; ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE"; ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY"; ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT"; ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE"; ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE"; ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY"; ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK"; ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI"; ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO"; ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN"; ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT"; ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE"; ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE"; ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID"; ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY"; BEGIN U0 : MicroBlaze GENERIC MAP ( C_SCO => 0, C_FREQ => 100000000, C_USE_CONFIG_RESET => 0, C_NUM_SYNC_FF_CLK => 2, C_NUM_SYNC_FF_CLK_IRQ => 1, C_NUM_SYNC_FF_CLK_DEBUG => 2, C_NUM_SYNC_FF_DBG_CLK => 1, C_FAULT_TOLERANT => 0, C_ECC_USE_CE_EXCEPTION => 0, C_LOCKSTEP_SLAVE => 0, C_ENDIANNESS => 1, C_FAMILY => "artix7", C_DATA_SIZE => 32, C_INSTANCE => "mbsys_microblaze_0_0", C_AVOID_PRIMITIVES => 0, C_AREA_OPTIMIZED => 0, C_OPTIMIZATION => 0, C_INTERCONNECT => 2, C_BASE_VECTORS => X"00000000", C_M_AXI_DP_THREAD_ID_WIDTH => 1, C_M_AXI_DP_DATA_WIDTH => 32, C_M_AXI_DP_ADDR_WIDTH => 32, C_M_AXI_DP_EXCLUSIVE_ACCESS => 0, C_M_AXI_D_BUS_EXCEPTION => 0, C_M_AXI_IP_THREAD_ID_WIDTH => 1, C_M_AXI_IP_DATA_WIDTH => 32, C_M_AXI_IP_ADDR_WIDTH => 32, C_M_AXI_I_BUS_EXCEPTION => 0, C_D_LMB => 1, C_D_AXI => 1, C_I_LMB => 1, C_I_AXI => 0, C_USE_MSR_INSTR => 0, C_USE_PCMP_INSTR => 0, C_USE_BARREL => 1, C_USE_DIV => 1, C_USE_HW_MUL => 1, C_USE_FPU => 1, C_USE_REORDER_INSTR => 1, C_UNALIGNED_EXCEPTIONS => 0, C_ILL_OPCODE_EXCEPTION => 0, C_DIV_ZERO_EXCEPTION => 0, C_FPU_EXCEPTION => 0, C_FSL_LINKS => 0, C_USE_EXTENDED_FSL_INSTR => 1, C_FSL_EXCEPTION => 0, C_USE_STACK_PROTECTION => 0, C_USE_INTERRUPT => 2, C_USE_EXT_BRK => 0, C_USE_EXT_NM_BRK => 0, C_USE_MMU => 0, C_MMU_DTLB_SIZE => 4, C_MMU_ITLB_SIZE => 2, C_MMU_TLB_ACCESS => 3, C_MMU_ZONES => 16, C_MMU_PRIVILEGED_INSTR => 0, C_USE_BRANCH_TARGET_CACHE => 0, C_BRANCH_TARGET_CACHE_SIZE => 0, C_PC_WIDTH => 32, C_PVR => 0, C_PVR_USER1 => X"00", C_PVR_USER2 => X"00000000", C_DYNAMIC_BUS_SIZING => 0, C_RESET_MSR => X"00000000", C_OPCODE_0x0_ILLEGAL => 0, C_DEBUG_ENABLED => 1, C_NUMBER_OF_PC_BRK => 1, C_NUMBER_OF_RD_ADDR_BRK => 0, C_NUMBER_OF_WR_ADDR_BRK => 0, C_DEBUG_EVENT_COUNTERS => 5, C_DEBUG_LATENCY_COUNTERS => 1, C_DEBUG_COUNTER_WIDTH => 32, C_DEBUG_TRACE_SIZE => 8192, C_DEBUG_EXTERNAL_TRACE => 0, C_DEBUG_PROFILE_SIZE => 0, C_INTERRUPT_IS_EDGE => 0, C_EDGE_IS_POSITIVE => 1, C_ASYNC_INTERRUPT => 1, C_M0_AXIS_DATA_WIDTH => 32, C_S0_AXIS_DATA_WIDTH => 32, C_M1_AXIS_DATA_WIDTH => 32, C_S1_AXIS_DATA_WIDTH => 32, C_M2_AXIS_DATA_WIDTH => 32, C_S2_AXIS_DATA_WIDTH => 32, C_M3_AXIS_DATA_WIDTH => 32, C_S3_AXIS_DATA_WIDTH => 32, C_M4_AXIS_DATA_WIDTH => 32, C_S4_AXIS_DATA_WIDTH => 32, C_M5_AXIS_DATA_WIDTH => 32, C_S5_AXIS_DATA_WIDTH => 32, C_M6_AXIS_DATA_WIDTH => 32, C_S6_AXIS_DATA_WIDTH => 32, C_M7_AXIS_DATA_WIDTH => 32, C_S7_AXIS_DATA_WIDTH => 32, C_M8_AXIS_DATA_WIDTH => 32, C_S8_AXIS_DATA_WIDTH => 32, C_M9_AXIS_DATA_WIDTH => 32, C_S9_AXIS_DATA_WIDTH => 32, C_M10_AXIS_DATA_WIDTH => 32, C_S10_AXIS_DATA_WIDTH => 32, C_M11_AXIS_DATA_WIDTH => 32, C_S11_AXIS_DATA_WIDTH => 32, C_M12_AXIS_DATA_WIDTH => 32, C_S12_AXIS_DATA_WIDTH => 32, C_M13_AXIS_DATA_WIDTH => 32, C_S13_AXIS_DATA_WIDTH => 32, C_M14_AXIS_DATA_WIDTH => 32, C_S14_AXIS_DATA_WIDTH => 32, C_M15_AXIS_DATA_WIDTH => 32, C_S15_AXIS_DATA_WIDTH => 32, C_ICACHE_BASEADDR => X"20000000", C_ICACHE_HIGHADDR => X"2007ffff", C_USE_ICACHE => 1, C_ALLOW_ICACHE_WR => 1, C_ADDR_TAG_BITS => 4, C_CACHE_BYTE_SIZE => 32768, C_ICACHE_LINE_LEN => 4, C_ICACHE_ALWAYS_USED => 1, C_ICACHE_STREAMS => 0, C_ICACHE_VICTIMS => 0, C_ICACHE_FORCE_TAG_LUTRAM => 0, C_ICACHE_DATA_WIDTH => 0, C_M_AXI_IC_THREAD_ID_WIDTH => 1, C_M_AXI_IC_DATA_WIDTH => 32, C_M_AXI_IC_ADDR_WIDTH => 32, C_M_AXI_IC_USER_VALUE => 31, C_M_AXI_IC_AWUSER_WIDTH => 5, C_M_AXI_IC_ARUSER_WIDTH => 5, C_M_AXI_IC_WUSER_WIDTH => 1, C_M_AXI_IC_RUSER_WIDTH => 1, C_M_AXI_IC_BUSER_WIDTH => 1, C_DCACHE_BASEADDR => X"20000000", C_DCACHE_HIGHADDR => X"2007ffff", C_USE_DCACHE => 1, C_ALLOW_DCACHE_WR => 1, C_DCACHE_ADDR_TAG => 4, C_DCACHE_BYTE_SIZE => 32768, C_DCACHE_LINE_LEN => 4, C_DCACHE_ALWAYS_USED => 1, C_DCACHE_USE_WRITEBACK => 0, C_DCACHE_VICTIMS => 0, C_DCACHE_FORCE_TAG_LUTRAM => 0, C_DCACHE_DATA_WIDTH => 0, C_M_AXI_DC_THREAD_ID_WIDTH => 1, C_M_AXI_DC_DATA_WIDTH => 32, C_M_AXI_DC_ADDR_WIDTH => 32, C_M_AXI_DC_EXCLUSIVE_ACCESS => 0, C_M_AXI_DC_USER_VALUE => 31, C_M_AXI_DC_AWUSER_WIDTH => 5, C_M_AXI_DC_ARUSER_WIDTH => 5, C_M_AXI_DC_WUSER_WIDTH => 1, C_M_AXI_DC_RUSER_WIDTH => 1, C_M_AXI_DC_BUSER_WIDTH => 1 ) PORT MAP ( Clk => Clk, Reset => Reset, Mb_Reset => '0', Config_Reset => '0', Scan_Reset => '0', Scan_Reset_Sel => '0', Dbg_Disable => '0', Interrupt => Interrupt, Interrupt_Address => Interrupt_Address, Interrupt_Ack => Interrupt_Ack, Ext_BRK => '0', Ext_NM_BRK => '0', Dbg_Stop => '0', Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)), Instr_Addr => Instr_Addr, Instr => Instr, IFetch => IFetch, I_AS => I_AS, IReady => IReady, IWAIT => IWAIT, ICE => ICE, IUE => IUE, M_AXI_IP_AWREADY => '0', M_AXI_IP_WREADY => '0', M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), M_AXI_IP_BVALID => '0', M_AXI_IP_ARREADY => '0', M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), M_AXI_IP_RLAST => '0', M_AXI_IP_RVALID => '0', Data_Addr => Data_Addr, Data_Read => Data_Read, Data_Write => Data_Write, D_AS => D_AS, Read_Strobe => Read_Strobe, Write_Strobe => Write_Strobe, DReady => DReady, DWait => DWait, DCE => DCE, DUE => DUE, Byte_Enable => Byte_Enable, M_AXI_DP_AWADDR => M_AXI_DP_AWADDR, M_AXI_DP_AWPROT => M_AXI_DP_AWPROT, M_AXI_DP_AWVALID => M_AXI_DP_AWVALID, M_AXI_DP_AWREADY => M_AXI_DP_AWREADY, M_AXI_DP_WDATA => M_AXI_DP_WDATA, M_AXI_DP_WSTRB => M_AXI_DP_WSTRB, M_AXI_DP_WVALID => M_AXI_DP_WVALID, M_AXI_DP_WREADY => M_AXI_DP_WREADY, M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), M_AXI_DP_BRESP => M_AXI_DP_BRESP, M_AXI_DP_BVALID => M_AXI_DP_BVALID, M_AXI_DP_BREADY => M_AXI_DP_BREADY, M_AXI_DP_ARADDR => M_AXI_DP_ARADDR, M_AXI_DP_ARPROT => M_AXI_DP_ARPROT, M_AXI_DP_ARVALID => M_AXI_DP_ARVALID, M_AXI_DP_ARREADY => M_AXI_DP_ARREADY, M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), M_AXI_DP_RDATA => M_AXI_DP_RDATA, M_AXI_DP_RRESP => M_AXI_DP_RRESP, M_AXI_DP_RLAST => '0', M_AXI_DP_RVALID => M_AXI_DP_RVALID, M_AXI_DP_RREADY => M_AXI_DP_RREADY, Dbg_Clk => Dbg_Clk, Dbg_TDI => Dbg_TDI, Dbg_TDO => Dbg_TDO, Dbg_Reg_En => Dbg_Reg_En, Dbg_Shift => Dbg_Shift, Dbg_Capture => Dbg_Capture, Dbg_Update => Dbg_Update, Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), Dbg_Trace_Clk => '0', Dbg_Trace_Ready => '0', Debug_Rst => Debug_Rst, M0_AXIS_TREADY => '0', M1_AXIS_TREADY => '0', M2_AXIS_TREADY => '0', M3_AXIS_TREADY => '0', M4_AXIS_TREADY => '0', M5_AXIS_TREADY => '0', M6_AXIS_TREADY => '0', M7_AXIS_TREADY => '0', M8_AXIS_TREADY => '0', M9_AXIS_TREADY => '0', M10_AXIS_TREADY => '0', M11_AXIS_TREADY => '0', M12_AXIS_TREADY => '0', M13_AXIS_TREADY => '0', M14_AXIS_TREADY => '0', M15_AXIS_TREADY => '0', S0_AXIS_TLAST => '0', S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S0_AXIS_TVALID => '0', S1_AXIS_TLAST => '0', S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S1_AXIS_TVALID => '0', S2_AXIS_TLAST => '0', S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S2_AXIS_TVALID => '0', S3_AXIS_TLAST => '0', S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S3_AXIS_TVALID => '0', S4_AXIS_TLAST => '0', S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S4_AXIS_TVALID => '0', S5_AXIS_TLAST => '0', S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S5_AXIS_TVALID => '0', S6_AXIS_TLAST => '0', S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S6_AXIS_TVALID => '0', S7_AXIS_TLAST => '0', S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S7_AXIS_TVALID => '0', S8_AXIS_TLAST => '0', S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S8_AXIS_TVALID => '0', S9_AXIS_TLAST => '0', S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S9_AXIS_TVALID => '0', S10_AXIS_TLAST => '0', S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S10_AXIS_TVALID => '0', S11_AXIS_TLAST => '0', S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S11_AXIS_TVALID => '0', S12_AXIS_TLAST => '0', S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S12_AXIS_TVALID => '0', S13_AXIS_TLAST => '0', S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S13_AXIS_TVALID => '0', S14_AXIS_TLAST => '0', S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S14_AXIS_TVALID => '0', S15_AXIS_TLAST => '0', S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), S15_AXIS_TVALID => '0', M_AXI_IC_AWID => M_AXI_IC_AWID, M_AXI_IC_AWADDR => M_AXI_IC_AWADDR, M_AXI_IC_AWLEN => M_AXI_IC_AWLEN, M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE, M_AXI_IC_AWBURST => M_AXI_IC_AWBURST, M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK, M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE, M_AXI_IC_AWPROT => M_AXI_IC_AWPROT, M_AXI_IC_AWQOS => M_AXI_IC_AWQOS, M_AXI_IC_AWVALID => M_AXI_IC_AWVALID, M_AXI_IC_AWREADY => M_AXI_IC_AWREADY, M_AXI_IC_WDATA => M_AXI_IC_WDATA, M_AXI_IC_WSTRB => M_AXI_IC_WSTRB, M_AXI_IC_WLAST => M_AXI_IC_WLAST, M_AXI_IC_WVALID => M_AXI_IC_WVALID, M_AXI_IC_WREADY => M_AXI_IC_WREADY, M_AXI_IC_BID => M_AXI_IC_BID, M_AXI_IC_BRESP => M_AXI_IC_BRESP, M_AXI_IC_BVALID => M_AXI_IC_BVALID, M_AXI_IC_BREADY => M_AXI_IC_BREADY, M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), M_AXI_IC_ARID => M_AXI_IC_ARID, M_AXI_IC_ARADDR => M_AXI_IC_ARADDR, M_AXI_IC_ARLEN => M_AXI_IC_ARLEN, M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE, M_AXI_IC_ARBURST => M_AXI_IC_ARBURST, M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK, M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE, M_AXI_IC_ARPROT => M_AXI_IC_ARPROT, M_AXI_IC_ARQOS => M_AXI_IC_ARQOS, M_AXI_IC_ARVALID => M_AXI_IC_ARVALID, M_AXI_IC_ARREADY => M_AXI_IC_ARREADY, M_AXI_IC_RID => M_AXI_IC_RID, M_AXI_IC_RDATA => M_AXI_IC_RDATA, M_AXI_IC_RRESP => M_AXI_IC_RRESP, M_AXI_IC_RLAST => M_AXI_IC_RLAST, M_AXI_IC_RVALID => M_AXI_IC_RVALID, M_AXI_IC_RREADY => M_AXI_IC_RREADY, M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), M_AXI_IC_ACVALID => '0', M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), M_AXI_IC_CRREADY => '0', M_AXI_IC_CDREADY => '0', M_AXI_DC_AWID => M_AXI_DC_AWID, M_AXI_DC_AWADDR => M_AXI_DC_AWADDR, M_AXI_DC_AWLEN => M_AXI_DC_AWLEN, M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE, M_AXI_DC_AWBURST => M_AXI_DC_AWBURST, M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK, M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE, M_AXI_DC_AWPROT => M_AXI_DC_AWPROT, M_AXI_DC_AWQOS => M_AXI_DC_AWQOS, M_AXI_DC_AWVALID => M_AXI_DC_AWVALID, M_AXI_DC_AWREADY => M_AXI_DC_AWREADY, M_AXI_DC_WDATA => M_AXI_DC_WDATA, M_AXI_DC_WSTRB => M_AXI_DC_WSTRB, M_AXI_DC_WLAST => M_AXI_DC_WLAST, M_AXI_DC_WVALID => M_AXI_DC_WVALID, M_AXI_DC_WREADY => M_AXI_DC_WREADY, M_AXI_DC_BRESP => M_AXI_DC_BRESP, M_AXI_DC_BID => M_AXI_DC_BID, M_AXI_DC_BVALID => M_AXI_DC_BVALID, M_AXI_DC_BREADY => M_AXI_DC_BREADY, M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), M_AXI_DC_ARID => M_AXI_DC_ARID, M_AXI_DC_ARADDR => M_AXI_DC_ARADDR, M_AXI_DC_ARLEN => M_AXI_DC_ARLEN, M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE, M_AXI_DC_ARBURST => M_AXI_DC_ARBURST, M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK, M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE, M_AXI_DC_ARPROT => M_AXI_DC_ARPROT, M_AXI_DC_ARQOS => M_AXI_DC_ARQOS, M_AXI_DC_ARVALID => M_AXI_DC_ARVALID, M_AXI_DC_ARREADY => M_AXI_DC_ARREADY, M_AXI_DC_RID => M_AXI_DC_RID, M_AXI_DC_RDATA => M_AXI_DC_RDATA, M_AXI_DC_RRESP => M_AXI_DC_RRESP, M_AXI_DC_RLAST => M_AXI_DC_RLAST, M_AXI_DC_RVALID => M_AXI_DC_RVALID, M_AXI_DC_RREADY => M_AXI_DC_RREADY, M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), M_AXI_DC_ACVALID => '0', M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), M_AXI_DC_CRREADY => '0', M_AXI_DC_CDREADY => '0' ); END mbsys_microblaze_0_0_arch;