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-- IP VLNV: xilinx.com:ip:axi_fifo_mm_s:4.1
-- IP Revision: 1

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT mbsys_axi_ethernet_0_fifo_0
  PORT (
    interrupt : OUT STD_LOGIC;
    s_axi_aclk : IN STD_LOGIC;
    s_axi_aresetn : IN STD_LOGIC;
    s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_awvalid : IN STD_LOGIC;
    s_axi_awready : OUT STD_LOGIC;
    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    s_axi_wvalid : IN STD_LOGIC;
    s_axi_wready : OUT STD_LOGIC;
    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    s_axi_bvalid : OUT STD_LOGIC;
    s_axi_bready : IN STD_LOGIC;
    s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_arvalid : IN STD_LOGIC;
    s_axi_arready : OUT STD_LOGIC;
    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    s_axi_rvalid : OUT STD_LOGIC;
    s_axi_rready : IN STD_LOGIC;
    mm2s_prmry_reset_out_n : OUT STD_LOGIC;
    axi_str_txd_tvalid : OUT STD_LOGIC;
    axi_str_txd_tready : IN STD_LOGIC;
    axi_str_txd_tlast : OUT STD_LOGIC;
    axi_str_txd_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    axi_str_txd_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
    axi_str_txc_tvalid : OUT STD_LOGIC;
    axi_str_txc_tready : IN STD_LOGIC;
    axi_str_txc_tlast : OUT STD_LOGIC;
    axi_str_txc_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    axi_str_txc_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    s2mm_prmry_reset_out_n : OUT STD_LOGIC;
    axi_str_rxd_tvalid : IN STD_LOGIC;
    axi_str_rxd_tready : OUT STD_LOGIC;
    axi_str_rxd_tlast : IN STD_LOGIC;
    axi_str_rxd_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    axi_str_rxd_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : mbsys_axi_ethernet_0_fifo_0
  PORT MAP (
    interrupt => interrupt,
    s_axi_aclk => s_axi_aclk,
    s_axi_aresetn => s_axi_aresetn,
    s_axi_awaddr => s_axi_awaddr,
    s_axi_awvalid => s_axi_awvalid,
    s_axi_awready => s_axi_awready,
    s_axi_wdata => s_axi_wdata,
    s_axi_wstrb => s_axi_wstrb,
    s_axi_wvalid => s_axi_wvalid,
    s_axi_wready => s_axi_wready,
    s_axi_bresp => s_axi_bresp,
    s_axi_bvalid => s_axi_bvalid,
    s_axi_bready => s_axi_bready,
    s_axi_araddr => s_axi_araddr,
    s_axi_arvalid => s_axi_arvalid,
    s_axi_arready => s_axi_arready,
    s_axi_rdata => s_axi_rdata,
    s_axi_rresp => s_axi_rresp,
    s_axi_rvalid => s_axi_rvalid,
    s_axi_rready => s_axi_rready,
    mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
    axi_str_txd_tvalid => axi_str_txd_tvalid,
    axi_str_txd_tready => axi_str_txd_tready,
    axi_str_txd_tlast => axi_str_txd_tlast,
    axi_str_txd_tkeep => axi_str_txd_tkeep,
    axi_str_txd_tdata => axi_str_txd_tdata,
    mm2s_cntrl_reset_out_n => mm2s_cntrl_reset_out_n,
    axi_str_txc_tvalid => axi_str_txc_tvalid,
    axi_str_txc_tready => axi_str_txc_tready,
    axi_str_txc_tlast => axi_str_txc_tlast,
    axi_str_txc_tkeep => axi_str_txc_tkeep,
    axi_str_txc_tdata => axi_str_txc_tdata,
    s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
    axi_str_rxd_tvalid => axi_str_rxd_tvalid,
    axi_str_rxd_tready => axi_str_rxd_tready,
    axi_str_rxd_tlast => axi_str_rxd_tlast,
    axi_str_rxd_tkeep => axi_str_rxd_tkeep,
    axi_str_rxd_tdata => axi_str_rxd_tdata
  );
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file mbsys_axi_ethernet_0_fifo_0.vhd when simulating
-- the core, mbsys_axi_ethernet_0_fifo_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.