//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4.1 (win64) Build 1149489 Thu Feb 19 16:23:09 MST 2015
//Date        : Wed Mar 11 13:49:37 2015
//Host        : lithe-ad-work running 64-bit Service Pack 1  (build 7601)
//Command     : generate_target mbsys_wrapper.bd
//Design      : mbsys_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module mbsys_wrapper
   (EXT_AXI_araddr,
    EXT_AXI_arprot,
    EXT_AXI_arready,
    EXT_AXI_arvalid,
    EXT_AXI_awaddr,
    EXT_AXI_awprot,
    EXT_AXI_awready,
    EXT_AXI_awvalid,
    EXT_AXI_bready,
    EXT_AXI_bresp,
    EXT_AXI_bvalid,
    EXT_AXI_rdata,
    EXT_AXI_rready,
    EXT_AXI_rresp,
    EXT_AXI_rvalid,
    EXT_AXI_wdata,
    EXT_AXI_wready,
    EXT_AXI_wstrb,
    EXT_AXI_wvalid,
    MGTREFCLK1_clk_n,
    MGTREFCLK1_clk_p,
    diff_clock_rtl_clk_n,
    diff_clock_rtl_clk_p,
    ext_axi_clk,
    ext_reset_in,
    mdio_rtl_mdc,
    mdio_rtl_mdio_io,
    reset_rtl,
    sgmii_rtl_rxn,
    sgmii_rtl_rxp,
    sgmii_rtl_txn,
    sgmii_rtl_txp);
  output [31:0]EXT_AXI_araddr;
  output [2:0]EXT_AXI_arprot;
  input [0:0]EXT_AXI_arready;
  output [0:0]EXT_AXI_arvalid;
  output [31:0]EXT_AXI_awaddr;
  output [2:0]EXT_AXI_awprot;
  input [0:0]EXT_AXI_awready;
  output [0:0]EXT_AXI_awvalid;
  output [0:0]EXT_AXI_bready;
  input [1:0]EXT_AXI_bresp;
  input [0:0]EXT_AXI_bvalid;
  input [31:0]EXT_AXI_rdata;
  output [0:0]EXT_AXI_rready;
  input [1:0]EXT_AXI_rresp;
  input [0:0]EXT_AXI_rvalid;
  output [31:0]EXT_AXI_wdata;
  input [0:0]EXT_AXI_wready;
  output [3:0]EXT_AXI_wstrb;
  output [0:0]EXT_AXI_wvalid;
  input MGTREFCLK1_clk_n;
  input MGTREFCLK1_clk_p;
  input diff_clock_rtl_clk_n;
  input diff_clock_rtl_clk_p;
  output ext_axi_clk;
  input ext_reset_in;
  output mdio_rtl_mdc;
  inout mdio_rtl_mdio_io;
  output reset_rtl;
  input sgmii_rtl_rxn;
  input sgmii_rtl_rxp;
  output sgmii_rtl_txn;
  output sgmii_rtl_txp;

  wire [31:0]EXT_AXI_araddr;
  wire [2:0]EXT_AXI_arprot;
  wire [0:0]EXT_AXI_arready;
  wire [0:0]EXT_AXI_arvalid;
  wire [31:0]EXT_AXI_awaddr;
  wire [2:0]EXT_AXI_awprot;
  wire [0:0]EXT_AXI_awready;
  wire [0:0]EXT_AXI_awvalid;
  wire [0:0]EXT_AXI_bready;
  wire [1:0]EXT_AXI_bresp;
  wire [0:0]EXT_AXI_bvalid;
  wire [31:0]EXT_AXI_rdata;
  wire [0:0]EXT_AXI_rready;
  wire [1:0]EXT_AXI_rresp;
  wire [0:0]EXT_AXI_rvalid;
  wire [31:0]EXT_AXI_wdata;
  wire [0:0]EXT_AXI_wready;
  wire [3:0]EXT_AXI_wstrb;
  wire [0:0]EXT_AXI_wvalid;
  wire MGTREFCLK1_clk_n;
  wire MGTREFCLK1_clk_p;
  wire diff_clock_rtl_clk_n;
  wire diff_clock_rtl_clk_p;
  wire ext_axi_clk;
  wire ext_reset_in;
  wire mdio_rtl_mdc;
  wire mdio_rtl_mdio_i;
  wire mdio_rtl_mdio_io;
  wire mdio_rtl_mdio_o;
  wire mdio_rtl_mdio_t;
  wire reset_rtl;
  wire sgmii_rtl_rxn;
  wire sgmii_rtl_rxp;
  wire sgmii_rtl_txn;
  wire sgmii_rtl_txp;

mbsys mbsys_i
       (.EXT_AXI_araddr(EXT_AXI_araddr),
        .EXT_AXI_arprot(EXT_AXI_arprot),
        .EXT_AXI_arready(EXT_AXI_arready),
        .EXT_AXI_arvalid(EXT_AXI_arvalid),
        .EXT_AXI_awaddr(EXT_AXI_awaddr),
        .EXT_AXI_awprot(EXT_AXI_awprot),
        .EXT_AXI_awready(EXT_AXI_awready),
        .EXT_AXI_awvalid(EXT_AXI_awvalid),
        .EXT_AXI_bready(EXT_AXI_bready),
        .EXT_AXI_bresp(EXT_AXI_bresp),
        .EXT_AXI_bvalid(EXT_AXI_bvalid),
        .EXT_AXI_rdata(EXT_AXI_rdata),
        .EXT_AXI_rready(EXT_AXI_rready),
        .EXT_AXI_rresp(EXT_AXI_rresp),
        .EXT_AXI_rvalid(EXT_AXI_rvalid),
        .EXT_AXI_wdata(EXT_AXI_wdata),
        .EXT_AXI_wready(EXT_AXI_wready),
        .EXT_AXI_wstrb(EXT_AXI_wstrb),
        .EXT_AXI_wvalid(EXT_AXI_wvalid),
        .MGTREFCLK1_clk_n(MGTREFCLK1_clk_n),
        .MGTREFCLK1_clk_p(MGTREFCLK1_clk_p),
        .diff_clock_rtl_clk_n(diff_clock_rtl_clk_n),
        .diff_clock_rtl_clk_p(diff_clock_rtl_clk_p),
        .ext_axi_clk(ext_axi_clk),
        .ext_reset_in(ext_reset_in),
        .mdio_rtl_mdc(mdio_rtl_mdc),
        .mdio_rtl_mdio_i(mdio_rtl_mdio_i),
        .mdio_rtl_mdio_o(mdio_rtl_mdio_o),
        .mdio_rtl_mdio_t(mdio_rtl_mdio_t),
        .reset_rtl(reset_rtl),
        .sgmii_rtl_rxn(sgmii_rtl_rxn),
        .sgmii_rtl_rxp(sgmii_rtl_rxp),
        .sgmii_rtl_txn(sgmii_rtl_txn),
        .sgmii_rtl_txp(sgmii_rtl_txp));
IOBUF mdio_rtl_mdio_iobuf
       (.I(mdio_rtl_mdio_o),
        .IO(mdio_rtl_mdio_io),
        .O(mdio_rtl_mdio_i),
        .T(mdio_rtl_mdio_t));
endmodule