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-- DO NOT MODIFY THIS FILE.

-- IP VLNV: xilinx.com:ip:axi_crossbar:2.1
-- IP Revision: 5

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT mbsys_xbar_0
  PORT (
    aclk : IN STD_LOGIC;
    aresetn : IN STD_LOGIC;
    s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    s_axi_awvalid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_awready : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    s_axi_wvalid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_wready : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    s_axi_bvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_bready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    s_axi_arvalid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_arready : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    s_axi_rvalid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    s_axi_rready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    m_axi_awaddr : OUT STD_LOGIC_VECTOR(223 DOWNTO 0);
    m_axi_awprot : OUT STD_LOGIC_VECTOR(20 DOWNTO 0);
    m_axi_awvalid : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_awready : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_wdata : OUT STD_LOGIC_VECTOR(223 DOWNTO 0);
    m_axi_wstrb : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);
    m_axi_wvalid : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_wready : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_bresp : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
    m_axi_bvalid : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_bready : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_araddr : OUT STD_LOGIC_VECTOR(223 DOWNTO 0);
    m_axi_arprot : OUT STD_LOGIC_VECTOR(20 DOWNTO 0);
    m_axi_arvalid : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_arready : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_rdata : IN STD_LOGIC_VECTOR(223 DOWNTO 0);
    m_axi_rresp : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
    m_axi_rvalid : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
    m_axi_rready : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : mbsys_xbar_0
  PORT MAP (
    aclk => aclk,
    aresetn => aresetn,
    s_axi_awaddr => s_axi_awaddr,
    s_axi_awprot => s_axi_awprot,
    s_axi_awvalid => s_axi_awvalid,
    s_axi_awready => s_axi_awready,
    s_axi_wdata => s_axi_wdata,
    s_axi_wstrb => s_axi_wstrb,
    s_axi_wvalid => s_axi_wvalid,
    s_axi_wready => s_axi_wready,
    s_axi_bresp => s_axi_bresp,
    s_axi_bvalid => s_axi_bvalid,
    s_axi_bready => s_axi_bready,
    s_axi_araddr => s_axi_araddr,
    s_axi_arprot => s_axi_arprot,
    s_axi_arvalid => s_axi_arvalid,
    s_axi_arready => s_axi_arready,
    s_axi_rdata => s_axi_rdata,
    s_axi_rresp => s_axi_rresp,
    s_axi_rvalid => s_axi_rvalid,
    s_axi_rready => s_axi_rready,
    m_axi_awaddr => m_axi_awaddr,
    m_axi_awprot => m_axi_awprot,
    m_axi_awvalid => m_axi_awvalid,
    m_axi_awready => m_axi_awready,
    m_axi_wdata => m_axi_wdata,
    m_axi_wstrb => m_axi_wstrb,
    m_axi_wvalid => m_axi_wvalid,
    m_axi_wready => m_axi_wready,
    m_axi_bresp => m_axi_bresp,
    m_axi_bvalid => m_axi_bvalid,
    m_axi_bready => m_axi_bready,
    m_axi_araddr => m_axi_araddr,
    m_axi_arprot => m_axi_arprot,
    m_axi_arvalid => m_axi_arvalid,
    m_axi_arready => m_axi_arready,
    m_axi_rdata => m_axi_rdata,
    m_axi_rresp => m_axi_rresp,
    m_axi_rvalid => m_axi_rvalid,
    m_axi_rready => m_axi_rready
  );
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file mbsys_xbar_0.vhd when simulating
-- the core, mbsys_xbar_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.