2014.4.1:
 * Version 2.1 (Rev. 5)
 * No changes

2014.4:
 * Version 2.1 (Rev. 5)
 * Internal device family change, no functional changes

2014.3:
 * Version 2.1 (Rev. 4)
 * Improved automation of Mmm_Sss_READ_CONNECTIVITY and Mmm_Sss_WRITE_CONNECTIVITY parameters in IPI.

2014.2:
 * Version 2.1 (Rev. 3)
 * Fixed IP integrator support when all read or write connectivity parameters are set to manual override.

2014.1:
 * Version 2.1 (Rev. 2)
 * Internal device family name change, no functional changes
 * FPGA primitive instantiations used only for 7-Series; changed to pure RTL for UltraScale and beyond.
 * Improved example design based on MI connectivity for more realistic waveforms.

2013.4:
 * Version 2.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support

2013.3:
 * Version 2.1
 * Fixed model parameter values for default values of user parameters Mmm_Aaa_BASE_ADDR, Mmm_Aaa_ADDR_WIDTH, Mmm_READ/WRITE_ISSUING.
 * Changed default Snn_READ/WRITE_ACCEPTANCE = 2, Mmm_READ/WRITE_ISSUING = 4 (for Strategy = Current Settings).
 * Changed default Mmm_Aaa_ADDR_WIDTH = 0 and Mmm_Aaa_BASE_ADDR = 0xFFFFFFFFFFFFFFFF (unused) for aa > 0.
 * Fixed Address table display for ADDR_RANGES = 16.
 * Added validation DRCs for Snn_THREAD_ID_WIDTH, Mmm_Aaa_ADDR_WIDTH and Mmm_Aaa_BASE_ADDR.
 * Added example design.
 * Reduced warnings in synthesis and simulation.
 * Added support for Cadence IES and Synopsys VCS simulators.
 * Internal FIFO buffers updated to use FIFO Generator v11.0.

2013.2:
 * Version 2.0 (Rev. 1)
 * Repackaged to enable internal version management, no functional changes.

2013.1:
 * Version 2.0
 * Native Vivado Release
 * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.

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