2014.4.1: * Version 9.4 (Rev. 1) * No changes 2014.4: * Version 9.4 (Rev. 1) * Added parameters to control synchronization primitives, no functional changes * Removed warnings for Block RAM instantiations, no functional changes * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 2014.3: * Version 9.4 * Added debug enhancement: External Program Trace * Set default value of parameter C_EDGE_IS_POSITIVE to 1 * Corrected issue causing exception in return instruction delay slot to be ignored in rare cases. Versions that have this issue: 9.3. Can only occur when branch target cache is enabled. * Avoid stall for multiple outstanding data cache write accesses followed by a single access occuring in rare cases. Versions that have this issue: 9.3. Can only occur when data cache is enabled. * Also allow reading SLR and SHR registers when the FPU is not enabled. Versions that have this issue: 9.3, 9.2, 9.1, 9.0, 8.50.c, 8.50.b, 8.50.a, 8.40.b, 8.40.a, 8.30.a, 8.20.b, 8.20.a, 8.10.d, 8.10.c, 8.10.b, 8.10.a. Can only occur when stack protection and area optimization is enabled and the FPU is not enabled. 2014.2: * Version 9.3 (Rev. 1) * Internal change management process enhancements, no functional changes 2014.1: * Version 9.3 * Added debug enhancements: Program Trace, Performance Monitoring, Non-intrusive Profiling and Cross Trigger support * Updated OOC constraints to include debug clocks * Removed unused code and signals to improve coverage metrics * Fixed issue causing an incorrect vector for External Non-maskable Break. Versions that have this issue: 9.2, 9.1, 9.0, 8.50.c, 8.50.b, 8.50.a, 8.40.b, 8.40.a, 8.30.a, 8.20.b, 8.20.a, 8.10.d, 8.10.c, 8.10.b, 8.10.a, 8.00.b, 8.00.a, 7.30.b, 7.30.a, 7.20.d, 7.20.c, 7.20.b, 7.20.a, 7.10.d, 7.10.c, 7.10.b, 7.10.a, 7.00.b, 7.00.a. Can only occur when area optimization is enabled. * Ensure that AXI4-Stream get instructions with exceptions never write to the destination register. Versions that have this issue: 9.2, 9.1, 9.0, 8.50.c, 8.50.b, 8.50.a, 8.40.b, 8.40.a, 8.30.a. Can only occur when area optimization is enabled. * Internal device family name change, no functional changes * Removed unused WebTalk core generation information, no functional changes 2013.4: * Version 9.2 (Rev. 1) * Improved automatic assignment of cache addresses 2013.3: * Version 9.2 * Vivado-only core, with no functional changes compared to EDK version 8.50.c * Fixed issues causing an Instruction Bus Exception on a branch instruction to be handled incorrectly. Versions that have this issue: 9.1, 9.0, 8.40.b, 8.40.a, 8.30.a, 8.20.b, 8.20.a, 8.10.d, 8.10.c, 8.10.b, 8.10.a, 8.00.b, 8.00.a, 7.30.b, 7.30.a, 7.20.d, 7.20.c, 7.20.b, 7.20.a, 7.10.d, 7.10.c, 7.10.b, 7.10.a, 7.00.b, 7.00.a. Can only occur when area optimization is enabled, and either instruction bus exception or fault tolerance is enabled. * Avoid rare issue that can cause loss of coherency. Versions that have this issue: 8.50.b, 8.50.a. Can only occur when coherency is enabled by setting C_INTERCONNECT = 3. * Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status * Reduced warnings in synthesis and simulation 2013.2: * Version 9.1 * Vivado-only core, with no functional changes compared to EDK version 8.50.b * Avoid stall for Stack Protection Violation exception caused by a cache miss memory access. Versions that have this issue: 9.0, 8.40.b, 8.40.a, 8.30.a, 8.20.b, 8.20.a, 8.10.d, 8.10.c, 8.10.b, 8.10.a. Can only occur when stack protection and area optimization are enabled, and write-back data cache is not used. * Prevent spurious write to SHR and SLR in rare cases when exception occurs. Versions that have this issue: v8.50.a, v8.40.b, v8.40.a, v8.30.a, v8.20.b, v8.20.a, v8.10.d, v8.10.c, v8.10.b, v8.10.a. Can only occur when stack protection and area optimization are enabled. 2013.1: * Version 9.0 * Vivado-only core, with no functional changes from EDK version 8.50.a * Cache coherency based on AXI Coherency Extension (ACE) * Fixed issue with swapb for area version when C_USE_PCMP_INSTR = 0. Versions that have this issue: 8.40.b, 8.40.a, 8.30.a. 2012.4: * Version 8.40.b * No changes 2012.3: * Version 8.40.b * Relocatable base vectors * Wizard mode in the Vivado configuration dialog * Removed support for qvirtex7l and virtex7l * Avoid timing issues due to unused flip-flops connecting clock to data. Version that has this issue: 8.40.a. * Ensure that memory barrier waits for adjacent data cache access in all cases. Version that has this issue: 8.40.a. 2012.2: * Version 8.40.a * Native Vivado release * Sleep mode for power reduction * Remove inadvertent dependence on C_USE_PCMP_INSTR for byte and halfword swap instructions, which can only occur when area optimization is not enabled. Version that has this issue: v8.30.a. * The changelog for previous MicroBlaze versions can be found in Answer Record 46824 (http://www.xilinx.com/support/answers/46824.htm) (c) Copyright 2002 - 2015 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. 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