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-- DO NOT MODIFY THIS FILE.

-- IP VLNV: xilinx.com:ip:mdm:3.2
-- IP Revision: 1

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT mbsys_mdm_1_0
  PORT (
    S_AXI_ACLK : IN STD_LOGIC;
    S_AXI_ARESETN : IN STD_LOGIC;
    Interrupt : OUT STD_LOGIC;
    Debug_SYS_Rst : OUT STD_LOGIC;
    S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    S_AXI_AWVALID : IN STD_LOGIC;
    S_AXI_AWREADY : OUT STD_LOGIC;
    S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    S_AXI_WVALID : IN STD_LOGIC;
    S_AXI_WREADY : OUT STD_LOGIC;
    S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    S_AXI_BVALID : OUT STD_LOGIC;
    S_AXI_BREADY : IN STD_LOGIC;
    S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    S_AXI_ARVALID : IN STD_LOGIC;
    S_AXI_ARREADY : OUT STD_LOGIC;
    S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    S_AXI_RVALID : OUT STD_LOGIC;
    S_AXI_RREADY : IN STD_LOGIC;
    Dbg_Clk_0 : OUT STD_LOGIC;
    Dbg_TDI_0 : OUT STD_LOGIC;
    Dbg_TDO_0 : IN STD_LOGIC;
    Dbg_Reg_En_0 : OUT STD_LOGIC_VECTOR(0 TO 7);
    Dbg_Capture_0 : OUT STD_LOGIC;
    Dbg_Shift_0 : OUT STD_LOGIC;
    Dbg_Update_0 : OUT STD_LOGIC;
    Dbg_Rst_0 : OUT STD_LOGIC
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : mbsys_mdm_1_0
  PORT MAP (
    S_AXI_ACLK => S_AXI_ACLK,
    S_AXI_ARESETN => S_AXI_ARESETN,
    Interrupt => Interrupt,
    Debug_SYS_Rst => Debug_SYS_Rst,
    S_AXI_AWADDR => S_AXI_AWADDR,
    S_AXI_AWVALID => S_AXI_AWVALID,
    S_AXI_AWREADY => S_AXI_AWREADY,
    S_AXI_WDATA => S_AXI_WDATA,
    S_AXI_WSTRB => S_AXI_WSTRB,
    S_AXI_WVALID => S_AXI_WVALID,
    S_AXI_WREADY => S_AXI_WREADY,
    S_AXI_BRESP => S_AXI_BRESP,
    S_AXI_BVALID => S_AXI_BVALID,
    S_AXI_BREADY => S_AXI_BREADY,
    S_AXI_ARADDR => S_AXI_ARADDR,
    S_AXI_ARVALID => S_AXI_ARVALID,
    S_AXI_ARREADY => S_AXI_ARREADY,
    S_AXI_RDATA => S_AXI_RDATA,
    S_AXI_RRESP => S_AXI_RRESP,
    S_AXI_RVALID => S_AXI_RVALID,
    S_AXI_RREADY => S_AXI_RREADY,
    Dbg_Clk_0 => Dbg_Clk_0,
    Dbg_TDI_0 => Dbg_TDI_0,
    Dbg_TDO_0 => Dbg_TDO_0,
    Dbg_Reg_En_0 => Dbg_Reg_En_0,
    Dbg_Capture_0 => Dbg_Capture_0,
    Dbg_Shift_0 => Dbg_Shift_0,
    Dbg_Update_0 => Dbg_Update_0,
    Dbg_Rst_0 => Dbg_Rst_0
  );
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file mbsys_mdm_1_0.vhd when simulating
-- the core, mbsys_mdm_1_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.