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# This constraints file contains default clock frequencies to be used during creation of a Synthesis Design Checkpoint (DCP). 
# For best results the frequencies should be modified to match the target frequencies. 
# This constraints file is not used in top-down/global synthesis (not the default flow of Vivado).

create_clock -name s_axi_lite_clk -period 10.000 [get_ports s_axi_lite_clk]
create_clock -name axis_clk -period 6.6667 [get_ports axis_clk]
create_clock -name ref_clk -period 5.000 [get_ports ref_clk]
create_clock -name mgt_clk -period 8.000 [get_ports mgt_clk_clk_p]