/* * * Xilinx, Inc. * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY * AND FITNESS FOR A PARTICULAR PURPOSE. */ /* * * * This file is a generated sample test application. * * This application is intended to test and/or illustrate some * functionality of your system. The contents of this file may * vary depending on the IP in your system and may use existing * IP driver functions. These drivers will be generated in your * SDK application project when you run the "Generate Libraries" menu item. * */ #include #include "xparameters.h" #include "xil_cache.h" #include "xintc.h" #include "intc_header.h" #include "xgpio.h" #include "gpio_header.h" #include "xtmrctr.h" #include "tmrctr_header.h" #include "tmrctr_intr_header.h" #include "xaxiethernet.h" #include "xaxiethernet_example.h" #include "xllfifo.h" #include "axiethernet_header.h" #include "axiethernet_fifo_intr_header.h" int main() { static XIntc intc; static XTmrCtr axi_timer_0_Timer; static XAxiEthernet axi_ethernet_0_eth_buf_AxiEthernet; static XLlFifo axi_ethernet_0_fifo_AxiFifo; Xil_ICacheEnable(); Xil_DCacheEnable(); print("---Entering main---\n\r"); { int status; print("\r\n Running IntcSelfTestExample() for microblaze_0_axi_intc...\r\n"); status = IntcSelfTestExample(XPAR_MICROBLAZE_0_AXI_INTC_DEVICE_ID); if (status == 0) { print("IntcSelfTestExample PASSED\r\n"); } else { print("IntcSelfTestExample FAILED\r\n"); } } { int Status; Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_0_AXI_INTC_DEVICE_ID); if (Status == 0) { print("Intc Interrupt Setup PASSED\r\n"); } else { print("Intc Interrupt Setup FAILED\r\n"); } } { u32 status; print("\r\nRunning GpioOutputExample() for axi_gpio_0...\r\n"); status = GpioOutputExample(XPAR_AXI_GPIO_0_DEVICE_ID,32); if (status == 0) { print("GpioOutputExample PASSED.\r\n"); } else { print("GpioOutputExample FAILED.\r\n"); } } { int status; print("\r\n Running TmrCtrSelfTestExample() for axi_timer_0...\r\n"); status = TmrCtrSelfTestExample(XPAR_AXI_TIMER_0_DEVICE_ID, 0x0); if (status == 0) { print("TmrCtrSelfTestExample PASSED\r\n"); } else { print("TmrCtrSelfTestExample FAILED\r\n"); } } { int Status; print("\r\n Running Interrupt Test for axi_timer_0...\r\n"); Status = TmrCtrIntrExample(&intc, &axi_timer_0_Timer, \ XPAR_AXI_TIMER_0_DEVICE_ID, \ XPAR_MICROBLAZE_0_AXI_INTC_AXI_TIMER_0_INTERRUPT_INTR, 0); if (Status == 0) { print("Timer Interrupt Test PASSED\r\n"); } else { print("Timer Interrupt Test FAILED\r\n"); } } /* * Peripheral SelfTest will not be run for mdm_1 * because it has been selected as the STDOUT device */ { int Status; print("\r\n Running AxiEthernetPolledExample() for axi_ethernet_0_eth_buf...\r\n"); Status = AxiEthernetPolledExample( XPAR_AXI_ETHERNET_0_ETH_BUF_DEVICE_ID, XPAR_AXI_ETHERNET_0_FIFO_DEVICE_ID ); if (Status == 0) { print("AxiEthernetPolledExample PASSED\r\n"); } else { print("AxiEthernetPolledExample FAILED\r\n"); } } { int Status; print("\r\nRunning AxiEthernetFifoIntrExample() for axi_ethernet_0_eth_buf...\r\n"); Status = AxiEthernetFifoIntrExample(&intc, &axi_ethernet_0_eth_buf_AxiEthernet, &axi_ethernet_0_fifo_AxiFifo, XPAR_AXI_ETHERNET_0_ETH_BUF_DEVICE_ID, XPAR_AXI_ETHERNET_0_FIFO_DEVICE_ID, XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_ETH_BUF_INTERRUPT_INTR, XPAR_MICROBLAZE_0_AXI_INTC_AXI_ETHERNET_0_FIFO_INTERRUPT_INTR); if(Status == 0) { print("AxiEthernet Interrupt Test PASSED.\r\n"); } else { print("AxiEthernet Interrupt Test FAILED.\r\n"); } } print("---Exiting main---\n\r"); Xil_DCacheDisable(); Xil_ICacheDisable(); return 0; }