Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedTue Mar 24 12:57:07 2015 product_versionVivado v2014.4 (64-bit)
build_version1071353 os_platformWIN64
registration_id210688187_1777495307_210568098_927 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a200t
target_packagefbg484 target_speed-2
random_id8f4686493dd052e7a12df2704f31a24f project_id6dbe3b0cd4d0479d982367492b714879
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7 CPU 960 @ 3.20GHz cpu_speed2800 MHz
total_processors1 system_ram25.000 GB

vivado_usage
project_data
srcsetcount=4 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=My test implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1

unisim_transformation
pre_unisim_transformation
and2b1l=4 bscane2=1 bufg=9 carry4=433
dsp48e1=5 fdce=637 fdpe=235 fdre=14981
fdse=390 gnd=1039 gtpe2_channel=1 gtpe2_common=1
ibuf=6 ibufds_gte2=2 iobuf=1 lut1=385
lut2=1279 lut3=1641 lut4=1821 lut5=1932
lut6=3548 lut6_2=64 mmcme2_adv=2 muxf7=244
muxf8=25 obuf=4 ram32m=28 ram32x1d=32
ram64m=122 ram64x1d=176 ramb36e1=192 srl16e=239
srlc16e=7 srlc32e=3 vcc=825
post_unisim_transformation
and2b1l=4 bscane2=1 bufg=9 carry4=433
dsp48e1=5 fdce=637 fdpe=235 fdre=14981
fdse=390 gnd=1039 gtpe2_channel=1 gtpe2_common=1
ibuf=7 ibufds_gte2=2 lut1=385 lut2=1279
lut3=1641 lut4=1821 lut5=1996 lut6=3612
mmcme2_adv=2 muxf7=244 muxf8=25 obuf=4
obuft=1 ramb36e1=192 ramd32=232 ramd64e=840
rams32=56 srl16e=239 srlc16e=7 srlc32e=3
vcc=825

placer
usage
lut=9979 ff=10920 bram36=192 bram18=0
ctrls=554 dsp=5 iob=3 bufg=0
global_clocks=9 pll=0 bufr=0 nets=29989
movable_instances=25421 pins=186460 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=67.985000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=10910 srls_augmented=0
srls_newly_gated=0 srls_total=246 bram_ports_augmented=192 bram_ports_newly_gated=17
bram_ports_total=384 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
MDM/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=mdm x_ipversion=3.2 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_jtag_chain=2 c_use_bscan=0
c_use_config_reset=0 c_interconnect=2 c_mb_dbg_ports=1 c_use_uart=1
c_dbg_reg_access=0 c_dbg_mem_access=0 c_use_cross_trigger=0 c_trace_output=0
c_trace_data_width=32 c_trace_clk_freq_hz=200000000 c_trace_clk_out_phase=90 c_s_axi_addr_width=32
c_s_axi_data_width=32 c_s_axi_aclk_freq_hz=100000000 c_m_axi_addr_width=32 c_m_axi_data_width=32
c_m_axi_thread_id_width=1 c_data_size=32 c_m_axis_data_width=32 c_m_axis_id_width=7
MicroBlaze/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=microblaze x_ipversion=9.4 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_sco=0 c_freq=100000000 c_use_config_reset=0
c_num_sync_ff_clk=2 c_num_sync_ff_clk_irq=1 c_num_sync_ff_clk_debug=2 c_num_sync_ff_dbg_clk=1
c_fault_tolerant=0 c_ecc_use_ce_exception=0 c_lockstep_slave=0 c_endianness=1
c_family=artix7 c_data_size=32 c_instance=mbsys_microblaze_0_0 c_avoid_primitives=0
c_area_optimized=0 c_optimization=0 c_interconnect=2 c_base_vectors=0x00000000
c_m_axi_dp_thread_id_width=1 c_m_axi_dp_data_width=32 c_m_axi_dp_addr_width=32 c_m_axi_dp_exclusive_access=0
c_m_axi_d_bus_exception=0 c_m_axi_ip_thread_id_width=1 c_m_axi_ip_data_width=32 c_m_axi_ip_addr_width=32
c_m_axi_i_bus_exception=0 c_d_lmb=1 c_d_axi=1 c_i_lmb=1
c_i_axi=0 c_use_msr_instr=0 c_use_pcmp_instr=0 c_use_barrel=1
c_use_div=1 c_use_hw_mul=1 c_use_fpu=1 c_use_reorder_instr=1
c_unaligned_exceptions=0 c_ill_opcode_exception=0 c_div_zero_exception=0 c_fpu_exception=0
c_fsl_links=0 c_use_extended_fsl_instr=1 c_fsl_exception=0 c_use_stack_protection=0
c_use_interrupt=2 c_use_ext_brk=0 c_use_ext_nm_brk=0 c_use_mmu=0
c_mmu_dtlb_size=4 c_mmu_itlb_size=2 c_mmu_tlb_access=3 c_mmu_zones=16
c_mmu_privileged_instr=0 c_use_branch_target_cache=0 c_branch_target_cache_size=0 c_pc_width=32
c_pvr=0 c_pvr_user1=0x00 c_pvr_user2=0x00000000 c_dynamic_bus_sizing=0
c_reset_msr=0x00000000 c_opcode_0x0_illegal=0 c_debug_enabled=1 c_number_of_pc_brk=1
c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0 c_debug_event_counters=5 c_debug_latency_counters=1
c_debug_counter_width=32 c_debug_trace_size=8192 c_debug_external_trace=0 c_debug_profile_size=0
c_interrupt_is_edge=0 c_edge_is_positive=1 c_async_interrupt=1 c_m0_axis_data_width=32
c_s0_axis_data_width=32 c_m1_axis_data_width=32 c_s1_axis_data_width=32 c_m2_axis_data_width=32
c_s2_axis_data_width=32 c_m3_axis_data_width=32 c_s3_axis_data_width=32 c_m4_axis_data_width=32
c_s4_axis_data_width=32 c_m5_axis_data_width=32 c_s5_axis_data_width=32 c_m6_axis_data_width=32
c_s6_axis_data_width=32 c_m7_axis_data_width=32 c_s7_axis_data_width=32 c_m8_axis_data_width=32
c_s8_axis_data_width=32 c_m9_axis_data_width=32 c_s9_axis_data_width=32 c_m10_axis_data_width=32
c_s10_axis_data_width=32 c_m11_axis_data_width=32 c_s11_axis_data_width=32 c_m12_axis_data_width=32
c_s12_axis_data_width=32 c_m13_axis_data_width=32 c_s13_axis_data_width=32 c_m14_axis_data_width=32
c_s14_axis_data_width=32 c_m15_axis_data_width=32 c_s15_axis_data_width=32 c_icache_baseaddr=0x20000000
c_icache_highaddr=0x2007ffff c_use_icache=1 c_allow_icache_wr=1 c_addr_tag_bits=4
c_cache_byte_size=32768 c_icache_line_len=4 c_icache_always_used=1 c_icache_streams=0
c_icache_victims=0 c_icache_force_tag_lutram=0 c_icache_data_width=0 c_m_axi_ic_thread_id_width=1
c_m_axi_ic_data_width=32 c_m_axi_ic_addr_width=32 c_m_axi_ic_user_value=31 c_m_axi_ic_awuser_width=5
c_m_axi_ic_aruser_width=5 c_m_axi_ic_wuser_width=1 c_m_axi_ic_ruser_width=1 c_m_axi_ic_buser_width=1
c_dcache_baseaddr=0x20000000 c_dcache_highaddr=0x2007ffff c_use_dcache=1 c_allow_dcache_wr=1
c_dcache_addr_tag=4 c_dcache_byte_size=32768 c_dcache_line_len=4 c_dcache_always_used=1
c_dcache_use_writeback=0 c_dcache_victims=0 c_dcache_force_tag_lutram=0 c_dcache_data_width=0
c_m_axi_dc_thread_id_width=1 c_m_axi_dc_data_width=32 c_m_axi_dc_addr_width=32 c_m_axi_dc_exclusive_access=0
c_m_axi_dc_user_value=31 c_m_axi_dc_awuser_width=5 c_m_axi_dc_aruser_width=5 c_m_axi_dc_wuser_width=1
c_m_axi_dc_ruser_width=1 c_m_axi_dc_buser_width=1
axi_bram_ctrl/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_bram_ctrl x_ipversion=4.0 x_ipcorerevision=3 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_bram_inst_mode=EXTERNAL c_memory_depth=131072 c_bram_addr_width=17
c_s_axi_addr_width=19 c_s_axi_data_width=32 c_s_axi_id_width=1 c_s_axi_protocol=AXI4
c_s_axi_supports_narrow_burst=0 c_single_port_bram=0 c_family=artix7 c_s_axi_ctrl_addr_width=32
c_s_axi_ctrl_data_width=32 c_ecc=0 c_ecc_type=0 c_fault_inject=0
c_ecc_onoff_reset_value=0
axi_crossbar_v2_1_axi_crossbar/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=1 c_num_master_slots=7
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=2
c_num_addr_ranges=1 c_m_axi_base_addr=0x000000004001000000000000400000000000000041c000000000000044a000000000000040c0000000000000414000000000000041200000 c_m_axi_addr_width=0x00000010000000100000001000000010000000120000000c00000010 c_s_axi_base_id=0x00000000
c_s_axi_thread_id_width=0x00000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x00000001000000010000000100000001000000010000000100000001
c_m_axi_read_connectivity=0x00000001000000010000000100000001000000010000000100000001 c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001
c_s_axi_read_acceptance=0x00000001 c_m_axi_write_issuing=0x00000001000000010000000100000001000000010000000100000001 c_m_axi_read_issuing=0x00000001000000010000000100000001000000010000000100000001 c_s_axi_arb_priority=0x00000000
c_m_axi_secure=0x00000000000000000000000000000000000000000000000000000000 c_connectivity_mode=0
axi_crossbar_v2_1_axi_crossbar/2
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=2 c_num_master_slots=1
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=0
c_num_addr_ranges=1 c_m_axi_base_addr=0x0000000020000000 c_m_axi_addr_width=0x00000013 c_s_axi_base_id=0x0000000100000000
c_s_axi_thread_id_width=0x0000000000000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x00000001
c_m_axi_read_connectivity=0x00000003 c_r_register=0 c_s_axi_single_thread=0x0000000000000000 c_s_axi_write_acceptance=0x0000000200000020
c_s_axi_read_acceptance=0x0000000200000002 c_m_axi_write_issuing=0x00000002 c_m_axi_read_issuing=0x00000002 c_s_axi_arb_priority=0x0000000000000000
c_m_axi_secure=0x00000000 c_connectivity_mode=1
axi_ethernet_buffer_v2_0/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_ethernet_buffer x_ipversion=2.0 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_txmem=4096 c_temac_addr_width=12
c_rxmem=4096 c_txcsum=0 c_rxcsum=0 c_phyaddr=3
c_avb=0 c_stats=1 c_phy_type=4 c_type=1
c_txvlan_tran=0 c_rxvlan_tran=0 c_txvlan_tag=0 c_rxvlan_tag=0
c_txvlan_strp=0 c_rxvlan_strp=0 c_mcast_extend=0 c_enable_lvds=0
c_simulation=0
axi_fifo_mm_s/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_fifo_mm_s x_ipversion=4.1 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_id_width=4 c_s_axi_addr_width=32
c_s_axi_data_width=32 c_s_axi4_data_width=32 c_tx_fifo_depth=4096 c_rx_fifo_depth=4096
c_tx_fifo_pf_threshold=4000 c_tx_fifo_pe_threshold=10 c_rx_fifo_pf_threshold=4000 c_rx_fifo_pe_threshold=10
c_use_tx_cut_through=0 c_data_interface_type=0 c_baseaddr=0x44A00000 c_highaddr=0x44A0FFFF
c_axi4_baseaddr=0x80001000 c_axi4_highaddr=0x80002FFF c_has_axis_tid=0 c_has_axis_tdest=0
c_has_axis_tuser=0 c_has_axis_tstrb=0 c_has_axis_tkeep=1 c_axis_tid_width=4
c_axis_tdest_width=4 c_axis_tuser_width=4 c_use_rx_cut_through=0 c_use_tx_data=1
c_use_tx_ctrl=1 c_use_rx_data=1
axi_gpio/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=32 c_gpio2_width=32 c_all_inputs=0 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=0 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_intc/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_intc x_ipversion=4.1 x_ipcorerevision=2 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_instance=axi_intc_inst c_s_axi_addr_width=9
c_s_axi_data_width=32 c_num_intr_inputs=5 c_num_sw_intr=0 c_kind_of_intr=0xffffffe6
c_kind_of_edge=0xffffffff c_kind_of_lvl=0xffffffff c_async_intr=0xFFFFFFE3 c_num_sync_ff=2
c_ivar_reset_value=0x00000010 c_enable_async=0 c_has_ipr=1 c_has_sie=1
c_has_cie=1 c_has_ivr=1 c_has_ilr=0 c_irq_is_level=1
c_irq_active=0x1 c_disable_synchronizers=1 c_mb_clk_not_connected=1 c_has_fast=1
c_en_cascade_mode=0 c_cascade_master=0
axi_timer/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_timer x_ipversion=2.0 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_count_width=32 c_one_timer_only=0
c_trig0_assert=1 c_trig1_assert=1 c_gen0_assert=1 c_gen1_assert=1
c_s_axi_data_width=32 c_s_axi_addr_width=5
bd_0/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_ethernet x_ipversion=6.2 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1
c_enable_32bit_address=1 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=2 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=mbsys_axi_bram_ctrl_0_bram_0.mem c_use_default_data=0
c_default_data=0 c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1
c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32
c_write_depth_a=131072 c_read_depth_a=131072 c_addra_width=32 c_has_rstb=1
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=1
c_has_regceb=0 c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST
c_write_width_b=32 c_read_width_b=32 c_write_depth_b=131072 c_read_depth_b=131072
c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_disable_warn_bhv_range=0 c_count_36k_bram=128 c_count_18k_bram=0 c_est_power_summary=Estimated Power for IP _ 20.388006 mW
blk_mem_gen_v8_2/2
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1
c_enable_32bit_address=1 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=2 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=mbsys_lmb_bram_0.mem c_use_default_data=0
c_default_data=0 c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1
c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32
c_write_depth_a=32768 c_read_depth_a=32768 c_addra_width=32 c_has_rstb=1
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=1
c_has_regceb=0 c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST
c_write_width_b=32 c_read_width_b=32 c_write_depth_b=32768 c_read_depth_b=32768
c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_disable_warn_bhv_range=0 c_count_36k_bram=32 c_count_18k_bram=0 c_est_power_summary=Estimated Power for IP _ 20.388 mW
clk_wiz_v5_1/1
iptotal=1 component_name=mbsys_clk_wiz_1_0 use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=MMCM num_out_clk=2
clkin1_period=5.0 clkin2_period=10.0 use_power_down=false use_reset=false
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
gig_ethernet_pcs_pma_v14_3/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=gig_ethernet_pcs_pma x_ipversion=14.3 x_ipcorerevision=2 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_elaboration_transient_dir=[user-defined] c_component_name=bd_0_pcs_pma_0 c_family=artix7
c_is_sgmii=true c_use_transceiver=true c_use_tbi=false c_use_lvds=false
c_has_an=true c_has_mdio=true c_has_ext_mdio=true c_sgmii_phy_mode=false
c_dynamic_switching=false c_transceiver_mode=A c_sgmii_fabric_buffer=true c_1588=0
gt_rx_byte_width=1 c_emac_if_temac=true c_phyaddr=3 example_simulation=0
c_support_level=true c_sub_core_name=bd_0_pcs_pma_0_gt c_transceivercontrol=false c_xdevicefamily=xc7a200t
c_gt_dmonitorout_width=15
lmb_bram_if_cntlr/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipversion=4.0 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_highaddr=0x0001FFFF c_baseaddr=0x00000000
c_num_lmb=1 c_mask=0x60000000 c_mask1=0x00800000 c_mask2=0x00800000
c_mask3=0x00800000 c_lmb_awidth=32 c_lmb_dwidth=32 c_ecc=0
c_interconnect=0 c_fault_inject=0 c_ce_failing_registers=0 c_ue_failing_registers=0
c_ecc_status_registers=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ce_counter_width=0
c_write_access=2 c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
lmb_bram_if_cntlr/2
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipversion=4.0 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_highaddr=0x0001FFFF c_baseaddr=0x00000000
c_num_lmb=1 c_mask=0x20000000 c_mask1=0x00800000 c_mask2=0x00800000
c_mask3=0x00800000 c_lmb_awidth=32 c_lmb_dwidth=32 c_ecc=0
c_interconnect=0 c_fault_inject=0 c_ce_failing_registers=0 c_ue_failing_registers=0
c_ecc_status_registers=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ce_counter_width=0
c_write_access=2 c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
lmb_v10/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_v10 x_ipversion=3.0 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_lmb_num_slaves=1 c_lmb_dwidth=32 c_lmb_awidth=32
c_ext_reset_high=1
lmb_v10/2
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_v10 x_ipversion=3.0 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_lmb_num_slaves=1 c_lmb_dwidth=32 c_lmb_awidth=32
c_ext_reset_high=1
proc_sys_reset/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=proc_sys_reset x_ipversion=5.0 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_ext_rst_width=4 c_aux_rst_width=4
c_ext_reset_high=0 c_aux_reset_high=0 c_num_bus_rst=1 c_num_perp_rst=1
c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
tri_mode_ethernet_mac_v8_3/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=tri_mode_ethernet_mac x_ipversion=8.3 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED x_iplicense=tri_mode_eth_mac@2014.10(hardware_evaluation) x_iplicense=10_100_mb_eth_mac@2014.10(hardware_evaluation) x_iplicense=eth_avb_endpoint@2014.10(design_linking)
c_component_name=bd_0_eth_mac_0 c_physical_interface=INTERNAL c_half_duplex=false c_has_host=true
c_has_mdio=true c_mdio_external=false c_add_filter=true c_at_entries=4
c_family=artix7 c_mac_speed=TRI_SPEED c_has_stats=true c_num_stats=34
c_cntr_rst=false c_stats_width=64 c_avb=false c_1588=0
c_tx_tuser_width=1 c_rx_vec_width=79 c_tx_vec_width=79 c_addr_width=12
c_pfc=false
xlconcat/1
iptotal=1 x_ipproduct=Vivado 2014.4.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlconcat x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED in0_width=1 in1_width=1 in2_width=1
in3_width=1 in4_width=1 in5_width=1 in6_width=1
in7_width=1 in8_width=1 in9_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in20_width=1 in21_width=1 in22_width=1
in23_width=1 in24_width=1 in25_width=1 in26_width=1
in27_width=1 in28_width=1 in29_width=1 in30_width=1
in31_width=1 dout_width=5 num_ports=5

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a200tfbg484-2 package=fbg484 speedgrade=-2 version=2014.4
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=8.000000 pct_inputs_defined=0 user_junc_temp=26.3 (C)
ambient_temp=25.0 (C) user_effective_thetaja=2.5 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.2 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=4.8 (C/W)
user_board_temp=25.0 (C) junction_temp=26.3 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=0.519939 dynamic=0.361754
effective_thetaja=2.5 thetasa=4.2 (C/W) thetajb=4.8 (C/W) off-chip_power=0.000000
clocks=0.029643 logic=0.021626 signals=0.032848 bram=0.012021
mmcm=0.159800 dsp=0.004385 i/o=0.000659 gtp=0.100773
devstatic=0.158184 vccint_voltage=1.000000 vccint_total_current=0.142171 vccint_dynamic_current=0.106372
vccint_static_current=0.035799 vccaux_voltage=1.800000 vccaux_total_current=0.119094 vccaux_dynamic_current=0.088487
vccaux_static_current=0.030608 vcco33_voltage=3.300000 vcco33_total_current=0.000000 vcco33_dynamic_current=0.000000
vcco33_static_current=0.000000 vcco25_voltage=2.500000 vcco25_total_current=0.005242 vcco25_dynamic_current=0.000242
vcco25_static_current=0.005000 vcco18_voltage=1.800000 vcco18_total_current=0.005000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.005000 vcco15_voltage=1.500000 vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco135_voltage=1.350000 vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco12_voltage=1.200000 vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vccaux_io_voltage=1.800000 vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccbram_voltage=1.000000 vccbram_total_current=0.006339 vccbram_dynamic_current=0.000929
vccbram_static_current=0.005410 mgtavcc_voltage=1.000000 mgtavcc_total_current=0.052151 mgtavcc_dynamic_current=0.050803
mgtavcc_static_current=0.001347 mgtavtt_voltage=1.200000 mgtavtt_total_current=0.039003 mgtavtt_dynamic_current=0.036475
mgtavtt_static_current=0.002528 vccadc_voltage=1.800000 vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 confidence_level_design_state=High confidence_level_clock_activity=Low confidence_level_io_activity=Low
confidence_level_internal_activity=Medium confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=9844 slice_luts_fixed=0 slice_luts_available=133800 slice_luts_util_percentage=7.35
lut_as_logic_used=8701 lut_as_logic_fixed=0 lut_as_logic_available=133800 lut_as_logic_util_percentage=6.50
lut_as_memory_used=1143 lut_as_memory_fixed=0 lut_as_memory_available=46200 lut_as_memory_util_percentage=2.47
lut_as_distributed_ram_used=984 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=159 lut_as_shift_register_fixed=0
slice_registers_used=10920 slice_registers_fixed=0 slice_registers_available=267600 slice_registers_util_percentage=4.08
register_as_flip_flop_used=10916 register_as_flip_flop_fixed=0 register_as_flip_flop_available=267600 register_as_flip_flop_util_percentage=4.07
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=267600 register_as_latch_util_percentage=0.00
register_as_and_or_used=4 register_as_and_or_fixed=0 register_as_and_or_available=267600 register_as_and_or_util_percentage=<0.01
f7_muxes_used=238 f7_muxes_fixed=0 f7_muxes_available=66900 f7_muxes_util_percentage=0.35
f8_muxes_used=23 f8_muxes_fixed=0 f8_muxes_available=33450 f8_muxes_util_percentage=0.06
slice_used=4498 slice_fixed=0 slice_available=33450 slice_util_percentage=13.44
slicel_used=2704 slicel_fixed=0 slicem_used=1794 slicem_fixed=0
lut_as_logic_used=8701 lut_as_logic_fixed=0 lut_as_logic_available=133800 lut_as_logic_util_percentage=6.50
using_o5_output_only_used=13 using_o5_output_only_fixed= using_o6_output_only_used=7205 using_o6_output_only_fixed=
using_o5_and_o6_used=1483 using_o5_and_o6_fixed= lut_as_memory_used=1143 lut_as_memory_fixed=0
lut_as_memory_available=46200 lut_as_memory_util_percentage=2.47 lut_as_distributed_ram_used=984 lut_as_distributed_ram_fixed=0
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=840 using_o6_output_only_fixed=
using_o5_and_o6_used=144 using_o5_and_o6_fixed= lut_as_shift_register_used=159 lut_as_shift_register_fixed=0
using_o5_output_only_used=8 using_o5_output_only_fixed= using_o6_output_only_used=64 using_o6_output_only_fixed=
using_o5_and_o6_used=87 using_o5_and_o6_fixed= lut_flip_flop_pairs_used=13163 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=133800 lut_flip_flop_pairs_util_percentage=9.83 fully_used_lut_ff_pairs_used=5329 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=3340 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=4494 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=554 minimum_number_of_registers_lost_to_control_set_restriction_used=1668(Lost)
memory
block_ram_tile_used=192 block_ram_tile_fixed=0 block_ram_tile_available=365 block_ram_tile_util_percentage=52.60
ramb36_fifo*_used=192 ramb36_fifo*_fixed=0 ramb36_fifo*_available=365 ramb36_fifo*_util_percentage=52.60
ramb36e1_only_used=192 ramb18_used=0 ramb18_fixed=0 ramb18_available=730
ramb18_util_percentage=0.00
dsp
dsps_used=5 dsps_fixed=0 dsps_available=740 dsps_util_percentage=0.67
dsp48e1_only_used=5
clocking
bufgctrl_used=9 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=28.12
bufio_used=0 bufio_fixed=0 bufio_available=40 bufio_util_percentage=0.00
mmcme2_adv_used=2 mmcme2_adv_fixed=0 mmcme2_adv_available=10 mmcme2_adv_util_percentage=20.00
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=10 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=20 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=120 bufhce_util_percentage=0.00
bufr_used=0 bufr_fixed=0 bufr_available=40 bufr_util_percentage=0.00
specific_feature
bscane2_used=1 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=25.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=9664 fdre_functional_category=Flop & Latch lut6_used=3237 lut6_functional_category=LUT
lut5_used=1939 lut5_functional_category=LUT lut3_used=1794 lut3_functional_category=LUT
lut4_used=1743 lut4_functional_category=LUT lut2_used=1274 lut2_functional_category=LUT
ramd64e_used=840 ramd64e_functional_category=Distributed Memory fdce_used=635 fdce_functional_category=Flop & Latch
carry4_used=432 carry4_functional_category=CarryLogic fdse_used=388 fdse_functional_category=Flop & Latch
muxf7_used=238 muxf7_functional_category=MuxFx srl16e_used=236 srl16e_functional_category=Distributed Memory
ramd32_used=232 ramd32_functional_category=Distributed Memory fdpe_used=229 fdpe_functional_category=Flop & Latch
lut1_used=197 lut1_functional_category=LUT ramb36e1_used=192 ramb36e1_functional_category=Block Memory
rams32_used=56 rams32_functional_category=Distributed Memory muxf8_used=23 muxf8_functional_category=MuxFx
bufg_used=9 bufg_functional_category=Clock srlc16e_used=7 srlc16e_functional_category=Distributed Memory
ibuf_used=7 ibuf_functional_category=IO dsp48e1_used=5 dsp48e1_functional_category=Block Arithmetic
obuf_used=4 obuf_functional_category=IO and2b1l_used=4 and2b1l_functional_category=Others
srlc32e_used=3 srlc32e_functional_category=Distributed Memory mmcme2_adv_used=2 mmcme2_adv_functional_category=Clock
ibufds_gte2_used=2 ibufds_gte2_functional_category=IO obuft_used=1 obuft_functional_category=IO
gtpe2_common_used=1 gtpe2_common_functional_category=IO gtpe2_channel_used=1 gtpe2_channel_functional_category=IO
bscane2_used=1 bscane2_functional_category=Others
io_standard
lvds_25=0 diff_hstl_i=0 hstl_i=0 sstl135=0
hsul_12=0 ppds_25=0 diff_sstl18_i=0 lvcmos15=0
diff_sstl135=0 lvttl=0 blvds_25=0 hstl_ii=0
mini_lvds_25=0 diff_hstl_ii_18=1 lvcmos12=0 diff_sstl15_r=0
lvcmos33=0 diff_sstl15=0 lvcmos25=1 diff_sstl18_ii=0
lvcmos18=1 hstl_i_18=0 diff_hsul_12=0 hstl_ii_18=0
sstl18_i=0 sstl18_ii=0 sstl15=0 sstl15_r=0
sstl135_r=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 diff_sstl135_r=0 pci33_3=0 mobile_ddr=0
diff_mobile_ddr=0

router
usage
lut=10624 ff=10920 bram36=192 bram18=0
ctrls=554 dsp=5 iob=3 bufg=0
global_clocks=9 pll=0 bufr=0 nets=29989
movable_instances=25421 pins=186460 bogomips=0 high_fanout_nets=11
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=20966304 actual_expansions=21984943 router_runtime=107.031000

synthesis
command_line_options
-part=xc7a200tfbg484-2 -name=default::[not_specified] -top=toplevel -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:14:10s memory_peak=1143.926MB memory_gain=860.129MB hls_ip=0