Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
| Date         : Tue Mar 24 12:53:14 2015
| Host         : phys-pc458-4 running 64-bit Service Pack 1  (build 7601)
| Command      : report_utilization -file toplevel_utilization_placed.rpt -pb toplevel_utilization_placed.pb
| Design       : toplevel
| Device       : xc7a200t
| Design State : Fully Placed
-------------------------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. Slice Logic
--------------

+----------------------------+-------+-------+-----------+-------+
|          Site Type         |  Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs                 |  9844 |     0 |    133800 |  7.35 |
|   LUT as Logic             |  8701 |     0 |    133800 |  6.50 |
|   LUT as Memory            |  1143 |     0 |     46200 |  2.47 |
|     LUT as Distributed RAM |   984 |     0 |           |       |
|     LUT as Shift Register  |   159 |     0 |           |       |
| Slice Registers            | 10920 |     0 |    267600 |  4.08 |
|   Register as Flip Flop    | 10916 |     0 |    267600 |  4.07 |
|   Register as Latch        |     0 |     0 |    267600 |  0.00 |
|   Register as AND/OR       |     4 |     0 |    267600 | <0.01 |
| F7 Muxes                   |   238 |     0 |     66900 |  0.35 |
| F8 Muxes                   |    23 |     0 |     33450 |  0.06 |
+----------------------------+-------+-------+-----------+-------+


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 4     |            _ |           - |            - |
| 0     |            _ |           - |          Set |
| 0     |            _ |           - |        Reset |
| 0     |            _ |         Set |            - |
| 0     |            _ |       Reset |            - |
| 0     |          Yes |           - |            - |
| 229   |          Yes |           - |          Set |
| 635   |          Yes |           - |        Reset |
| 388   |          Yes |         Set |            - |
| 9664  |          Yes |       Reset |            - |
+-------+--------------+-------------+--------------+


2. Slice Logic Distribution
---------------------------

+-------------------------------------------------------------+------------+-------+-----------+-------+
|                          Site Type                          |    Used    | Fixed | Available | Util% |
+-------------------------------------------------------------+------------+-------+-----------+-------+
| Slice                                                       |       4498 |     0 |     33450 | 13.44 |
|   SLICEL                                                    |       2704 |     0 |           |       |
|   SLICEM                                                    |       1794 |     0 |           |       |
| LUT as Logic                                                |       8701 |     0 |    133800 |  6.50 |
|   using O5 output only                                      |         13 |       |           |       |
|   using O6 output only                                      |       7205 |       |           |       |
|   using O5 and O6                                           |       1483 |       |           |       |
| LUT as Memory                                               |       1143 |     0 |     46200 |  2.47 |
|   LUT as Distributed RAM                                    |        984 |     0 |           |       |
|     using O5 output only                                    |          0 |       |           |       |
|     using O6 output only                                    |        840 |       |           |       |
|     using O5 and O6                                         |        144 |       |           |       |
|   LUT as Shift Register                                     |        159 |     0 |           |       |
|     using O5 output only                                    |          8 |       |           |       |
|     using O6 output only                                    |         64 |       |           |       |
|     using O5 and O6                                         |         87 |       |           |       |
| LUT Flip Flop Pairs                                         |      13163 |     0 |    133800 |  9.83 |
|   fully used LUT-FF pairs                                   |       5329 |       |           |       |
|   LUT-FF pairs with unused LUT                              |       3340 |       |           |       |
|   LUT-FF pairs with unused Flip Flop                        |       4494 |       |           |       |
| Unique Control Sets                                         |        554 |       |           |       |
| Minimum number of registers lost to control set restriction | 1668(Lost) |       |           |       |
+-------------------------------------------------------------+------------+-------+-----------+-------+


3. Memory
---------

+-------------------+------+-------+-----------+-------+
|     Site Type     | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile    |  192 |     0 |       365 | 52.60 |
|   RAMB36/FIFO*    |  192 |     0 |       365 | 52.60 |
|     RAMB36E1 only |  192 |       |           |       |
|   RAMB18          |    0 |     0 |       730 |  0.00 |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


4. DSP
------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs           |    5 |     0 |       740 |  0.67 |
|   DSP48E1 only |    5 |       |           |       |
+----------------+------+-------+-----------+-------+


5. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+-------+
|          Site Type          | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB                  |    3 |     3 |       285 |  1.05 |
|   IOB Master Pads           |    3 |       |           |       |
|   IOB Slave Pads            |    0 |       |           |       |
| Bonded IPADs                |    6 |     6 |        14 | 42.85 |
| Bonded OPADs                |    2 |     2 |         8 | 25.00 |
| PHY_CONTROL                 |    0 |     0 |        10 |  0.00 |
| PHASER_REF                  |    0 |     0 |        10 |  0.00 |
| OUT_FIFO                    |    0 |     0 |        40 |  0.00 |
| IN_FIFO                     |    0 |     0 |        40 |  0.00 |
| IDELAYCTRL                  |    0 |     0 |        10 |  0.00 |
| IBUFGDS                     |    0 |     0 |       274 |  0.00 |
| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |        40 |  0.00 |
| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |        40 |  0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       500 |  0.00 |
| IBUFDS_GTE2                 |    2 |     2 |         8 | 25.00 |
| ILOGIC                      |    0 |     0 |       285 |  0.00 |
| OLOGIC                      |    0 |     0 |       285 |  0.00 |
+-----------------------------+------+-------+-----------+-------+


6. Clocking
-----------

+------------+------+-------+-----------+-------+
|  Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL   |    9 |     0 |        32 | 28.12 |
| BUFIO      |    0 |     0 |        40 |  0.00 |
| MMCME2_ADV |    2 |     0 |        10 | 20.00 |
| PLLE2_ADV  |    0 |     0 |        10 |  0.00 |
| BUFMRCE    |    0 |     0 |        20 |  0.00 |
| BUFHCE     |    0 |     0 |       120 |  0.00 |
| BUFR       |    0 |     0 |        40 |  0.00 |
+------------+------+-------+-----------+-------+


7. Specific Feature
-------------------

+-------------+------+-------+-----------+-------+
|  Site Type  | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2     |    1 |     0 |         4 | 25.00 |
| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
| DNA_PORT    |    0 |     0 |         1 |  0.00 |
| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
| ICAPE2      |    0 |     0 |         2 |  0.00 |
| PCIE_2_1    |    0 |     0 |         1 |  0.00 |
| STARTUPE2   |    0 |     0 |         1 |  0.00 |
| XADC        |    0 |     0 |         1 |  0.00 |
+-------------+------+-------+-----------+-------+


8. Primitives
-------------

+---------------+------+---------------------+
|    Ref Name   | Used | Functional Category |
+---------------+------+---------------------+
| FDRE          | 9664 |        Flop & Latch |
| LUT6          | 3237 |                 LUT |
| LUT5          | 1939 |                 LUT |
| LUT3          | 1794 |                 LUT |
| LUT4          | 1743 |                 LUT |
| LUT2          | 1274 |                 LUT |
| RAMD64E       |  840 |  Distributed Memory |
| FDCE          |  635 |        Flop & Latch |
| CARRY4        |  432 |          CarryLogic |
| FDSE          |  388 |        Flop & Latch |
| MUXF7         |  238 |               MuxFx |
| SRL16E        |  236 |  Distributed Memory |
| RAMD32        |  232 |  Distributed Memory |
| FDPE          |  229 |        Flop & Latch |
| LUT1          |  197 |                 LUT |
| RAMB36E1      |  192 |        Block Memory |
| RAMS32        |   56 |  Distributed Memory |
| MUXF8         |   23 |               MuxFx |
| BUFG          |    9 |               Clock |
| SRLC16E       |    7 |  Distributed Memory |
| IBUF          |    7 |                  IO |
| DSP48E1       |    5 |    Block Arithmetic |
| OBUF          |    4 |                  IO |
| AND2B1L       |    4 |              Others |
| SRLC32E       |    3 |  Distributed Memory |
| MMCME2_ADV    |    2 |               Clock |
| IBUFDS_GTE2   |    2 |                  IO |
| OBUFT         |    1 |                  IO |
| GTPE2_COMMON  |    1 |                  IO |
| GTPE2_CHANNEL |    1 |                  IO |
| BSCANE2       |    1 |              Others |
+---------------+------+---------------------+


9. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


10. Instantiated Netlists
-------------------------

+----------+------+
| Ref Name | Used |
+----------+------+


