Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version     : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
| Date             : Tue Mar 24 12:55:30 2015
| Host             : phys-pc458-4 running 64-bit Service Pack 1  (build 7601)
| Command          : report_power -file toplevel_power_routed.rpt -pb toplevel_power_summary_routed.pb
| Design           : toplevel
| Device           : xc7a200tfbg484-2
| Design State     : Routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
---------------------------------------------------------------------------------------------------------------

Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+-------+
| Total On-Chip Power (W)  | 0.520 |
| Dynamic (W)              | 0.362 |
| Device Static (W)        | 0.158 |
| Effective TJA (C/W)      | 2.5   |
| Max Ambient (C)          | 83.7  |
| Junction Temperature (C) | 26.3  |
| Confidence Level         | Low   |
| Setting File             | ---   |
| Simulation Activity File | ---   |
| Design Nets Matched      | NA    |
+--------------------------+-------+


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.030 |        9 |       --- |             --- |
| Slice Logic              |     0.022 |    25203 |       --- |             --- |
|   LUT as Logic           |     0.018 |     8701 |    133800 |            6.50 |
|   Register               |     0.001 |    10920 |    267600 |            4.08 |
|   CARRY4                 |     0.001 |      432 |     33450 |            1.29 |
|   LUT as Distributed RAM |    <0.001 |      984 |     46200 |            2.12 |
|   F7/F8 Muxes            |    <0.001 |      261 |    133800 |            0.19 |
|   LUT as Shift Register  |    <0.001 |      159 |     46200 |            0.34 |
|   BUFG                   |    <0.001 |        3 |        32 |            9.37 |
|   Others                 |    <0.001 |     2031 |       --- |             --- |
|   BUFR                   |     0.000 |        2 |       160 |            1.25 |
| Signals                  |     0.033 |    18304 |       --- |             --- |
| Block RAM                |     0.012 |      192 |       365 |           52.60 |
| MMCM                     |     0.160 |        2 |        10 |           20.00 |
| DSPs                     |     0.004 |        5 |       740 |            0.67 |
| I/O                      |    <0.001 |        3 |       285 |            1.05 |
| GTP                      |     0.101 |        1 |       --- |             --- |
| Static Power             |     0.158 |          |           |                 |
| Total                    |     0.520 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.142 |       0.106 |      0.036 |
| Vccaux    |       1.800 |     0.119 |       0.088 |      0.031 |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |
| Vcco25    |       2.500 |     0.005 |       0.000 |      0.005 |
| Vcco18    |       1.800 |     0.005 |       0.000 |      0.005 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.006 |       0.001 |      0.005 |
| MGTAVcc   |       1.000 |     0.052 |       0.051 |      0.001 |
| MGTAVtt   |       1.200 |     0.039 |       0.036 |      0.003 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
| Clock nodes activity        | Low        | User specified less than 75% of clocks                 | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
| Device models               | High       | Device models are Production                           |                                                                                                                    |
|                             |            |                                                        |                                                                                                                    |
| Overall confidence level    | Low        |                                                        |                                                                                                                    |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 2.5                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 4.2                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+-----------------+
| Clock                                                                                                                             | Domain                                                                                                                    | Constraint (ns) |
+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+-----------------+
| clkfbout                                                                                                                          | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkfbout                                                             |            16.0 |
| clkout0                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0                                                              |             8.0 |
| clkout1                                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1                                                              |            16.0 |
| mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/RXOUTCLK | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/I        |            16.0 |
| mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtpe2_i/TXOUTCLK | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/txoutclk |            16.0 |
| mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/DRCK                                                                                            | mbsys_i/mdm_1/U0/I                                                                                                        |            33.3 |
| mbsys_i/mdm_1/U0/Use_E2.BSCANE2_I/UPDATE                                                                                          | mbsys_i/mdm_1/U0/Dbg_Update_0__0                                                                                          |            33.3 |
+-----------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+-----------------------------------------------------------------------------------+-----------+
| Name                                                                              | Power (W) |
+-----------------------------------------------------------------------------------+-----------+
| toplevel                                                                          |     0.362 |
|   mbsys_i                                                                         |     0.361 |
|     axi_bram_ctrl_0                                                               |     0.004 |
|       U0                                                                          |     0.004 |
|         gext_inst.abcv4_0_ext_inst                                                |     0.004 |
|           GEN_AXI4.I_FULL_AXI                                                     |     0.004 |
|             I_RD_CHNL                                                             |     0.003 |
|               I_WRAP_BRST                                                         |    <0.001 |
|             I_WR_CHNL                                                             |    <0.001 |
|               BID_FIFO                                                            |    <0.001 |
|               I_WRAP_BRST                                                         |    <0.001 |
|     axi_bram_ctrl_0_bram                                                          |     0.006 |
|       U0                                                                          |     0.006 |
|         inst_blk_mem_gen                                                          |     0.006 |
|           gnative_mem_map_bmg.native_mem_map_blk_mem_gen                          |     0.006 |
|             valid.cstr                                                            |     0.006 |
|               has_mux_b.B                                                         |    <0.001 |
|               ramloop[0].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[10].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[11].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[12].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[13].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[14].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[15].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[16].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[17].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[18].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[19].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[1].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[20].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[21].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[22].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[23].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[24].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[25].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[26].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[27].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[28].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[29].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[2].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[30].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[31].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[32].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[33].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[34].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[35].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[36].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[37].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[38].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[39].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[3].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[40].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[41].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[42].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[43].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[44].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[45].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[46].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[47].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[48].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[49].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[4].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[50].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[51].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[52].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[53].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[54].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[55].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[56].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[57].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[58].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[59].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[5].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[60].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[61].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[62].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[63].ram.r                                                   |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[6].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[7].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[8].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|               ramloop[9].ram.r                                                    |    <0.001 |
|                 prim_noinit.ram                                                   |    <0.001 |
|     axi_ethernet_0                                                                |     0.262 |
|       U0                                                                          |     0.262 |
|         eth_buf                                                                   |     0.015 |
|           U0                                                                      |     0.015 |
|             AXITX_2_TXCLIENT_FSM_GO                                               |    <0.001 |
|               ClkB_reset_inst                                                     |    <0.001 |
|             CLK2AXICLK_ISR_7                                                      |     0.000 |
|             COMBINE_RESETS                                                        |     0.002 |
|               AXI_RESET_TO_GTX                                                    |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               AXI_RESET_TO_RXCLIENT                                               |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               AXI_RESET_TO_RXD_AXSTREAM                                           |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               AXI_RESET_TO_RXS_AXSTREAM                                           |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               AXI_RESET_TO_TXCLIENT                                               |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               AXI_RESET_TO_TXC_AXSTREAM                                           |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               AXI_RESET_TO_TXD_AXSTREAM                                           |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               RXD_AXSTREAM_TO_RXS_AXSTREAM                                        |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               TXC_AXSTREAM_TO_RXD_AXSTREAM                                        |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               TXC_AXSTREAM_TO_RXS_AXSTREAM                                        |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               TXD_AXSTREAM_TO_RXD_AXSTREAM                                        |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               TXD_AXSTREAM_TO_RXS_AXSTREAM                                        |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|               TXD_AXSTREAM_TO_TXC_AXSTREAM                                        |    <0.001 |
|                 ClkA_reset_inst                                                   |    <0.001 |
|                 ClkB_reset_inst                                                   |    <0.001 |
|             I_ADDR_SHIM                                                           |    <0.001 |
|             I_AXI_LITE_IPIF                                                       |    <0.001 |
|               I_SLAVE_ATTACHMENT                                                  |    <0.001 |
|                 I_DECODER                                                         |    <0.001 |
|             I_REGISTERS                                                           |    <0.001 |
|               CR_I                                                                |    <0.001 |
|               IE_I                                                                |     0.000 |
|               IFGP_I                                                              |     0.000 |
|               IP_I                                                                |    <0.001 |
|               IS_I                                                                |     0.000 |
|               RTAG_I                                                              |     0.000 |
|               TPID0_I                                                             |     0.000 |
|               TPID1_I                                                             |     0.000 |
|               TP_I                                                                |     0.000 |
|               TTAG_I                                                              |     0.000 |
|               UAWL_I                                                              |     0.000 |
|               UAWU_I                                                              |     0.000 |
|             PCSPMA_STATUS_CROSS_I[0].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[10].sync_pcspma_status                          |     0.000 |
|             PCSPMA_STATUS_CROSS_I[11].sync_pcspma_status                          |     0.000 |
|             PCSPMA_STATUS_CROSS_I[12].sync_pcspma_status                          |     0.000 |
|             PCSPMA_STATUS_CROSS_I[13].sync_pcspma_status                          |     0.000 |
|             PCSPMA_STATUS_CROSS_I[14].sync_pcspma_status                          |     0.000 |
|             PCSPMA_STATUS_CROSS_I[15].sync_pcspma_status                          |     0.000 |
|             PCSPMA_STATUS_CROSS_I[1].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[2].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[3].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[4].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[5].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[6].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[7].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[8].sync_pcspma_status                           |     0.000 |
|             PCSPMA_STATUS_CROSS_I[9].sync_pcspma_status                           |     0.000 |
|             RAF_REG_CROSS_I                                                       |    <0.001 |
|             RCV_INTFCE_I                                                          |     0.006 |
|               NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I                                     |     0.004 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[0].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[13].SYNC_RXD_LAST_READ_GRAY       |     0.000 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[1].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[2].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[35].SYNC_RXD_LAST_READ_GRAY       |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[3].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[4].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[5].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[6].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[7].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[8].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXD_LAST_READ_GRAY_PROCESS[9].SYNC_RXD_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[0].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[12].SYNC_RXS_LAST_READ_GRAY       |     0.000 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[1].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[2].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[34].SYNC_RXS_LAST_READ_GRAY       |     0.000 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[35].SYNC_RXS_LAST_READ_GRAY       |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[3].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[4].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[5].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[6].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[7].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|                 SYNC_RXS_LAST_READ_GRAY_PROCESS[8].SYNC_RXS_LAST_READ_GRAY        |    <0.001 |
|               RX_AXISTREAM_IF_I                                                   |    <0.001 |
|                 ELASTIC_FIFO                                                      |    <0.001 |
|                   I_BASIC_SFIFO                                                   |    <0.001 |
|                     inst_fifo_gen                                                 |    <0.001 |
|                       gconvfifo.rf                                                |    <0.001 |
|                         grf.rf                                                    |    <0.001 |
|                           gntv_or_sync_fifo.gl0.rd                                |    <0.001 |
|                             gr1.gdcf.dc                                           |    <0.001 |
|                               dc                                                  |    <0.001 |
|                             gr1.rfwft                                             |    <0.001 |
|                             grss.rsts                                             |    <0.001 |
|                             rpntr                                                 |    <0.001 |
|                           gntv_or_sync_fifo.gl0.wr                                |    <0.001 |
|                             gwss.wsts                                             |    <0.001 |
|                             wpntr                                                 |    <0.001 |
|                           gntv_or_sync_fifo.mem                                   |     0.000 |
|                             gdm.dm                                                |     0.000 |
|                               RAM_reg_0_31_0_5                                    |     0.000 |
|                               RAM_reg_0_31_12_17                                  |     0.000 |
|                               RAM_reg_0_31_18_23                                  |     0.000 |
|                               RAM_reg_0_31_24_29                                  |     0.000 |
|                               RAM_reg_0_31_30_35                                  |     0.000 |
|                               RAM_reg_0_31_6_11                                   |     0.000 |
|               RX_DP_MEM_IF_I                                                      |     0.001 |
|                 I_RXD_MEM                                                         |    <0.001 |
|                   FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN                   |    <0.001 |
|                     inst_blk_mem_gen                                              |    <0.001 |
|                       gnativebmg.native_blk_mem_gen                               |    <0.001 |
|                         valid.cstr                                                |    <0.001 |
|                           ramloop[0].ram.r                                        |    <0.001 |
|                             prim_noinit.ram                                       |    <0.001 |
|                 I_RXS_MEM                                                         |    <0.001 |
|                   FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN                   |    <0.001 |
|                     inst_blk_mem_gen                                              |    <0.001 |
|                       gnativebmg.native_blk_mem_gen                               |    <0.001 |
|                         valid.cstr                                                |    <0.001 |
|                           ramloop[0].ram.r                                        |    <0.001 |
|                             prim_noinit.ram                                       |    <0.001 |
|             RXCLCLK2AXICLK_INTRPT0                                                |    <0.001 |
|               data_sync                                                           |     0.000 |
|             RXCLCLK2AXICLK_INTRPT1                                                |    <0.001 |
|               data_sync                                                           |     0.000 |
|             RXCLCLK2AXICLK_INTRPT2                                                |    <0.001 |
|               data_sync                                                           |     0.000 |
|             RXCLCLK2AXICLK_ISR_6                                                  |     0.000 |
|             TXCLCLK2AXICLK_ISR_1                                                  |    <0.001 |
|               data_sync                                                           |     0.000 |
|             TXCLCLK2AXICLK_ISR_5                                                  |    <0.001 |
|               data_sync                                                           |     0.000 |
|             TXCLCLK2AXICLK_ISR_8                                                  |     0.000 |
|             TX_IFGP_CROSS_I                                                       |    <0.001 |
|             TX_INTFCE_I                                                           |     0.006 |
|               TX_AXISTREAM_INTERFACE                                              |    <0.001 |
|                 GEN_BASIC.TX_BASIC_INTERFACE                                      |    <0.001 |
|               TX_EMAC_INTERFACE                                                   |     0.002 |
|               TX_MEM_INTERFACE                                                    |     0.003 |
|                 TXC_MEM                                                           |     0.002 |
|                   FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN                   |     0.002 |
|                     inst_blk_mem_gen                                              |     0.002 |
|                       gnativebmg.native_blk_mem_gen                               |     0.002 |
|                         valid.cstr                                                |     0.002 |
|                           ramloop[0].ram.r                                        |     0.002 |
|                             prim_init.ram                                         |     0.002 |
|                 TXD_MEM                                                           |     0.002 |
|                   FAMILY_SUPPORTED.I_TRUE_DUAL_PORT_BLK_MEM_GEN                   |     0.002 |
|                     inst_blk_mem_gen                                              |     0.002 |
|                       gnativebmg.native_blk_mem_gen                               |     0.002 |
|                         valid.cstr                                                |     0.002 |
|                           ramloop[0].ram.r                                        |     0.002 |
|                             prim_noinit.ram                                       |     0.002 |
|             TX_PAUSE_FRAME_CROSS_I                                                |    <0.001 |
|               data_sync                                                           |    <0.001 |
|             gen_sample_rx_mac_config                                              |    <0.001 |
|               data_sync                                                           |    <0.001 |
|             gen_sample_tx_mac_config                                              |    <0.001 |
|               data_sync                                                           |    <0.001 |
|         eth_mac                                                                   |     0.028 |
|           U0                                                                      |     0.028 |
|             axi4_lite_ipif                                                        |     0.003 |
|               axi_lite_top                                                        |     0.003 |
|                 I_SLAVE_ATTACHMENT                                                |     0.003 |
|                   DATA_PHASE_WDT.I_DPTO_COUNTER                                   |    <0.001 |
|                   I_DECODER                                                       |    <0.001 |
|             bd_0_eth_mac_0_core                                                   |     0.024 |
|               addr_filter_top                                                     |     0.002 |
|                 address_filter_inst                                               |     0.001 |
|                   addr_regs.unicast_address_compare                               |    <0.001 |
|                     byte_wide_ram[0].header_compare_dist_ram                      |    <0.001 |
|                     byte_wide_ram[0].header_field_dist_ram                        |    <0.001 |
|                     byte_wide_ram[1].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[1].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[2].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[2].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[3].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[3].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[4].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[4].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[5].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[5].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[6].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[6].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[7].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[7].header_field_dist_ram                        |     0.000 |
|                   address_filters[0].configurable_addresses                       |    <0.001 |
|                     byte_wide_ram[0].header_compare_dist_ram                      |    <0.001 |
|                     byte_wide_ram[0].header_field_dist_ram                        |    <0.001 |
|                     byte_wide_ram[1].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[1].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[2].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[2].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[3].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[3].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[4].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[4].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[5].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[5].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[6].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[6].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[7].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[7].header_field_dist_ram                        |     0.000 |
|                   address_filters[0].sync_enable                                  |    <0.001 |
|                   address_filters[1].configurable_addresses                       |    <0.001 |
|                     byte_wide_ram[0].header_compare_dist_ram                      |    <0.001 |
|                     byte_wide_ram[0].header_field_dist_ram                        |    <0.001 |
|                     byte_wide_ram[1].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[1].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[2].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[2].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[3].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[3].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[4].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[4].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[5].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[5].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[6].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[6].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[7].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[7].header_field_dist_ram                        |     0.000 |
|                   address_filters[1].sync_enable                                  |    <0.001 |
|                   address_filters[2].configurable_addresses                       |    <0.001 |
|                     byte_wide_ram[0].header_compare_dist_ram                      |    <0.001 |
|                     byte_wide_ram[0].header_field_dist_ram                        |    <0.001 |
|                     byte_wide_ram[1].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[1].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[2].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[2].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[3].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[3].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[4].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[4].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[5].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[5].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[6].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[6].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[7].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[7].header_field_dist_ram                        |     0.000 |
|                   address_filters[2].sync_enable                                  |    <0.001 |
|                   address_filters[3].configurable_addresses                       |    <0.001 |
|                     byte_wide_ram[0].header_compare_dist_ram                      |    <0.001 |
|                     byte_wide_ram[0].header_field_dist_ram                        |    <0.001 |
|                     byte_wide_ram[1].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[1].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[2].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[2].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[3].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[3].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[4].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[4].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[5].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[5].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[6].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[6].header_field_dist_ram                        |     0.000 |
|                     byte_wide_ram[7].header_compare_dist_ram                      |     0.000 |
|                     byte_wide_ram[7].header_field_dist_ram                        |     0.000 |
|                   address_filters[3].sync_enable                                  |    <0.001 |
|                   byte_wide_ram[0].header_field_dist_ram                          |    <0.001 |
|                   byte_wide_ram[1].header_field_dist_ram                          |    <0.001 |
|                   byte_wide_ram[2].header_field_dist_ram                          |    <0.001 |
|                   byte_wide_ram[3].header_field_dist_ram                          |    <0.001 |
|                   byte_wide_ram[4].header_field_dist_ram                          |    <0.001 |
|                   byte_wide_ram[5].header_field_dist_ram                          |    <0.001 |
|                   byte_wide_ram[6].header_field_dist_ram                          |    <0.001 |
|                   byte_wide_ram[7].header_field_dist_ram                          |    <0.001 |
|                   resync_promiscuous_mode                                         |    <0.001 |
|                   sync_update                                                     |    <0.001 |
|               flow                                                                |     0.002 |
|                 pfc_tx                                                            |    <0.001 |
|                 rx                                                                |    <0.001 |
|                 rx_pause                                                          |    <0.001 |
|                 sync_rx_enable                                                    |    <0.001 |
|                 sync_tx_enable                                                    |    <0.001 |
|                 tx                                                                |     0.001 |
|                 tx_pause                                                          |    <0.001 |
|                   sync_good_rx                                                    |    <0.001 |
|               intc_control.intc                                                   |    <0.001 |
|                 gen_sync[0].sync_request                                          |    <0.001 |
|               ipic_mux_inst                                                       |    <0.001 |
|               man_block.managen                                                   |    <0.001 |
|                 conf                                                              |    <0.001 |
|                 mdio_enabled.phy                                                  |    <0.001 |
|               man_reset.sync_mgmt_reset_host_i                                    |    <0.001 |
|               rx_axi_shim                                                         |    <0.001 |
|               rxgen                                                               |     0.004 |
|                 CONFIG_SELECT.CALCULATE_CRC2                                      |    <0.001 |
|                   CRC1                                                            |    <0.001 |
|                   CRC2                                                            |    <0.001 |
|                   CRC3                                                            |    <0.001 |
|                   CRC4                                                            |    <0.001 |
|                   CRC5                                                            |    <0.001 |
|                 CONFIG_SELECT.SPEED_0_SYNC                                        |    <0.001 |
|                 CONFIG_SELECT.SPEED_1_SYNC                                        |    <0.001 |
|                 FCS_CHECK                                                         |    <0.001 |
|                 FRAME_CHECKER                                                     |    <0.001 |
|                 FRAME_DECODER                                                     |    <0.001 |
|                 RX_SM                                                             |    <0.001 |
|               stats_block.statistics_counters                                     |     0.011 |
|                 fast_statistic_control[0].fast_statistics                         |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 fast_statistic_control[1].fast_statistics                         |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 fast_statistic_control[2].fast_statistics                         |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 fast_statistic_control[3].fast_statistics                         |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control1[10].frame_size_stats1                     |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control1[4].frame_size_stats1                      |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control1[5].frame_size_stats1                      |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control1[6].frame_size_stats1                      |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control1[7].frame_size_stats1                      |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control1[8].frame_size_stats1                      |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control1[9].frame_size_stats1                      |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control2[11].frame_size_stats2                     |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control2[12].frame_size_stats2                     |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control2[13].frame_size_stats2                     |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control2[14].frame_size_stats2                     |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control2[15].frame_size_stats2                     |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control2[16].frame_size_stats2                     |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 frame_size_bin_control2[17].frame_size_stats2                     |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 gen_distributed_mem[0].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[10].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[11].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[12].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[13].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[14].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[15].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[16].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[17].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[18].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[19].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[1].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[20].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[21].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[22].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[23].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[24].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[25].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[26].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[27].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[28].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[29].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[2].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[30].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[31].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[32].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[33].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[34].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[35].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[36].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[37].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[38].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[39].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[3].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[40].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[41].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[42].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[43].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[44].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[45].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[46].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[47].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[48].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[49].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[4].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[50].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[51].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[52].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[53].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[54].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[55].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[56].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[57].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[58].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[59].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[5].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[60].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[61].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[62].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[63].RAM64X1D_inst                             |    <0.001 |
|                 gen_distributed_mem[6].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[7].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[8].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_mem[9].RAM64X1D_inst                              |    <0.001 |
|                 gen_distributed_parity[0].RAM64X1D_inst                           |    <0.001 |
|                 gen_distributed_parity[1].RAM64X1D_inst                           |    <0.001 |
|                 gen_distributed_parity[2].RAM64X1D_inst                           |    <0.001 |
|                 gen_distributed_parity[3].RAM64X1D_inst                           |    <0.001 |
|                 gen_distributed_parity[4].RAM64X1D_inst                           |    <0.001 |
|                 gen_distributed_parity[5].RAM64X1D_inst                           |    <0.001 |
|                 gen_distributed_parity[6].RAM64X1D_inst                           |    <0.001 |
|                 gen_distributed_parity[7].RAM64X1D_inst                           |    <0.001 |
|                 general_statisic_control[18].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[19].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[20].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[21].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[22].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[23].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[24].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[25].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[26].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[27].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[28].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[29].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[30].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[31].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[32].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 general_statisic_control[33].general_statisics                    |    <0.001 |
|                   sync_inc_vector                                                 |    <0.001 |
|                 rx_byte_counter                                                   |    <0.001 |
|                   SYNC_STATS_RESET                                                |    <0.001 |
|                   accum_gray_resync[0].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[1].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[2].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[3].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[4].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[5].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[6].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[7].sync_accum_gray_i                          |    <0.001 |
|                 rx_fragment_counter                                               |    <0.001 |
|                   accum_gray_resync[0].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[1].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[2].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[3].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[4].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[5].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[6].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[7].sync_accum_gray_i                          |    <0.001 |
|                 rx_undersized_counter                                             |    <0.001 |
|                   accum_gray_resync[0].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[1].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[2].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[3].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[4].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[5].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[6].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[7].sync_accum_gray_i                          |    <0.001 |
|                 sync_request                                                      |    <0.001 |
|                 sync_response                                                     |    <0.001 |
|                 tx_byte_counter                                                   |    <0.001 |
|                   SYNC_STATS_RESET                                                |    <0.001 |
|                   accum_gray_resync[0].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[1].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[2].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[3].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[4].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[5].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[6].sync_accum_gray_i                          |    <0.001 |
|                   accum_gray_resync[7].sync_accum_gray_i                          |    <0.001 |
|               sync_rx_reset_i                                                     |    <0.001 |
|               sync_stats_reset                                                    |    <0.001 |
|               sync_tx_reset_i                                                     |    <0.001 |
|               tx_axi_intf.tx_axi_shim                                             |    <0.001 |
|               txgen                                                               |     0.003 |
|                 CONFIG_SELECT.CRCGEN2                                             |    <0.001 |
|                   CRC1                                                            |    <0.001 |
|                   CRC2                                                            |    <0.001 |
|                   CRC3                                                            |    <0.001 |
|                   CRC4                                                            |    <0.001 |
|                   CRC5                                                            |    <0.001 |
|                 CONFIG_SELECT.SPEED_0_SYNC                                        |    <0.001 |
|                 CONFIG_SELECT.SPEED_1_SYNC                                        |    <0.001 |
|                 TX_SM1                                                            |     0.002 |
|                   CRCGEN                                                          |    <0.001 |
|             vector_decode_inst                                                    |    <0.001 |
|         pcs_pma                                                                   |     0.220 |
|           U0                                                                      |     0.220 |
|             core_clocking_i                                                       |     0.106 |
|             core_gt_common_i                                                      |    <0.001 |
|             core_resets_i                                                         |    <0.001 |
|             pcs_pma_block_i                                                       |     0.113 |
|               bd_0_pcs_pma_0_core                                                 |     0.004 |
|                 gpcs_pma_inst                                                     |     0.004 |
|                   HAS_AUTO_NEG.AUTO_NEGOTIATION                                   |     0.001 |
|                   HAS_MANAGEMENT.MDIO                                             |    <0.001 |
|                     MDIO_INTERFACE_1                                              |    <0.001 |
|                     SYNC_MDC                                                      |    <0.001 |
|                     SYNC_MDIO_IN                                                  |    <0.001 |
|                   RECEIVER                                                        |    <0.001 |
|                   SYNCHRONISATION                                                 |    <0.001 |
|                   SYNC_SIGNAL_DETECT                                              |    <0.001 |
|                   TRANSMITTER                                                     |    <0.001 |
|               sgmii_logic                                                         |    <0.001 |
|                 clock_generation                                                  |    <0.001 |
|                   clk_div_stage1                                                  |    <0.001 |
|                   clk_div_stage2                                                  |    <0.001 |
|                 gen_sync_reset                                                    |    <0.001 |
|                 receiver                                                          |    <0.001 |
|                 resync_speed_100                                                  |    <0.001 |
|                 resync_speed_10_100                                               |    <0.001 |
|                 transmitter                                                       |    <0.001 |
|               sync_block_reset_done                                               |    <0.001 |
|               transceiver_inst                                                    |     0.108 |
|                 gtwizard_inst                                                     |     0.104 |
|                   U0                                                              |     0.104 |
|                     gt0_rxresetfsm_i                                              |    <0.001 |
|                       sync_RXRESETDONE                                            |     0.000 |
|                       sync_data_valid                                             |    <0.001 |
|                       sync_mmcm_lock_reclocked                                    |     0.000 |
|                       sync_pll0lock                                               |    <0.001 |
|                       sync_run_phase_alignment_int                                |    <0.001 |
|                       sync_rx_fsm_reset_done_int                                  |    <0.001 |
|                       sync_time_out_wait_bypass                                   |    <0.001 |
|                     gt0_txresetfsm_i                                              |     0.001 |
|                       sync_PLL0LOCK                                               |    <0.001 |
|                       sync_TXRESETDONE                                            |     0.000 |
|                       sync_mmcm_lock_reclocked                                    |     0.000 |
|                       sync_run_phase_alignment_int                                |    <0.001 |
|                       sync_time_out_wait_bypass                                   |    <0.001 |
|                       sync_tx_fsm_reset_done_int                                  |    <0.001 |
|                     gtwizard_i                                                    |     0.102 |
|                       gt0_GTWIZARD_i                                              |     0.102 |
|                         gtrxreset_seq_i                                           |    <0.001 |
|                           sync_gtrxreset_in                                       |    <0.001 |
|                           sync_rst_sync                                           |    <0.001 |
|                           sync_rxpmaresetdone                                     |    <0.001 |
|                         rxpmarst_seq_i                                            |    <0.001 |
|                           sync_RXPMARESETDONE                                     |    <0.001 |
|                           sync_rst_sync                                           |    <0.001 |
|                     sync_block_gtrxreset                                          |    <0.001 |
|                 reclock_encommaalign                                              |    <0.001 |
|                 reclock_rxreset                                                   |    <0.001 |
|                 reclock_txreset                                                   |    <0.001 |
|                 reset_wtd_timer                                                   |    <0.001 |
|                 rx_elastic_buffer_inst                                            |     0.003 |
|                   ram_reg_0_63_0_2                                                |    <0.001 |
|                   ram_reg_0_63_12_14                                              |    <0.001 |
|                   ram_reg_0_63_15_17                                              |    <0.001 |
|                   ram_reg_0_63_18_20                                              |    <0.001 |
|                   ram_reg_0_63_21_23                                              |    <0.001 |
|                   ram_reg_0_63_24_26                                              |    <0.001 |
|                   ram_reg_0_63_27_29                                              |    <0.001 |
|                   ram_reg_0_63_3_5                                                |    <0.001 |
|                   ram_reg_0_63_6_8                                                |    <0.001 |
|                   ram_reg_0_63_9_11                                               |    <0.001 |
|                   reclock_rd_addrgray[0].sync_rd_addrgray                         |    <0.001 |
|                   reclock_rd_addrgray[1].sync_rd_addrgray                         |    <0.001 |
|                   reclock_rd_addrgray[2].sync_rd_addrgray                         |    <0.001 |
|                   reclock_rd_addrgray[3].sync_rd_addrgray                         |    <0.001 |
|                   reclock_rd_addrgray[4].sync_rd_addrgray                         |    <0.001 |
|                   reclock_rd_addrgray[5].sync_rd_addrgray                         |    <0.001 |
|                   reclock_wr_addrgray[0].sync_wr_addrgray                         |    <0.001 |
|                   reclock_wr_addrgray[1].sync_wr_addrgray                         |    <0.001 |
|                   reclock_wr_addrgray[2].sync_wr_addrgray                         |    <0.001 |
|                   reclock_wr_addrgray[3].sync_wr_addrgray                         |    <0.001 |
|                   reclock_wr_addrgray[4].sync_wr_addrgray                         |    <0.001 |
|                   reclock_wr_addrgray[5].sync_wr_addrgray                         |    <0.001 |
|                   sync_initialize_ram_comp                                        |    <0.001 |
|                 sync_block_data_valid                                             |    <0.001 |
|     axi_ethernet_0_fifo                                                           |     0.003 |
|       U0                                                                          |     0.003 |
|         COMP_IPIC2AXI_S                                                           |     0.002 |
|           grxd.COMP_RX_FIFO                                                       |    <0.001 |
|             gfifo_gen.COMP_AXIS_FG_FIFO                                           |    <0.001 |
|               COMP_FIFO                                                           |    <0.001 |
|                 inst_fifo_gen                                                     |    <0.001 |
|                   gaxis_fifo.gaxisf.axisf                                         |    <0.001 |
|                     grf.rf                                                        |    <0.001 |
|                       gntv_or_sync_fifo.gl0.rd                                    |    <0.001 |
|                         gr1.gdcf.dc                                               |    <0.001 |
|                           dc                                                      |    <0.001 |
|                         gr1.rfwft                                                 |    <0.001 |
|                         grss.gpe.rdpe                                             |    <0.001 |
|                         grss.rsts                                                 |    <0.001 |
|                           c1                                                      |     0.000 |
|                           c2                                                      |    <0.001 |
|                         rpntr                                                     |    <0.001 |
|                       gntv_or_sync_fifo.gl0.wr                                    |    <0.001 |
|                         gwss.gpf.wrpf                                             |    <0.001 |
|                         gwss.wsts                                                 |    <0.001 |
|                           c0                                                      |     0.000 |
|                           c1                                                      |    <0.001 |
|                         wpntr                                                     |    <0.001 |
|                       gntv_or_sync_fifo.mem                                       |    <0.001 |
|                         gbm.gbmg.gbmga.ngecc.bmg                                  |    <0.001 |
|                           inst_blk_mem_gen                                        |    <0.001 |
|                             gnativebmg.native_blk_mem_gen                         |    <0.001 |
|                               valid.cstr                                          |    <0.001 |
|                                 ramloop[0].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                                 ramloop[1].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                                 ramloop[2].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                                 ramloop[3].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                                 ramloop[4].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                       rstblk                                                      |    <0.001 |
|           grxd.COMP_rx_len_fifo                                                   |    <0.001 |
|             FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM                                     |    <0.001 |
|               inst_fifo_gen                                                       |    <0.001 |
|                 gconvfifo.rf                                                      |    <0.001 |
|                   grf.rf                                                          |    <0.001 |
|                     gntv_or_sync_fifo.gl0.rd                                      |    <0.001 |
|                       gr1.rfwft                                                   |    <0.001 |
|                       grss.rsts                                                   |    <0.001 |
|                         c1                                                        |     0.000 |
|                         c2                                                        |    <0.001 |
|                       rpntr                                                       |    <0.001 |
|                     gntv_or_sync_fifo.gl0.wr                                      |    <0.001 |
|                       gwss.wsts                                                   |    <0.001 |
|                         c0                                                        |     0.000 |
|                         c1                                                        |    <0.001 |
|                       wpntr                                                       |    <0.001 |
|                     gntv_or_sync_fifo.mem                                         |    <0.001 |
|                       gdm.dm                                                      |    <0.001 |
|                         RAM_reg_0_63_0_2                                          |    <0.001 |
|                         RAM_reg_0_63_12_14                                        |    <0.001 |
|                         RAM_reg_0_63_15_17                                        |    <0.001 |
|                         RAM_reg_0_63_18_20                                        |    <0.001 |
|                         RAM_reg_0_63_21_21                                        |    <0.001 |
|                         RAM_reg_0_63_3_5                                          |    <0.001 |
|                         RAM_reg_0_63_6_8                                          |    <0.001 |
|                         RAM_reg_0_63_9_11                                         |    <0.001 |
|                         RAM_reg_128_191_0_2                                       |    <0.001 |
|                         RAM_reg_128_191_12_14                                     |    <0.001 |
|                         RAM_reg_128_191_15_17                                     |    <0.001 |
|                         RAM_reg_128_191_18_20                                     |    <0.001 |
|                         RAM_reg_128_191_21_21                                     |    <0.001 |
|                         RAM_reg_128_191_3_5                                       |    <0.001 |
|                         RAM_reg_128_191_6_8                                       |    <0.001 |
|                         RAM_reg_128_191_9_11                                      |    <0.001 |
|                         RAM_reg_192_255_0_2                                       |    <0.001 |
|                         RAM_reg_192_255_12_14                                     |    <0.001 |
|                         RAM_reg_192_255_15_17                                     |    <0.001 |
|                         RAM_reg_192_255_18_20                                     |    <0.001 |
|                         RAM_reg_192_255_21_21                                     |    <0.001 |
|                         RAM_reg_192_255_3_5                                       |    <0.001 |
|                         RAM_reg_192_255_6_8                                       |    <0.001 |
|                         RAM_reg_192_255_9_11                                      |    <0.001 |
|                         RAM_reg_256_319_0_2                                       |    <0.001 |
|                         RAM_reg_256_319_12_14                                     |    <0.001 |
|                         RAM_reg_256_319_15_17                                     |    <0.001 |
|                         RAM_reg_256_319_18_20                                     |    <0.001 |
|                         RAM_reg_256_319_21_21                                     |    <0.001 |
|                         RAM_reg_256_319_3_5                                       |    <0.001 |
|                         RAM_reg_256_319_6_8                                       |    <0.001 |
|                         RAM_reg_256_319_9_11                                      |    <0.001 |
|                         RAM_reg_320_383_0_2                                       |    <0.001 |
|                         RAM_reg_320_383_12_14                                     |    <0.001 |
|                         RAM_reg_320_383_15_17                                     |    <0.001 |
|                         RAM_reg_320_383_18_20                                     |    <0.001 |
|                         RAM_reg_320_383_21_21                                     |    <0.001 |
|                         RAM_reg_320_383_3_5                                       |    <0.001 |
|                         RAM_reg_320_383_6_8                                       |    <0.001 |
|                         RAM_reg_320_383_9_11                                      |    <0.001 |
|                         RAM_reg_384_447_0_2                                       |    <0.001 |
|                         RAM_reg_384_447_12_14                                     |    <0.001 |
|                         RAM_reg_384_447_15_17                                     |    <0.001 |
|                         RAM_reg_384_447_18_20                                     |    <0.001 |
|                         RAM_reg_384_447_21_21                                     |    <0.001 |
|                         RAM_reg_384_447_3_5                                       |    <0.001 |
|                         RAM_reg_384_447_6_8                                       |    <0.001 |
|                         RAM_reg_384_447_9_11                                      |    <0.001 |
|                         RAM_reg_448_511_0_2                                       |    <0.001 |
|                         RAM_reg_448_511_12_14                                     |    <0.001 |
|                         RAM_reg_448_511_15_17                                     |    <0.001 |
|                         RAM_reg_448_511_18_20                                     |    <0.001 |
|                         RAM_reg_448_511_21_21                                     |    <0.001 |
|                         RAM_reg_448_511_3_5                                       |    <0.001 |
|                         RAM_reg_448_511_6_8                                       |    <0.001 |
|                         RAM_reg_448_511_9_11                                      |    <0.001 |
|                         RAM_reg_512_575_0_2                                       |    <0.001 |
|                         RAM_reg_512_575_12_14                                     |    <0.001 |
|                         RAM_reg_512_575_15_17                                     |    <0.001 |
|                         RAM_reg_512_575_18_20                                     |    <0.001 |
|                         RAM_reg_512_575_21_21                                     |    <0.001 |
|                         RAM_reg_512_575_3_5                                       |    <0.001 |
|                         RAM_reg_512_575_6_8                                       |    <0.001 |
|                         RAM_reg_512_575_9_11                                      |    <0.001 |
|                         RAM_reg_576_639_0_2                                       |    <0.001 |
|                         RAM_reg_576_639_12_14                                     |    <0.001 |
|                         RAM_reg_576_639_15_17                                     |    <0.001 |
|                         RAM_reg_576_639_18_20                                     |    <0.001 |
|                         RAM_reg_576_639_21_21                                     |    <0.001 |
|                         RAM_reg_576_639_3_5                                       |    <0.001 |
|                         RAM_reg_576_639_6_8                                       |    <0.001 |
|                         RAM_reg_576_639_9_11                                      |    <0.001 |
|                         RAM_reg_640_703_0_2                                       |    <0.001 |
|                         RAM_reg_640_703_12_14                                     |    <0.001 |
|                         RAM_reg_640_703_15_17                                     |    <0.001 |
|                         RAM_reg_640_703_18_20                                     |    <0.001 |
|                         RAM_reg_640_703_21_21                                     |    <0.001 |
|                         RAM_reg_640_703_3_5                                       |    <0.001 |
|                         RAM_reg_640_703_6_8                                       |    <0.001 |
|                         RAM_reg_640_703_9_11                                      |    <0.001 |
|                         RAM_reg_64_127_0_2                                        |    <0.001 |
|                         RAM_reg_64_127_12_14                                      |    <0.001 |
|                         RAM_reg_64_127_15_17                                      |    <0.001 |
|                         RAM_reg_64_127_18_20                                      |    <0.001 |
|                         RAM_reg_64_127_21_21                                      |    <0.001 |
|                         RAM_reg_64_127_3_5                                        |    <0.001 |
|                         RAM_reg_64_127_6_8                                        |    <0.001 |
|                         RAM_reg_64_127_9_11                                       |    <0.001 |
|                         RAM_reg_704_767_0_2                                       |    <0.001 |
|                         RAM_reg_704_767_12_14                                     |    <0.001 |
|                         RAM_reg_704_767_15_17                                     |    <0.001 |
|                         RAM_reg_704_767_18_20                                     |    <0.001 |
|                         RAM_reg_704_767_21_21                                     |    <0.001 |
|                         RAM_reg_704_767_3_5                                       |    <0.001 |
|                         RAM_reg_704_767_6_8                                       |    <0.001 |
|                         RAM_reg_704_767_9_11                                      |    <0.001 |
|                         RAM_reg_768_831_0_2                                       |    <0.001 |
|                         RAM_reg_768_831_12_14                                     |    <0.001 |
|                         RAM_reg_768_831_15_17                                     |    <0.001 |
|                         RAM_reg_768_831_18_20                                     |    <0.001 |
|                         RAM_reg_768_831_21_21                                     |    <0.001 |
|                         RAM_reg_768_831_3_5                                       |    <0.001 |
|                         RAM_reg_768_831_6_8                                       |    <0.001 |
|                         RAM_reg_768_831_9_11                                      |    <0.001 |
|                         RAM_reg_832_895_0_2                                       |    <0.001 |
|                         RAM_reg_832_895_12_14                                     |    <0.001 |
|                         RAM_reg_832_895_15_17                                     |    <0.001 |
|                         RAM_reg_832_895_18_20                                     |    <0.001 |
|                         RAM_reg_832_895_21_21                                     |    <0.001 |
|                         RAM_reg_832_895_3_5                                       |    <0.001 |
|                         RAM_reg_832_895_6_8                                       |    <0.001 |
|                         RAM_reg_832_895_9_11                                      |    <0.001 |
|                         RAM_reg_896_959_0_2                                       |    <0.001 |
|                         RAM_reg_896_959_12_14                                     |    <0.001 |
|                         RAM_reg_896_959_15_17                                     |    <0.001 |
|                         RAM_reg_896_959_18_20                                     |    <0.001 |
|                         RAM_reg_896_959_21_21                                     |    <0.001 |
|                         RAM_reg_896_959_3_5                                       |    <0.001 |
|                         RAM_reg_896_959_6_8                                       |    <0.001 |
|                         RAM_reg_896_959_9_11                                      |    <0.001 |
|                         RAM_reg_960_1023_0_2                                      |    <0.001 |
|                         RAM_reg_960_1023_12_14                                    |    <0.001 |
|                         RAM_reg_960_1023_15_17                                    |    <0.001 |
|                         RAM_reg_960_1023_18_20                                    |    <0.001 |
|                         RAM_reg_960_1023_21_21                                    |    <0.001 |
|                         RAM_reg_960_1023_3_5                                      |    <0.001 |
|                         RAM_reg_960_1023_6_8                                      |    <0.001 |
|                         RAM_reg_960_1023_9_11                                     |    <0.001 |
|           gtxd.COMP_TXD_FIFO                                                      |    <0.001 |
|             gfifo_gen.COMP_AXIS_FG_FIFO                                           |    <0.001 |
|               COMP_FIFO                                                           |    <0.001 |
|                 inst_fifo_gen                                                     |    <0.001 |
|                   gaxis_fifo.gaxisf.axisf                                         |    <0.001 |
|                     grf.rf                                                        |    <0.001 |
|                       gntv_or_sync_fifo.gl0.rd                                    |    <0.001 |
|                         gr1.rfwft                                                 |    <0.001 |
|                         grss.gpe.rdpe                                             |    <0.001 |
|                         grss.rsts                                                 |    <0.001 |
|                           c1                                                      |     0.000 |
|                           c2                                                      |    <0.001 |
|                         rpntr                                                     |    <0.001 |
|                       gntv_or_sync_fifo.gl0.wr                                    |    <0.001 |
|                         gwss.gpf.wrpf                                             |    <0.001 |
|                         gwss.wsts                                                 |    <0.001 |
|                           c0                                                      |     0.000 |
|                           c1                                                      |    <0.001 |
|                           gaf.c2                                                  |    <0.001 |
|                         wpntr                                                     |    <0.001 |
|                       gntv_or_sync_fifo.mem                                       |    <0.001 |
|                         gbm.gbmg.gbmga.ngecc.bmg                                  |    <0.001 |
|                           inst_blk_mem_gen                                        |    <0.001 |
|                             gnativebmg.native_blk_mem_gen                         |    <0.001 |
|                               valid.cstr                                          |    <0.001 |
|                                 ramloop[0].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                                 ramloop[1].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                                 ramloop[2].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                                 ramloop[3].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                                 ramloop[4].ram.r                                  |    <0.001 |
|                                   prim_noinit.ram                                 |    <0.001 |
|                       rstblk                                                      |    <0.001 |
|         COMP_IPIF                                                                 |    <0.001 |
|           I_SLAVE_ATTACHMENT                                                      |    <0.001 |
|             I_DECODER                                                             |    <0.001 |
|     axi_gpio_0                                                                    |    <0.001 |
|       U0                                                                          |    <0.001 |
|         AXI_LITE_IPIF_I                                                           |    <0.001 |
|           I_SLAVE_ATTACHMENT                                                      |    <0.001 |
|             I_DECODER                                                             |    <0.001 |
|         gpio_core_1                                                               |    <0.001 |
|           Not_Dual.INPUT_DOUBLE_REGS3                                             |     0.000 |
|     axi_interconnect_0                                                            |     0.002 |
|       xbar                                                                        |     0.002 |
|         inst                                                                      |     0.002 |
|           gen_samd.crossbar_samd                                                  |     0.002 |
|             addr_arbiter_ar                                                       |    <0.001 |
|             addr_arbiter_aw                                                       |    <0.001 |
|             gen_decerr_slave.decerr_slave_inst                                    |    <0.001 |
|             gen_master_slots[0].gen_mi_write.wdata_mux_w                          |    <0.001 |
|               gen_wmux.wmux_aw_fifo                                               |    <0.001 |
|                 gen_srls[0].gen_rep[0].srl_nx1                                    |    <0.001 |
|             gen_master_slots[0].reg_slice_mi                                      |    <0.001 |
|               b_pipe                                                              |    <0.001 |
|               r_pipe                                                              |    <0.001 |
|             gen_master_slots[1].gen_mi_write.wdata_mux_w                          |    <0.001 |
|               gen_wmux.wmux_aw_fifo                                               |    <0.001 |
|                 gen_srls[0].gen_rep[0].srl_nx1                                    |     0.000 |
|             gen_master_slots[1].reg_slice_mi                                      |    <0.001 |
|               b_pipe                                                              |    <0.001 |
|               r_pipe                                                              |    <0.001 |
|             gen_slave_slots[0].gen_si_read.si_transactor_ar                       |    <0.001 |
|             gen_slave_slots[0].gen_si_write.si_transactor_aw                      |    <0.001 |
|             gen_slave_slots[0].gen_si_write.splitter_aw_si                        |    <0.001 |
|             gen_slave_slots[0].gen_si_write.wdata_router_w                        |    <0.001 |
|               wrouter_aw_fifo                                                     |    <0.001 |
|                 gen_srls[0].gen_rep[0].srl_nx1                                    |    <0.001 |
|             gen_slave_slots[1].gen_si_read.si_transactor_ar                       |    <0.001 |
|             splitter_aw_mi                                                        |    <0.001 |
|     axi_timer_0                                                                   |     0.003 |
|       U0                                                                          |     0.003 |
|         AXI4_LITE_I                                                               |    <0.001 |
|           I_SLAVE_ATTACHMENT                                                      |    <0.001 |
|             I_DECODER                                                             |    <0.001 |
|         TC_CORE_I                                                                 |     0.002 |
|           COUNTER_0_I                                                             |     0.001 |
|             COUNTER_I                                                             |     0.001 |
|           GEN_SECOND_TIMER.COUNTER_1_I                                            |     0.001 |
|             COUNTER_I                                                             |     0.001 |
|           READ_MUX_I                                                              |     0.000 |
|           TIMER_CONTROL_I                                                         |    <0.001 |
|             INPUT_DOUBLE_REGS3                                                    |    <0.001 |
|     clk_wiz_1                                                                     |     0.055 |
|       U0                                                                          |     0.055 |
|     mdm_1                                                                         |     0.001 |
|       U0                                                                          |     0.001 |
|         MDM_Core_I1                                                               |    <0.001 |
|           JTAG_CONTROL_I                                                          |    <0.001 |
|             Use_UART.RX_FIFO_I                                                    |    <0.001 |
|             Use_UART.TX_FIFO_I                                                    |    <0.001 |
|         Use_AXI_IPIF.AXI_LITE_IPIF_I                                              |    <0.001 |
|           I_SLAVE_ATTACHMENT                                                      |    <0.001 |
|             I_DECODER                                                             |    <0.001 |
|     microblaze_0                                                                  |     0.023 |
|       U0                                                                          |     0.023 |
|         MicroBlaze_Core_I                                                         |     0.023 |
|           Performance.Core                                                        |     0.023 |
|             Data_Flow_I                                                           |     0.011 |
|               ALU_I                                                               |    <0.001 |
|                 ALL_Bits[0].ALU_Bit_I1                                            |    <0.001 |
|                   Last_Bit.I_ALU_LUT_2                                            |    <0.001 |
|                   Last_Bit.I_ALU_LUT_V5                                           |    <0.001 |
|                   Last_Bit.MULT_AND_I                                             |    <0.001 |
|                   Last_Bit.MUXCY_XOR_I                                            |    <0.001 |
|                 ALL_Bits[10].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[11].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[12].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[13].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[14].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[15].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[16].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[17].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[18].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[19].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[1].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[20].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[21].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[22].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[23].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[24].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[25].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[26].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[27].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[28].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[29].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[2].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[30].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[31].ALU_Bit_I1                                           |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[3].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[4].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[5].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[6].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[7].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[8].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|                 ALL_Bits[9].ALU_Bit_I1                                            |    <0.001 |
|                   Not_Last_Bit.I_ALU_LUT_V5                                       |    <0.001 |
|                     Using_FPGA.Native                                             |    <0.001 |
|                   Not_Last_Bit.MUXCY_XOR_I                                        |     0.000 |
|               Barrel_Shifter_I                                                    |    <0.001 |
|               Byte_Doublet_Handle_gti_I                                           |    <0.001 |
|               Data_Flow_Logic_I                                                   |    <0.001 |
|                 Gen_Bits[0].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[10].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[11].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[12].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[13].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[14].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[15].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[16].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[17].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[18].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[19].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[1].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[20].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[21].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[22].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[23].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[24].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[25].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[26].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[27].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[28].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[29].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[2].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[30].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[31].MEM_EX_Result_Inst                                   |     0.000 |
|                 Gen_Bits[3].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[4].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[5].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[6].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[7].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[8].MEM_EX_Result_Inst                                    |     0.000 |
|                 Gen_Bits[9].MEM_EX_Result_Inst                                    |     0.000 |
|               FPU_I                                                               |     0.005 |
|                 Use_FPU.FPU_ADDSUB_I                                              |     0.002 |
|                 Use_FPU.FPU_DIV_I                                                 |    <0.001 |
|                 Use_FPU.FPU_MUL_I                                                 |     0.002 |
|                   Use_DSP48E1.dsp_module_lower                                    |    <0.001 |
|                   Use_DSP48E1.dsp_module_upper                                    |     0.002 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[10].AddSub_MULT_AND |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[10].I_ALU_LUT       |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[10].MUXCY_XOR_I     |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[1].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[1].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[2].AddSub_MULT_AND  |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[2].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[2].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[3].AddSub_MULT_AND  |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[3].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[3].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[4].AddSub_MULT_AND  |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[4].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[4].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[5].AddSub_MULT_AND  |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[5].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[5].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[6].AddSub_MULT_AND  |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[6].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[6].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[7].AddSub_MULT_AND  |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[7].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[7].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[8].AddSub_MULT_AND  |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[8].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[8].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[9].AddSub_MULT_AND  |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[9].I_ALU_LUT        |     0.000 |
|                 Use_FPU.Stage3_Add_Sub_With_Const.AddSub_Pass[9].MUXCY_XOR_I      |     0.000 |
|                 Use_FPU.Using_FPGA_3.Gen_Bits[1].mem_fpu_norm_delay_Inst          |    <0.001 |
|                 Use_FPU.Using_FPGA_3.Gen_Bits[2].mem_fpu_norm_delay_Inst          |    <0.001 |
|                 Use_FPU.Using_FPGA_3.Gen_Bits[3].mem_fpu_norm_delay_Inst          |    <0.001 |
|                 Use_FPU.Using_FPGA_3.first_mem_fpu_norm_delay_Inst                |     0.000 |
|                 Use_FPU.ex_Exp_Equal_2                                            |     0.000 |
|                   The_Compare[0].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[1].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[2].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                 Use_FPU.ex_Exp_Mant_Equal_2                                       |     0.000 |
|                   The_Compare[0].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[1].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[2].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[3].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[4].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[5].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[6].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[7].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                 Use_FPU.ex_MantA_Zero_2                                           |    <0.001 |
|                   The_Compare[0].carry_and_I1                                     |    <0.001 |
|                     MUXCY_I                                                       |    <0.001 |
|                   The_Compare[1].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[2].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[3].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[4].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[5].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                 Use_FPU.ex_MantB_Zero_2                                           |     0.000 |
|                   The_Compare[0].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[1].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[2].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[3].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[4].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|                   The_Compare[5].carry_and_I1                                     |     0.000 |
|                     MUXCY_I                                                       |     0.000 |
|               MUL_Unit_I                                                          |     0.003 |
|                 Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2       |     0.001 |
|                 Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3       |     0.001 |
|                 Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1                |     0.001 |
|               Operand_Select_I                                                    |    <0.001 |
|                 Gen_Bit[0].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[10].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[11].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[12].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[13].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[14].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[15].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[16].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[17].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[18].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[19].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[1].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[20].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[21].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[22].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[23].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[24].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[25].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[26].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[27].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[28].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[29].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[2].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[30].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[31].MUXF7_I1                                              |    <0.001 |
|                 Gen_Bit[3].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[4].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[5].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[6].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[7].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[8].MUXF7_I1                                               |    <0.001 |
|                 Gen_Bit[9].MUXF7_I1                                               |    <0.001 |
|               Register_File_I                                                     |    <0.001 |
|                 Using_LUT6.All_RAM32M[0].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[10].ram32m_i                                |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[11].ram32m_i                                |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[12].ram32m_i                                |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[13].ram32m_i                                |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[14].ram32m_i                                |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[15].ram32m_i                                |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[1].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[2].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[3].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[4].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[5].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[6].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[7].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[8].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_LUT6.All_RAM32M[9].ram32m_i                                 |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|               Shift_Logic_Module_I                                                |    <0.001 |
|                 ALL_Bits[0].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[10].HighBits.I_SHIFT_LUT6_H                              |    <0.001 |
|                 ALL_Bits[11].HighBits.I_SHIFT_LUT6_H                              |    <0.001 |
|                 ALL_Bits[12].HighBits.I_SHIFT_LUT6_H                              |    <0.001 |
|                 ALL_Bits[13].HighBits.I_SHIFT_LUT6_H                              |    <0.001 |
|                 ALL_Bits[14].HighBits.I_SHIFT_LUT6_H                              |    <0.001 |
|                 ALL_Bits[15].HighBits.I_SHIFT_LUT6_H                              |    <0.001 |
|                 ALL_Bits[16].MiddleBits.I_SHIFT_LUT6_M                            |    <0.001 |
|                 ALL_Bits[17].MiddleBits.I_SHIFT_LUT6_M                            |    <0.001 |
|                 ALL_Bits[18].MiddleBits.I_SHIFT_LUT6_M                            |    <0.001 |
|                 ALL_Bits[19].MiddleBits.I_SHIFT_LUT6_M                            |    <0.001 |
|                 ALL_Bits[1].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[20].MiddleBits.I_SHIFT_LUT6_M                            |    <0.001 |
|                 ALL_Bits[21].MiddleBits.I_SHIFT_LUT6_M                            |    <0.001 |
|                 ALL_Bits[22].MiddleBits.I_SHIFT_LUT6_M                            |    <0.001 |
|                 ALL_Bits[23].MiddleBits.I_SHIFT_LUT6_M                            |    <0.001 |
|                 ALL_Bits[24].LowBits.I_SHIFT_LUT6_L                               |    <0.001 |
|                 ALL_Bits[25].LowBits.I_SHIFT_LUT6_L                               |    <0.001 |
|                 ALL_Bits[26].LowBits.I_SHIFT_LUT6_L                               |    <0.001 |
|                 ALL_Bits[27].LowBits.I_SHIFT_LUT6_L                               |    <0.001 |
|                 ALL_Bits[28].LowBits.I_SHIFT_LUT6_L                               |    <0.001 |
|                 ALL_Bits[29].LowBits.I_SHIFT_LUT6_L                               |    <0.001 |
|                 ALL_Bits[2].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[30].LowBits.I_SHIFT_LUT6_L                               |    <0.001 |
|                 ALL_Bits[31].LowBits.I_SHIFT_LUT6_L                               |    <0.001 |
|                 ALL_Bits[3].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[4].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[5].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[6].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[7].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[8].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|                 ALL_Bits[9].HighBits.I_SHIFT_LUT6_H                               |    <0.001 |
|               Using_DAXI_ALU_Carry.Post_MUXCY_I                                   |     0.000 |
|               Using_DAXI_ALU_Carry.direct_lut_INST                                |     0.000 |
|               Using_Div_Unit.Div_unit_I1                                          |    <0.001 |
|                 D_Handle[0].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[10].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[11].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[12].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[13].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[14].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[15].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[16].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[17].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[18].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[19].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[1].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[20].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[21].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[22].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[23].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[24].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[25].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[26].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[27].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[28].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[29].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[2].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[30].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[31].MUXCY_XOR_I                                          |     0.000 |
|                 D_Handle[3].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[4].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[5].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[6].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[7].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[8].MUXCY_XOR_I                                           |     0.000 |
|                 D_Handle[9].MUXCY_XOR_I                                           |     0.000 |
|                 New_Q_Handle[0].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[0].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[10].MUXCY_XOR_I                                      |    <0.001 |
|                 New_Q_Handle[10].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[11].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[11].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[12].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[12].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[13].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[13].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[14].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[14].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[15].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[15].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[16].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[16].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[17].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[17].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[18].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[18].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[19].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[19].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[1].MUXCY_XOR_I                                       |    <0.001 |
|                 New_Q_Handle[1].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[20].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[20].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[21].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[21].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[22].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[22].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[23].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[23].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[24].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[24].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[25].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[25].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[26].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[26].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[27].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[27].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[28].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[28].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[29].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[29].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[2].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[2].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[30].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[30].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[31].MUXCY_XOR_I                                      |     0.000 |
|                 New_Q_Handle[31].New_Q_LUT4                                       |    <0.001 |
|                 New_Q_Handle[3].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[3].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[4].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[4].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[5].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[5].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[6].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[6].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[7].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[7].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[8].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[8].New_Q_LUT4                                        |    <0.001 |
|                 New_Q_Handle[9].MUXCY_XOR_I                                       |     0.000 |
|                 New_Q_Handle[9].New_Q_LUT4                                        |    <0.001 |
|               Zero_Detect_I                                                       |    <0.001 |
|                 Part_Of_Zero_Carry_Start                                          |    <0.001 |
|                 Zero_Detecting[2].I_Part_Of_Zero_Detect                           |     0.000 |
|                 Zero_Detecting[3].I_Part_Of_Zero_Detect                           |    <0.001 |
|                 Zero_Detecting[5].I_Part_Of_Zero_Detect                           |     0.000 |
|               exception_registers_I1                                              |    <0.001 |
|                 CarryIn_MUXCY                                                     |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[0].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[0].MUXCY_XOR_I                       |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[0].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[10].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[10].MUXCY_XOR_I                      |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[10].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[11].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[11].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[11].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[12].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[12].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[12].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[13].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[13].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[13].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[14].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[14].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[14].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[15].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[15].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[15].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[16].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[16].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[16].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[17].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[17].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[17].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[18].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[18].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[18].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[19].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[19].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[19].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[1].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[1].MUXCY_XOR_I                       |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[1].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[20].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[20].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[20].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[21].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[21].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[21].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[22].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[22].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[22].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[23].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[23].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[23].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[24].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[24].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[24].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[25].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[25].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[25].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[26].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[26].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[26].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[27].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[27].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[27].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[28].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[28].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[28].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[29].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[29].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[29].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[2].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[2].MUXCY_XOR_I                       |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[2].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[30].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[30].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[30].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[31].I_RET_ADDR_WB                    |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[31].MUXCY_XOR_I                      |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[31].WB_PC_FDE                        |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[3].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[3].MUXCY_XOR_I                       |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[3].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[4].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[4].MUXCY_XOR_I                       |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[4].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[5].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[5].MUXCY_XOR_I                       |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[5].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[6].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[6].MUXCY_XOR_I                       |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[6].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[7].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[7].MUXCY_XOR_I                       |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[7].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[8].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[8].MUXCY_XOR_I                       |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[8].WB_PC_FDE                         |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[9].I_RET_ADDR_WB                     |    <0.001 |
|                   Using_FPGA.Native                                               |    <0.001 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[9].MUXCY_XOR_I                       |     0.000 |
|                 Using_FPGA_LUT6.Gen_Ret_Addr[9].WB_PC_FDE                         |    <0.001 |
|               msr_reg_i                                                           |    <0.001 |
|                 MEM_MSR_Bits[24].Using_FDR.MSR_I                                  |    <0.001 |
|                 MEM_MSR_Bits[25].Using_FDR.MSR_I                                  |    <0.001 |
|                 MEM_MSR_Bits[26].Using_FDR.MSR_I                                  |    <0.001 |
|                 MEM_MSR_Bits[28].Using_FDR.MSR_I                                  |     0.000 |
|                 MEM_MSR_Bits[29].Using_FDR.MSR_I                                  |     0.000 |
|                 MEM_MSR_Bits[30].Using_FDR.MSR_I                                  |    <0.001 |
|                 OF_EX_MSR_Bits[24].Using_FDR.MSR_ex_I                             |    <0.001 |
|                 OF_EX_MSR_Bits[25].Using_FDR.MSR_ex_I                             |    <0.001 |
|                 OF_EX_MSR_Bits[26].Using_FDR.MSR_ex_I                             |    <0.001 |
|                 OF_EX_MSR_Bits[28].Using_FDR.MSR_ex_I                             |    <0.001 |
|                 OF_EX_MSR_Bits[28].Using_FDR.MSR_of_I                             |    <0.001 |
|                 OF_EX_MSR_Bits[29].Using_FDR.MSR_ex_I                             |    <0.001 |
|                 OF_EX_MSR_Bits[30].Using_FDR.MSR_ex_I                             |    <0.001 |
|                 OF_EX_MSR_Bits[30].Using_FDR.MSR_of_I                             |     0.000 |
|             Decode_I                                                              |     0.004 |
|               PC_Module_I                                                         |    <0.001 |
|                 Incr_PC[0].MUXCY_XOR_I                                            |    <0.001 |
|                 Incr_PC[10].MUXCY_XOR_I                                           |    <0.001 |
|                 Incr_PC[11].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[12].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[13].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[14].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[15].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[16].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[17].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[18].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[19].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[1].MUXCY_XOR_I                                            |    <0.001 |
|                 Incr_PC[20].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[21].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[22].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[23].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[24].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[25].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[26].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[27].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[28].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[29].MUXCY_XOR_I                                           |     0.000 |
|                 Incr_PC[2].MUXCY_XOR_I                                            |     0.000 |
|                 Incr_PC[3].MUXCY_XOR_I                                            |     0.000 |
|                 Incr_PC[4].MUXCY_XOR_I                                            |     0.000 |
|                 Incr_PC[5].MUXCY_XOR_I                                            |     0.000 |
|                 Incr_PC[6].MUXCY_XOR_I                                            |     0.000 |
|                 Incr_PC[7].MUXCY_XOR_I                                            |     0.000 |
|                 Incr_PC[8].MUXCY_XOR_I                                            |     0.000 |
|                 Incr_PC[9].MUXCY_XOR_I                                            |     0.000 |
|                 Instruction_Prefetch_Mux[0].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[0].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[10].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[10].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[11].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[11].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[12].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[12].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[13].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[13].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[14].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[14].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[15].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[15].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[16].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[16].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[17].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[17].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[18].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[18].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[19].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[19].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[1].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[1].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[20].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[20].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[21].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[21].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[22].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[22].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[23].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[23].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[24].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[24].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[25].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[25].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[26].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[26].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[27].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[27].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[28].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[28].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[29].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[29].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[2].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[2].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[30].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[30].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[31].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[31].PC_Mux_MUXF7                         |    <0.001 |
|                 Instruction_Prefetch_Mux[3].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[3].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[4].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[4].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[5].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[5].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[6].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[6].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[7].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[7].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[8].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[8].PC_Mux_MUXF7                          |    <0.001 |
|                 Instruction_Prefetch_Mux[9].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[9].PC_Mux_MUXF7                          |    <0.001 |
|               PreFetch_Buffer_I1                                                  |     0.003 |
|                 Gen_Mux_Select_LUT6[1].Gen_Sel_DFF                                |     0.000 |
|                 Gen_Mux_Select_LUT6[1].Mux_Select_LUT6                            |    <0.001 |
|                 Gen_Mux_Select_LUT6[2].Gen_Sel_DFF                                |    <0.001 |
|                 Gen_Mux_Select_LUT6[2].Mux_Select_LUT6                            |    <0.001 |
|                 Gen_Mux_Select_LUT6[3].Gen_Sel_DFF                                |     0.000 |
|                 Gen_Mux_Select_LUT6[3].Mux_Select_LUT6                            |    <0.001 |
|                 Gen_Mux_Select_LUT6[4].Gen_Sel_DFF                                |    <0.001 |
|                 Gen_Mux_Select_LUT6[4].Mux_Select_LUT6                            |    <0.001 |
|                 Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Mux_Select_Delayslot_LUT6   |    <0.001 |
|                 Gen_Mux_Select_LUT6[4].Using_ExtraMUX.Sel_Mux_MUXF7               |    <0.001 |
|                 Instruction_Prefetch_Mux[0].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[0].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[10].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[10].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[11].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[11].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[12].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[12].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[13].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[13].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[14].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[14].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[15].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[15].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[16].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[16].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[17].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[17].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[18].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[18].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[19].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[19].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[1].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[1].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[20].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[20].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[21].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[21].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[22].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[22].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[23].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[23].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[24].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[24].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[25].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[25].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[26].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[26].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[27].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[27].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[28].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[28].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[29].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[29].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[2].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[2].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[30].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[30].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[31].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[31].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[32].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[32].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[33].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[33].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[34].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[34].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[35].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[35].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[36].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[36].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[37].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[37].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[38].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[38].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[39].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[39].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[3].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[3].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[40].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[40].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[41].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[41].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[42].Gen_Instr_DFF                        |    <0.001 |
|                 Instruction_Prefetch_Mux[42].Instr_Mux_MUXF7                      |    <0.001 |
|                 Instruction_Prefetch_Mux[4].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[4].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[5].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[5].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[6].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[6].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[7].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[7].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[8].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[8].Instr_Mux_MUXF7                       |    <0.001 |
|                 Instruction_Prefetch_Mux[9].Gen_Instr_DFF                         |    <0.001 |
|                 Instruction_Prefetch_Mux[9].Instr_Mux_MUXF7                       |    <0.001 |
|                 Last_Sel_DFF                                                      |    <0.001 |
|                 Mux_Select_Empty_LUT6                                             |    <0.001 |
|                 Mux_Select_OF_Valid_LUT6                                          |    <0.001 |
|                 OF_Valid_DFF                                                      |     0.002 |
|               Use_MuxCy[10].OF_Piperun_Stage                                      |    <0.001 |
|                 MUXCY_I                                                           |    <0.001 |
|               Use_MuxCy[1].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_MuxCy[2].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_MuxCy[3].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_MuxCy[4].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_MuxCy[5].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_MuxCy[6].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_MuxCy[7].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_MuxCy[8].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_MuxCy[9].OF_Piperun_Stage                                       |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Using_FPGA.Gen_Bits[28].MEM_EX_Result_Inst                          |     0.000 |
|               Using_FPGA.Gen_Bits[30].MEM_EX_Result_Inst                          |    <0.001 |
|               Using_FPGA.Gen_Bits[31].MEM_EX_Result_Inst                          |     0.000 |
|               Using_FPGA_2.ex_byte_access_i_Inst                                  |     0.000 |
|               Using_FPGA_2.ex_doublet_access_i_Inst                               |    <0.001 |
|               Using_FPGA_2.ex_is_load_instr_Inst                                  |     0.000 |
|               Using_FPGA_2.ex_is_lwx_instr_Inst                                   |     0.000 |
|               Using_FPGA_2.ex_is_swx_instr_Inst                                   |    <0.001 |
|               Using_FPGA_2.ex_load_store_instr_Inst                               |    <0.001 |
|               Using_FPGA_2.ex_reverse_mem_access_inst                             |     0.000 |
|               Using_FPGA_3.ex_clear_MSR_BIP_instr_Inst                            |    <0.001 |
|               Using_FPGA_3.of_clear_MSR_BIP_hold_Inst                             |    <0.001 |
|               Using_FPGA_4.of_read_ex_write_op1_conflict_INST1                    |     0.000 |
|               Using_FPGA_4.of_read_ex_write_op1_conflict_INST2                    |    <0.001 |
|               Using_FPGA_4.of_read_ex_write_op2_conflict_INST1                    |     0.000 |
|               Using_FPGA_4.of_read_ex_write_op2_conflict_INST2                    |    <0.001 |
|               Using_FPGA_4.of_read_ex_write_op3_conflict_INST1                    |     0.000 |
|               Using_FPGA_4.of_read_ex_write_op3_conflict_INST2                    |    <0.001 |
|               Using_FPGA_4.of_read_mem_write_op1_conflict_INST1                   |     0.000 |
|               Using_FPGA_4.of_read_mem_write_op1_conflict_INST2                   |    <0.001 |
|               Using_FPGA_4.of_read_mem_write_op2_conflict_INST1                   |     0.000 |
|               Using_FPGA_4.of_read_mem_write_op2_conflict_INST2                   |    <0.001 |
|               Using_FPGA_4.of_read_mem_write_op3_conflict_INST1                   |     0.000 |
|               Using_FPGA_4.of_read_mem_write_op3_conflict_INST2                   |    <0.001 |
|               Using_ICache_Carry_Chain.Using_Latch_AS_Logic.AND2B1L_I1            |    <0.001 |
|               Using_ICache_Carry_Chain.ib_addr_strobe_i_carry_and                 |    <0.001 |
|                 MUXCY_I                                                           |    <0.001 |
|               Using_ICache_Carry_Chain.ib_addr_strobe_i_carry_or                  |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Using_ICache_Carry_Chain.ib_ready_MMU_carry_or                      |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Using_PC_Incr_Dbg_or_Prot.if_pc_incr_carry_and_1                    |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               if_pc_incr_carry_and_0                                              |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               if_pc_incr_carry_and_3                                              |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               jump_logic_I1                                                       |    <0.001 |
|                 MUXCY_JUMP_CARRY                                                  |     0.000 |
|                 MUXCY_JUMP_CARRY2                                                 |    <0.001 |
|                 MUXCY_JUMP_CARRY3                                                 |     0.000 |
|                 MUXCY_JUMP_CARRY4                                                 |     0.000 |
|                 MUXCY_JUMP_CARRY5                                                 |     0.000 |
|                 MUXCY_JUMP_CARRY6                                                 |    <0.001 |
|               mem_PipeRun_carry_and                                               |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               mem_wait_on_ready_N_carry_or                                        |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|             Use_DBUS.DAXI_Interface_I1                                            |    <0.001 |
|             Use_DLMB.Using_Latch_AS_Logic.AND2B1L_I1                              |     0.000 |
|             Use_Debug_Logic.Master_Core.Debug_Perf                                |     0.001 |
|               SRL16E_1                                                            |    <0.001 |
|               SRL16E_2                                                            |    <0.001 |
|               SRL16E_3                                                            |    <0.001 |
|               SRL16E_4                                                            |    <0.001 |
|               SRL16E_7                                                            |    <0.001 |
|               SRL16E_8                                                            |    <0.001 |
|               The_Cache_Addresses[1].SRL16E_Cache_I                               |    <0.001 |
|               The_Cache_Addresses[2].SRL16E_Cache_I                               |    <0.001 |
|               The_Cache_Addresses[3].SRL16E_Cache_I                               |    <0.001 |
|               The_Cache_Addresses[4].SRL16E_Cache_I                               |    <0.001 |
|               The_Cache_Addresses[5].SRL16E_Cache_I                               |    <0.001 |
|               The_Cache_Addresses[6].SRL16E_Cache_I                               |    <0.001 |
|               The_Cache_Addresses[7].SRL16E_Cache_I                               |    <0.001 |
|               The_Cache_Addresses[8].SRL16E_Cache_I                               |    <0.001 |
|               Using_PC_Breakpoints.All_PC_Brks[0].address_hit_I                   |    <0.001 |
|                 Compare[0].MUXCY_I                                                |     0.000 |
|                 Compare[0].SRLC16E_I                                              |    <0.001 |
|                 Compare[1].MUXCY_I                                                |     0.000 |
|                 Compare[1].SRLC16E_I                                              |    <0.001 |
|                 Compare[2].MUXCY_I                                                |     0.000 |
|                 Compare[2].SRLC16E_I                                              |    <0.001 |
|                 Compare[3].MUXCY_I                                                |     0.000 |
|                 Compare[3].SRLC16E_I                                              |    <0.001 |
|                 Compare[4].MUXCY_I                                                |    <0.001 |
|                 Compare[4].SRLC16E_I                                              |    <0.001 |
|                 Compare[5].MUXCY_I                                                |     0.000 |
|                 Compare[5].SRLC16E_I                                              |    <0.001 |
|                 Compare[6].MUXCY_I                                                |     0.000 |
|                 Compare[6].SRLC16E_I                                              |    <0.001 |
|                 Compare[7].MUXCY_I                                                |     0.000 |
|                 Compare[7].SRLC16E_I                                              |    <0.001 |
|                 The_First_BreakPoints.MUXCY_Post                                  |    <0.001 |
|               sync_dbg_brk_hit                                                    |    <0.001 |
|               sync_dbg_hit                                                        |    <0.001 |
|                 sync_bits[0].sync_bit                                             |    <0.001 |
|                 sync_bits[10].sync_bit                                            |    <0.001 |
|                 sync_bits[11].sync_bit                                            |    <0.001 |
|                 sync_bits[12].sync_bit                                            |    <0.001 |
|                 sync_bits[13].sync_bit                                            |    <0.001 |
|                 sync_bits[14].sync_bit                                            |    <0.001 |
|                 sync_bits[15].sync_bit                                            |    <0.001 |
|                 sync_bits[1].sync_bit                                             |    <0.001 |
|                 sync_bits[2].sync_bit                                             |    <0.001 |
|                 sync_bits[3].sync_bit                                             |    <0.001 |
|                 sync_bits[4].sync_bit                                             |    <0.001 |
|                 sync_bits[5].sync_bit                                             |    <0.001 |
|                 sync_bits[6].sync_bit                                             |    <0.001 |
|                 sync_bits[7].sync_bit                                             |    <0.001 |
|                 sync_bits[8].sync_bit                                             |    <0.001 |
|                 sync_bits[9].sync_bit                                             |    <0.001 |
|               sync_running_clock                                                  |    <0.001 |
|               sync_sample                                                         |     0.000 |
|                 sync_bits[0].sync_bit                                             |     0.000 |
|                 sync_bits[1].sync_bit                                             |     0.000 |
|                 sync_bits[2].sync_bit                                             |     0.000 |
|                 sync_bits[3].sync_bit                                             |     0.000 |
|                 sync_bits[4].sync_bit                                             |     0.000 |
|                 sync_bits[5].sync_bit                                             |     0.000 |
|                 sync_bits[6].sync_bit                                             |     0.000 |
|               sync_sleep                                                          |    <0.001 |
|               sync_stop_CPU                                                       |    <0.001 |
|               sync_trig_out_0                                                     |    <0.001 |
|             Using_DCache.Using_WriteThrough.DCache_I1                             |     0.003 |
|               DATA_RAM_Module                                                     |     0.002 |
|                 Using_B36_S4.The_BRAMs[0].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[1].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[2].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[3].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[4].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[5].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[6].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[7].RAMB36_I1                               |    <0.001 |
|               Gen_WE[0].SUM_I                                                     |     0.000 |
|               Gen_WE[1].SUM_I                                                     |     0.000 |
|               Gen_WE[2].SUM_I                                                     |     0.000 |
|               Gen_WE[3].SUM_I                                                     |     0.000 |
|               TAG_RAM_Module                                                      |    <0.001 |
|                 Using_B36_S18.The_BRAMs[0].RAMB36_I1                              |    <0.001 |
|               Use_XX_Accesses3.xx_access_read_miss                                |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Use_XX_Accesses_Hit.dcache_data_strobe_sel2_carry_or                |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               Using_Latch_AS_Logic_1.AND2B1L_I1                                   |     0.000 |
|               Using_Latch_AS_Logic_3.AND2B1L_I1                                   |    <0.001 |
|               Using_New_CacheInterface_for_AXI.Cache_Interface_I1                 |    <0.001 |
|                 Using_AXI.Use_AXI_Write.Addr_bit[0].Addr_bit_FDSE                 |    <0.001 |
|                 Using_AXI.Use_AXI_Write.Addr_bit[0].Addr_bit_LUT                  |    <0.001 |
|                 Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_FDSE                 |    <0.001 |
|                 Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_LUT                  |    <0.001 |
|                 Using_AXI.Use_AXI_Write.Addr_bit[2].Addr_bit_FDSE                 |    <0.001 |
|                 Using_AXI.Use_AXI_Write.Addr_bit[2].Addr_bit_LUT                  |    <0.001 |
|                 Using_AXI.Use_AXI_Write.Addr_bit[3].Addr_bit_FDSE                 |    <0.001 |
|                 Using_AXI.Use_AXI_Write.Addr_bit[3].Addr_bit_LUT                  |    <0.001 |
|                 Using_AXI.Use_AXI_Write.exist_bit_FDRE                            |    <0.001 |
|                 Using_AXI.Use_AXI_Write.exist_bit_LUT                             |    <0.001 |
|               Using_New_CacheInterface_for_AXI.cacheline_copy_reg_0_3_0_5         |    <0.001 |
|               Using_New_CacheInterface_for_AXI.cacheline_copy_reg_0_3_12_17       |    <0.001 |
|               Using_New_CacheInterface_for_AXI.cacheline_copy_reg_0_3_18_23       |    <0.001 |
|               Using_New_CacheInterface_for_AXI.cacheline_copy_reg_0_3_24_29       |    <0.001 |
|               Using_New_CacheInterface_for_AXI.cacheline_copy_reg_0_3_30_31       |    <0.001 |
|               Using_New_CacheInterface_for_AXI.cacheline_copy_reg_0_3_6_11        |    <0.001 |
|               Valid_Check_With_4word_Cacheline.lut6_valid_check_carry_and         |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[0].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[0].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[10].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[10].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[11].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[11].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[12].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[12].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[13].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[13].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[14].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[14].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[15].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[15].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[16].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[16].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[17].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[17].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[18].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[18].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[19].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[19].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[1].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[1].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[20].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[20].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[21].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[21].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[22].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[22].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[23].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[23].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[24].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[24].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[25].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[25].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[26].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[26].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[27].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[27].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[28].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[28].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[29].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[29].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[2].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[2].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[30].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[30].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[31].Gen_Instr_DFF                     |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[31].Mux_Select_LUT5                   |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[3].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[3].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[4].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[4].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[5].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[5].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[6].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[6].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[7].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[7].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[8].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[8].Mux_Select_LUT5                    |    <0.001 |
|               WB_DCache_Valid_Read_data_Mux[9].Gen_Instr_DFF                      |     0.000 |
|               WB_DCache_Valid_Read_data_Mux[9].Mux_Select_LUT5                    |    <0.001 |
|               dcache_data_strobe_sel_carry_or_0                                   |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               dcache_data_strobe_sel_carry_or_1                                   |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               dcache_data_strobe_sel_carry_or_2                                   |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               mem_read_cache_hit_carry_or                                         |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               mem_read_cache_hit_direct_carry_and                                 |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               mem_read_cache_miss_sel_carry_and                                   |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               mem_tag_hit_comparator                                              |     0.000 |
|                 Comp_Carry_Chain[0].MUXCY_I                                       |     0.000 |
|                 Comp_Carry_Chain[1].MUXCY_I                                       |     0.000 |
|               mem_tag_miss_comparator                                             |     0.000 |
|                 Comp_Carry_Chain[0].MUXCY_I                                       |     0.000 |
|                 Comp_Carry_Chain[1].MUXCY_I                                       |     0.000 |
|             Using_Debug.Using_ICache.combined_carry_and_I2                        |     0.000 |
|               MUXCY_I                                                             |     0.000 |
|             Using_Debug.Using_ICache.combined_carry_or_I                          |     0.000 |
|               MUXCY_I                                                             |     0.000 |
|             Using_Debug.Using_ICache.debug_combinded_carry_or_I                   |     0.000 |
|               MUXCY_I                                                             |     0.000 |
|             Using_ICache.ICache_I1                                                |     0.004 |
|               Cache_Interface_I1                                                  |    <0.001 |
|               Data_RAM_Module                                                     |     0.003 |
|                 Using_B36_S4.The_BRAMs[0].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[1].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[2].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[3].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[4].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[5].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[6].RAMB36_I1                               |    <0.001 |
|                 Using_B36_S4.The_BRAMs[7].RAMB36_I1                               |    <0.001 |
|               Tag_RAM_Module                                                      |    <0.001 |
|                 Using_B36_S18.The_BRAMs[0].RAMB36_I1                              |    <0.001 |
|               Using_FPGA_FSL_1.tag_hit_comparator                                 |     0.000 |
|                 Comp_Carry_Chain[0].MUXCY_I                                       |     0.000 |
|                 Comp_Carry_Chain[1].MUXCY_I                                       |     0.000 |
|                 Using_Extra_Carry.MUXCY_EXTRA_I                                   |     0.000 |
|               Using_XX_Access_Part2.carry_or_I1                                   |     0.000 |
|                 MUXCY_I                                                           |     0.000 |
|               cache_valid_bit_detect_I1                                           |     0.000 |
|                 Valid_Check_With_4word_Cacheline.lut6_valid_check_carry_and       |     0.000 |
|                   MUXCY_I                                                         |     0.000 |
|             mem_databus_ready_sel_carry_or                                        |     0.000 |
|               MUXCY_I                                                             |     0.000 |
|             read_data_mux_I                                                       |    <0.001 |
|           Reset_DFF                                                               |    <0.001 |
|     microblaze_0_axi_intc                                                         |    <0.001 |
|       U0                                                                          |    <0.001 |
|         AXI_LITE_IPIF_I                                                           |    <0.001 |
|           I_SLAVE_ATTACHMENT                                                      |    <0.001 |
|             I_DECODER                                                             |    <0.001 |
|         INTC_CORE_I                                                               |    <0.001 |
|           IVAR_FAST_MODE_GEN.IVAR_REG_MEM_AXI_CLK_GEN.IVAR_REG_MEM_I              |    <0.001 |
|             ram_reg_0_15_0_0                                                      |    <0.001 |
|             ram_reg_0_15_10_10                                                    |     0.000 |
|             ram_reg_0_15_11_11                                                    |     0.000 |
|             ram_reg_0_15_12_12                                                    |     0.000 |
|             ram_reg_0_15_13_13                                                    |     0.000 |
|             ram_reg_0_15_14_14                                                    |     0.000 |
|             ram_reg_0_15_15_15                                                    |     0.000 |
|             ram_reg_0_15_16_16                                                    |     0.000 |
|             ram_reg_0_15_17_17                                                    |     0.000 |
|             ram_reg_0_15_18_18                                                    |     0.000 |
|             ram_reg_0_15_19_19                                                    |     0.000 |
|             ram_reg_0_15_1_1                                                      |    <0.001 |
|             ram_reg_0_15_20_20                                                    |     0.000 |
|             ram_reg_0_15_21_21                                                    |     0.000 |
|             ram_reg_0_15_22_22                                                    |     0.000 |
|             ram_reg_0_15_23_23                                                    |     0.000 |
|             ram_reg_0_15_24_24                                                    |     0.000 |
|             ram_reg_0_15_25_25                                                    |    <0.001 |
|             ram_reg_0_15_26_26                                                    |     0.000 |
|             ram_reg_0_15_27_27                                                    |     0.000 |
|             ram_reg_0_15_28_28                                                    |     0.000 |
|             ram_reg_0_15_29_29                                                    |     0.000 |
|             ram_reg_0_15_2_2                                                      |    <0.001 |
|             ram_reg_0_15_30_30                                                    |     0.000 |
|             ram_reg_0_15_31_31                                                    |     0.000 |
|             ram_reg_0_15_3_3                                                      |    <0.001 |
|             ram_reg_0_15_4_4                                                      |     0.000 |
|             ram_reg_0_15_5_5                                                      |     0.000 |
|             ram_reg_0_15_6_6                                                      |     0.000 |
|             ram_reg_0_15_7_7                                                      |     0.000 |
|             ram_reg_0_15_8_8                                                      |    <0.001 |
|             ram_reg_0_15_9_9                                                      |    <0.001 |
|     microblaze_0_axi_periph                                                       |    <0.001 |
|       xbar                                                                        |    <0.001 |
|         inst                                                                      |    <0.001 |
|           gen_sasd.crossbar_sasd_0                                                |    <0.001 |
|             addr_arbiter_inst                                                     |    <0.001 |
|             gen_decerr.decerr_slave_inst                                          |    <0.001 |
|             reg_slice_r                                                           |    <0.001 |
|             splitter_ar                                                           |    <0.001 |
|             splitter_aw                                                           |    <0.001 |
|     microblaze_0_local_memory                                                     |     0.001 |
|       dlmb_bram_if_cntlr                                                          |    <0.001 |
|         U0                                                                        |    <0.001 |
|       dlmb_v10                                                                    |     0.000 |
|         U0                                                                        |     0.000 |
|       ilmb_bram_if_cntlr                                                          |    <0.001 |
|         U0                                                                        |    <0.001 |
|       ilmb_v10                                                                    |     0.000 |
|         U0                                                                        |     0.000 |
|       lmb_bram                                                                    |     0.001 |
|         U0                                                                        |     0.001 |
|           inst_blk_mem_gen                                                        |     0.001 |
|             gnative_mem_map_bmg.native_mem_map_blk_mem_gen                        |     0.001 |
|               valid.cstr                                                          |     0.001 |
|                 ramloop[0].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[10].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[11].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[12].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[13].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[14].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[15].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[16].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[17].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[18].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[19].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[1].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[20].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[21].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[22].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[23].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[24].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[25].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[26].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[27].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[28].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[29].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[2].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[30].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[31].ram.r                                                 |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[3].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[4].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[5].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[6].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[7].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[8].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|                 ramloop[9].ram.r                                                  |    <0.001 |
|                   prim_noinit.ram                                                 |    <0.001 |
|     microblaze_0_xlconcat                                                         |     0.000 |
|     rst_clk_wiz_1_100M                                                            |    <0.001 |
|       U0                                                                          |    <0.001 |
|         EXT_LPF                                                                   |    <0.001 |
|           ACTIVE_LOW_EXT.ACT_LO_EXT                                               |    <0.001 |
|         SEQ                                                                       |    <0.001 |
|           SEQ_COUNTER                                                             |    <0.001 |
|   mdio_rtl_mdio_iobuf                                                             |    <0.001 |
+-----------------------------------------------------------------------------------+-----------+


