Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
| Date         : Tue Mar 24 12:53:14 2015
| Host         : phys-pc458-4 running 64-bit Service Pack 1  (build 7601)
| Command      : report_control_sets -verbose -file toplevel_control_sets_placed.rpt
| Design       : toplevel
| Device       : xc7a200t
-------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+-------------------------------------------------------------------+-------+
|                               Status                              | Count |
+-------------------------------------------------------------------+-------+
| Number of unique control sets                                     |   554 |
| Minimum Number of register sites lost to control set restrictions |  1668 |
+-------------------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |            2324 |          760 |
| No           | No                    | Yes                    |             320 |           91 |
| No           | Yes                   | No                     |            2449 |          889 |
| Yes          | No                    | No                     |            1375 |          480 |
| Yes          | No                    | Yes                    |             211 |           60 |
| Yes          | Yes                   | No                     |            4237 |         1555 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|                          Clock Signal                          |                                                                                                        Enable Signal                                                                                                        |                                                                                                 Set/Reset Signal                                                                                                 | Slice Load Count | Bel Load Count |
+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int5q                                                                                                                                  |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1         |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                                            | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_start_single_step_reg                                                                                      |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_39                                                                                                          |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int6                                                                                                                                   |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                                            | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_normal_stop_cmd_i_reg                                                                                      |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[0]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_30_out                                                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[10]_i_1                                                                                                                    |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_31_out                                                                                                                                                            |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_32_out                                                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[11]_i_1                                                                                                                    |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rx_byte_counter/SYNC_STATS_RESET/async_rst4                                                                             |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/I90[0]                                                                                                                  | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/O71                                                                                                          |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/tx_byte_counter/SYNC_STATS_RESET/n_0_async_rst4_reg                                                                     |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/wr_rst_asreg_d1                                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                                   |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_33_out                                                                                                                                                            |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[12]_i_1                                                                                                                    |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/O4                                                                                                                                               |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/p_34_out                                                                                                                                                            |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1__0       |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/push                                                                                                                                            |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CAPTURE5_out                                                                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg                   | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                       |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[13]_i_1                                                                                                                    |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_1                                                                                                                    |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_stats_reset/async_rst4                                                                                                                             |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[1]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/n_0_async_rst4_reg                                                                                                                      |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[3]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[4]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/mem_start_div                                                                                                                | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Data_Flow_Logic_I/O7[0]                                                                                                                   |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/n_0_async_rst4_reg                                                                                                                      |                1 |              1 |
| ~mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/CE                                                                                                                                                                              | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/D                                                                                                                                                                    |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[5]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[7]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[8]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[9]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                                            | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/n_0_continue_from_brk_reg                                                                                      |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/rd_rst_asreg_d1                                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                                   |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                                            | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/O4                                                                                                             |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg                   | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                       |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/RESET_INT                                                                                                                 |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/n_0_async_rst4_reg                                                                                                     |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int6                                                                                                                            |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int5q                                                                                                                           |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 |                                                                                                                                                                                                                             | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Use_UART.execute_i_2                                                                                                                                             |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/I98[0]                                                                                                                                                  |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/O5                                                                                                                                               |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/push                                                              |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[14]_i_2                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_FRAME_COUNT[6]_i_1                                                                                                                     |                1 |              1 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/gtrxreset_ss                                                                    |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/I_WRAP_BRST/bram_addr_ld_en                                                                                                             | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/I_WRAP_BRST/O5                                                                                                               |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/push                                                          |                                                                                                                                                                                                                  |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/flush_pipe                                                                                                                                                   |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/O78                                                                                                                                          |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/capture_1                                                                                                      |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_wrce[0]                                                                                                                        |                1 |              1 |
| ~mbsys_i/mdm_1/U0/Dbg_Update_0                                 |                                                                                                                                                                                                                             | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Insert_Delays[0].LUT_Delay_i_1                                                                                                                                   |                1 |              1 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__8                                                                                            |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXCLIENT/ClkB_reset_inst/async_rst4                                                                                                             |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1         |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_GTX/ClkB_reset_inst/async_rst4                                                                                                                  |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/AXITX_2_TXCLIENT_FSM_GO/ClkB_reset_inst/n_0_sync_rst1_i_1                                                                                                                   |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXCLIENT/ClkB_reset_inst/async_rst4                                                                                                             |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__12                                                                                           |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].reg_slice_mi/r_pipe/p_1_in                                                                                                                  |                                                                                                                                                                                                                  |                2 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__11                                                                                           |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__16                                                                                           |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0       |                1 |              2 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 |                                                                                                                                                                                                                             |                                                                                                                                                                                                                  |                2 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_RXD_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__4                                                                                            |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/p_3_out                                                                                               |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__14                                                                                           |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_TXC_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__10                                                                                           |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_RXS_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__7                                                                                            |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__18                                                                                           |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int4q                                                                                                                           |                                                                                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__9                                                                                               |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXD_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__1                                                                                               |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXD_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__5                                                                                               |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/RXD_AXSTREAM_TO_RXS_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__15                                                                                           |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/RXD_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__19                                                                                           |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXD_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__13                                                                                              |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXS_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__3                                                                                               |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXD_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__0                                                                                               |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_TXC_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__6                                                                                            |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXS_AXSTREAM/ClkB_reset_inst/n_0_sync_rst1_i_1__17                                                                                              |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int4q                                                                                                                                  |                                                                                                                                                                                                                  |                1 |              2 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/n_0_sync_rst1_i_1__2                                                                                               |                1 |              2 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Command_Reg_En                                                                                                            | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/command_reg_clear                                                                                              |                1 |              2 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Debug_Rst_i0                                                                                                                                                                    |                                                                                                                                                                                                                  |                1 |              2 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/n_0_Tx_Client_TxC_2_Mem_Addr_int[2]_i_1                                                                                                                  |                                                                                                                                                                                                                  |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                                    |                2 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/n_0_FSM_onehot_state[4]_i_1                                                                      | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/SR[0]                                                                                 |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                                  |                2 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                          |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/mdm_1/U0/MDM_Core_I1/O1                                                                                                                                                                                  |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/n_0_FSM_onehot_state[4]_i_1__0                                                               | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/SR[0]                                                                             |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Cache_Interface_I1/O9[0]                                                                                                                  | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[1].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/n_0_FSM_onehot_state[4]_i_1__1                                                               | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].gen_mi_write.wdata_mux_w/gen_wmux.wmux_aw_fifo/SR[0]                                                                             |                1 |              3 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/AS[0]                                                                                                                                                       |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_reset_time_out_reg                                                                                   |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Using_AXI.Use_AXI_Write.exist_bit_FDRE/E[0]                        | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/n_0_IP2Bus_WrAck_i_1                                                                                                                                              |                3 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_FDSE/E[0]             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear                                                                                                                                                   |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/SR[0]                                                                                                                                             |                2 |              4 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/mdm_1/U0/MDM_Core_I1/TDI_Shifter0                                                                                                                                                                                   | mbsys_i/mdm_1/U0/MDM_Core_I1/sel_n_reset                                                                                                                                                                         |                1 |              4 |
| ~mbsys_i/mdm_1/U0/Dbg_Update_0                                 |                                                                                                                                                                                                                             | mbsys_i/mdm_1/U0/MDM_Core_I1/sel_n_reset                                                                                                                                                                         |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_FDSE/O1               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_FDSE/SR[0] |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_FDSE/O1               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_Latch_AS_Logic_3.AND2B1L_I1/SR[0]                                                                     |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_PLL0LOCK/E[0]                                                                                                  | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/Q[0]                                                                                                                                                          |                2 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/O8                                                                                                    |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/O5[0]                                                                                                 |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2                                                                                                                                                     | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                                                                                                             |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.TX_FIFO_I/O1                                                                                                                                                           | mbsys_i/mdm_1/U0/MDM_Core_I1/n_0_Use_Uart.reset_TX_FIFO_reg                                                                                                                                                      |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SYNCHRONISATION/n_0_FSM_sequential_STATE[3]_i_1                                                                           |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.RX_FIFO_I/O1                                                                                                                                                           | mbsys_i/mdm_1/U0/MDM_Core_I1/n_0_Use_Uart.reset_RX_FIFO_reg                                                                                                                                                      |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/CE041_out                                                                                                                                                   | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/E[0]                                                                                                           | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/SR[0]                                                                                                                                |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/n_0_bus2ip_addr_i[5]_i_1                                                                                                                                        | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                                  |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/n_0_gen_arbiter.last_rr_hot[1]_i_1__0                                                                                                           | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/SR[0]                                                                                                                                |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/O1[0]                                                                                                           |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/broadcastaddressmatch_int_0                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/n_0_address_match_i_1                                                                                               |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/n_0_address_filters[0].configurable_match_cap[0]_i_2                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/O5                                                                                                                                                |                2 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/pfc_tx/n_0_FSM_onehot_legacy_state[4]_i_1                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_data_valid/E[0]                                                                                                | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/Q[0]                                                                                                                                                          |                3 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/MDIO_INTERFACE_1/n_0_BIT_COUNT[3]_i_1                                                                            |                                                                                                                                                                                                                  |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/n_0_Axi_Str_TxD_2_Mem_We[3]_i_1                                                                             |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_addr_reg0                                                                                                                  | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/int_mgmt_host_reset                                                                                                    |                3 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/MDIO_INTERFACE_1/LOOPBACK_REG                                                                                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                                    |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/wrdata_reg_ld                                                                                                                           | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/n_0_GEN_WR_NO_ECC.bram_we_int[3]_i_1                                                                                         |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/n_0_rd_data_sm_cs[3]_i_1                                                                                                                | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/I_WRAP_BRST/O5                                                                                                               |                4 |              4 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/MDM_SEL                                                                                                                                                                                        | mbsys_i/mdm_1/U0/MDM_Core_I1/sel_n_reset                                                                                                                                                                         |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/TRANSMITTER/CONFIG_K28p5_0                                                                                                           | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/MGT_TX_RESET                                                                                                              |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/rst_clk_wiz_1_100M/U0/bus_struct_reset[0]                                                                                                                                                                |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/I22[0]                                                                                                                 |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/rst_d2                                               |                3 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/I6[0]                                                                                                                                                                   |                                                                                                                                                                                                                  |                2 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram0                                                                                                     |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Cache_Interface_I1/DIBDI[0]                                                                                                               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Cache_Interface_I1/update_idle                                                                                                 |                1 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Cache_Interface_I1/p_3_out                                                                                                                | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Cache_Interface_I1/n_0_Using_AXI.r_read_fifo_addr[0]_i_1                                                                                  | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                3 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/n_0_Using_AXI.Use_AXI_Write.aw_read_fifo_addr[0]_i_1               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                2 |              4 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/clear                                                                                                                                        |                1 |              4 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_counter0                                                                                                            | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/initialize_ram0                                                                                                     |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk  |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/MGT_TX_RESET                                                                                                              |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_out                                                          |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/data_in                                                                                                  |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/clk_div_stage1/reg5                                                                                                            |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/p_1_out                                                                                                                   |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/p_0_out                                                                                                                   |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/MDIO_INTERFACE_1/n_0_ADDR_WR[4]_i_1                                                                              | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                                    |                2 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/n_0_async_rst0_i_1__2                                                                                                  |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/n_0_gen_rep[0].fifoaddr[4]_i_1                                                                   | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/SR[0]                                                                                                                                |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/int_tx_ifg_del_en                                                                                                                                    |                                                                                                                                                                                                                  |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/REG5_OUT                                                                                                                                          |                2 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_ADDSUB_I/n_0_mem_left_shift_4[0]_i_1                                                                                    |                2 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                             |                2 |              5 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Control_Reg_En                                                                                                            |                                                                                                                                                                                                                  |                3 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                3 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/E[0]                                                                                                                         | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                3 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CE_REG1_OUT7_out                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CE_REG5_OUT                                                                                                                                       |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_stats_reset/int_rst                                                                                                                                |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/conf/int_tx_rst_asynch                                                                                                                |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/O1                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/REG5_OUT                                                                                                                                          |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/rst_clk_wiz_1_100M/U0/EXT_LPF/lpf_int                                                                                                                                                                    |                4 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/p_8_in                                                                                                                                        | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/SR[0]                                                                                                                                                               |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/clk_en                                                                                                                                    | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/clk_div_stage2/reg5                                                                                                            |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/conf/int_rx_rst_asynch                                                                                                                |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/INT_CRC_MODE                                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/O2                                                                                                                          |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/tx_init_in_prog                                                                                             |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/O1                                                                                                               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[9].Gen_Instr_DFF/ex_mbar_decode                                                                  |                4 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXS_AXSTREAM/ClkB_reset_inst/O1                                                                                                                 |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/n_0_Using_AXI.Use_AXI_Write.pending_write[4]_i_1                   | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                2 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_31                                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/I9[0]                                                                                                                                                        |                2 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SYNCHRONISATION/enablealign                                                                                               |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/MGT_RX_RESET                                                                                                              |                1 |              5 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/CE_REG1_OUT8_out                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CE_REG5_OUT                                                                                                                                       |                1 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/WB_Halted                                                                                                                                               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                4 |              5 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/O1                                                                                                               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[5].Gen_Instr_DFF/use_Reg_Neg_DI                                                                  |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/I96[0]                                                                                                                                                  | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                4 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXCLIENT/ClkB_reset_inst/RESET2RX_CLIENT                                                                                                        |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/rst_clk_wiz_1_100M/U0/SEQ/seq_cnt_en                                                                                                                                                                                | mbsys_i/rst_clk_wiz_1_100M/U0/SEQ/SEQ_COUNTER/clear                                                                                                                                                              |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/E[0]                                                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/I47[0]                                                                                                                                            |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/O1                                                                                                                                        |                                                                                                                                                                                                                  |                6 |              6 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_count[0]__0_i_1                                                                                                                                                             |                                                                                                                                                                                                                  |                2 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_IFG_COUNT[7]_i_2                                                                                                                                  | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_IFG_COUNT[7]_i_1                                                                                                                       |                2 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx/data_count                                                                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/SR[0]                                                                                                                                             |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/n_0_counter_stg1[5]_i_1                                                                                                    |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/conf/SR[0]                                                                                                                            |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/O4[0]                                                                                                                                             |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/clear                                                                                                                                                      |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/p_8_out[0]                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/n_0_next_count_read[6]_i_1                                                                                              |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                                        |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/O10[0]                                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/int_mgmt_host_reset                                                                                                    |                1 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/tx_pause/sync_good_rx/SR[0]                                                                                                                        |                1 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/O4[0]                                                                                                                                                | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/int_mgmt_host_reset                                                                                                    |                3 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O3[0]                                                   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/srst_wrst_busy                                                                                                  |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/DATA_PHASE_WDT.I_DPTO_COUNTER/n_0_icount_out[5]_i_1                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/DATA_PHASE_WDT.I_DPTO_COUNTER/O3                                                                                             |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/int_rx_ps_lt_disable                                                                                                                                 |                                                                                                                                                                                                                  |                5 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/mdio_enabled.phy/mdio_clk_fall                                                                                                                   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/mdio_enabled.phy/n_0_state_count[5]_i_1                                                                                               |                5 |              6 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/gen_sync_reset/reset_out                                                                                                                        |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.si_transactor_aw/n_0_gen_single_thread.accept_cnt[5]_i_1                                                                        | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/SR[0]                                                                                                                                |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/O4[0]                                                                                                                                          |                                                                                                                                                                                                                  |                2 |              6 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/I_WRAP_BRST/bram_addr_ld_en                                                                                                             | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/I_WRAP_BRST/SR[0]                                                                                                            |                3 |              7 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/n_0_Tx_Client_TxC_2_Mem_Addr_int[2]_i_1                                                                                                                  | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/n_0_Tx_Client_TxC_2_Mem_Addr_int[9]_i_1                                                                                                       |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/start2                                                                                                                                                                | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                                                                                                                        |                1 |              7 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/vector_decode_inst/n_0_tx_pause_frame_i_1                                                                                                                                              |                                                                                                                                                                                                                  |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/I_WRAP_BRST/O6                                                                                                                          |                                                                                                                                                                                                                  |                4 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/I_SLAVE_ATTACHMENT/clear                                                                                                                                    |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_init_wait_count[6]_i_1__0                                                                                       | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/Q[0]                                                                                                                                                          |                2 |              7 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/RX_SM/O10                                                                                                                                                    | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |                3 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/n_0_wait_time_cnt[6]_i_2                                                                                            | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/clear                                                                                                    |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_wait_time_cnt[6]_i_2__0                                                                                         | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_wait_time_cnt[6]_i_1__0                                                                              |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/n_0_bus2ip_addr_i[8]_i_1                                                                                                                                | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                          |                2 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/n_0_init_wait_count[6]_i_1                                                                                          | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/Q[0]                                                                                                                                                          |                3 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/srst_wrst_busy                                                                                                  |                3 |              7 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/write_data_done                                                                                                                                              |                6 |              7 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/set_byte_en_pipe[0]                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                3 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/O10                                                                                                                                                                        | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int1q                                                                                                                                  |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/O13                                                                                                               |                6 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/n_0_Axi_Str_TxC_2_Mem_Addr_int[9]_i_1                                                                       |                3 |              8 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/E[0]                                                                                                                                                                            |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/tx_byte_counter/SYNC_STATS_RESET/SR[0]                                                                                  |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/CE027_out                                                                                                                                                   | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/tx/n_0_pause_value_sample[7]_i_1                                                                                                                   |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/n_0_tx_data[7]_i_1                                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                3 |              8 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter0                                                                                                                                                                    |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_Use_UART.tdo_reg[0]_i_1                                                                                                                                                     |                                                                                                                                                                                                                  |                3 |              8 |
| ~mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/n_0_command[0]_i_1                                                                                                                                                              |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int2q                                                                                                                                  |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/int3q                                                                                                                                  |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/SR[0]                                                                                                 |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/O3                                                                                                                              |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/SR[0]                                                                                                                           |                2 |              8 |
|  mbsys_i/mdm_1/U0/Dbg_Update_0                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/command_10                                                                                                                                                                      |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_decerr_slave.decerr_slave_inst/n_0_gen_axi.read_cnt[7]_i_1                                                                                                  | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/SR[0]                                                                                                                                |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_CORE_DOES_NO_HD_IFG.INT_IFG_DEL_MASKED[7]_i_1                                                                                          |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_DATA_REG[2][7]_i_1                                                                                                                     |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/E[0]                                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXCLIENT/ClkB_reset_inst/E[0]                                                                                                                              |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/CRC1/n_0_X36_1I263_i_1                                                                                                                 |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                       |                3 |              8 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/Using_PC_Breakpoints.All_PC_Brks[0].address_hit_I/Compare[0].SRLC16E_I/SRL16_En                                           |                                                                                                                                                                                                                  |                7 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_interconnect_0/xbar/inst/gen_master_slots[1].reg_slice_mi/reset                                                                                                                                      |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_rxs_mem_addr_cntr[8]_i_1                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |                4 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/Axi_Str_TxC_AReset                                                                                                                                                |                4 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/n_0_update_bram_cnt[7]_i_2                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/update_bram_cnt0                                                                                            |                3 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_gt_common_i/n_0_init_wait_count[7]_i_1                                                                                                                                            |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[7]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/n_0_txd[7]_i_1                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/set_byte_en                                                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/set_byte_en_pipe[1]                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                3 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx/n_0_pause_opcode_early[7]_i_1                                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/SR[0]                                                                                                                                             |                1 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[7]_i_1                                                                                                                                   | mbsys_i/mdm_1/U0/Use_AXI_IPIF.AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                             |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.TX_FIFO_I/CI                                                                                                                                                           |                                                                                                                                                                                                                  |                1 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/mdm_1/U0/MDM_Core_I1/JTAG_CONTROL_I/Use_UART.RX_FIFO_I/CI                                                                                                                                                           |                                                                                                                                                                                                                  |                1 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rx_axi_shim/rx_mac_tdata0                                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/CRC1/n_0_X36_1I263_i_1__0                                                                                                       |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int1q                                                                                                                           |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int2q                                                                                                                           |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/CONFIG_SELECT.CALCULATE_CRC2/int3q                                                                                                                           |                                                                                                                                                                                                                  |                2 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/O9                                                                                                                                                                         | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                3 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/O12                                                                                                                                                                        | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                3 |              8 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/O11                                                                                                                                                                        | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                4 |              8 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_AUTO_NEG.AUTO_NEGOTIATION/PULSE4096                                                                                              | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_AUTO_NEG.AUTO_NEGOTIATION/n_0_LINK_TIMER[8]_i_1                                                                       |                3 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/p_79_in                                                                                                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                4 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/rxs_mem_last_read_out_ptr_toconvertto_gray0                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                2 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/n_0_rxs_mem_next_available4write_ptr_1_reg[8]_i_1                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                2 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_TXC_AXSTREAM/ClkA_reset_inst/reset2axi_str_txd                                                                                               |                5 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/n_0_rxs_mem_next_available4write_ptr_reg[8]_i_1                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                4 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/CE                                                                                                                                                          | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                3 |              9 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_out                                                         |                3 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/n_0_rxs_mem_last_read_out_ptr_true_reg[8]_i_1                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                3 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/n_0_rxs_mem_last_read_out_ptr_toconvertto_gray_clean[8]_i_1                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                2 |              9 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[6]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |                4 |              9 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/vector_decode_inst/rx_stats_valid                                                                                                                                                      |                                                                                                                                                                                                                  |                5 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/PLL0RESET_IN                                                                                             |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/O1                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/REG0_OUT2                                                                                                                                         |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/txd_mem_full1                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_TXC_AXSTREAM/ClkA_reset_inst/reset2axi_str_txd                                                                                               |                3 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_rxd_mem_addr_cntr[9]_i_1                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |                3 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/n_0_txc_wr_pntr[9]_i_1                                                                                                                                   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/I_WRAP_BRST/SR[0]                                                                                                            |                5 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/REG0_OUT2                                                                                                                                         |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gdcf.dc/dc/O5[0]                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/srst_wrst_busy                                                                                                  |                4 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/txd_rd_pntr_10                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_TXC_AXSTREAM/ClkA_reset_inst/reset2axi_str_txd                                                                                               |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/txc_rd_addr2_pntr_10                                                                                                   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkA_reset_inst/O4                                                                                                              |                4 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/txc_wr_pntr_10                                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                5 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/n_0_update_bram_cnt_reg[9]_i_2                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/update_bram_cnt0                                                                                                                              |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_mmcm_lock_count[9]_i_2__0                                                                                       | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/SR[0]                                                                           |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/n_0_txd_rd_pntr[9]_i_1                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_TXC_AXSTREAM/ClkA_reset_inst/reset2axi_str_txd                                                                                               |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/n_0_txc_rd_addr2_pntr[9]_i_1                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkA_reset_inst/O4                                                                                                              |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gdcf.dc/dc/O6[0]                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                5 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/O5                                                                                                                 |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/n_0_Tx_Client_TxC_2_Mem_Din_int[9]_i_1                                                                                                        |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/n_0_rxd_mem_next_available4write_ptr_1_reg[9]_i_1                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                4 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0]                                                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/srst_wrst_busy                                                                                                  |                2 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/n_0_Axi_Str_TxC_2_Mem_Din_int[9]_i_1                                                                        |                3 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/n_0_mmcm_lock_count[9]_i_2                                                                                          | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/SR[0]                                                                           |                4 |             10 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O2[0]                                                   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/srst_wrst_busy                                                                                                  |                2 |             10 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/RX_SM/O4                                                                                                                                          |                3 |             11 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkA_reset_inst/O4                                                                                                              |                7 |             11 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gdcf.dc/dc/O4[0]                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                5 |             11 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/RX_SM/E[0]                                                                                                                                                   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/I6[0]                                                                                                                                   |                2 |             11 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/txc_rd_end_dly1                                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                3 |             12 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/n_0_phy_reset_count[0]_i_1                                                                                                                                              | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_GTX/ClkB_reset_inst/RESET2GTX_CLK                                                                                                               |                3 |             12 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_EMAC_INTERFACE/n_0_txd_rd_addr[0]_i_1                                                                                                                                   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                3 |             12 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/counter_stg30                                                                                                                         | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/n_0_counter_stg1[5]_i_1                                                                                                    |                3 |             12 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/eqOp                                                                                                                                  | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reset_wtd_timer/n_0_counter_stg1[5]_i_1                                                                                                    |                3 |             12 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/O2[0]                                                                                                                                                | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/int_mgmt_host_reset                                                                                                    |                2 |             12 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_wait_bypass_count[0]_i_2__0                                                                                     | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_wait_bypass_count[0]_i_1__0                                                                          |                4 |             13 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_rxreset/reset_out                                                                                                                  |                5 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/E[0]                                                                                                                                                  | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/sig_Bus2IP_Reset                                                                                                                                                  |                7 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/cntr_en                              | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                                  |                4 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/start2                                                                                                                                                          | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/O19                                                                                                                                                               |                3 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/O30                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                                   |                4 |             13 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SYNCHRONISATION/SYNC_STATUS_REG0                                                                                          |                4 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[9]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |                8 |             13 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.mem/O28                                              | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                                   |                4 |             13 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/MDC_RISING_REG1                                                                                                  | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                                    |                7 |             14 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXCLIENT/ClkB_reset_inst/ClkBRst                                                                                                                |                5 |             14 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/WR_RST                                               |                5 |             14 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/AR[0]                                                 |                4 |             14 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/FRAME_DECODER/n_0_STATISTICS_LENGTH[13]_i_1                                                                                                                  |                                                                                                                                                                                                                  |                6 |             14 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/sync_block_gtrxreset/data_out                                                                                             |                5 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/O5[0]                                                                                                                                                |                                                                                                                                                                                                                  |                4 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/O6[0]                                                                                                                                                |                                                                                                                                                                                                                  |                7 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O3                                                          | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/O3                                                                                                              |                4 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/RX_SM/O11[0]                                                                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |                4 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/FRAME_DECODER/n_0_STATISTICS_LENGTH[13]_i_1                                                                                                                  | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/RX_SM/O4                                                                                                                                          |                4 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_BYTE_COUNT[0][14]_i_1                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/O2                                                                                                                          |                4 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Tag_RAM_Module/Using_B36_S18.The_BRAMs[0].RAMB36_I1/O6[0]                                                                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                7 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_AUTO_NEG.AUTO_NEGOTIATION/RX_CONFIG_SNAPSHOT                                                                                     | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                                    |                3 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Cache_Interface_I1/update_idle                                                                                                            |                                                                                                                                                                                                                  |                7 |             15 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_resets_i/Q[0]                                                                                                                                                          |               11 |             15 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_frame_length_bytes[0]_i_2                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_frame_length_bytes[0]_i_1                                                                                                  |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_REGISTERS/TP_I/E[0]                                                                                                                                                                  | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/O5                                                                                                                 |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/I_SLAVE_ATTACHMENT/n_0_bus2ip_addr_i[17]_i_1                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                      |                5 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/n_0_rd_data[15]_i_1__0                                                                      | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/sync_rst_sync/reset_out                                                          |                6 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/E[0]                                                                                                                                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/int_mgmt_host_reset                                                                                                    |                7 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[8]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |                5 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_field_wr[2]                                                                                                                |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/mdio_enabled.phy/I82[0]                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/int_mgmt_host_reset                                                                                                    |                3 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/original_rd_data0                                                                          |                                                                                                                                                                                                                  |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[2]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |               10 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/n_0_rd_data[15]_i_1                                                                        | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtrxreset_seq_i/sync_rst_sync/reset_out                                                         |                6 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_axi_arvalid[5]                                                                                                                       | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                       |                5 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_field_wr[3]                                                                                                                |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | n_0_axi_addr_write[15]_i_2                                                                                                                                                                                                  | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                       |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_field_wr[1]                                                                                                                |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_field_wr[0]                                                                                                                |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_compare_wr[3]                                                                                                              |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/RECEIVER/RX_CONFIG_VALID                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/RECEIVER/O18[0]                                                                                                           |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_compare_wr[2]                                                                                                              |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_raw_checksum[15]_i_1                                                                                                       |                9 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/I99[0]                                                                                                                  | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_FDSE/SR[0]            | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                6 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/n_0_addr_reg_cpu_field_wr.ram_field_wr_uc_reg                                                                                  |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/tx_pause/sync_good_rx/O17                                                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_Latch_AS_Logic_1.AND2B1L_I1/E[0]                                                                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |                6 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_PAUSE_FRAME_CROSS_I/data_sync/E[0]                                                                                                                                                  | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXCLIENT/ClkB_reset_inst/ClkBRst                                                                                                                |                5 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/O2[0]                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/O2                                                                                                                          |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_compare_wr[1]                                                                                                              |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/ram_compare_wr[0]                                                                                                              |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/MDIO_INTERFACE_1/SHIFT_REG0                                                                                      |                                                                                                                                                                                                                  |                6 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/load_wr                                                                                                                        |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/wepa                                                                                                                               |                                                                                                                                                                                                                  |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/rx/E[0]                                                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |                5 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/flow/tx/E[0]                                                                                                                                                       | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |                4 |             16 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/rxpmarst_seq_i/original_rd_data0                                                                           |                                                                                                                                                                                                                  |                3 |             16 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/O1                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/Shim2IP_CS1                                                                                                                                                     |                6 |             17 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_31                                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Data_Flow_Logic_I/SR[0]                                                                                                                   |                4 |             17 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2                                                                                                                                                  | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                                                                                                          |                3 |             17 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/O2                                                                                                                          |                6 |             17 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk  | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/n_0_wait_bypass_count[0]_i_2                                                                                        | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/n_0_wait_bypass_count[0]_i_1                                                                             |                5 |             17 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0]                                                                                                                       |                7 |             18 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/I_WRAP_BRST/bram_addr_ld_en                                                                                                             | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/I_WRAP_BRST/O5                                                                                                               |                9 |             18 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                                   |                6 |             18 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/n_0_time_out_counter[0]_i_1                                                                                         | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/reset_time_out                                                                                           |                5 |             19 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/p_0_in                                                                                                                                                                  | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_GTX/ClkB_reset_inst/RESET2GTX_CLK                                                                                                               |                6 |             19 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_aw/p_1_in                                                                                                                                          | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/SR[0]                                                                                                                                |                4 |             19 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0]                                            | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                       |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_31                                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               10 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Read_Req_Granted                                                   |                                                                                                                                                                                                                  |                5 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/mm2s_prmry_reset_out_n                                                                                                                                            |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Cache_Interface_I1/Read_Req_Granted                                                                                                       |                                                                                                                                                                                                                  |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                                 |                7 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/mm2s_cntrl_reset_out_n                                                                                                                                            |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_time_out_counter[0]_i_1__0                                                                                      | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/n_0_reset_time_out_reg                                                                                   |                5 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/n_0_GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe[2]_i_1                                                                               |                                                                                                                                                                                                                  |                9 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_RXS_AXSTREAM/ClkB_reset_inst/O1                                                                                                                 |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/n_0_txd_rd_pntr_hold_plus3[9]_i_1                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXD_AXSTREAM_TO_TXC_AXSTREAM/ClkA_reset_inst/reset2axi_str_txd                                                                                               |                4 |             20 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_31                                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/O12[0]                                                                                                            |                6 |             21 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                                  |                7 |             21 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/O15                                  | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/O24                       |                9 |             22 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/p_1_in                                                                                                                                          | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/SR[0]                                                                                                                                |                6 |             22 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O2[0]                                           | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                       |                7 |             22 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O10[0]                                          | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                       |               22 |             22 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/n_0_toggle_i_1                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/MGT_TX_RESET                                                                                                              |                6 |             22 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/sig_Bus2IP_Reset                                                                                                                                                  |               19 |             23 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_INT_MAX_FRAME_LENGTH[14]_i_1                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/O2                                                                                                                          |                4 |             23 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                |                                                                                                                                                                                                                             | mbsys_i/mdm_1/U0/MDM_Core_I1/shift_n_reset                                                                                                                                                                       |                7 |             23 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/I89[0]                                                                                                                  |                                                                                                                                                                                                                  |                7 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/I90[0]                                                                                                                  |                                                                                                                                                                                                                  |                8 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/araddr_pipe_ld45_out                                                                                                                    |                                                                                                                                                                                                                  |               11 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/sel                                  | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                                  |                4 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/O1                                                                                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_DIV_I/mem_reset_Q                                                                                                       |                6 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/DATA_PHASE_WDT.I_DPTO_COUNTER/O3                                                                                             |               10 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/sel                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/Q[1]                                                 |                5 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0]                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/AR[0]                                                 |                4 |             24 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/rx_byte_counter/SYNC_STATS_RESET/SR[0]                                                                                  |                6 |             24 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/n_0_frame_length_words[14]_i_1                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |                8 |             25 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/rx_statistics_valid                                                                                                                                          | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/n_0_rx_statistics_vector_i[26]_i_1                                                                                                                             |                9 |             26 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/SR[0]                                                                                                                                                               |               10 |             26 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Data_Flow_Logic_I/O7[0]                                                                                                                   |                7 |             26 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_statistics_vector[25]_i_1                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |                9 |             26 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_rxs_mem_next_available4write_ptr_reg[8]_i_1__0                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |               12 |             28 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/p_0_in45_in                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/n_0_count_read[6]_i_1                                                                                                   |                9 |             28 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |               20 |             28 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O14                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O13                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O4                                                  |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O11                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O9                                                  |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O16                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O8                                                  |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O17                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O10                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O6                                                  |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/n_0_txc_mem_wr_addr_0[9]_i_1                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkA_reset_inst/O4                                                                                                              |                7 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O18                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O5                                                  |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_block.managen/mdio_enabled.phy/n_0_mdio_data[30]_i_1                                                                                                           |                                                                                                                                                                                                                  |               10 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O1                                                  |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Using_ICache_Carry_Chain.ib_addr_strobe_i_carry_and/MUXCY_I/O5                                                                                          |                                                                                                                                                                                                                  |               16 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O15                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O12                                                 |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/O7                                                  |                                                                                                                                                                                                                  |                8 |             30 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/MGT_RX_RESET                                                                                                              |               14 |             31 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Tag_RAM_Module/Using_B36_S18.The_BRAMs[0].RAMB36_I1/O1                                                                                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               13 |             31 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/TAG_RAM_Module/Using_B36_S18.The_BRAMs[0].RAMB36_I1/Read_Req                                                           | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               11 |             31 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/CONFIG_SELECT.CRCGEN2/O2                                                                                                                          |               11 |             31 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/txd_wr_en                                                                                                                                                                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/n_0_gtxd.sig_txd_packet_size[0]_i_1                                                                                                                               |                8 |             31 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Start_Div                                                                                                                                            |                                                                                                                                                                                                                  |                8 |             32 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/txgen/TX_SM1/n_0_PREAMBLE_PIPE_reg[2]                                                                                                                   |               10 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/axi_rdata_en                                                                                                                            | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/n_0_GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1                                                                     |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/I98[0]                                                                                                                                                  | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Start_Div                                                                                                                                 |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/n_0_sig_ip2bus_data[0]_i_1                                                                                                                                        |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/rd_skid_buf_ld                                                                                                                          | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/I_WRAP_BRST/O5                                                                                                               |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[31]_i_1                                                                                                                                       | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                                  |                6 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/wrdata_reg_ld                                                                                                                           |                                                                                                                                                                                                                  |               10 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/E[0]                                                                                                                                                     | mbsys_i/axi_gpio_0/U0/bus2ip_reset                                                                                                                                                                               |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_ICache.ICache_I1/Cache_Interface_I1/E[0]                                                                                                                   | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               17 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_gpio_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[31]_i_1                                                                                                                                          | mbsys_i/axi_gpio_0/U0/bus2ip_reset                                                                                                                                                                               |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/n_0_ip2bus_data[31]_i_1__2                                                                                          |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[0]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[1]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_31                                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/SR[0]                                                                                                                                                        |               16 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[3]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |               18 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[31]_i_1                                                                                                                               | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                          |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[4]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |               20 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_intc/U0/INTC_CORE_I/irq                                                                                                                                                                            |                                                                                                                                                                                                                  |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/p_0_in1_in                                                                                                                             | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0]                                                                                                                       |                7 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_FDSE/Write_Data_Valid |                                                                                                                                                                                                                  |                4 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/m_axi_wvalid[5]                                                                                                                        | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                       |               18 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_rvalid[0]                                                                                                                        | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/I8[0]                                                                                                                                                        |               21 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | axi_we_axi_reg_0                                                                                                                                                                                                            | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                       |               19 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | axi_we_axi_reg_1                                                                                                                                                                                                            | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                       |               19 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | axi_we_axi_reg_2                                                                                                                                                                                                            | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                       |               19 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | axi_we_axi_reg_3                                                                                                                                                                                                            | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                       |               18 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | axi_we_axi_reg_4                                                                                                                                                                                                            | n_0_axi_addr_write[15]_i_1                                                                                                                                                                                       |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_ADDR_SHIM/O1[5]                                                                                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |               18 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[31]_i_1                                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/I_AXI_LITE_IPIF/I_SLAVE_ATTACHMENT/rst                                                                                                                                      |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/TX_INTFCE_I/TX_AXISTREAM_INTERFACE/GEN_BASIC.TX_BASIC_INTERFACE/p_51_in                                                                                                                |                                                                                                                                                                                                                  |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_reg[31]_i_1                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/DATA_PHASE_WDT.I_DPTO_COUNTER/O3                                                                                             |               15 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/O26[0]                                                                                            | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               10 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_gpio_0/U0/gpio_core_1/Read_Reg_Rst                                                                                                                                                                   |               17 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/E[0]                                                                                                                    | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/addr_filter_top/address_filter_inst/n_0_cpu_data_shift[31]_i_1                                                                                                     | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/int_mgmt_host_reset                                                                                                    |                8 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/txd_wr_en                                                                                                                                                                    | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/O1                                                   |               12 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/I_DECODER/bus2ip_wrce[0]                                                                                                                                              | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |               13 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/n_0_s_axi_rdata_i[31]_i_1                                                                                                                                             | mbsys_i/axi_timer_0/U0/AXI4_LITE_I/I_SLAVE_ATTACHMENT/rst                                                                                                                                                        |               32 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIF/I_SLAVE_ATTACHMENT/I_DECODER/I48[0]                                                                                                                                                | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/sig_Bus2IP_Reset                                                                                                                                                  |               14 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/INPUT_DOUBLE_REGS3/E[0]                                                                                                                                                    | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_timer_0/U0/TC_CORE_I/TIMER_CONTROL_I/INPUT_DOUBLE_REGS3/O21[0]                                                                                                                                                  | mbsys_i/axi_timer_0/U0/TC_CORE_I/GEN_SECOND_TIMER.COUNTER_1_I/COUNTER_I/O35                                                                                                                                      |                7 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/I24[0]                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/I23[0]                                                                                                                 |                9 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/ipic_mux_inst/SR[0]                                                                                                                                     |               12 |             32 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_bytes_14_and_15_d19[15]_i_1                                                                                                           | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |               11 |             32 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_39                                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_Logic_I/R                                                                                                                                   |               11 |             32 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Use_Debug_Logic.Master_Core.Debug_Perf/New_Dbg_Instr_TCK                                                                                                         |                                                                                                                                                                                                                  |               15 |             32 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/FCS_CHECK/n_0_CALC[31]_i_2                                                                                                                                   | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/rxgen/RX_SM/SR[0]                                                                                                                                       |               11 |             32 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_GTX/ClkB_reset_inst/RESET2GTX_CLK                                                                                                               |               10 |             33 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/p_8_out[0]                                                                                                                         |                                                                                                                                                                                                                  |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Q0                                                                                                                        | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/I97[0]                                                                                                                         |                9 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/reg_slice_r/aa_rready                                                                                                                                    |                                                                                                                                                                                                                  |               19 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/E[0]                                                                                                                                   |                                                                                                                                                                                                                  |               18 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O16[0]                               |                                                                                                                                                                                                                  |               10 |             33 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r_pipe/O1                                                                                                                      |                                                                                                                                                                                                                  |               11 |             34 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_31                                                                                                          |                                                                                                                                                                                                                  |               13 |             34 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/gen_master_slots[0].reg_slice_mi/r_pipe/p_1_in                                                                                                                  |                                                                                                                                                                                                                  |               11 |             34 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_39                                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/I10[0]                                                                                                                                                       |               13 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O4[0]                                                   | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/srst_wrst_busy                                                                                                  |                6 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0]                                | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/WR_RST                                               |                7 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/E[0]                                                    | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXD_AXSTREAM/ClkB_reset_inst/srst_wrst_busy                                                                                                  |               11 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_interconnect_0/xbar/inst/gen_samd.crossbar_samd/addr_arbiter_ar/SR[0]                                                                                                                                |               13 |             36 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O3[0]                               |                                                                                                                                                                                                                  |               16 |             37 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_bram_ctrl_0/U0/gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_RD_CHNL/I_WRAP_BRST/O5                                                                                                               |               21 |             38 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/wr_enable                                                                                                                      |                                                                                                                                                                                                                  |               10 |             40 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/O3                                   |                8 |             40 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk  |                                                                                                                                                                                                                             |                                                                                                                                                                                                                  |               12 |             40 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_gpio_0/U0/bus2ip_reset                                                                                                                                                                               |               21 |             42 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/O3                                              | mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_rx_len_fifo/FAMILY_SUPPORTED.I_SYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/O1                                       |               11 |             42 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/rd_enable                                                                                                                      | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reset_modified                                                                                                      |                9 |             43 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/MGT_TX_RESET                                                                                                              |               14 |             47 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Using_AXI.Use_AXI_Write.Addr_bit[1].Addr_bit_FDSE/O1               |                                                                                                                                                                                                                  |                6 |             48 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/RX_AXISTREAM_IF_I/ELASTIC_FIFO/I_BASIC_SFIFO/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/E[0]                                                    |                                                                                                                                                                                                                  |                6 |             48 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_multicast_addr_upper_d10[15]_i_1                                                                                                      | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |               16 |             48 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/OF_Valid_DFF/O86                                                                                                                     | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               15 |             48 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/O1                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/gen_sync_reset/reset_out                                                                                                                        |               12 |             50 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_stats_reset/stats_reset                                                                                                                            |               14 |             51 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/rx_elastic_buffer_inst/reset_modified                                                                                                      |               13 |             53 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/transceiver_inst/reclock_rxreset/SR[0]                                                                                                                      |               13 |             54 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_tx_reset_i/O1                                                                                                                                      |               26 |             60 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                | mbsys_i/mdm_1/U0/Dbg_Capture_0                                                                                                                                                                                              |                                                                                                                                                                                                                  |               23 |             61 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0_axi_intc/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/O7                                                                                                                                            |                                                                                                                                                                                                                  |                8 |             64 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/n_0_rx_data_valid_array[1][0]_i_1                                                                                                         | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |               16 |             65 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/TXC_AXSTREAM_TO_RXS_AXSTREAM/ClkB_reset_inst/O2[0]                                                                                                           |               21 |             69 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       |                                                                                                                                                                                                                             |                                                                                                                                                                                                                  |               19 |             69 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/enb                                                                                                                                |                                                                                                                                                                                                                  |               16 |             72 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Using_ICache_Carry_Chain.Using_Latch_AS_Logic.AND2B1L_I1/O3                                                                                             |                                                                                                                                                                                                                  |               11 |             75 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/RCV_INTFCE_I/NO_INCLUDE_RX_VLAN.RX_EMAC_IF_I/O1                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |               33 |             77 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/SR[0]                                                                                                              |               34 |             85 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/tx_axi_intf.tx_axi_shim/tx_ce_sample                                                                                                                               |                                                                                                                                                                                                                  |               28 |             85 |
|  mbsys_i/clk_wiz_1/U0/clk_out2                                 |                                                                                                                                                                                                                             |                                                                                                                                                                                                                  |               22 |             87 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/bd_0_pcs_pma_0_core/gpcs_pma_inst/SRESET                                                                                                                    |               32 |             93 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/p_0_in45_in                                                                                                                        |                                                                                                                                                                                                                  |               40 |             96 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/O1                                                                                                                                        |                                                                                                                                                                                                                  |               34 |             98 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Using_New_CacheInterface_for_AXI.Cache_Interface_I1/Write_Req_Granted                                                  |                                                                                                                                                                                                                  |               18 |             99 |
|  mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                |                                                                                                                                                                                                                             |                                                                                                                                                                                                                  |               44 |            114 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/sgmii_logic/clock_generation/O1                                                                                                                                        | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |               48 |            122 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/O8[30]                                                                                                                                                  |                                                                                                                                                                                                                  |               16 |            128 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/stats_block.statistics_counters/wea                                                                                                                                |                                                                                                                                                                                                                  |               32 |            128 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/lopt_39                                                                                                          | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               60 |            139 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/man_reset.sync_mgmt_reset_host_i/int_mgmt_host_reset                                                                                                    |               50 |            157 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/O5                                                                                                                 |               30 |            204 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/MUXCY_I/O1                                                                                                               | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |               80 |            216 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             | mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Reset_DFF/Synced                                                                                                                                                       |              140 |            274 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             | mbsys_i/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core/sync_rx_reset_i/O1                                                                                                                                      |               91 |            368 |
|  mbsys_i/clk_wiz_1/U0/clk_out1                                 |                                                                                                                                                                                                                             |                                                                                                                                                                                                                  |              373 |           1008 |
|  mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |                                                                                                                                                                                                                             |                                                                                                                                                                                                                  |              305 |           1063 |
+----------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+


