Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------
| Tool Version : Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
| Date         : Tue Mar 24 12:53:14 2015
| Host         : phys-pc458-4 running 64-bit Service Pack 1  (build 7601)
| Command      : report_clock_utilization -file toplevel_clock_utilization_placed.rpt
| Design       : toplevel
| Device       : xc7a200t
--------------------------------------------------------------------------------------

Clock Utilization Report

Table of Contents
-----------------
1. Clock Primitive Utilization
2. Details of Global Clocks
3. Details of Regional Clocks
4. Details of Multi-Regional Clocks
5. Details of I/O Clocks
6. Details of Local Clocks
7. Clock Regions : Key Resource Utilization
8. Net wise resources used in clock region X0Y1
9. Net wise resources used in clock region X1Y1
10. Net wise resources used in clock region X0Y2
11. Net wise resources used in clock region X1Y2
12. Net wise resources used in clock region X0Y3
13. Net wise resources used in clock region X1Y3
14. Net wise resources used in clock region X0Y4
15. Net wise resources used in clock region X1Y4

1. Clock Primitive Utilization
------------------------------

+-------+------+-----------+-----------+
| Type  | Used | Available | Num Fixed |
+-------+------+-----------+-----------+
| BUFG  |    9 |        32 |         0 |
| BUFH  |    0 |       120 |         0 |
| BUFIO |    0 |        40 |         0 |
| MMCM  |    2 |        10 |         0 |
| PLL   |    0 |        10 |         0 |
| BUFR  |    0 |        40 |         0 |
| BUFMR |    0 |        20 |         0 |
+-------+------+-----------+-----------+


2. Details of Global Clocks
---------------------------

+-------+--------------------------------------------------------------------+--------------------------------------------------------------------+--------------+-------+---------------+-----------+
|       |                                                                    |                                                                    |   Num Loads  |       |               |           |
+-------+--------------------------------------------------------------------+--------------------------------------------------------------------+------+-------+-------+---------------+-----------+
| Index | BUFG Cell                                                          | Net Name                                                           | BELs | Sites | Fixed | MaxDelay (ns) | Skew (ns) |
+-------+--------------------------------------------------------------------+--------------------------------------------------------------------+------+-------+-------+---------------+-----------+
|     1 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg |    1 |     1 |    no |         1.565 |     0.078 |
|     2 | mbsys_i/clk_wiz_1/U0/clkf_buf                                      | mbsys_i/clk_wiz_1/U0/clkfbout_buf_mbsys_clk_wiz_1_0                |    1 |     1 |    no |         1.722 |     0.086 |
|     3 | mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst                            | mbsys_i/mdm_1/U0/Dbg_Update_0                                      |   41 |    19 |    no |         1.628 |     0.144 |
|     4 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk  | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk       |   63 |    20 |    no |         1.780 |     0.222 |
|     5 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg  | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1            |  209 |    58 |    no |         1.778 |     0.379 |
|     6 | mbsys_i/clk_wiz_1/U0/clkout2_buf                                   | mbsys_i/clk_wiz_1/U0/clk_out2                                      |  259 |    83 |    no |         1.770 |     0.223 |
|     7 | mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK                       | mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                     |  273 |   106 |    no |         1.633 |     0.230 |
|     8 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2      | 4063 |  1214 |    no |         1.775 |     0.443 |
|     9 | mbsys_i/clk_wiz_1/U0/clkout1_buf                                   | mbsys_i/clk_wiz_1/U0/clk_out1                                      | 7587 |  2978 |    no |         1.785 |     0.457 |
+-------+--------------------------------------------------------------------+--------------------------------------------------------------------+------+-------+-------+---------------+-----------+


+-------+--------------------------------------------------------------------+---------------------------------------------------------------+--------------+-------+---------------+-----------+
|       |                                                                    |                                                               |   Num Loads  |       |               |           |
+-------+--------------------------------------------------------------------+---------------------------------------------------------------+------+-------+-------+---------------+-----------+
| Index | MMCM Cell                                                          | Net Name                                                      | BELs | Sites | Fixed | MaxDelay (ns) | Skew (ns) |
+-------+--------------------------------------------------------------------+---------------------------------------------------------------+------+-------+-------+---------------+-----------+
|     1 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkfbout |    1 |     1 |    no |         0.012 |     0.001 |
|     2 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout0  |    1 |     1 |    no |         1.559 |     0.078 |
|     3 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/clkout1  |    1 |     1 |    no |         1.559 |     0.078 |
|     4 | mbsys_i/clk_wiz_1/U0/mmcm_adv_inst                                 | mbsys_i/clk_wiz_1/U0/clk_out1_mbsys_clk_wiz_1_0               |    1 |     1 |    no |         1.766 |     0.088 |
|     5 | mbsys_i/clk_wiz_1/U0/mmcm_adv_inst                                 | mbsys_i/clk_wiz_1/U0/clk_out2_mbsys_clk_wiz_1_0               |    1 |     1 |    no |         1.766 |     0.088 |
|     6 | mbsys_i/clk_wiz_1/U0/mmcm_adv_inst                                 | mbsys_i/clk_wiz_1/U0/clkfbout_mbsys_clk_wiz_1_0               |    1 |     1 |    no |         1.766 |     0.088 |
+-------+--------------------------------------------------------------------+---------------------------------------------------------------+------+-------+-------+---------------+-----------+


3. Details of Regional Clocks
-----------------------------

4. Details of Multi-Regional Clocks
-----------------------------------

5. Details of I/O Clocks
------------------------

6. Details of Local Clocks
--------------------------

7. Clock Regions : Key Resource Utilization
-------------------------------------------

+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E1   |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 21600 |    0 |  3200 |    0 |    60 |    0 |    30 |    0 |    60 |
| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 20000 |    0 |  3200 |    0 |    40 |    0 |    20 |    0 |    40 |
| X0Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 33600 |    0 |  5600 |    0 |   100 |   18 |    50 |    0 |   100 |
| X1Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 32000 |    0 |  5600 |    0 |    80 |   23 |    40 |    0 |    80 |
| X0Y2              |    5 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 3175 | 28800 |  361 |  5600 |    0 |   100 |   48 |    50 |    5 |   100 |
| X1Y2              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |   15 | 32000 |    0 |  5600 |    0 |    80 |   40 |    40 |    0 |    80 |
| X0Y3              |    5 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 6042 | 28800 |  973 |  5600 |    0 |   100 |   25 |    50 |    0 |   100 |
| X1Y3              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |  590 | 32000 |    0 |  5600 |    0 |    80 |   37 |    40 |    0 |    80 |
| X0Y4              |    6 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    1 |     1 |    0 |     1 |    2 |     5 |    0 |     1 |    0 |    50 |    0 |    50 | 1094 | 20400 |   40 |  3000 |    0 |    50 |    0 |    25 |    0 |    60 |
| X1Y4              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     5 |    0 |     0 |    0 |    50 |    0 |    50 |    0 | 20000 |    0 |  3200 |    0 |    40 |    1 |    20 |    0 |    40 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* RAMB36 site can be used as two RAMB18/FIFO18 sites


8. Net wise resources used in clock region X0Y1
-----------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s |         Clock Net Name        |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+
| BUFG        |     ---     |   no  |         0 |        0 |       0 |        36 |       0 |       0 |   0 |     0 |        0 | mbsys_i/clk_wiz_1/U0/clk_out1 |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+


9. Net wise resources used in clock region X1Y1
-----------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s |         Clock Net Name        |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+
| BUFG        |     ---     |   no  |         0 |        0 |       0 |        46 |       0 |       0 |   0 |     0 |        0 | mbsys_i/clk_wiz_1/U0/clk_out1 |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+


10. Net wise resources used in clock region X0Y2
------------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+------+-------+----------+--------------------------------------------------------------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs |  FFs | LUTMs | DSP48E1s |                           Clock Net Name                           |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+------+-------+----------+--------------------------------------------------------------------+
| BUFG        |     ---     |   no  |         1 |        0 |       0 |         0 |       0 |       0 |    0 |     0 |        0 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/txoutclk_bufg |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         0 |       0 |       0 |   11 |     0 |        0 | mbsys_i/mdm_1/U0/Dbg_Update_0                                      |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         0 |       0 |       0 |  165 |    26 |        0 | mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                     |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         1 |       0 |       0 |  398 |     1 |        0 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2      |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |        95 |       0 |       0 | 2601 |   334 |        5 | mbsys_i/clk_wiz_1/U0/clk_out1                                      |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+------+-------+----------+--------------------------------------------------------------------+


11. Net wise resources used in clock region X1Y2
------------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s |         Clock Net Name        |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+
| BUFG        |     ---     |   no  |         0 |        0 |       0 |        80 |       0 |       0 |  15 |     0 |        0 | mbsys_i/clk_wiz_1/U0/clk_out1 |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+


12. Net wise resources used in clock region X0Y3
------------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+------+-------+----------+---------------------------------------------------------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs |  FFs | LUTMs | DSP48E1s |                         Clock Net Name                        |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+------+-------+----------+---------------------------------------------------------------+
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         0 |       0 |       0 |    6 |     0 |        0 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         0 |       0 |       0 |   30 |     0 |        0 | mbsys_i/mdm_1/U0/Dbg_Update_0                                 |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         0 |       0 |       0 |   79 |     3 |        0 | mbsys_i/mdm_1/U0/Ext_JTAG_DRCK                                |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         1 |       0 |       0 | 2762 |   201 |        0 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |        49 |       0 |       0 | 3165 |   769 |        0 | mbsys_i/clk_wiz_1/U0/clk_out1                                 |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+------+-------+----------+---------------------------------------------------------------+


13. Net wise resources used in clock region X1Y3
------------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+---------------------------------------------------------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s |                         Clock Net Name                        |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+---------------------------------------------------------------+
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         2 |       0 |       0 | 168 |     0 |        0 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |        72 |       0 |       0 | 422 |     0 |        0 | mbsys_i/clk_wiz_1/U0/clk_out1                                 |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+---------------------------------------------------------------+


14. Net wise resources used in clock region X0Y4
------------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+---------------------------------------------------------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s |                         Clock Net Name                        |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+---------------------------------------------------------------+
| BUFG        |     ---     |   no  |         1 |        0 |       0 |         0 |       0 |       0 |   0 |     0 |        0 | mbsys_i/clk_wiz_1/U0/clkfbout_buf_mbsys_clk_wiz_1_0           |
| BUFG        |     ---     |   no  |         0 |        0 |       2 |         0 |       0 |       0 |  62 |     0 |        0 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk  |
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         0 |       0 |       0 |  84 |     0 |        0 | mbsys_i/clk_wiz_1/U0/clk_out1                                 |
| BUFG        |     ---     |   no  |         0 |        0 |       2 |         0 |       0 |       0 | 162 |    40 |        0 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1       |
| BUFG        |     ---     |   no  |         0 |        0 |       1 |         0 |       0 |       0 | 258 |     0 |        0 | mbsys_i/clk_wiz_1/U0/clk_out2                                 |
| BUFG        |     ---     |   no  |         0 |        0 |       1 |         0 |       0 |       0 | 528 |     0 |        0 | mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2 |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+---------------------------------------------------------------+


15. Net wise resources used in clock region X1Y4
------------------------------------------------

+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+
| Source Type | BUFHCE Site | Fixed | MMCM Pins | PLL Pins | GT Pins | BRAM Pins | ILOGICs | OLOGICs | FFs | LUTMs | DSP48E1s |         Clock Net Name        |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+
| BUFG        |     ---     |   no  |         0 |        0 |       0 |         2 |       0 |       0 |   0 |     0 |        0 | mbsys_i/clk_wiz_1/U0/clk_out1 |
+-------------+-------------+-------+-----------+----------+---------+-----------+---------+---------+-----+-------+----------+-------------------------------+



# Location of BUFG Primitives 
set_property LOC BUFGCTRL_X0Y19 [get_cells mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_txoutclk]
set_property LOC BUFGCTRL_X0Y1 [get_cells mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk]
set_property LOC BUFGCTRL_X0Y0 [get_cells mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2]
set_property LOC BUFGCTRL_X0Y16 [get_cells mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg]
set_property LOC BUFGCTRL_X0Y17 [get_cells mbsys_i/clk_wiz_1/U0/clkout1_buf]
set_property LOC BUFGCTRL_X0Y18 [get_cells mbsys_i/clk_wiz_1/U0/clkout2_buf]
set_property LOC BUFGCTRL_X0Y20 [get_cells mbsys_i/clk_wiz_1/U0/clkf_buf]
set_property LOC BUFGCTRL_X0Y3 [get_cells mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst]
set_property LOC BUFGCTRL_X0Y2 [get_cells mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK]

# Location of IO Clock Primitives

# Location of MMCM Clock Primitives
set_property LOC MMCME2_ADV_X0Y2 [get_cells mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/mmcm_adv_inst]
set_property LOC MMCME2_ADV_X0Y4 [get_cells mbsys_i/clk_wiz_1/U0/mmcm_adv_inst]

# Location of BUFH Clock Primitives

# Location of BUFR Clock Primitives

# Location of BUFMR Clock Primitives

# Location of PLL Clock Primitives

# Location of IO Primitives which is load of clock spine

# Location of clock ports
set_property LOC IPAD_X1Y47 [get_ports MGTREFCLK1N]
set_property LOC IPAD_X1Y46 [get_ports MGTREFCLK1P]

# Clock net "mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk" driven by instance "mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk" located at site "BUFGCTRL_X0Y1"
#startgroup
create_pblock CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk
add_cells_to_pblock [get_pblocks  CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk] [get_cells  -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk"}]]]
resize_pblock [get_pblocks CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup

# Clock net "mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2" driven by instance "mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/bufg_userclk2" located at site "BUFGCTRL_X0Y0"
#startgroup
create_pblock CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2
add_cells_to_pblock [get_pblocks  CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2] [get_cells  -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2"}]]]
resize_pblock [get_pblocks CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/core_clocking_i/userclk2] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup

# Clock net "mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1" driven by instance "mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/rxrecclkbufg" located at site "BUFGCTRL_X0Y16"
#startgroup
create_pblock CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1
add_cells_to_pblock [get_pblocks  CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1] [get_cells  -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1"}]]]
resize_pblock [get_pblocks CLKAG_mbsys_i/axi_ethernet_0/U0/pcs_pma/U0/pcs_pma_block_i/O1] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup

# Clock net "mbsys_i/clk_wiz_1/U0/clk_out1" driven by instance "mbsys_i/clk_wiz_1/U0/clkout1_buf" located at site "BUFGCTRL_X0Y17"
#startgroup
create_pblock CLKAG_mbsys_i/clk_wiz_1/U0/clk_out1
add_cells_to_pblock [get_pblocks  CLKAG_mbsys_i/clk_wiz_1/U0/clk_out1] [get_cells  -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="mbsys_i/clk_wiz_1/U0/clk_out1"}]]]
resize_pblock [get_pblocks CLKAG_mbsys_i/clk_wiz_1/U0/clk_out1] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup

# Clock net "mbsys_i/clk_wiz_1/U0/clk_out2" driven by instance "mbsys_i/clk_wiz_1/U0/clkout2_buf" located at site "BUFGCTRL_X0Y18"
#startgroup
create_pblock CLKAG_mbsys_i/clk_wiz_1/U0/clk_out2
add_cells_to_pblock [get_pblocks  CLKAG_mbsys_i/clk_wiz_1/U0/clk_out2] [get_cells  -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="mbsys_i/clk_wiz_1/U0/clk_out2"}]]]
resize_pblock [get_pblocks CLKAG_mbsys_i/clk_wiz_1/U0/clk_out2] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup

# Clock net "mbsys_i/mdm_1/U0/Dbg_Update_0" driven by instance "mbsys_i/mdm_1/U0/Dbg_Update_0_BUFG_inst" located at site "BUFGCTRL_X0Y3"
#startgroup
create_pblock CLKAG_mbsys_i/mdm_1/U0/Dbg_Update_0
add_cells_to_pblock [get_pblocks  CLKAG_mbsys_i/mdm_1/U0/Dbg_Update_0] [get_cells  -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="mbsys_i/mdm_1/U0/Dbg_Update_0"}]]]
resize_pblock [get_pblocks CLKAG_mbsys_i/mdm_1/U0/Dbg_Update_0] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup

# Clock net "mbsys_i/mdm_1/U0/Ext_JTAG_DRCK" driven by instance "mbsys_i/mdm_1/U0/No_Dbg_Reg_Access.BUFG_DRCK" located at site "BUFGCTRL_X0Y2"
#startgroup
create_pblock CLKAG_mbsys_i/mdm_1/U0/Ext_JTAG_DRCK
add_cells_to_pblock [get_pblocks  CLKAG_mbsys_i/mdm_1/U0/Ext_JTAG_DRCK] [get_cells  -filter { IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="mbsys_i/mdm_1/U0/Ext_JTAG_DRCK"}]]]
resize_pblock [get_pblocks CLKAG_mbsys_i/mdm_1/U0/Ext_JTAG_DRCK] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}
#endgroup
