*** Running vivado
    with args -log toplevel.vdi -applog -m64 -messageDb vivado.pb -mode batch -source toplevel.tcl -notrace


****** Vivado v2014.4 (64-bit)
  **** SW Build 1071353 on Tue Nov 18 18:29:27 MST 2014
  **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
    ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.

source toplevel.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 1061 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2014.4
Loading clock regions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a200t/ClockRegion.xml
Loading clock buffers from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a200t/ClockBuffers.xml
Loading clock placement rules from C:/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml
Loading package pin functions from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/PinFunctions.xml...
Loading package from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/artix7/xc7a200t/fbg484/Package.xml
Loading io standards from C:/Xilinx/Vivado/2014.4/data\./parts/xilinx/artix7/IOStandards.xml
Loading device configuration modes from C:/Xilinx/Vivado/2014.4/data\parts/xilinx/artix7/ConfigModes.xml
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
WARNING: [Constraints 18-1079] Register mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.
WARNING: [Constraints 18-1079] Register mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.
WARNING: [Constraints 18-1079] Register mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.
WARNING: [Constraints 18-1079] Register mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_microblaze_0_0/mbsys_microblaze_0_0.xdc] for cell 'mbsys_i/microblaze_0/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_microblaze_0_0/mbsys_microblaze_0_0.xdc] for cell 'mbsys_i/microblaze_0/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_dlmb_v10_0/mbsys_dlmb_v10_0.xdc] for cell 'mbsys_i/microblaze_0_local_memory/dlmb_v10/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_dlmb_v10_0/mbsys_dlmb_v10_0.xdc] for cell 'mbsys_i/microblaze_0_local_memory/dlmb_v10/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_ilmb_v10_0/mbsys_ilmb_v10_0.xdc] for cell 'mbsys_i/microblaze_0_local_memory/ilmb_v10/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_ilmb_v10_0/mbsys_ilmb_v10_0.xdc] for cell 'mbsys_i/microblaze_0_local_memory/ilmb_v10/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_microblaze_0_axi_intc_0/mbsys_microblaze_0_axi_intc_0.xdc] for cell 'mbsys_i/microblaze_0_axi_intc/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_microblaze_0_axi_intc_0/mbsys_microblaze_0_axi_intc_0.xdc] for cell 'mbsys_i/microblaze_0_axi_intc/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_mdm_1_0/mbsys_mdm_1_0.xdc] for cell 'mbsys_i/mdm_1/U0'
INFO: [Timing 38-35] Done setting XDC timing constraints. [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_mdm_1_0/mbsys_mdm_1_0.xdc:50]
get_clocks: Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1127.148 ; gain = 537.488
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_mdm_1_0/mbsys_mdm_1_0.xdc] for cell 'mbsys_i/mdm_1/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_clk_wiz_1_0/mbsys_clk_wiz_1_0_board.xdc] for cell 'mbsys_i/clk_wiz_1/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_clk_wiz_1_0/mbsys_clk_wiz_1_0_board.xdc] for cell 'mbsys_i/clk_wiz_1/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_clk_wiz_1_0/mbsys_clk_wiz_1_0.xdc] for cell 'mbsys_i/clk_wiz_1/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_clk_wiz_1_0/mbsys_clk_wiz_1_0.xdc] for cell 'mbsys_i/clk_wiz_1/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_rst_clk_wiz_1_100M_0/mbsys_rst_clk_wiz_1_100M_0_board.xdc] for cell 'mbsys_i/rst_clk_wiz_1_100M'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_rst_clk_wiz_1_100M_0/mbsys_rst_clk_wiz_1_100M_0_board.xdc] for cell 'mbsys_i/rst_clk_wiz_1_100M'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_rst_clk_wiz_1_100M_0/mbsys_rst_clk_wiz_1_100M_0.xdc] for cell 'mbsys_i/rst_clk_wiz_1_100M'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_rst_clk_wiz_1_100M_0/mbsys_rst_clk_wiz_1_100M_0.xdc] for cell 'mbsys_i/rst_clk_wiz_1_100M'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_0/bd_0_eth_buf_0_board.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_buf/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_0/bd_0_eth_buf_0_board.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_buf/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0_board.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_mac/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0_board.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_mac/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_mac/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_mac/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_2/bd_0_pcs_pma_0_board.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/pcs_pma'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_2/bd_0_pcs_pma_0_board.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/pcs_pma'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_2/synth/bd_0_pcs_pma_0.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/pcs_pma'
INFO: [Timing 38-2] Deriving generated clocks [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_2/synth/bd_0_pcs_pma_0.xdc:44]
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_2/synth/bd_0_pcs_pma_0.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/pcs_pma'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_timer_0_0/mbsys_axi_timer_0_0.xdc] for cell 'mbsys_i/axi_timer_0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_timer_0_0/mbsys_axi_timer_0_0.xdc] for cell 'mbsys_i/axi_timer_0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_gpio_0_0/mbsys_axi_gpio_0_0_board.xdc] for cell 'mbsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_gpio_0_0/mbsys_axi_gpio_0_0_board.xdc] for cell 'mbsys_i/axi_gpio_0/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_gpio_0_0/mbsys_axi_gpio_0_0.xdc] for cell 'mbsys_i/axi_gpio_0/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_gpio_0_0/mbsys_axi_gpio_0_0.xdc] for cell 'mbsys_i/axi_gpio_0/U0'
Parsing XDC File [C:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/constrs_1/new/toplevel.xdc]
Finished Parsing XDC File [C:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/constrs_1/new/toplevel.xdc]
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_microblaze_0_axi_intc_0/mbsys_microblaze_0_axi_intc_0_clocks.xdc] for cell 'mbsys_i/microblaze_0_axi_intc/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_microblaze_0_axi_intc_0/mbsys_microblaze_0_axi_intc_0_clocks.xdc] for cell 'mbsys_i/microblaze_0_axi_intc/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_0/synth/bd_0_eth_buf_0.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_buf/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_0/synth/bd_0_eth_buf_0.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_buf/U0'
Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0_clocks.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_mac/U0'
Finished Parsing XDC File [c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/bd/mbsys/ip/mbsys_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0_clocks.xdc] for cell 'mbsys_i/axi_ethernet_0/U0/eth_mac/U0'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Generating merged BMM file for the design top 'toplevel'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_4/e11bcbd5/data/mb_bootloop_le.elf 

INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 423 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 1 instances
  LUT6_2 => LUT6_2 (LUT5, LUT6): 64 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 28 instances
  RAM64M => RAM64M (RAMD64E, RAMD64E, RAMD64E, RAMD64E): 122 instances
  RAM64X1D => RAM64X1D (RAMD64E, RAMD64E): 176 instances

link_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 1140.938 ; gain = 944.820
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.453 . Memory (MB): peak = 1140.938 ; gain = 0.000

Starting Logic Optimization Task

Phase 1 Retarget

INFO: [Opt 31-138] Pushed 4 inverter(s) to 20 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1f8cb533b

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1140.938 ; gain = 0.000

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 2 inverter(s) to 17 load pin(s).
INFO: [Opt 31-10] Eliminated 1001 cells.
Phase 2 Constant Propagation | Checksum: 24882331e

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1140.938 ; gain = 0.000

Phase 3 Sweep
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/LO.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/ALL_Bits[0].ALU_Bit_I1/LO.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/ALL_Bits[1].ALU_Bit_I1/EX_CarryOut.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Equal_2/The_Compare[0].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Equal_2/The_Compare[1].carry_and_I1/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Equal_2/The_Compare[1].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Equal_2/The_Compare[2].carry_and_I1/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[0].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[1].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[1].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[2].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[3].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[4].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[4].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[5].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[5].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_Exp_Mant_Equal_2/The_Compare[6].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantA_Zero_2/The_Compare[0].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantA_Zero_2/The_Compare[1].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantA_Zero_2/The_Compare[2].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantA_Zero_2/The_Compare[3].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantA_Zero_2/The_Compare[3].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantA_Zero_2/The_Compare[4].carry_and_I1/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantA_Zero_2/The_Compare[4].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantA_Zero_2/The_Compare[5].carry_and_I1/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantB_Zero_2/The_Compare[0].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantB_Zero_2/The_Compare[1].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantB_Zero_2/The_Compare[2].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantB_Zero_2/The_Compare[3].carry_and_I1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantB_Zero_2/The_Compare[3].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantB_Zero_2/The_Compare[4].carry_and_I1/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantB_Zero_2/The_Compare[4].carry_and_I1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.ex_MantB_Zero_2/The_Compare[5].carry_and_I1/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Carry_OUT.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[10].OF_Piperun_Stage/I2.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[1].OF_Piperun_Stage/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[2].OF_Piperun_Stage/I2.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[2].OF_Piperun_Stage/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[3].OF_Piperun_Stage/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[5].OF_Piperun_Stage/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[6].OF_Piperun_Stage/I2.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[6].OF_Piperun_Stage/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[7].OF_Piperun_Stage/I2.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[7].OF_Piperun_Stage/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[8].OF_Piperun_Stage/I2.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Use_MuxCy[9].OF_Piperun_Stage/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Using_ICache_Carry_Chain.ib_addr_strobe_i_carry_and/I2.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Using_ICache_Carry_Chain.ib_addr_strobe_i_carry_or/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Using_PC_Incr_Dbg_or_Prot.if_pc_incr_carry_and_1/Carry_IN0_in.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Using_PC_Incr_Dbg_or_Prot.if_pc_incr_carry_and_1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/if_pc_incr_carry_and_0/Carry_IN0_in.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/if_pc_incr_carry_and_3/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_PipeRun_carry_and/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_wait_on_ready_N_carry_or/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_wait_on_ready_N_carry_or/Carry_OUT.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/Use_XX_Accesses3.xx_access_read_miss/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/dcache_data_strobe_sel_carry_or_0/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/dcache_data_strobe_sel_carry_or_0/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/dcache_data_strobe_sel_carry_or_1/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/dcache_data_strobe_sel_carry_or_1/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/dcache_data_strobe_sel_carry_or_2/I2.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/mem_read_cache_hit_carry_or/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_DCache.Using_WriteThrough.DCache_I1/mem_read_cache_miss_sel_carry_and/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_Debug.Using_ICache.combined_carry_and_I2/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_Debug.Using_ICache.combined_carry_and_I2/O1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_Debug.Using_ICache.combined_carry_or_I/Carry_IN.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Using_Debug.Using_ICache.debug_combinded_carry_or_I/I1.
WARNING: [Opt 31-6] Deleting driverless net: mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/mem_databus_ready_sel_carry_or/Carry_OUT.
INFO: [Opt 31-12] Eliminated 6269 unconnected nets.
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-11] Eliminated 5783 unconnected cells.
Phase 3 Sweep | Checksum: 132a1d778

Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1140.938 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 132a1d778

Time (s): cpu = 00:00:00 ; elapsed = 00:00:12 . Memory (MB): peak = 1140.938 ; gain = 0.000
Implement Debug Cores | Checksum: 2bbcb9702
Logic Optimization | Checksum: 2bbcb9702

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 75 BRAM(s) out of a total of 192 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 8 WE to EN ports
Number of BRAM Ports augmented: 192 newly gated: 17 Total Ports: 384
Number of Flops added for Enable Generation: 6

Ending PowerOpt Patch Enables Task | Checksum: 19ee1b7d3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.359 . Memory (MB): peak = 1484.695 ; gain = 0.000
Ending Power Optimization Task | Checksum: 19ee1b7d3

Time (s): cpu = 00:00:00 ; elapsed = 00:00:30 . Memory (MB): peak = 1484.695 ; gain = 343.758
INFO: [Common 17-83] Releasing license: Implementation
29 Infos, 72 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 1484.695 ; gain = 343.758
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1484.695 ; gain = 0.000
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.runs/impl_1/toplevel_drc_opted.rpt.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Runtime Estimator
Phase 1 Placer Runtime Estimator | Checksum: e5b3a62d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.359 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 2 Placer Initialization

Phase 2.1 Placer Initialization Core
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.125 . Memory (MB): peak = 1484.695 ; gain = 0.000
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.094 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device

Phase 2.1.1.1 Pre-Place Cells
Phase 2.1.1.1 Pre-Place Cells | Checksum: 9058820a

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1484.695 ; gain = 0.000
WARNING: [Constraints 18-1079] Register mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.
WARNING: [Constraints 18-1079] Register mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/grxd.COMP_RX_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.
WARNING: [Constraints 18-1079] Register mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg and mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.
WARNING: [Constraints 18-1079] Register mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg and mbsys_i/axi_ethernet_0_fifo/U0/COMP_IPIC2AXI_S/gtxd.COMP_TXD_FIFO/gfifo_gen.COMP_AXIS_FG_FIFO/COMP_FIFO/inst_fifo_gen/gaxis_fifo.gaxisf.axisf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg are from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints or mismatched control signals on the registers.
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 2.1.1.2 IO & Clk Clean Up
Phase 2.1.1.2 IO & Clk Clean Up | Checksum: 9058820a

Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 2.1.1.3 Implementation Feasibility check On IDelay
Phase 2.1.1.3 Implementation Feasibility check On IDelay | Checksum: 9058820a

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 2.1.1.4 Commit IO Placement
Phase 2.1.1.4 Commit IO Placement | Checksum: 77d51bae

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 9a2b76ba

Time (s): cpu = 00:00:13 ; elapsed = 00:00:12 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 2.1.2 Build Placer Netlist Model

Phase 2.1.2.1 Place Init Design

Phase 2.1.2.1.1 Init Lut Pin Assignment
Phase 2.1.2.1.1 Init Lut Pin Assignment | Checksum: dba0a931

Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 2.1.2.1 Place Init Design | Checksum: 9ec5875a

Time (s): cpu = 00:00:42 ; elapsed = 00:00:28 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 2.1.2 Build Placer Netlist Model | Checksum: 9ec5875a

Time (s): cpu = 00:00:42 ; elapsed = 00:00:28 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 2.1.3 Constrain Clocks/Macros

Phase 2.1.3.1 Constrain Global/Regional Clocks
Phase 2.1.3.1 Constrain Global/Regional Clocks | Checksum: 9ec5875a

Time (s): cpu = 00:00:42 ; elapsed = 00:00:28 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 2.1.3 Constrain Clocks/Macros | Checksum: 9ec5875a

Time (s): cpu = 00:00:43 ; elapsed = 00:00:29 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 2.1 Placer Initialization Core | Checksum: 9ec5875a

Time (s): cpu = 00:00:43 ; elapsed = 00:00:29 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 2 Placer Initialization | Checksum: 9ec5875a

Time (s): cpu = 00:00:43 ; elapsed = 00:00:29 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 3 Global Placement
Phase 3 Global Placement | Checksum: 113279936

Time (s): cpu = 00:01:15 ; elapsed = 00:00:49 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4 Detail Placement

Phase 4.1 Commit Multi Column Macros
Phase 4.1 Commit Multi Column Macros | Checksum: 113279936

Time (s): cpu = 00:01:15 ; elapsed = 00:00:49 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.2 Commit Most Macros & LUTRAMs
Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 155663ef1

Time (s): cpu = 00:01:21 ; elapsed = 00:00:53 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.3 Area Swap Optimization
Phase 4.3 Area Swap Optimization | Checksum: 1cc9f8a51

Time (s): cpu = 00:01:21 ; elapsed = 00:00:53 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.4 updateClock Trees: DP
Phase 4.4 updateClock Trees: DP | Checksum: 1cc9f8a51

Time (s): cpu = 00:01:21 ; elapsed = 00:00:53 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.5 Timing Path Optimizer
Phase 4.5 Timing Path Optimizer | Checksum: fdd46c53

Time (s): cpu = 00:01:23 ; elapsed = 00:00:54 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.6 Small Shape Detail Placement

Phase 4.6.1 Commit Small Macros & Core Logic

Phase 4.6.1.1 setBudgets
Phase 4.6.1.1 setBudgets | Checksum: ea82c179

Time (s): cpu = 00:01:23 ; elapsed = 00:00:54 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.6.1.2 Commit Slice Clusters
Phase 4.6.1.2 Commit Slice Clusters | Checksum: 113ba313f

Time (s): cpu = 00:01:30 ; elapsed = 00:01:01 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 4.6.1 Commit Small Macros & Core Logic | Checksum: 113ba313f

Time (s): cpu = 00:01:30 ; elapsed = 00:01:01 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.6.2 Clock Restriction Legalization for Leaf Columns
Phase 4.6.2 Clock Restriction Legalization for Leaf Columns | Checksum: 113ba313f

Time (s): cpu = 00:01:30 ; elapsed = 00:01:01 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins
Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 113ba313f

Time (s): cpu = 00:01:31 ; elapsed = 00:01:01 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 4.6 Small Shape Detail Placement | Checksum: 113ba313f

Time (s): cpu = 00:01:31 ; elapsed = 00:01:01 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 4.7 Re-assign LUT pins
Phase 4.7 Re-assign LUT pins | Checksum: 113ba313f

Time (s): cpu = 00:01:32 ; elapsed = 00:01:02 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 4 Detail Placement | Checksum: 113ba313f

Time (s): cpu = 00:01:32 ; elapsed = 00:01:02 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 5 Post Placement Optimization and Clean-Up

Phase 5.1 PCOPT Shape updates
Phase 5.1 PCOPT Shape updates | Checksum: f9c1670b

Time (s): cpu = 00:01:32 ; elapsed = 00:01:03 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 5.2 Post Commit Optimization

Phase 5.2.1 updateClock Trees: PCOPT
Phase 5.2.1 updateClock Trees: PCOPT | Checksum: f9c1670b

Time (s): cpu = 00:01:32 ; elapsed = 00:01:03 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 5.2.2 Post Placement Optimization

Phase 5.2.2.1 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=3.055. For the most accurate timing information please run report_timing.
Phase 5.2.2.1 Post Placement Timing Optimization | Checksum: 1380ef46a

Time (s): cpu = 00:01:40 ; elapsed = 00:01:07 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 5.2.2 Post Placement Optimization | Checksum: 1380ef46a

Time (s): cpu = 00:01:40 ; elapsed = 00:01:07 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 5.2 Post Commit Optimization | Checksum: 1380ef46a

Time (s): cpu = 00:01:41 ; elapsed = 00:01:07 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 5.3 Sweep Clock Roots: Post-Placement
Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 1380ef46a

Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 5.4 Post Placement Cleanup
Phase 5.4 Post Placement Cleanup | Checksum: 1380ef46a

Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 5.5 Placer Reporting

Phase 5.5.1 Restore STA
Phase 5.5.1 Restore STA | Checksum: 1380ef46a

Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 5.5 Placer Reporting | Checksum: 1380ef46a

Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 5.6 Final Placement Cleanup
Phase 5.6 Final Placement Cleanup | Checksum: 1af390b8f

Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 1484.695 ; gain = 0.000
Phase 5 Post Placement Optimization and Clean-Up | Checksum: 1af390b8f

Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 1484.695 ; gain = 0.000
Ending Placer Task | Checksum: 15b010a61

Time (s): cpu = 00:00:00 ; elapsed = 00:01:08 . Memory (MB): peak = 1484.695 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
45 Infos, 76 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:45 ; elapsed = 00:01:11 . Memory (MB): peak = 1484.695 ; gain = 0.000
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 1484.695 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1484.695 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.546 . Memory (MB): peak = 1484.695 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1484.695 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command route_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 134bb133c

Time (s): cpu = 00:01:30 ; elapsed = 00:01:16 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 134bb133c

Time (s): cpu = 00:01:30 ; elapsed = 00:01:17 . Memory (MB): peak = 1484.695 ; gain = 0.000

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 134bb133c

Time (s): cpu = 00:01:30 ; elapsed = 00:01:17 . Memory (MB): peak = 1487.133 ; gain = 2.438
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: de839f79

Time (s): cpu = 00:01:47 ; elapsed = 00:01:28 . Memory (MB): peak = 1543.453 ; gain = 58.758
INFO: [Route 35-57] Estimated Timing Summary | WNS=3.06   | TNS=0      | WHS=-0.379 | THS=-363   |

Phase 2 Router Initialization | Checksum: d48c6b8f

Time (s): cpu = 00:01:50 ; elapsed = 00:01:30 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 195bf2fac

Time (s): cpu = 00:01:59 ; elapsed = 00:01:35 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1585
 Number of Nodes with overlaps = 46
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0

Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: 1ea4b537d

Time (s): cpu = 00:02:14 ; elapsed = 00:01:43 . Memory (MB): peak = 1543.453 ; gain = 58.758
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.29   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 23a533af1

Time (s): cpu = 00:02:14 ; elapsed = 00:01:43 . Memory (MB): peak = 1543.453 ; gain = 58.758
Phase 4 Rip-up And Reroute | Checksum: 23a533af1

Time (s): cpu = 00:02:14 ; elapsed = 00:01:43 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 5 Delay CleanUp

Phase 5.1 Update Timing
Phase 5.1 Update Timing | Checksum: 1be2de8ff

Time (s): cpu = 00:02:15 ; elapsed = 00:01:44 . Memory (MB): peak = 1543.453 ; gain = 58.758
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.29   | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 5 Delay CleanUp | Checksum: 1be2de8ff

Time (s): cpu = 00:02:15 ; elapsed = 00:01:44 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 6 Clock Skew Optimization
Phase 6 Clock Skew Optimization | Checksum: 1be2de8ff

Time (s): cpu = 00:02:15 ; elapsed = 00:01:44 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 7 Post Hold Fix

Phase 7.1 Update Timing
Phase 7.1 Update Timing | Checksum: 16ef6df0c

Time (s): cpu = 00:02:17 ; elapsed = 00:01:45 . Memory (MB): peak = 1543.453 ; gain = 58.758
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.29   | TNS=0      | WHS=0.037  | THS=0      |

Phase 7 Post Hold Fix | Checksum: 1b83e0771

Time (s): cpu = 00:02:17 ; elapsed = 00:01:45 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 8 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.80366 %
  Global Horizontal Routing Utilization  = 2.1541 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 8 Route finalize | Checksum: 1b84fd013

Time (s): cpu = 00:02:18 ; elapsed = 00:01:45 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 9 Verifying routed nets

 Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 1b84fd013

Time (s): cpu = 00:02:18 ; elapsed = 00:01:45 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 10 Depositing Routes
Phase 10 Depositing Routes | Checksum: 2154c111a

Time (s): cpu = 00:02:20 ; elapsed = 00:01:47 . Memory (MB): peak = 1543.453 ; gain = 58.758

Phase 11 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.29   | TNS=0      | WHS=0.037  | THS=0      |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 11 Post Router Timing | Checksum: 2154c111a

Time (s): cpu = 00:02:20 ; elapsed = 00:01:47 . Memory (MB): peak = 1543.453 ; gain = 58.758
INFO: [Route 35-16] Router Completed Successfully

Routing Is Done.

Time (s): cpu = 00:00:00 ; elapsed = 00:01:47 . Memory (MB): peak = 1543.453 ; gain = 58.758
INFO: [Common 17-83] Releasing license: Implementation
58 Infos, 76 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:02:24 ; elapsed = 00:01:50 . Memory (MB): peak = 1543.453 ; gain = 58.758
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 1543.453 ; gain = 0.000
write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1543.453 ; gain = 0.000
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.runs/impl_1/toplevel_drc_routed.rpt.
report_drc: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 1549.195 ; gain = 5.742
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
report_timing_summary: Time (s): cpu = 00:00:14 ; elapsed = 00:00:08 . Memory (MB): peak = 1549.195 ; gain = 0.000
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-218] MMCM/PLL RST static_probability should be either 0 or 1, power analysis is using 0 by default.
Use 'set_switching_activity -static_probability 1 -signal_rate 0 [get_nets mbsys_i/axi_ethernet_0/U0/eth_buf/U0/COMBINE_RESETS/AXI_RESET_TO_TXC_AXSTREAM/ClkA_reset_inst/O5]'  to set the static_probability to '1'  if desired.
report_power: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1549.195 ; gain = 0.000
Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 2 threads
WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_lower/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_upper/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I2/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [Drc 23-20] Rule violation (DPIP-1) Input pipelining - DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1 input A B is not pipelined. Pipelining DSP48 input will improve performance.
WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/FPU_I/Use_FPU.FPU_MUL_I/Use_DSP48E1.dsp_module_lower/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.No_MUL64.dsp_module_I3/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
WARNING: [Drc 23-20] Rule violation (DPOP-1) Output pipelining - DSP mbsys_i/microblaze_0/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/MUL_Unit_I/Use_HW_MUL.Using_DSP48_Architectures.dsp_module_I1/Using_DSP48E1.DSP48E1_I1 output P is not pipelined. Pipelining DSP48 output will improve performance. Both multiplier/adder output can be pipelined.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 8 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Generating merged BMM file for the design top 'toplevel'...
INFO: [Memdata 28-144] Successfully populated the BRAM INIT strings from the following elf files: c:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.srcs/sources_1/ipshared/xilinx.com/microblaze_v9_4/e11bcbd5/data/mb_bootloop_le.elf 
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./toplevel.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-186] 'C:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Tue Mar 24 12:57:10 2015. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2014.4/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:01:38 ; elapsed = 00:01:39 . Memory (MB): peak = 1929.563 ; gain = 380.367
bdTcl: C:/Users/kjohns/Documents/a7_l1ddc_mb_udp.xpr/a7_mmfe_mb_udp/a7_mmfe_mb_udp.runs/impl_1/.Xil/Vivado-3484-phys-pc458-4/HWH/mbsys_bd.tcl
INFO: [Common 17-206] Exiting Vivado at Tue Mar 24 12:57:10 2015...