| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| inst_ADC_TDO_A |
6 |
3 |
0 |
3 |
19 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| inst_ADC_PDO_A |
6 |
1 |
0 |
1 |
19 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| VMM2_TST_PULSE_inst |
59 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| VMM2_READOUT_INST |
37 |
0 |
2 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst2 |
548 |
215 |
4 |
215 |
528 |
215 |
215 |
215 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|wrfull_eq_comp |
22 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|rdempty_eq_comp |
22 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|ws_dgrp|dffpipe15 |
13 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|ws_dgrp |
13 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 |
13 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|rs_dgwp |
13 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|fifo_ram |
42 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst5 |
21 |
1 |
0 |
1 |
18 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|wrfull_eq_comp |
22 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|rdempty_eq_comp |
22 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|ws_dgrp|dffpipe15 |
13 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|ws_dgrp |
13 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 |
13 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|rs_dgwp |
13 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|fifo_ram |
42 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst4 |
21 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst3 |
40 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|wrfull_eq_comp |
28 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|rdempty_eq_comp |
28 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|ws_dgrp|dffpipe16 |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|ws_dgrp |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|ws_bwp |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|ws_brp |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|rs_dgwp|dffpipe12 |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|rs_dgwp |
16 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|fifo_ram |
48 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|ws_dgrp_gray2bin |
14 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated|wrptr_g_gray2bin |
14 |
0 |
0 |
0 |
14 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2|dcfifo_component|auto_generated |
21 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst2 |
21 |
0 |
0 |
0 |
30 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1|inst1 |
19 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst1 |
43 |
3 |
3 |
3 |
44 |
3 |
3 |
3 |
16 |
0 |
0 |
0 |
0 |
| b2v_inst_pll_50|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst_pll_50 |
1 |
1 |
0 |
1 |
4 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst_pll|altpll_component|auto_generated |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| b2v_inst_pll |
1 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |